Wafer polishing high buffer gradient protective substrate and preparation method thereof

By using a three-layer gradient structure to protect the substrate with high buffer gradient, the problems of insufficient adhesion, buffering and processing stability in the high-drop wafer grinding process of the prior art are solved, and a high-efficiency processing effect with low pollution and low breakage is achieved, which is suitable for wafer grinding of high-bump circuits.

CN122626548APending Publication Date: 2026-08-25ANHUI ZIJIANG NEW MATERIAL TECH CO LTD
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Patent Information

Application Number
CN202610672031.4
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-05-15
Publication Date
2026-08-25

AI Technical Summary

Technical Problem

Existing wafer grinding protection substrates cannot be adapted to wafers with high drop, and their adhesion, buffering and processing stability are insufficient, resulting in high wafer breakage and contamination rates, and failing to meet the structural followability requirements of high-bump circuits.

Method used

The high-buffered gradient protective substrate adopts a three-layer gradient structure, consisting of a corona layer, an intermediate buffer layer, and a back support layer. These layers are respectively composed of semi-crosslinked EPDM/PPTPV, maleic anhydride modified polyethylene PE-g-MAH, epoxy functionalized POE, partially crosslinked ethylene propylene rubber (EPM) in the intermediate buffer layer, narrow-density metallocene polyethylene (mPE), block copolymer PP in the back support layer, high-resilience POE, and semiconductor-grade nano-SiO2 anti-blocking agent. It is prepared by melt grafting and co-extrusion casting processes to achieve optimization of gradient hardness and elastic modulus.

Benefits of technology

It achieves low contamination rate (≤0.04%) and low breakage rate (≤0.05%) in the high-drop wafer grinding process, and has high adhesion, buffering and processing stability. It is suitable for the process requirements of high-drop wafers and improves processing yield and reliability.

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Abstract

The present application relates to the technical field of semiconductor wafer processing protection materials, and specifically relates to a high-buffer-gradient protective substrate for wafer grinding and a preparation method thereof, which is composed of a corona layer, an intermediate buffer layer and a back support layer in sequence; the substrate has a double-gradient structure of gradient hardness and gradient elastic modulus, the hardness of the three layers is 43A-47A, 53A-56A and 67A-70A in sequence, and the elastic modulus of the three layers is 18-28 MPa, 35-45 MPa and 70-90 MPa in sequence; the present application realizes overall optimization from micro components, interface structure to macro performance through the synergistic cooperation of three-layer gradient structure design, full polyolefin non-extraction material system and three-layer co-extrusion flow forming process, and systematically solves the technical problems that the existing wafer grinding protective substrate cannot adapt to high-fall wafer, is insufficient in adhesion and buffering, and has a high pollution and damage rate.
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Description

Technical Field

[0001] This invention relates to the field of semiconductor wafer process protection materials, specifically to a high-buffered gradient protection substrate for wafer polishing and its preparation method. Background Technology

[0002] In semiconductor wafer manufacturing processes, back-side grinding and thinning is a core process for achieving device miniaturization, 3D packaging, and high-performance integration. During the grinding process, the circuit functional surfaces on the front side of the wafer are continuously subjected to vertical pressure, lateral shear force, and frictional heat generated during grinding. Simultaneously, the environment contains a large amount of grinding debris and chemical polishing fluid. Without effective protection, this can easily lead to chip circuit damage, surface contamination, and short circuits, and in severe cases, directly cause the entire wafer to shatter. Therefore, applying a dedicated grinding protective tape to the front side of the wafer is a necessary technical means to achieve physical buffering and support, disperse grinding stress, prevent edge chipping and cracking, seal and cover the uneven circuit structure, prevent the penetration of grinding debris and polishing fluid, and ensure stable peeling after grinding without residue or damage to the circuit.

[0003] Currently, the substrates for UV anti-adhesion protective tapes used in wafer grinding mainly fall into three technical categories. The first category is PET-based composite tape, which consists of a rigid PET substrate combined with a coated TPU or EVA buffer layer, and then a UV anti-adhesion layer. This type of substrate has high modulus and rigidity, making it prone to tearing the chip circuitry during peeling. Furthermore, its manufacturing process is complex and costly, making it only suitable for flat glass substrates and unsuitable for wafers with significant unevenness. The second category is flexible PVC substrate. Because plasticizers are added to the substrate, they are prone to migration during high-temperature processes, causing surface contamination of the wafer. It also has poor environmental performance and is gradually being phased out by the industry. The third category is co-extruded casting substrates of polyolefins (PO) or EVA, which is the current mainstream technology. Existing technologies have optimized parameters such as elastic modulus and hardness to improve adhesion and height difference tracking.

[0004] However, existing publicly available technologies still have significant limitations: some solutions are only applicable to low-displacement wafers with a height difference of 6μm and a floating width of less than 50μm; other technologies achieve grinding planarization by setting a grinding layer on the outside of the tape, but can only achieve good thickness uniformity control for wafers with a height difference of 20μm, and cannot meet the requirements of larger height difference conditions. Overall, conventional polyolefin and EVA substrates generally have Shore hardness higher than 70A and elastic modulus greater than 100MPa, making them relatively hard and lacking in structural conformity to high-bump circuits. After bonding, the interface gap is relatively large, and grinding debris and grinding fluid can easily penetrate into the interior, causing wafer contamination and circuit damage. Especially for high-displacement wafers such as MEMS chips with height differences greater than 100μm, or even reaching 200μm, existing substrates cannot simultaneously meet the requirements of adhesion, buffering, support, and processing stability, resulting in persistently high wafer breakage and contamination rates, becoming a key technical bottleneck restricting the improvement of high-displacement wafer grinding yield. Based on the above problems, the industry urgently needs to develop a new type of protective substrate and its preparation method that can adapt to high-drop wafers and has the characteristics of high buffering, high adhesion, low pollution and low damage. Summary of the Invention

[0005] To address the problems existing in the prior art, the present invention provides a high buffer gradient protective substrate for wafer grinding and its preparation method.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A high-buffered gradient protective substrate for wafer polishing is composed of a corona layer, an intermediate buffer layer, and a back support layer in sequence. The substrate has a dual-gradient structure with gradient hardness and gradient elastic modulus. The hardness of the three layers is 43A-47A, 53A-56A, and 67A-70A, respectively, and the elastic modulus of the three layers is 18-28MPa, 35-45MPa, and 70-90MPa, respectively. The corona layer is composed of semi-crosslinked EPDM / PPTPV, maleic anhydride modified polyethylene PE-g-MAH, and epoxy functionalized POE; The intermediate buffer layer is composed of partially cross-linked ethylene propylene rubber (EPM) and narrow-density metallocene polyethylene (mPE). The back support layer is composed of block copolymer PP, high resilience POE, and semiconductor-grade nano-SiO2 anti-blocking agent.

[0007] As a further technical solution, the gelation rate of semi-crosslinked TPV in the corona layer is 40%-65%, the grafting rate of PE-g-MAH is 0.65%-0.85% and the addition percentage is 8%-12%, the addition percentage of epoxy-functionalized POE is 0.3%-0.8%, and the balance is semi-crosslinked TPV.

[0008] As a further technical solution, the gelation rate of the partially cross-linked EPM in the intermediate buffer layer is 25%-40%, and the addition percentage is 72%-78%, while the density of the remaining mPE is 0.865-0.875 g / cm³. 3 .

[0009] As a further technical solution, the high-resilience POE in the back support layer has an octene content of 18%-24% and an addition percentage of 22%-28%, and the nano-SiO2 anti-blocking agent has a particle size of 10-25nm and an addition percentage of 2.5%-3.5%; the back support layer may also optionally contain 0.5%-1.2% nano-talc, with the remainder being block copolymer PP.

[0010] As a further technical solution, the total thickness of the substrate is 80-160μm, and the thickness ratio of the corona layer: intermediate buffer layer: back support layer is 1:4.8-5.2:1.

[0011] A method for preparing a high-buffered gradient protective substrate for wafer grinding includes the following steps: (1) Preparation of epoxy-functionalized POE by melt grafting: Ethylene-octene copolymer, glycidyl methacrylate and peroxide initiator are mixed evenly at high speed according to the ratio and added to a co-rotating twin-screw extruder for melt grafting reaction. Unreacted monomers and small molecule volatiles are removed by vacuum devolatilization, and the mixture is cooled with water, air-dried and granulated to obtain epoxy-functionalized POE. The peroxide initiator is dicumyl peroxide; (2) After the materials of the corona layer, intermediate buffer layer and back support layer are premixed and dried, they are fed into a single screw extruder for gradient heating and plasticizing melting. (3) After the viscosity of the three-layer melt is adjusted by a multi-stage gradient temperature control distributor, it enters the low-pressure, low-shear T-die head for co-extrusion casting. (4) Cool the molded substrate, apply constant tension traction, and shape and rewind to obtain the high buffer gradient protection substrate.

[0012] As a further technical solution, the melting grafting temperature in step (1) is 180-200℃, and the grafting rate of the prepared epoxy functionalized POE is 0.3%-1.0%.

[0013] As a further technical solution, the temperature of gradient heating plasticization in step (2) is: 195-210℃ for the corona layer, 205-222℃ for the intermediate buffer layer, and 222-228℃ for the back support layer.

[0014] As a further technical solution, in step (3), the temperatures of the multi-level gradient temperature control distributor are 218℃, 215℃, and 212℃ respectively; the temperature of the T-shaped mold head is 210-218℃, and the internal pressure of the mold head is 80-120 bar.

[0015] As a further technical solution, in step (4), the constant tension traction adopts closed-loop control, with a tension of 50-150 N / m and a traction speed ratio of 1.02-1.05.

[0016] Compared with the prior art, the beneficial effects of the present invention are: This invention achieves comprehensive optimization from microscopic composition and interface structure to macroscopic performance through the synergistic combination of a three-layer gradient structure design, a non-precipitated all-polyolefin material system, and a three-layer co-extrusion casting process. It systematically solves the technical problems of existing wafer grinding protection substrates being unable to adapt to high-drop wafers, insufficient adhesion and buffering, and high contamination and breakage rates.

[0017] The corona layer is a composite of semi-crosslinked EPDM / PPTPV, PE-g-MAH with a specific grafting ratio, and epoxy-functionalized POE. Because the gel rate of the semi-crosslinked TPV is controlled at 40%-65%, the Shore hardness of the corona layer is stabilized at 43A-47A and the elastic modulus is 18-28MPa, forming an ultra-soft and densely adherent layer that can tightly encapsulate circuit structures with height differences greater than 100μm, eliminating interfacial voids and penetration channels, and blocking the intrusion of polishing fluid and debris from the source. At the same time, PE-g-MAH and epoxy-functionalized POE achieve in-situ interfacial bonding, improving the interlayer bonding strength and inhibiting small molecule migration, giving the corona layer semiconductor-grade cleanliness and effectively reducing the risk of wafer contamination. The intermediate buffer layer is a composite of partially cross-linked EPM with a gel rate of 25%-40% and narrow-density metallocene polyethylene (mPE), with a hardness controlled at 53A-56A and an elastic modulus of 35-45MPa. This forms a high-energy-absorbing buffer structure that can efficiently absorb and disperse stress impacts during the grinding process, preventing stress concentration from causing chip damage and providing core protection for the circuit. The back support layer is a composite of block copolymer PP, high-resilience POE, and semiconductor-grade nano-SiO2 anti-blocking agent, with a hardness increased to 67A-70A and an elastic modulus of 70-90MPa. This provides sufficient stiffness and anti-curling performance for the substrate, ensuring stable and smooth bonding, grinding, UV debonding, and peeling processes. The nano-SiO2 achieves the anti-blocking function without affecting the cleanliness of the process.

[0018] The three-layer structure forms a continuous gradient distribution along the thickness direction, from soft to medium to hard and from low to medium to high modulus. The corona layer provides high-density coating, the intermediate buffer layer efficiently absorbs energy, and the back support layer provides stable shaping. These three layers work together to achieve a balance between adhesion, buffering, support, and processability. The fabrication process employs layered gradient temperature-controlled melting, multi-stage gradient temperature distributors to regulate melt viscosity, low-pressure low-shear co-extrusion casting, and constant-tension traction shaping. This protects the semi-crosslinked and partially crosslinked rubber phase structures from damage, ensuring the integrity of the gradient properties, while also strengthening interlayer bonding and preventing interface separation. This invention uses a full polyolefin plasticizer-free system, eliminating the risk of small molecule migration and contamination. Ultimately, it achieves excellent levels of contamination rate ≤0.04% and breakage rate ≤0.05% in high-drop wafer grinding. It also possesses advantages such as easy UV debonding, no residue, and compatibility with automated processes, significantly improving the yield and reliability of high-drop wafer grinding, fully meeting the advanced process requirements of high-drop wafers such as MEMS. Detailed Implementation

[0019] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] This invention provides a high-buffered gradient protective substrate for wafer grinding, which is composed of a corona layer, an intermediate buffer layer, and a back support layer in sequence. The substrate has a dual-gradient structure with gradient hardness and gradient elastic modulus. The hardness of the three layers is 43A-47A, 53A-56A, and 67A-70A respectively, and the elastic modulus of the three layers is 18-28MPa, 35-45MPa, and 70-90MPa respectively.

[0021] The corona layer is composed of semi-crosslinked EPDM / PPTPV, maleic anhydride modified polyethylene PE-g-MAH, and epoxy-functionalized POE; the gel rate of semi-crosslinked TPV is 40%-65%, the grafting rate of PE-g-MAH is 0.65%-0.85% and the addition percentage is 8%-12%, the addition percentage of epoxy-functionalized POE is 0.3%-0.8%, and the balance is semi-crosslinked TPV.

[0022] The intermediate buffer layer is composed of partially cross-linked ethylene propylene rubber (EPM) and narrow-density metallocene polyethylene (mPE); the partially cross-linked EPM has a gel rate of 25%-40% and an addition percentage of 72%-78%, while the remaining mPE has a density of 0.865-0.875 g / cm³. 3 .

[0023] The back support layer is composed of block copolymer PP, high-resilience POE, and semiconductor-grade nano-SiO2 anti-blocking agent; the high-resilience POE has an octene content of 18%-24% and an addition percentage of 22%-28%, and the nano-SiO2 anti-blocking agent has a particle size of 10-25nm and an addition percentage of 2.5%-3.5%; the back support layer may also optionally contain 0.5%-1.2% nano-talc, with the balance being block copolymer PP.

[0024] The total thickness of the substrate is 80-160μm, and the thickness ratio of the corona layer: intermediate buffer layer: back support layer is 1:4.8-5.2:1.

[0025] This invention also provides a method for preparing a high-buffered gradient protective substrate for wafer polishing, comprising the following steps: Epoxy-functionalized POE was prepared by melt grafting: ethylene-octene copolymer, glycidyl methacrylate, and dicumyl peroxide were mixed uniformly at high speed according to the specified ratio and added to a co-rotating twin-screw extruder. The melt grafting reaction was carried out at 180-200℃. Unreacted monomers and small volatile molecules were removed by vacuum devolatilization. The mixture was then water-cooled, air-dried, and granulated to obtain epoxy-functionalized POE with a grafting rate of 0.3%-1.0%.

[0026] After the materials of the corona layer, intermediate buffer layer and back support layer are premixed and dried, they are fed into a single screw extruder for gradient heating and plasticizing melting. The plasticizing temperature of the corona layer is 195-210℃, the plasticizing temperature of the intermediate buffer layer is 205-222℃, and the plasticizing temperature of the back support layer is 222-228℃.

[0027] The three-layer melt enters a multi-stage gradient temperature control distributor, with distributor temperatures of 218℃, 215℃, and 212℃ respectively. After adjusting the melt viscosity, it enters a low-pressure, low-shear T-die for co-extrusion casting. The T-die temperature is 210-218℃, and the internal pressure of the die is 80-120 bar.

[0028] The molded substrate is cooled and then traction is controlled by constant tension closed loop, with a tension of 50-150 N / m and a traction speed ratio of 1.02-1.05. After shaping and winding, a high buffer gradient protective substrate is obtained.

[0029] All raw materials used in this invention are commercially available products commonly used in the field: Raw material source: Semi-crosslinked TPV: Santoprene™ 103-50 / 121-73W175 (gel rate 40%–65%); PEgMAH: SK OREVAC® OE825 (grafting rate 0.7%–0.8%); Epoxy-functionalized POE: Dow / ExxonMobil epoxy-modified POE; Partially crosslinked EPM: Sumitomo Chemical ESPRENE™ SPO V0141; mPE: Mitsui Chemicals Evolue™ SP0540 (density 0.865–0.875); Block copolymer PP: Hyosung J351F; High-resilience POE: ENGAGE 8200; Anti-blocking agent: Semiconductor-grade nano-SiO2 masterbatch (10–25nm).

[0030] Example 1: Preparation of epoxy-functionalized POE: Ethylene-octene copolymer, glycidyl methacrylate, and dicumyl peroxide are mixed evenly at high speed and fed into a co-rotating twin-screw extruder. The mixture is then subjected to a melt grafting reaction at 180°C. After vacuum devolatilization, the mixture is water-cooled, air-dried, and granulated to obtain epoxy-functionalized POE.

[0031] Prepare the corona layer materials: by mass fraction, semi-crosslinked EPDM / PPTPV is 90.0%, maleic anhydride modified polyethylene PE-g-MAH is 9.5%, and epoxy functionalized POE is 0.5%. Mix all components evenly.

[0032] The intermediate buffer layer material is prepared as follows: by mass fraction, the partially cross-linked ethylene propylene rubber (EPM) is 75.0% and the narrow-density metallocene polyethylene (mPE) is 25.0%. All components are mixed evenly.

[0033] The back support layer material is configured as follows: by mass fraction, block copolymer PP is 72.0%, high resilience POE is 25.0%, and semiconductor-grade nano-SiO2 anti-blocking agent is 3.0%. All components are mixed evenly.

[0034] The corona layer material is fed into a single-screw extruder and plasticized and melted at 195°C; the intermediate buffer layer material is fed into a single-screw extruder and plasticized and melted at 205°C; the back support layer material is fed into a single-screw extruder and plasticized and melted at 222°C.

[0035] The three layers of melt sequentially enter a multi-stage gradient temperature control distributor with temperatures of 218℃, 215℃, and 212℃, and then enter a low-pressure, low-shear T-die head with a temperature of 210℃ and an internal pressure of 80 bar for co-extrusion casting.

[0036] The molded substrate is cooled, and constant tension closed-loop control traction with a tension of 50 N / m and a traction speed ratio of 1.02 is used for shaping and winding to obtain a high buffer gradient protection substrate for wafer grinding.

[0037] The total thickness of the substrate is controlled to be 80μm, and the thickness ratio of the corona layer, intermediate buffer layer and back support layer is 1:4.8:1.

[0038] Example 2: Preparation of epoxy-functionalized POE: Ethylene-octene copolymer, glycidyl methacrylate, and dicumyl peroxide are mixed evenly at high speed and fed into a co-rotating twin-screw extruder. The mixture is then subjected to a melt grafting reaction at 190°C. After vacuum devolatilization, the mixture is water-cooled, air-dried, and granulated to obtain epoxy-functionalized POE.

[0039] The corona layer materials are prepared as follows: by mass fraction, semi-crosslinked EPDM / PPTPV is 88.0%, maleic anhydride modified polyethylene PE-g-MAH is 11.5%, and epoxy functionalized POE is 0.5%. All components are mixed evenly.

[0040] The intermediate buffer layer material is prepared as follows: by mass fraction, the partially cross-linked ethylene propylene rubber (EPM) is 75.0% and the narrow-density metallocene polyethylene (mPE) is 25.0%. All components are mixed evenly.

[0041] The back support layer material is configured as follows: by mass fraction, block copolymer PP is 72.0%, high resilience POE is 25.0%, and semiconductor-grade nano-SiO2 anti-blocking agent is 3.0%. All components are mixed evenly.

[0042] The corona layer material is fed into a single-screw extruder and plasticized and melted at 200°C; the intermediate buffer layer material is fed into a single-screw extruder and plasticized and melted at 210°C; the back support layer material is fed into a single-screw extruder and plasticized and melted at 225°C.

[0043] The three layers of melt sequentially enter a multi-stage gradient temperature control distributor with temperatures of 218℃, 215℃, and 212℃, and then enter a low-pressure, low-shear T-die head with an internal pressure of 100 bar at 215℃ for co-extrusion casting.

[0044] The molded substrate is cooled and then traction is controlled by a constant tension closed loop with a tension of 100 N / m and a traction speed ratio of 1.03. The substrate is then shaped and wound up to obtain a high buffer gradient protection substrate for wafer grinding.

[0045] The total thickness of the substrate is controlled to be 120μm, and the thickness ratio of the corona layer, intermediate buffer layer and back support layer is 1:5.0:1.

[0046] Example 3: Preparation of epoxy-functionalized POE: Ethylene-octene copolymer, glycidyl methacrylate, and dicumyl peroxide are mixed evenly at high speed and fed into a co-rotating twin-screw extruder. The mixture is then subjected to a melt grafting reaction at 200°C. After vacuum devolatilization, the mixture is water-cooled, air-dried, and granulated to obtain epoxy-functionalized POE.

[0047] The corona layer materials are prepared as follows: by mass fraction, semi-crosslinked EPDM / PPTPV is 87.0%, maleic anhydride modified polyethylene PE-g-MAH is 12.0%, and epoxy functionalized POE is 1.0%. All components are mixed evenly.

[0048] The intermediate buffer layer material is prepared as follows: by mass fraction, the partially cross-linked ethylene propylene rubber (EPM) is 76.0% and the narrow-density metallocene polyethylene (mPE) is 24.0%. All components are mixed evenly.

[0049] The back support layer material is configured as follows: by mass fraction, block copolymer PP is 72.0%, high resilience POE is 25.0%, and semiconductor-grade nano-SiO2 anti-blocking agent is 3.0%. All components are mixed evenly.

[0050] The corona layer material is fed into a single-screw extruder and plasticized and melted at 210°C; the intermediate buffer layer material is fed into a single-screw extruder and plasticized and melted at 222°C; the back support layer material is fed into a single-screw extruder and plasticized and melted at 228°C.

[0051] The three layers of melt sequentially enter a multi-stage gradient temperature control distributor with temperatures of 218℃, 215℃, and 212℃, and then enter a low-pressure, low-shear T-die head with a temperature of 218℃ and an internal pressure of 120 bar for co-extrusion casting.

[0052] The molded substrate is cooled and then traction is controlled by a constant tension closed loop with a tension of 150 N / m and a traction speed ratio of 1.05. The substrate is then shaped and wound up to obtain a high buffer gradient protection substrate for wafer grinding.

[0053] The total thickness of the substrate is controlled to be 160μm, and the thickness ratio of the corona layer, intermediate buffer layer and back support layer is 1:5.2:1.

[0054] Comparative Example 1: The corona layer material is prepared as follows: by mass fraction, semi-crosslinked EPDM / PPTPV is 80.0%, maleic anhydride modified polyethylene PE-g-MAH is 20.0%, and no epoxy functionalized POE is added. All components are mixed evenly.

[0055] The intermediate buffer layer material is prepared as follows: by mass fraction, partially cross-linked ethylene propylene rubber (EPM) is 80.0% and narrow-density metallocene polyethylene (mPE) is 20.0%. All components are mixed evenly.

[0056] The back support layer material is configured as follows: by mass fraction, block copolymer PP is 72.0%, high resilience POE is 25.0%, and semiconductor-grade nano-SiO2 anti-blocking agent is 3.0%. All components are mixed evenly.

[0057] The substrate was prepared using the same extrusion, co-extrusion casting, cooling traction, and winding process as in Example 1, with the thickness parameters remaining consistent with those in Example 1.

[0058] Comparative Example 2: The corona layer material is prepared as follows: by mass fraction, semi-crosslinked EPDM / PPTPV is 80.0%, maleic anhydride modified polyethylene PE-g-MAH is 20.0%, and no epoxy functionalized POE is added. All components are mixed evenly.

[0059] The intermediate buffer layer material is prepared as follows: by mass fraction, partially cross-linked ethylene propylene rubber (EPM) is 60.0% and narrow-density metallocene polyethylene (mPE) is 40.0%. All components are mixed evenly.

[0060] The back support layer material is configured as follows: by mass fraction, block copolymer PP is 72.0%, high resilience POE is 25.0%, and semiconductor-grade nano-SiO2 anti-blocking agent is 3.0%. All components are mixed evenly.

[0061] The substrate was prepared using the same extrusion, co-extrusion casting, cooling traction, and winding process as in Example 1, with the thickness parameters remaining consistent with those in Example 1.

[0062] Comparative Example 3: The corona layer material is prepared as follows: by mass fraction, semi-crosslinked EPDM / PPTPV is 70.0%, maleic anhydride modified polyethylene PE-g-MAH is 30.0%, and epoxy functionalized POE is not added. All components are mixed evenly.

[0063] The intermediate buffer layer material is prepared as follows: by mass fraction, partially cross-linked ethylene propylene rubber (EPM) is 60.0% and narrow-density metallocene polyethylene (mPE) is 40.0%. All components are mixed evenly.

[0064] The back support layer material is configured as follows: by mass fraction, block copolymer PP is 77.0%, high resilience POE is 20.0%, and semiconductor-grade nano-SiO2 anti-blocking agent is 3.0%. All components are mixed evenly.

[0065] The substrate was prepared using the same extrusion, co-extrusion casting, cooling traction, and winding process as in Example 1, with the thickness parameters remaining consistent with those in Example 1.

[0066] test: Experiment 1: Shore Hardness Test Test standard: GB / T2411-2008 Sample preparation: Each layer of the substrate material of Examples 1-3 and Comparative Examples 1-3 was individually pressed into sheets with a thickness of 2.0 mm ± 0.2 mm and placed at room temperature for 24 h.

[0067] Test conditions: room temperature 23 ± 2°C, relative humidity 50 ± 5%RH; use a Shore A durometer, maintain the pressure for 5 s and take the reading, test 5 points for each sample, and take the average value.

[0068] Table 1 Shore hardness test results of each layer Result analysis: The hardness of the three layers in Examples 1-3 shows a continuous gradient distribution of 43A - 47A, 53A - 56A, and 67A - 70A. In Comparative Example 1, the hardness of the corona layer is too high, and the hardness of the intermediate layer deviates from the gradient range; in Comparative Examples 2 and 3, the hardness of the intermediate layer and the back layer is too high, the hardness of the corona layer exceeds the preferred range, and the gradient structure is damaged, making it impossible to achieve the synergistic effects of soft layer adhesion, middle layer buffering, and hard layer support.

[0069] Test 2 Elastic modulus test: Test standard: GB / T1040.1-2018; Specimen preparation: The substrates of Examples 1-3 and Comparative Examples 1-3 are made into dumbbell-shaped specimens with a width of 6 mm and a thickness equal to the actual thickness of the substrate.

[0070] Test conditions: room temperature 23 ± 2°C, tensile speed 1 mm / min; test the longitudinal MD and transverse TD respectively, and take the numerical value of the initial linear segment of the elastic modulus.

[0071] Table 2 Elastic modulus test results Result analysis: The elastic modulus of Examples 1-3 shows a continuous gradient transition of 18 - 28 MPa,

[0072] Test 3 Wafer contamination rate test: Test method: 1) After grinding and peeling, use a combination of optical microscope and ion contamination tester for detection; 2) Observe the contaminated area areas such as residual glue, precipitates, spots, and oil stains on the wafer surface; 3) The contamination rate is calculated as the contaminated area / the effective area of the wafer; 4) At the same time, conduct an ion precipitation test: Na + 、K + 、Cl - The total content ≤ 5 ppb is qualified.

[0073] Table 3 Wafer contamination rate test results Results Analysis: Examples 1-3 employed a non-precipitating all-polyolefin system and an in-situ interface bonding design, resulting in contamination rates below 0.04%, meeting semiconductor cleanliness requirements. Comparative Example 1, lacking epoxy-functionalized POE, exhibited poor interfacial bonding and was prone to precipitate formation. Comparative Examples 2 and 3 had excessively low TPV content in the corona layer and excessive PE-g-MAH, leading to easy migration of small molecules and significantly increased contamination rates.

[0074] Experiment 4: Wafer Grinding Breakage Rate Test Test methods: 1) First, coat the corona-exposed surface of the prepared protective tape with a 45%-55% solids content acrylic single-component UV anti-tack adhesive (Changxing Chemical), cure at 120℃ for 180 seconds, resulting in a cured adhesive layer thickness of 10µm ± 2µm and an initial peel strength of 16N / 25mm; 2) Adhere the tape to the surface of an 8-inch CMOS wafer with a circuit height difference > 100µm; 3) Use a wafer back-side grinder with a grinder pressure of 1.5-2.5psi and a rotation speed of 300-500rpm to thin the wafer to 80µm; 4) Irradiate with UV light at 300-500mJ / cm². 2 5) Observe the entire wafer under a 100x metallographic microscope, count the number of damaged chips / total number of chips, and calculate the damage rate.

[0075] Table 4. Wafer Grinding Breakage Rate Test Results Results Analysis: Examples 1-3 effectively dispersed grinding stress through a gradient buffer structure, with breakage rates all below 0.05%. Comparative Example 1 had excessively high EPM content in the intermediate layer and insufficient buffering performance; Comparative Examples 2 and 3 had missing buffer components in the intermediate layer and excessively rigid back layers, resulting in ineffective stress dispersion and a significant increase in wafer breakage rates.

[0076] Test 5 Adhesion / Step Coverage Test: Test method: Steps: 1) Use a simulated wafer with a 100μm height photoresist step structure; 2) Hot press the protective tape at 50℃ and 0.3MPa for 30s; 3) Use a scanning electron microscope (SEM) to observe whether there are gaps, bubbles, or detachment at the interface between the tape and the step; 4) Judgment criteria: No gaps, no gaps, and no penetration channels are considered qualified.

[0077] Results analysis: The ultra-soft corona layer formulations in Examples 1-3 can tightly coat a 100μm high-drop structure without gaps or penetration channels, and are qualified.

[0078] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not describe all details exhaustively, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification.

Claims

1. A high-buffered gradient protective substrate for wafer grinding, characterized in that, It is composed of a corona layer, an intermediate buffer layer, and a back support layer in sequence; the substrate has a dual gradient structure of gradient hardness and gradient elastic modulus, with the hardness of the three layers being 43A-47A, 53A-56A, and 67A-70A respectively, and the elastic modulus of the three layers being 18-28MPa, 35-45MPa, and 70-90MPa respectively. The corona layer is composed of semi-crosslinked EPDM / PPTPV, maleic anhydride modified polyethylene PE-g-MAH, and epoxy functionalized POE; The intermediate buffer layer is composed of partially cross-linked ethylene propylene rubber (EPM) and narrow-density metallocene polyethylene (mPE). The back support layer is composed of block copolymer PP, high resilience POE, and semiconductor-grade nano-SiO2 anti-blocking agent.

2. The high buffer gradient protective substrate for wafer grinding according to claim 1, characterized in that, The corona layer has a gelation rate of 40%-65% for semi-crosslinked TPV, a grafting rate of 0.65%-0.85% for PE-g-MAH with an addition percentage of 8%-12%, an addition percentage of 0.3%-0.8% for epoxy-functionalized POE, and the remainder is semi-crosslinked TPV.

3. The high buffer gradient protective substrate for wafer grinding according to claim 1, characterized in that, The intermediate buffer layer contains partially cross-linked EPM with a gelation rate of 25%-40% and an addition percentage of 72%-78%, while the remaining mPE has a density of 0.865-0.875 g / cm³. 3 .

4. The high buffer gradient protective substrate for wafer grinding according to claim 1, characterized in that, The high-resilience POE in the back support layer has an octene content of 18%-24% and an addition percentage of 22%-28%, and the nano-SiO2 anti-blocking agent has a particle size of 10-25nm and an addition percentage of 2.5%-3.5%. The back support layer may also optionally contain 0.5%-1.2% nano-talc, with the remainder being block copolymer PP.

5. The high buffer gradient protective substrate for wafer grinding according to claim 1, characterized in that, The total thickness of the substrate is 80-160μm, and the thickness ratio of the corona layer: intermediate buffer layer: back support layer is 1:4.8-5.2:

1.

6. A method for preparing a high-buffered gradient protective substrate for wafer polishing according to any one of claims 1-5, characterized in that, Includes the following steps: (1) Preparation of epoxy-functionalized POE by melt grafting: Ethylene-octene copolymer, glycidyl methacrylate and peroxide initiator are mixed evenly at high speed according to the ratio and added to a co-rotating twin-screw extruder for melt grafting reaction. Unreacted monomers and small molecule volatiles are removed by vacuum devolatilization, and the mixture is cooled with water, air-dried and granulated to obtain epoxy-functionalized POE. The peroxide initiator is dicumyl peroxide; (2) After the materials of the corona layer, intermediate buffer layer and back support layer are premixed and dried, they are fed into a single screw extruder for gradient heating and plasticizing melting. (3) After the viscosity of the three-layer melt is adjusted by a multi-stage gradient temperature control distributor, it enters the low-pressure, low-shear T-die head for co-extrusion casting. (4) Cool the molded substrate, apply constant tension traction, and shape and rewind to obtain the high buffer gradient protection substrate.

7. The preparation method according to claim 6, characterized in that, In step (1), the temperature of melt grafting is 180-200℃, and the grafting rate of the prepared epoxy functionalized POE is 0.3%-1.0%.

8. The preparation method according to claim 6, characterized in that, The gradient heating temperatures in step (2) are: 195-210℃ for the corona layer, 205-222℃ for the intermediate buffer layer, and 222-228℃ for the back support layer.

9. The preparation method according to claim 6, characterized in that, In step (3), the temperatures of the multi-stage gradient temperature control distributor are 218℃, 215℃, and 212℃ respectively; the temperature of the T-shaped die head is 210-218℃, and the internal pressure of the die head is 80-120 bar.

10. The preparation method according to claim 6, characterized in that, In step (4), the constant tension traction adopts closed-loop control, with a tension of 50-150 N / m and a traction speed ratio of 1.02-1.05.