A histogram-on-chip circuit applied to SPAD array detection imaging

Abstract

The application discloses a kind of on-chip histogram circuit applied to SPAD array detection imaging, in which: series-parallel conversion module and decoder module, including shift register and combination logic gate;Signal processing module, through counter and multiplexer control other module operating state and signal input;Mode control module is state machine, controls the working mode of each pixel;Histogram establishment module, peak storage module, through SRAM storage histogram, peak and mode information;Peak detection module, through counter and comparator peak searching is carried out to histogram;Peak correction and output module is state machine, according to the peak correction or peak output of pixel working mode.This application circuit uses scaling histogram method, reduces the storage area required for on-chip histogram, avoids peak value error detection generated by peak value falling at coarse histogram boundary through boundary correction, and increases boundary detection based on traditional scaling histogram, improves frame rate while reducing power consumption.

Description

Technical Field

[0001] This invention relates to the fields of laser ranging and infrared detection imaging, and particularly to an on-chip histogram circuit for SPAD array detection imaging. Background Technology

[0002] In SPAD single-photon detection and imaging systems, the timestamp data output from the time-to-digital converter (TDC) contains a large number of invalid or erroneous signals due to factors such as the detector's own dark count, detection efficiency, and ambient background noise. The valid photon return signals truly originating from the target object are thus obscured. To extract the true target information, a common approach is to use histogram statistics. This involves constructing a histogram by accumulating multiple frames of TDC timestamp data and outputting the statistical peak as the true timestamp corresponding to the distance to the target object.

[0003] However, as single-photon avalanche diode detectors evolve towards integration, miniaturization, and large-scale arrays, the number of on-chip integrated functional units is increasing, and the amount of data generated is growing exponentially. Against this backdrop, relying on off-chip systems for subsequent data processing is no longer sufficient to meet the demands of practical applications in terms of speed, power consumption, and integration.

[0004] Therefore, integrating histogram processing circuitry on-chip has become an inevitable trend. However, traditional on-chip histogram solutions face serious challenges: First, while full histogram circuits are simple to implement and can retain complete information, the storage resources required are exponentially related to the accuracy of the time-division multiplexing (TDC) (number of timestamp bits). In high-precision TDC applications, the circuit area overhead becomes unacceptable. Second, scaling histogram circuits (such as the two-step histogram method) compress storage area by reducing data dimensionality, but inevitably lead to a decrease in system frame rate and laser energy utilization. More importantly, to address the false peak detection problem at coarse interval boundaries caused by data compression, such methods often require the introduction of complex auxiliary circuits, consuming additional resources beyond the "saved" storage space.

[0005] In summary, how to effectively compress the histogram circuit area while simultaneously solving the inherent problems of low frame rate, poor energy efficiency, and unreliable boundary peak detection in traditional scaling architectures has become a technical bottleneck that urgently needs to be overcome in this field. Summary of the Invention

[0006] The problem this invention aims to solve is to propose an on-chip histogram circuit for SPAD array detection imaging. While reducing the circuit storage area by using a scaled histogram, it overcomes the peak detection problem of incorrectly selecting coarse peaks when the actual peak falls at the boundary of a coarse interval. It correctly selects the interval where the actual peak is located by utilizing the binary codeword characteristics of the timestamp. Simultaneously, it leverages the spatial continuity of moving objects in detection imaging, where the previous coarse peak code is often the same as the next coarse peak code. Based on the position of the actual peak in the coarse interval, it determines the next histogram operating mode for that pixel, thereby improving the average output frame rate of the scaled histogram circuit and reducing the average power consumption per frame output.

[0007] This invention adopts the following technical solution: an on-chip histogram circuit for SPAD array detection imaging, comprising:

[0008] The serial-to-parallel conversion module and decoder module include shift registers and combinational logic gates. They receive and process serial timestamp data streams from the front-end TDC circuit. First, the serial data is converted into parallel data by the serial-to-parallel conversion unit. Then, the decoder unit converts and maps the parallel codewords according to specific combinational logic, translating them into the standardized data format required by the subsequent processing flow, and outputting them to the signal processing module.

[0009] Signal processing module: including counters and multiplexers, serving as the timing control center of the entire circuit, is used to generate and coordinate enable signals for each working stage, and control the working status and signal input of other modules; based on the processing completion signals fed back by other functional modules, this module sequentially generates control sequences including mode conversion stage, clearing stage, histogram establishment stage, peak detection stage, and peak correction and output stage.

[0010] Mode control module: Used during the system's operating mode transition phase to select the subsequent operating mode for a pixel based on the current pixel information. This module reads the current pixel information from the peak storage module and, based on the externally input pixel address signal, selects the subsequent operating mode for the pixel, generating a mode selection signal.

[0011] Histogram building module: Connected to the signal processing module, it consists of SRAM and is used to build and store timestamp histograms.

[0012] Peak storage module: This module stores peak and mode information generated by each pixel during processing, including but not limited to coarse peaks, fine peaks, secondary coarse peaks, detection failure signals, and operating mode signals. Through an optimized data encapsulation strategy, this module merges low-frequency or low-bit-width auxiliary signals with the main peak data for efficient utilization of storage resources.

[0013] Peak detection module: used to read timestamp histogram data and determine statistical peak values. Its core includes an addressing counter, a numerical comparator and a pixel counter.

[0014] The peak correction and output module is used to correct and fuse coarse and fine peak data according to different histogram patterns, and output the peak value and timestamp. The core of this module is a state machine, which is responsible for coordinating the entire correction and output process.

[0015] As a preferred option, to adapt to working environments with different photon detection rates, the signal processing module integrates a frame counter whose counting period can be configured externally, allowing users to flexibly set the cumulative number of frames used to construct the histogram according to the actual application scenario, thereby ensuring the reliability of the statistical results.

[0016] In addition, considering the characteristic of multi-pixel data merging and serial output in array SPAD imaging, the signal processing module also has a built-in pixel counter, which tracks pixel addresses to distinguish different pixel information from the same data stream, ensuring correct routing and synchronization of data processing.

[0017] As a preferred embodiment, the core control logic of the mode control module is implemented based on a state machine, which decides whether to start the coarse histogram establishment process or continue the fine histogram establishment process based on a mode judgment logic.

[0018] The decision condition for the pattern judgment logic is: the coarse histogram will be rebuilt only if the system does not receive an initialization signal or a detection failure signal, and the following specific conditions are met; otherwise, the fine histogram will continue to be built by default.

[0019] The specific condition refers to the following: the previously established histogram is a fine histogram, and its fine peak value is located near the boundary of the interval formed by merging the main coarse interval and the secondary coarse interval.

[0020] Furthermore, the efficient boundary judgment is implemented through a combinational logic circuit. This circuit performs logical operations based on the extended bit information of the coarse peak, the low-order binary bits of the coarse peak, and the high-order bits of the refined peak to quickly generate the boundary judgment result. The sensitivity of the boundary judgment is defined by a judgment bit number N. N represents the number of bits used to perform a 2x2 check on the merged coarse interval. N Divide the data into equal parts. When the peak value falls into the edge sub-interval of the divided data, it is determined to be near the boundary.

[0021] Specifically, N is a fixed value preset based on the maximum detection speed of the target object. Alternatively, N can be designed as an externally configurable parameter, allowing the system to flexibly balance detection speed and energy efficiency: the larger the value of N, the lower the system's adaptability to high-speed moving objects, but the higher the average frame rate and power efficiency.

[0022] Optionally, to improve system throughput, the mode control module can be configured to a pipeline working mode, which effectively reduces the overall mode switching time of multi-pixel channels by dividing the processing flow into multiple stages and having them work in parallel.

[0023] As a preferred embodiment, the histogram building module includes a capacity of It includes an SRAM memory, an address counter for SRAM initialization and clearing, and several data selectors.

[0024] Among them, parameters , The number of pixels corresponding to one TDC output channel; parameter The bit width allocated to the coarse / fine timestamp; parameter The storage depth of SRAM depends primarily on the cumulative frame count of TDC and the maximum detection rate of SPAD under strong light, which together determine the statistical reliability of the histogram.

[0025] Furthermore, the histogram building module operates throughout the clearing phase, the histogram building phase, and the peak detection phase. In the clearing phase, the address counter traverses all SRAM addresses and performs a clearing operation; in the histogram building phase, the module updates the count value of the corresponding SRAM address based on the input timestamp data; in the peak detection phase, the module outputs the stored histogram data to the peak detection module for use by the peak-finding algorithm.

[0026] Furthermore, to address the issue of false peak detection in the coarse histogram, this invention employs a timestamp bit-width extension technique. Given that the peak values ​​of the TDC histogram typically exhibit a normal distribution with a small standard deviation, they will not span more than two coarse intervals within a reasonable range. Therefore, the bit width of the fine timestamp should be extended to higher bits to cover a wider range for peak confirmation; simultaneously, to maximize SRAM utilization efficiency, the bit widths of the coarse and fine timestamps should be kept as consistent as possible.

[0027] Specifically, for a bit width of The allocation rules for the coarse / fine timestamp bit width B of the TDC raw timecode are as follows:

[0028] like If it is an odd number, then ;

[0029] like If it is even, then .

[0030] Furthermore, the two-step scaling histogram method described in this invention can be extended to multi-step scaling architectures. In application scenarios where frame rate requirements can be further relaxed and chip area requirements are more stringent, an S-step scaling histogram method (where S is an integer greater than 2) can be used. In this case, the bit width B is calculated as follows: Let T be not less than ( The smallest integer that is divisible by S is... This extended approach retains the core false positive prevention mechanism while offering a more flexible trade-off between performance and cost.

[0031] As a preferred embodiment, the peak storage module includes two SRAMs and corresponding data selection logic:

[0032] The first SRAM has a storage structure size of [size missing]. This is used to store coarse and fine peak values. In some applications, the coarse peak value is converted into a 1-bit flag bit and is preferably appended to the least significant bit of the coarse peak value data; the detection failure signal is used as a 1-bit status bit and is preferably appended to the least significant bit of the fine peak value data.

[0033] The second SRAM has a storage structure size of [size missing]. It is used to store the working mode signal of each pixel.

[0034] It should be noted that the above-described data splicing position and storage allocation method are merely one example of implementing the present invention. Without departing from the core idea of ​​the present invention, the storage positions of the secondary coarse peak flag, the detection failure signal, and the mode signal can be combined and adjusted in various ways. For example, the detection failure signal can also be stored together with the mode signal in the second SRAM and represented by expanding its data bit width; or, the data splicing can occur in the high bit or middle bit of the data word.

[0035] As a preferred embodiment, the peak detection module traverses the address space of the histogram SRAM using the addressing counter, distinguishes the currently processed pixel sequence using the pixel counter, and compares the count values ​​corresponding to adjacent addresses sequentially using a numerical comparator. The comparator continuously retains and updates the largest values ​​and addresses encountered until the entire histogram is scanned, thereby locating and outputting the peak information of each pixel.

[0036] Furthermore, since the present invention adopts an architecture in which multiple pixels share the same SRAM, the pixel counter is used to distinguish the currently processed pixel sequence, ensuring that the peak finding operation can be correctly associated with the corresponding pixel unit.

[0037] Furthermore, to avoid statistical unreliability issues caused by insufficient accumulated frames, the peak detection module also integrates a peak validity judgment mechanism. A configurable peak threshold is preset within the module, and the finally found peak value is compared with this threshold: if the peak value is higher than or equal to the threshold, it is determined to be a valid detection, and normal peak data is output; if the peak value is lower than the threshold, it is determined to be a detection failure, and a detection failure signal is output to the mode control module. This detection failure signal will prevent the circuit from outputting data and re-establish a coarse histogram in the next cycle.

[0038] Furthermore, the peak threshold can be configured according to different environmental noise levels and application scenarios to ensure the accuracy of its judgment. In some applications, the threshold is preset to a fixed value during circuit manufacturing to simplify design and reduce area overhead; in other applications, the threshold can be set as a parameter configured by external signals or registers, thereby giving the system the ability to dynamically adjust the detection sensitivity according to the actual working environment, enhancing its adaptability and robustness in different application scenarios.

[0039] As a preferred embodiment, the peak correction and output module performs the following correction logic:

[0040] When the mode signal read from the peak storage module indicates a coarse histogram mode, the module selects the peak with a larger count value that is adjacent to the main coarse peak from the histogram data as the secondary coarse peak and writes the secondary coarse peak information back to the peak storage module.

[0041] When the read mode signal indicates a fine histogram mode, this module performs a crucial true coarse peak discrimination operation: comparing the most significant bit of the fine timecode with the least significant bit of the coarse timecode; if they match, the primary coarse peak is determined to be a true coarse peak; if they do not match, the secondary coarse peak is determined to be a true coarse peak. Finally, the discerned true coarse peak timecode is concatenated with the fine peak timecode to generate and output a complete high-precision timestamp.

[0042] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects:

[0043] 1. Based on the characteristic that the peak value of the TDC histogram exhibits a normal distribution with a small standard deviation, this invention proposes a specific codeword expansion rule and collaborative correction mechanism: by providing different bit width allocation formulas for odd and even bit widths and ensuring that the coarse and fine time code bit widths are consistent to optimize storage efficiency, and combined with the true and false coarse peak discrimination logic of the peak correction module, a complete solution is formed. Without introducing a large amount of additional area overhead, it accurately solves the problem of erroneous peak finding caused by the actual peak value at the coarse peak boundary, and realizes the correct detection of the circuit across the entire range.

[0044] 2. Based on the spatiotemporal continuity characteristics of actual moving objects, this invention retains the high-bit coarse time code that does not change frequently to the next frame, and only performs fine histogram establishment most of the time, which significantly reduces the amount of data processing per frame, thereby effectively improving the output frame rate and energy utilization of the circuit, enabling the system to achieve the same imaging effect with fewer laser detections. Attached Figure Description

[0045] Figure 1 This is a block diagram of the on-chip histogram circuit system of the present invention;

[0046] Figure 2 This is a flowchart of the on-chip histogram circuit of the present invention;

[0047] Figure 3 This is a schematic diagram of a mode-switching combinational logic circuit according to an embodiment of the present invention;

[0048] Figure 4 This invention presents an example of pixel-shared SRAM.

[0049] Figure 5 This is a schematic diagram of a peak detection module according to an embodiment of the present invention;

[0050] Figure 6 This is a schematic diagram of object detection information detection according to an embodiment of the present invention;

[0051] Figure 7 This is a schematic diagram of a peak correction and output module according to an embodiment of the present invention;

[0052] Figure 8 This is a schematic diagram of the coarse peak boundary problem in traditional scaled histograms. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the application will be further described in detail below with reference to the accompanying drawings. The described embodiments are only a part of the embodiments involved in this invention. All non-innovative embodiments based on these embodiments by other researchers in the art are within the protection scope of this invention. Furthermore, the step numbers in the embodiments of this invention are only set for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0054] In one embodiment of the present invention, taking an imaging system for SPAD dToF as an example, a two-step scaling histogram method is employed to achieve a smaller storage area by using a longer counting cycle. The system parameters are configured as follows: the TDC timestamp width is 13 bits, the SPAD pixel array size is 4×8, meaning one front-end output channel corresponds to 32 pixels. The boundary judgment bit width is set to 2, and the cumulative frame count configured externally to the peak counter is 256 frames.

[0055] like Figure 1 As shown, the histogram circuit provided in this embodiment includes eight core functional modules: a serial-to-parallel conversion module, a decoder module, a signal processing module, a mode control module, a histogram building module, a peak storage module, a peak detection module, and a peak correction and output module. These modules cooperate with each other through carefully designed control signals and data paths to form a complete histogram statistics and peak extraction processing chain.

[0056] The circuit operation in this embodiment is as follows: Figure 2 As shown, the complete operation sequence consists of the following five consecutive working stages:

[0057] During the mode switching phase, the mode control module decides and switches the coarse / fine operating mode of the circuit based on the processing results of the previous cycle and the current input signal, and stores the corresponding mode signal in the peak storage module.

[0058] After entering the clearing stage, the SRAM memory inside the circuit performs address-by-address clearing operations under the control of the address counter. The SRAM in the histogram building module is the main target of clearing, which prepares for the new round of histogram building.

[0059] In the subsequent histogram building stage, the circuit accumulates and counts the corresponding addresses in the SRAM of the histogram building module based on the input TDC timestamp data, and gradually builds the statistical histogram of timestamps.

[0060] When entering the peak detection stage, the peak detection module reads the established histogram data, accurately locates the peak position through the peak finding algorithm, and judges whether the histogram has statistical significance based on the preset peak threshold. If the peak is valid, the peak data is output; if invalid, a detection failure signal is generated.

[0061] Finally, in the peak correction and output stage, this module is responsible for finding the secondary coarse peak adjacent to the main coarse peak in coarse histogram mode, providing key data for subsequent boundary correction; in fine histogram mode, it distinguishes between true and false coarse peaks through the logical relationship between fine timecode and coarse timecode, and finally splices the identified true coarse peak timecode with the fine peak timecode to output a complete and accurate high-precision timestamp.

[0062] Specifically, in the mode conversion stage, to effectively improve the data output frame rate of the scaling histogram and significantly enhance the utilization efficiency of laser energy, this embodiment proposes a conditional mode preservation strategy. The core of this strategy is that when certain conditions are met, the system retains the coarse timecode of the previous frame and only updates the fine timecode. Thus, in most work cycles, the system does not need to repeatedly build both the complete coarse and fine histograms; it only needs to build the fine histogram once to obtain an effective timestamp output, thereby significantly improving processing efficiency.

[0063] The determination of the above specific conditions is based on the principle of interval merging and segmentation. Specifically, the system merges the primary coarse peak interval and the secondary coarse peak interval obtained in subsequent processes into a unified coarse interval, and then performs 2... N Divide into equal parts, where N is a configurable number of bits for judgment, and the judgment is based on the first N bits of the peak value.

[0064] The conditional mode switching strategy is implemented through a mode control module, which is essentially a state machine controlled by a counter. It reads the coarse time code, fine time code, working mode signal and object detection information from the peak storage module and makes mode switching judgments through a dedicated combinational logic circuit.

[0065] In this embodiment, the number of bits N is set to 2, so the two highest bits of the timing code are used as the discrimination bits. The specific combinational logic judgment mechanism is as follows: Figure 3 As shown: First, the least significant bit of the main coarse peak timecode, addr_cpk_0, is XORed with the 1-bit secondary coarse peak position information, cpk_lorr, to determine the theoretical value combination ("00", "11" or "01", "10") of the first two bits of the fine timecode at the boundary. Simultaneously, the first two bits of the fine timecode, addr_fpk_6 and addr_fpk_5, are XORed to determine their actual relationship. Finally, the output of this combinational logic follows these rules: when the initialization signal generated by an external reset is valid, or the object detection information det_nothing indicates detection failure, or the fine peak value is determined to be in the boundary region, the pixel is forced to enter coarse histogram mode; otherwise, it always enters fine histogram mode.

[0066] Once the mode information is stored, the mode control module will pull the initialization signal low and send an acknowledgment signal back to the signal processing module. The signal processing module responds to this signal, and the control circuit system transitions from the mode switching phase to the reset phase.

[0067] Specifically, during the zeroing phase, the circuit performs a complete zeroing of the SRAM used to store timestamp statistics in the histogram building module, while selectively zeroing the SRAM in the peak value storage module. This selective zeroing operation clears the transient data (including fine peak values) from the previous working cycle while retaining the coarse time code and coarse-to-fine conversion mode signal as reference information. The zeroing operation is implemented through a dedicated address counter, which cyclically generates all addresses of the SRAM and writes data that is fixed to zero to the corresponding address, completing the address-by-address zeroing of the target storage area.

[0068] Once all specified SRAM regions have been cleared, the relevant modules send a clearing completion signal to the signal processing module. Based on this signal, the signal processing module controls the circuit to enter the histogram creation stage.

[0069] Specifically, during the histogram creation phase, the frame counter and pixel counter within the signal processing module are activated. The frame counter's counting period is externally configured to 256 frames to control the cumulative scale of a single histogram statistical analysis. The pixel counter's operating mode is configured based on the type of the connected front-end TDC: for a standard single-echo TDC, the pixel counter increments the pixel address once for each external write input signal; while for a multi-echo TDC, the pixel counter increments the pixel address only after accumulating M external write input signals (M being the number of multi-echo signals).

[0070] This module outputs a 12-bit pixel time code to the histogram building module through a data selector. The high 5 bits of this time code come from the pixel address generated by the pixel counter, and the low 7 bits are dynamically selected according to the working mode: in coarse histogram mode, it is taken from the high 7 bits of the 13-bit original timestamp input by TDC, and in fine histogram mode, it is taken from its low 7 bits.

[0071] Meanwhile, the module integrates a timing filtering logic that ensures that a valid SRAM write enable signal is generated only when the input data is determined to be valid and the high 7 bits (i.e., the coarse time code part) of the TDC input timestamp in the fine histogram mode are determined by subsequent processes to be within the range of the merged coarse interval specified by the peak storage module.

[0072] The core storage unit of the histogram building module is an SRAM, the capacity of which is given by formula 2. (A+B) ×C determines the value. In this embodiment, parameter A = log232 = 5, and parameter B is calculated using the formula B = T / S, where T is not less than (N... TDC The smallest integer N that is divisible by S (+S-1) is found in N. TDC Given =13 and S=2, we can get B=7. The parameter C is configured to 10 according to system requirements.

[0073] It should be noted that when the histogram circuit adopts a full-custom circuit design, the area optimization advantage of the scheme of multiple pixels sharing a single SRAM is not very significant. However, in practical applications where SRAM IP cores are widely used, the peripheral circuits of the SRAM (such as decoders, sensitive amplifiers, control logic, etc.) can bring considerable area overhead. This invention addresses this issue by... Figure 4 The architecture shown, in which multiple pixels share the same SRAM, allows the fixed area overhead to be distributed among all shared pixels, thereby significantly improving the chip's integration and area utilization at the system level. This advantage is particularly prominent in large-scale pixel arrays.

[0074] Once the timestamp histogram is established, the histogram establishment module sends an establishment completion signal to the signal processing module, which then controls the circuit to enter the peak detection stage.

[0075] Specifically, during the peak detection phase, the peak detection module activates its internal peak-finding counter and pixel counter to perform a pixel-by-pixel histogram peak search operation. In this embodiment, the peak-finding counter's counting period is configured to 128, and the pixel counter's counting period is configured to 32.

[0076] The peak detection process employs a lookup-by-lookup and dynamic comparison mechanism, the specific process of which is as follows: Figure 5 As shown, the peak-finding counter sequentially generates query addresses for the histogram SRAM and reads the histogram count value at the corresponding address. Upon the first read, the count value and its corresponding address are stored in the value register and peak address register, respectively. For subsequent addresses, the module uses a value comparator to compare the currently read count value with the value stored in the value register in real time. If the current count value is larger, the value comparator triggers update logic, overwriting the original register contents with the current value and its address. Through this mechanism, the register ultimately stores the maximum value and its precise location in the pixel's histogram. Once the peak-finding process for a single pixel is complete, the pixel counter automatically increments by 1, and the module then begins performing the same peak-finding operation on the next pixel.

[0077] In terms of the addressing mechanism, the complete address for accessing SRAM is formed by concatenating the high 5 bits of the pixel counter (pixel address) and the low 7 bits of the peak finding counter (historical cell address within the pixel), thereby enabling peak finding by traversing all 32 pixels.

[0078] This module also integrates object detection information to address application scenarios with insufficient signal statistics or unreliable data. For weak signal scenarios, when low laser intensity results in insufficient effective returned photons, the module compares the final peak count with a preset threshold using a judgment logic: if the peak value is below the threshold, the detection is deemed invalid, and a detection failure signal is output, thereby masking the histogram output of the current frame and preventing erroneous data from affecting subsequent processing.

[0079] For edge detection and noise interference scenarios, considering that the coarse timecode preservation technique used in this invention may not work in some extreme cases (such as... Figure 6 The scenario shown (where objects rapidly enter and exit) results in erroneous timecodes being retained. This detection function provides two reliability assurance mechanisms: one is to determine whether the percentage of the coarse peak count value relative to the total effective data of the current frame reaches a preset threshold to confirm its statistical significance; the other is to enable a timed refresh mechanism to force periodic output of detection failure signals to trigger the system to reset to coarse counting mode, effectively clearing erroneous coarse timecodes and ensuring that the system can reliably recover from abnormal states.

[0080] Once all pixels have completed peak finding, the peak detection module sends a peak finding completion signal to the signal processing module, which then controls the circuit to enter the peak correction and output stage.

[0081] Specifically, in the peak correction and output stage, such as Figure 7 The peak correction and output module shown is the core processing unit. Its main function is to prevent false peak detection caused by the actual peak value falling into the coarse interval boundary. This error situation is as follows: Figure 8 As shown. The core of this module is a state machine controlled by a modulo-8 counter, which performs different correction operations based on the coarse and fine mode information read from the peak storage module.

[0082] Given that the peak values ​​of the TDC histogram typically exhibit a normal distribution with a small standard deviation, they will not span more than two coarse intervals within a reasonable range. Therefore, even if the actual peak value is at the boundary, the complete normal distribution exhibited by the target object is sufficient to be encompassed by two coarse intervals, namely, the interval of the main coarse peak with the largest count value and the interval of the second coarse peak with the largest count value among the two intervals adjacent to the main coarse peak. In coarse histogram mode, this module reads the time address code of the main coarse peak from the peak value storage module and uses this address code to find and determine the second coarse peak from the timestamp histogram data.

[0083] In the fine histogram mode, this module achieves correct codeword concatenation through a set of combinational logic circuits. As previously mentioned in the histogram establishment phase, the bit width allocated to the coarse and fine timestamps is calculated using a specific formula. This design ensures that at least one bit (denoted as P bits) overlaps between the least significant bit of the coarse timestamp and the most significant bit of the fine timestamp. This means that the actual physical peak value corresponding to any fine timestamp must fall within the same coarse interval, where the P bits after the coarse timestamp and the P bits before the fine timestamp are the same.

[0084] In the specific implementation of the 13-bit TDC timecode in this embodiment, the discrimination logic is as follows: when the highest bit of the refined timecode is the same as the lowest bit of the main coarse peak timecode, it is determined that the actual peak value is located within the main coarse peak interval, and the main coarse peak is the true coarse peak. At this time, the refined timecode and the main coarse peak timecode are concatenated and output. When the two are different, it is determined that the actual peak value is located within the secondary coarse peak interval, and the secondary coarse peak is the true coarse peak. At this time, the refined timecode and the secondary coarse peak timecode are concatenated and the final correct timestamp is output.

[0085] Furthermore, to significantly optimize storage space, this invention compresses the storage method for the secondary coarse peak. Based on the spatial characteristic that the secondary coarse peak must be adjacent to the primary coarse peak on the time axis, that is, its position can only be located to the left (corresponding to a time code minus one) or to the right (corresponding to a time code plus one) of the primary coarse peak, this invention converts the complete secondary coarse peak information into a 1-bit relative position flag for storage.

[0086] Specifically, this 1-bit flag defines the positional relationship between the secondary coarse peak and the primary coarse peak. In the circuit implementation, when the secondary coarse peak is detected, the module uses simple logic to encode its address relationship with the primary coarse peak as a single bit (e.g., defining "0" for the left and "1" for the right), and stores this flag in the peak storage module. In scenarios requiring the recovery of the complete information of the secondary coarse peak, the circuit can reconstruct the complete address of the secondary coarse peak in real time using a simple addition or subtraction logic based on the address of the primary coarse peak and this 1-bit flag.

[0087] By using the above method, the present invention avoids allocating a complete storage space for the coarser peak, thereby saving the SRAM capacity required for the peak storage module and improving the chip's area utilization efficiency.

[0088] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An on-chip histogram circuit for SPAD array detection imaging, characterized in that, include: Serial-to-parallel conversion module and decoder module: including shift registers and combinational logic gates, receiving serial timestamp data stream from the front-end TDC circuit, converting serial data into parallel data, and outputting standardized data to the signal processing module; Signal processing module: includes counters and multiplexers, used to generate and coordinate enable signals for each working stage, and control the working status and signal input of other modules; Mode control module: This is a state machine that reads the current pixel information from the peak storage module and selects the subsequent working mode of the pixel based on the externally input pixel address signal, generating a mode selection signal. Histogram building module: Connected to the signal processing module, it consists of SRAM and builds and stores timestamp histograms; Peak storage module: Stores peak information and mode information generated by each pixel during processing, including coarse peak, fine peak, second coarse peak, detection failure signal and working mode signal; Peak detection module: used to read timestamp histogram data and determine statistical peak values, including an addressing counter, a numerical comparator and a pixel counter; Peak correction and output module; This tool is used to correct and fuse coarse and fine peak data using a state machine based on different histogram patterns, and output the peak value and timestamp.

2. The on-chip histogram circuit according to claim 1, characterized in that, The signal processing module, based on the processing completion signals received from each module, sequentially generates a control sequence including a mode conversion stage, a zeroing stage, a histogram establishment stage, a peak detection stage, and a peak correction and output stage.

3. The on-chip histogram circuit according to claim 2, characterized in that, The signal processing module integrates a frame counter and a pixel counter; The frame counter, with a counting period configured by the user, is used to accumulate the number of frames for constructing the histogram; The pixel counter distinguishes different pixel information from the same data stream by tracking pixel addresses.

4. The on-chip histogram circuit according to claim 1, characterized in that, The mode control module is configured to work in pipeline mode. The state machine decides whether to start the coarse histogram building process or continue the fine histogram building process based on the mode judgment logic. The decision condition of the pattern judgment logic is as follows: the coarse histogram establishment process is triggered if and only if the system does not receive an initialization signal or a detection failure signal, and the following specific conditions are met; otherwise, the fine histogram establishment process continues. The specific condition is that the previously established histogram is a fine histogram, and its fine peak value is located within the boundary range of the interval formed by merging the main coarse interval and the secondary coarse interval.

5. The on-chip histogram circuit according to claim 4, characterized in that, The boundary range determination is achieved through combinational logic circuits, which perform logical operations based on the extended bit information of the coarse peak value, the low-order binary bits of the coarse peak value, and the high-order bits of the fine peak value to generate the boundary determination result. The sensitivity of boundary judgment is defined by the number of judgment bits N, where N represents the number of bits to be used to judge the merged coarse interval. N Divide into equal parts. When the peak value falls into the edge sub-interval of the divided part, it is determined to be within the boundary range.

6. The on-chip histogram circuit according to claim 1, characterized in that, The histogram building module includes a capacity of The system includes an SRAM memory, an address counter for SRAM initialization and clearing, and several data selectors; among which, the parameters... , This represents the number of pixels corresponding to one TDC output channel. The bit width allocated to coarse / fine timestamps; The storage depth of SRAM depends on the cumulative frame count of TDC and the maximum detection rate of SPAD under strong light. The histogram building module performs the following steps: in the clearing phase, it traverses the SRAM address using an address counter and performs a clearing operation; in the histogram building phase, it updates the count value of the corresponding SRAM address based on the input timestamp data; and in the peak detection phase, it outputs the stored histogram data to the peak detection module.

7. The on-chip histogram circuit according to claim 6, characterized in that, The histogram building module adopts... Step-by-step scaling histogram method ; The bit width of the precise timestamp is extended to the higher bits using a timestamp bit width extension method.

8. The on-chip histogram circuit according to claim 6, characterized in that, The peak storage module includes two SRAMs and corresponding data selection logic; the size of the first SRAM storage structure is [size missing]. The first SRAM is used to store coarse and fine peak values; the second SRAM storage structure has a size of [missing information]. It is used to store the working mode signal of each pixel.

9. The on-chip histogram circuit according to claim 1, characterized in that, The peak detection module traverses the address space of the histogram SRAM through the addressing counter, distinguishes the currently processed pixel sequence through the pixel counter, and compares the count values ​​corresponding to adjacent addresses sequentially through the numerical comparator. It continuously retains and updates the largest value and address encountered until the scanning of the entire histogram is completed, and locates and outputs the peak information of each pixel. The peak detection module has a preset configurable peak threshold. If the peak value found is higher than or equal to the peak threshold, it is determined to be a valid detection and normal peak data is output. If the peak value found is lower than the peak threshold, the detection is determined to be a failure and a detection failure signal is output to the mode control module.

10. The on-chip histogram circuit according to claim 9, characterized in that, The peak correction and output module has the following correction logic: When the mode signal read from the peak storage module is a coarse histogram mode, the peak value that is adjacent to the main coarse peak value and has a larger count value is selected from the histogram data as the secondary coarse peak value, and the information of the secondary coarse peak value is written back to the peak storage module. When the read mode signal is the fine histogram mode, the true coarse peak discrimination operation is performed: the highest bit of the fine time code is compared with the lowest bit of the coarse time code. If they match, the main coarse peak is determined to be the true coarse peak. If they do not match, the secondary coarse peak is determined to be the true coarse peak. The identified coarse peak timecode and fine peak timecode are concatenated to generate and output a complete timestamp.

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