Task processing method and system, electronic device, and storage medium

Abstract

The present disclosure provides a task processing method and system, an electronic device, and a storage medium, which are applied to a front-end unit in a graphics processor. The front-end unit includes an instruction execution unit, an instruction acquisition unit, and a plurality of counters. The method includes: acquiring, by the instruction acquisition unit, a target loop execution task generated by a central processing unit; assigning a value to a target counter and executing instructions in an instruction queue of the target loop execution task in sequence from an (i+1)th instruction, by the instruction execution unit, in a case where it is determined that an ith instruction is a loop start instruction; and determining whether a loop end condition is met according to a current value of the target counter in a case where it is determined that an (i+j)th instruction is a loop end judgment instruction, and jumping to the (i+1)th instruction and continuing loop execution until the loop end condition is met. According to embodiments of the present disclosure, the task processing efficiency can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a task processing method and system, electronic device, and computer-readable storage medium. Background Technology

[0002] With the continuous development of computer technology, computers can be used in various business scenarios to perform corresponding tasks, thereby meeting the needs of practical applications.

[0003] For tasks that need to be executed repeatedly, related technologies often generate multiple tasks and send them to the task processing system for execution. In this process, the storage and transmission of multiple tasks consume a lot of computer resources and reduce the efficiency of task processing. Therefore, how to improve task processing efficiency and save computer resources has become an urgent problem to be solved. Summary of the Invention

[0004] This disclosure provides a task processing method, a task processing system, an electronic device, and a computer-readable storage medium.

[0005] In a first aspect, this disclosure provides a task processing method for a front-end unit in a graphics processing unit (GPU). The front-end unit includes an instruction execution unit, an instruction fetching unit, and multiple counters. The method includes: using the instruction fetching unit to obtain a target loop execution task generated by a central processing unit (CPU), wherein the instruction queue of the target loop execution task includes a loop start instruction, a task execution instruction, and a loop end judgment instruction; during the execution of the instruction queue by the instruction execution unit, if the i-th instruction is determined to be a loop start instruction to be executed, determining the target loop execution task from the multiple counters based on the counter index value and the initial value of the counter in the i-th instruction. A counter is set and a target counter is assigned a value; i is an integer greater than or equal to 1; using the instruction execution unit, the instructions in the instruction queue are executed sequentially starting from the (i+1)th instruction; using the instruction execution unit, if it is determined that the (i+j)th instruction is a loop termination judgment instruction to be executed, the loop termination condition is determined based on the comparison value in the (i+j)th instruction and the current value of the target counter; j is an integer greater than 1; using the instruction execution unit, if the loop termination condition is not met, the current value of the target counter is updated, and the execution jumps to the (i+1)th instruction, and the instructions in the instruction queue are executed sequentially starting from the (i+1)th instruction.

[0006] Secondly, this disclosure provides a task processing system, which includes a graphics processing unit (GPU) and a front-end unit. The front-end unit includes an instruction execution unit, an instruction fetching unit, and multiple counters. The instruction fetching unit is configured to: fetch a target loop execution task generated by a central processing unit (CPU), wherein the instruction queue of the target loop execution task includes a loop start instruction, a task execution instruction, and a loop end judgment instruction. The instruction execution unit is configured to: during the execution of the instruction queue, if it is determined that the i-th instruction is a loop start instruction to be executed, determine the loop start instruction based on the counter index value in the i-th instruction and... The initial value of the counter is determined from the plurality of counters, and the target counter is assigned a value; i is an integer greater than or equal to 1; starting from the (i+1)th instruction, the instructions in the instruction queue are executed sequentially; if the (i+j)th instruction is determined to be a loop termination judgment instruction to be executed, the loop termination condition is determined based on the comparison value in the (i+j)th instruction and the current value of the target counter; j is an integer greater than 1; if the loop termination condition is not met, the current value of the target counter is updated, and the process jumps to the (i+1)th instruction, and the instructions in the instruction queue are executed sequentially starting from the (i+1)th instruction.

[0007] Thirdly, this disclosure provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, the one or more computer programs being executed by the at least one processor to enable the at least one processor to perform the above-described task processing method.

[0008] Fourthly, this disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the above-described task processing method.

[0009] The task processing method provided in this disclosure is applied to a front-end unit in a graphics processing unit. The front-end unit includes an instruction execution unit, an instruction fetching unit, and multiple counters. During task processing, the instruction fetching unit acquires a target loop execution task generated by the central processing unit. The instruction queue of the target loop execution task includes a loop start instruction, a task execution instruction, and a loop end judgment instruction. The instruction execution unit executes the instruction queue. During the execution of the instruction queue, if the i-th instruction is determined to be a loop start instruction to be executed, a target counter is determined from multiple counters and assigned a value based on the counter index value and initial counter value in the i-th instruction. Then, the instructions in the instruction queue are executed sequentially starting from the (i+1)-th instruction. If the (i+j)-th instruction is determined to be a loop end judgment instruction to be executed, it is determined whether the loop end condition is met. If the loop end condition is not met, the execution jumps to the (i+1)-th instruction and continues to execute the (i+1)-th instruction, thereby achieving loop execution of instructions. In this process, since the present disclosure can execute the instructions in the instruction queue in a loop, it achieves the effect and purpose of executing multiple tasks by executing one target in a loop, thereby improving task processing efficiency and avoiding the problem of consuming a lot of computer resources when storing and transmitting multiple tasks, thus saving computer resources.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0011] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed exemplary embodiments described with reference to the accompanying drawings.

[0012] Figure 1 A flowchart of a task processing method provided in an embodiment of this disclosure.

[0013] Figure 2 This is a schematic diagram of the GPU front end in a task processing method provided in an embodiment of this disclosure.

[0014] Figure 3 This is a schematic diagram of a command encoding format in a task processing method provided in an embodiment of the present disclosure.

[0015] Figure 4 This is a schematic diagram of a loop start command in a task processing method provided in an embodiment of this disclosure.

[0016] Figure 5 This is a flowchart of a loop start command in a task processing method provided in an embodiment of the present disclosure.

[0017] Figure 6 This is a schematic diagram of a loop termination judgment instruction in a task processing method provided in an embodiment of the present disclosure.

[0018] Figure 7 This is a schematic diagram illustrating the determination of whether to execute a loop termination judgment instruction in a task processing method provided in an embodiment of this disclosure.

[0019] Figure 8 This is a schematic diagram illustrating the execution of a loop termination judgment instruction in a task processing method provided in an embodiment of the present disclosure.

[0020] Figure 9 This is a schematic diagram of a set-view-id command in a task processing method provided in an embodiment of this disclosure.

[0021] Figure 10 This is a schematic diagram of another set-view-id command in a task processing method provided in an embodiment of this disclosure.

[0022] Figure 11 This is a block diagram of a task processing system provided in an embodiment of the present disclosure.

[0023] Figure 12 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0024] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0025] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0026] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, they specify the presence of features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0028] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0029] The task processing method according to embodiments of this disclosure can be executed by an electronic device such as a terminal device or a server. The terminal device can be an in-vehicle device, user equipment (UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (PDA), handheld device, computing device, in-vehicle device, wearable device, etc. The method can be implemented by a processor calling computer-readable program instructions stored in memory. Alternatively, the method can be executed by a server.

[0030] The technical terms used in the embodiments of this disclosure are explained below.

[0031] View-Instance: refers to multiple views.

[0032] Multi-View Rendering refers to the rendering of the same scene from two different perspectives (left eye and right eye) in virtual reality (VR) or stereoscopic 3D rendering. The image rendered from each perspective is called a View, and the rendering process of each View is almost exactly the same, except that the perspective parameters are different.

[0033] View-id: is an integer number (such as 0, 1, 2, etc.) used to identify which "view" or "perspective" is currently being rendered. This View-id can also be written as View id.

[0034] The GPU front-end is a crucial component of the graphics processing unit (GPU) architecture, playing a vital role in the GPU's overall pipeline, acting as a "command and scheduler" and "task distributor." This GPU front-end, also known as the GPU's front-end unit, is a hardware module that performs operations such as instruction fetching, decoding, scheduling, and initial data preparation within the GPU, providing executable threads or instruction packages to downstream back-end execution units. Examples of back-end execution units include, but are not limited to, Streaming Multiprocessors (SMs) and Execution Units (EUs).

[0035] With the continuous development of computer technology, computers can be used in various business scenarios to perform corresponding tasks, thereby meeting the needs of practical applications.

[0036] For tasks that need to be executed repeatedly, related technologies often generate multiple tasks and send them to the task processing system for execution. In this process, storing multiple tasks requires a lot of storage resources, and transmitting multiple tasks requires a lot of transmission resources. Therefore, storing and transmitting multiple tasks consumes a lot of computer resources and reduces the efficiency of task processing.

[0037] Specifically, for command streams that need to be executed repeatedly, software (such as drivers) is often used to repeatedly issue commands multiple times. For example, in a scenario that supports multiple View-Instances, the driver first sets the view id to 0, issues and executes the drawing command; then it sets the view id to 1, issues and executes the drawing command again, and so on.

[0038] For command streams that require cyclic execution, the need to repeatedly issue commands in software incurs additional storage overhead. Furthermore, in some scenarios, the loop count for the command stream may be dynamically generated by the GPU. Since the CPU and GPU execute asynchronously, software-based solutions for cyclic command stream execution require explicit synchronization between the CPU and GPU in such scenarios. Specifically, the CPU needs to wait for the GPU to complete a specific command, obtain the loop count from the GPU, and then generate the command to be executed. This synchronization reduces GPU throughput and processing performance.

[0039] Based on this, this disclosure provides a task processing method and system, an electronic device, and a computer-readable storage medium, as detailed in the following embodiments.

[0040] Figure 1 A flowchart illustrating a task processing method provided in an embodiment of this disclosure. (Refer to...) Figure 1This method is applied to the front-end unit in a graphics processor. The front-end unit includes an instruction execution unit, an instruction fetching unit, and multiple counters. This method includes steps S11 to S15.

[0041] Step S11: Using the instruction acquisition unit, acquire the target loop execution task generated by the central processing unit, wherein the instruction queue of the target loop execution task includes a loop start instruction, a task execution instruction, and a loop end judgment instruction.

[0042] The target loop execution task can be understood as a task that needs to be executed repeatedly by the graphics processor (GPU). This target loop execution task can be retrieved from the GPU's corresponding storage unit using an instruction fetching unit. The GPU's corresponding storage unit stores data required by the GPU's front-end unit or the target loop execution task to be executed. This storage unit includes, but is not limited to, memory, video memory, cache, and databases. In some embodiments, the target loop execution task can be generated by the central processing unit (CPU) and sent to the GPU's front-end unit; the CPU can generate the target loop execution task and instruct the GPU's front-end unit to execute it repeatedly.

[0043] The instruction fetching unit can be understood as a unit in the front-end unit used to fetch or receive target loop instruction tasks. The instruction fetching unit can be a logic circuit in the front-end unit; that is, the instruction fetching unit is the front-end unit in the graphics processor, and the data transmission unit between the front-end unit and the corresponding memory unit or central processing unit, which can realize the data transmission between the front-end unit in the graphics processor and the corresponding memory unit or central processing unit.

[0044] The instruction execution unit can be understood as the unit in the front-end unit that executes the instruction queue of the target cyclic instruction task. The instruction execution unit can be a logic circuit, controller or scheduler in the front-end unit, and is used to realize the cyclic execution of the instruction according to the cyclic start instruction and cyclic end judgment instruction in the instruction queue.

[0045] In some embodiments, the instruction execution unit, the instruction fetching unit, and the multiple counters are all hardware modules of the front-end unit. The hardware module implements the processing of the target loop instruction task and obtains the task execution result. The task execution result can be understood as the result obtained by the front-end unit in the graphics processor after it has completed the instruction queue of the target loop execution task.

[0046] The instruction queue can be understood as a queue of multiple instructions arranged in the order of execution. The instructions in the instruction queue include loop start instructions, task execution instructions, and loop end judgment instructions, etc.

[0047] The loop start instruction can be understood as an instruction in the instruction queue used to mark the loop entry or the start of the loop; through this loop start instruction, it can be determined whether loop execution is required and to locate the instruction that needs to be executed in a loop; that is to say, this loop start instruction is used to implement the instruction execution unit to execute instructions in a loop.

[0048] In this context, task execution instructions can be understood as instructions in the instruction queue used to implement the target task. This target task can be set according to the actual application scenario. For example, the target task could be a multi-view rendering (MVR) task. In this case, the task execution instructions could be the view rendering instructions corresponding to the MVR task. The front-end unit in the graphics processor (GPU) executes these view rendering instructions repeatedly to obtain the multi-view rendering result (i.e., the task execution result). Another example is that the target task could be a batch processing task in neural network inference. In this case, the task execution instructions could be the batch processing instructions corresponding to the batch processing task. The front-end unit in the GPU executes these batch processing instructions multiple times in a loop to achieve multiple batch processing operations, thereby obtaining the batch processing result (i.e., the task execution result) during the neural network inference process.

[0049] The loop end judgment instruction can be understood as the instruction used in the target loop execution task to determine whether the loop has ended.

[0050] Step S12: During the execution of the instruction queue using the instruction execution unit, if the i-th instruction is determined to be the loop start instruction to be executed, a target counter is determined from the plurality of counters and assigned a value to the target counter according to the counter index value and the initial value of the counter in the i-th instruction; i is an integer greater than or equal to 1.

[0051] The counter index value can be understood as the value used to identify the target counter from multiple counters. This index value can be a value that uniquely identifies a counter. For example, the target counter index value can be the counter number of the target counter, the ID of the target counter, etc.

[0052] The initial value of the counter can be understood as the initial value required to perform the assignment operation on the target counter; that is, the value that needs to be assigned to the target counter. The initial value of the counter can be set according to the actual application scenario. For example, the initial value of the counter can be the value 0, the value 1, the value 100, the value 500, etc.

[0053] Step S13: Using the instruction execution unit, execute the instructions in the instruction queue sequentially, starting from the (i+1)th instruction.

[0054] Step S14: Using the instruction execution unit, if it is determined that the (i+j)th instruction is the loop termination judgment instruction to be executed, determine whether the loop termination condition is met based on the comparison value in the (i+j)th instruction and the current value of the target counter; j is an integer greater than 1.

[0055] The current value of the target counter can be understood as the value currently recorded or configured by the target counter. The comparison value can be a value used for comparison with the current value. The comparison value can be used to determine whether the loop termination condition is met. In other words, the comparison value can be a condition for determining whether the loop termination condition is met.

[0056] The loop termination condition can be understood as a condition used to determine whether the current loop has ended. This loop termination condition can be set according to the actual application scenario, and this disclosure does not make specific limitations in this embodiment.

[0057] Step S15: Using the instruction execution unit, if the loop termination condition is not met, update the current value of the target counter and jump to the (i+1)th instruction, and execute the instructions in the instruction queue sequentially starting from the (i+1)th instruction.

[0058] Taking the application of the task processing method provided in this disclosure in the GPU front end as an example, the task processing method will be explained and illustrated; the GPU device (graphics processor) in this disclosure includes the GPU front end (i.e., the front end unit in the graphics processor).

[0059] Figure 2 This is a schematic diagram of the GPU front-end in a task processing method provided in an embodiment of this disclosure; based on Figure 2 As can be seen, the front-end unit includes a command fetching unit (i.e., instruction fetching unit), a command execution unit (i.e., instruction execution unit), and a counter unit, which includes multiple counters. Furthermore, the GPU front-end unit of this disclosure may also include an internal loop counter, an overflow flag, and a loop threshold value. The downstream of the GPU front-end unit can be the GPU's back-end execution unit.

[0060] The command acquisition unit primarily retrieves the commands to be executed (i.e., the instruction sequence of the target cyclic execution task) provided by the central processing unit from the storage unit and sends these commands (also called instructions) to the command execution unit. In the command execution unit, the unit parses the command type according to the encoding format of each command and then executes the command based on the specific type.

[0061] A command encoding format such as Figure 3 As shown, Figure 3 This is a schematic diagram of a command encoding format in a task processing method provided by an embodiment of the present disclosure, based on Figure 3 As can be seen, the basic unit of a command can be a 32-bit (Double Word) or a 64-bit (Quad Word) command. For each command, its type is indicated by specific high-order (or low-order) bits, for example... Figure 3 The opcode is shown in the diagram. It should be noted that the commands executed by the GPU front end are usually variable-length, which means that the command execution unit needs to determine or identify the length of the command based on different opcodes.

[0062] Considering that the instructions in the target loop execution task proposed in this disclosure need to be executed cyclically, this disclosure proposes a loop start command, the format of which is as follows: Figure 4 As shown. Figure 4 This is a schematic diagram of a loop start command in a task processing method provided in this embodiment of the present disclosure, based on... Figure 4 As can be seen, the opcode of the loop start command disclosed in this paper carries the loopstart encoding, which indicates that the currently executed command or instruction is a loop start command. When the loop start command (i.e., the loop start instruction) is recognized, the GPU front-end determines that the loop start command needs to be executed according to the flow corresponding to the loop command. First, the counter index value needs to be obtained from the loop start command, and the corresponding target counter needs to be determined from the multiple counters included in the counter unit based on the counter index value; then, the initial value of the counter is obtained from the loop start command, and the initial value of the counter is assigned to the target counter.

[0063] After the target counter is assigned a value, the command execution unit of this disclosure will continue to execute commands starting from the next command after the loop start command (i.e., the (i+1)th instruction).

[0064] When the command execution unit determines that the command to be executed (i.e., the (i+j)th instruction) is a loop end judgment command (i.e., a loop end judgment instruction), it proceeds to determine whether the current loop has ended. That is, it obtains the comparison value from the loop end judgment command and obtains the current value of the target counter. Then, it determines whether the loop end condition is met by using the comparison value and the current value.

[0065] When the command execution unit determines that the loop termination condition is not met, it updates the current value of the target counter. After updating the value of the given target counter, the command execution unit needs to jump back to the instruction following the original loop start command and continue execution, thereby achieving cyclic execution of the command until the loop termination condition is met.

[0066] As can be seen from the above embodiments, the task processing method provided in this disclosure is applied to the front-end unit in a graphics processor. The front-end unit includes an instruction execution unit, an instruction fetching unit, and multiple counters. In the task processing process, the instruction fetching unit obtains a target loop execution task generated by the central processing unit. The instruction queue of the target loop execution task includes a loop start instruction, a task execution instruction, and a loop end judgment instruction. The instruction execution unit executes the instruction queue. During the execution of the instruction queue, if it is determined that the i-th instruction is a loop start instruction to be executed, the target counter is determined from multiple counters and assigned a value according to the counter index value and the initial value of the counter in the i-th instruction. Then, the instructions in the instruction queue are executed sequentially starting from the (i+1)-th instruction. If it is determined that the (i+j)-th instruction is a loop end judgment instruction to be executed, it is determined whether the loop end condition is met. If the loop end condition is not met, the execution jumps to the (i+1)-th instruction and continues to execute the (i+1)-th instruction, thereby realizing the loop execution of instructions. In this process, since the present disclosure can execute the instructions in the instruction queue in a loop, it achieves the effect and purpose of executing multiple tasks by executing one target in a loop, thereby improving task processing efficiency and avoiding the problem of consuming a lot of computer resources when storing and transmitting multiple tasks, thus saving computer resources.

[0067] In some embodiments, jumping to the (i+1)th instruction includes: using the instruction execution unit to obtain a jump address offset value from the address offset bit of the loop end judgment instruction; determining the instruction address corresponding to the (i+1)th instruction based on the jump address offset value and the instruction address of the loop end judgment instruction; jumping to the (i+1)th instruction based on the instruction address, and continuing to execute the instructions in the instruction queue sequentially starting from the (i+1)th instruction.

[0068] The address offset bit is used to store the jump address offset value; the jump address offset value can be understood as the offset value used to identify the instruction address of the (i+1)th instruction; in some embodiments, the instruction address can be understood as the instruction position or instruction line number of the (i+1)th instruction in the instruction queue.

[0069] Following the previous example, the command execution unit in the GPU front end can, after updating the current value of the target counter, jump back to the instruction following the original loop start instruction (i.e., the (i+1)th instruction) and continue executing the instructions in the instruction queue sequentially, starting from the (i+1)th instruction. To achieve accurate jumping, the loop end judgment instruction designed in this disclosure also encodes a jump address offset value. At this time, the command execution unit adds this jump address offset value to the address of the currently executed instruction (i.e., the address of the (i+j)th instruction) and uses it as the address of the next instruction to be executed (i.e., the address of the (i+1)th instruction). Then, it retrieves this instruction (i.e., the (i+j)th instruction) from the command fetching unit and continues to execute it sequentially. Through the above operations, the jumping purpose can be achieved.

[0070] It should be noted that the CPU driver needs to correctly set this jump address offset value and set it to the location to be jumped to, relative to the offset of the current loop end judgment instruction.

[0071] As can be seen from the above embodiments, this disclosure achieves precise loop body back jump by directly encoding the jump address offset in the loop end judgment instruction and combining it with the counter update operation. By directly embedding the jump address offset into the loop judgment instruction, the command execution unit only needs to perform a simple "current instruction address plus offset" operation to obtain the instruction address of the (i+1)th instruction, thereby simplifying the instruction address calculation logic and reducing the hardware area and power consumption of the front-end unit.

[0072] In some embodiments, the method further includes: using the instruction execution unit to sequentially execute the instructions in the instruction queue, starting from the (i+j+1)th instruction, when the loop termination condition is met.

[0073] Following the example above, the command execution unit of this disclosure will jump back to the next command after the loop start command and continue execution if the loop termination condition is not met. At the same time, if the loop termination condition is met, the command execution unit will determine that the current loop has ended and continue execution from the next command after the loop termination judgment command (i.e., the i+j+1th instruction).

[0074] For example, the instruction queue provided in this disclosure may include the following multiple instructions.

[0075] {……

[0076] loop_start_1 (i.e., the loop start instruction).

[0077] exec_part (the instruction following the loop start instruction).

[0078] loop_end_1 (i.e., the loop end judgment instruction).

[0079] other_part (i.e., the instruction following the loop termination condition instruction).

[0080] ...}

[0081] Based on the examples of the above instructions, when the command execution unit reaches loop_end_1, it will determine whether the loop termination condition is met. If the loop termination condition is not met, it will jump to the next instruction exec_part after loop_start_1 and continue to execute the instructions in the instruction queue in sequence. If the loop termination condition is met, it will execute the next instruction other_part after loop_end_1 (i.e., the i+j+1th instruction) in sequence until all instructions in the instruction queue have been executed.

[0082] As can be seen from the above embodiments, this disclosure automatically determines whether to perform cyclic execution of the quality control by comparing the current value of the target counter with the loop termination condition. If the condition is not met, the counter is updated and the loop continues; if the condition is met, the loop is automatically terminated, achieving automated, closed-loop instruction loop control. Using a hardware counter to determine whether the loop termination condition is met simplifies the control flow of the loop structure, ensures the accuracy and continuity of instruction queue execution, and improves the processing efficiency of the GPU.

[0083] In some embodiments, determining whether the loop termination condition is met based on the comparison value in the (i+j)th instruction and the current value of the target counter includes: using the instruction execution unit to compare the comparison value and the current value, and determining that the loop termination condition is met if the comparison fails.

[0084] Specifically, the instruction execution unit disclosed herein can perform a comparison operation between the comparison value and the current value, and determine that the loop termination condition is met if the comparison fails.

[0085] The comparison operation can be understood as a method of comparing the current value and the comparison value. It should be noted that the comparison operation between the current value and the comparison value can be set according to the actual application scenario, and this disclosure does not impose specific restrictions on it; for example, after obtaining the current value of the given target counter and the given comparison value, the command execution unit of this disclosure needs to use the comparison operation method in the loop termination judgment instruction to compare the two. The comparison operation methods proposed in this disclosure include, but are not limited to, the following types: equal to, not equal to, unsigned greater than, unsigned greater than or equal to, unsigned less than, unsigned less than or equal to, signed greater than, signed greater than or equal to, signed less than, and signed less than or equal to.

[0086] Following the previous example, the command execution unit of this disclosure, after obtaining the current value of the given target counter and the given comparison value, then compares the current value and the comparison value. If the comparison between the current value and the comparison value fails (for example, the current value is not equal to the comparison value, or the current value is signed greater than or equal to the comparison value), then the loop termination judgment instruction can be considered to have ended the loop. At this time, the instruction to be executed is set as the next instruction after the loop termination judgment instruction (i.e., the (i+j+1)th instruction).

[0087] In some embodiments, the method further includes: using the instruction execution unit to compare the comparison value with the current value, and determining that the loop termination condition is not met if the comparison passes.

[0088] Following the example above, the command execution unit of this disclosure compares the current value and the comparison value. If the comparison passes (for example, the current value is equal to the comparison value, or the current value is signed less than the comparison value), then the loop end judgment instruction here can be considered that the loop has not ended. The current value of the target counter is then updated, and the next instruction after the loop start instruction (i.e., the i+1th instruction) is executed until the loop is determined to end.

[0089] As can be seen from the above embodiments, this disclosure directly compares the comparison value with the current value through the instruction execution unit, thereby efficiently and accurately determining whether the loop termination condition is met; effectively improving the judgment efficiency, enhancing the response speed of loop control and the execution efficiency of the GPU.

[0090] In some embodiments, determining whether the loop termination condition is met based on the comparison value in the (i+j)th instruction and the current value of the target counter includes: using the instruction execution unit to compare the comparison value and the current value; if the comparison passes, updating the count value of the internal loop counter included in the front-end unit; using the instruction execution unit, if the updated count value is greater than the loop threshold value, setting the overflow flag included in the front-end unit to a valid overflow value; and using the instruction execution unit, if the current value of the overflow flag is a valid overflow value, determining that the loop termination condition is met.

[0091] The inner loop counter can be understood as a counter set in the front-end unit to count the number of iterations of the current loop. When the current loop is a single-level loop, the inner loop counter records each iteration of that single-level loop. When the current loop is a nested loop (including multi-level loops), the inner loop counter records each iteration of any loop within that nested loop.

[0092] The loop threshold can be understood as a value used to determine whether the current loop has overflowed. Specifically, if the count value of the inner loop counter is greater than the loop threshold, an overflow is determined to have occurred; if the count value of the inner loop counter is less than or equal to the loop threshold, an overflow is determined not to have occurred. It should be noted that the overflow in this disclosure can be used to indicate that the current loop has iterated too many times, which may result in an infinite loop or a loop that cannot terminate automatically.

[0093] An overflow flag can be understood as a flag used to indicate whether an overflow has occurred. The current value of the overflow flag includes a valid overflow value and an invalid overflow value. An invalid overflow value indicates that no overflow has occurred, and a valid overflow value indicates that an overflow has occurred. The invalid overflow value can be the value 0 or false; the valid overflow value can be the value 1 or true. The instruction execution unit in this disclosure can set the overflow flag to a valid overflow value when the count value of the internal loop counter is greater than the loop threshold value.

[0094] In some embodiments, the current values ​​of the loop threshold and overflow flag in this disclosure may be stored in registers in the front-end unit.

[0095] In some embodiments, the method for updating the count value of the internal loop counter included in the front-end unit can be set according to the actual application scenario. For example, the count value of the internal loop counter can be incremented by 1 or 2. This specification does not specifically limit this.

[0096] Following the previous example, according to Figure 2 As can be seen, the command execution unit of this disclosure compares the current value with the comparison value. If the comparison passes, the loop termination judgment instruction here can be considered as the loop not having ended. In this case, the command execution unit first increments the count value of the internal loop counter by 1, and then compares the incremented count value of the internal loop counter with the loop threshold value. If the count value of the internal loop counter is greater than the loop threshold value, then the number of loop executions has exceeded the set number, confirming an overflow. In this case, the command execution unit sets the overflow flag to true, and the comparison judgment operation at this time can be treated as a failure.

[0097] As can be seen from the above embodiments, this disclosure uses a loop threshold and an overflow flag to further determine whether the loop termination condition is met. When the count value of the internal loop counter is greater than the loop threshold, the current value of the overflow flag is set to a valid overflow value, and it is determined that the loop termination condition is met, thereby ensuring that the loop can terminate accurately and in a timely manner when the preset upper limit is reached, effectively preventing the loop from running out of control or becoming dead.

[0098] In some embodiments, the method further includes: using the instruction execution unit to skip instructions that do not need to be executed until the next instruction to be executed is the loop start instruction whose current value of the outermost flag is valid, wherein the instructions to be executed during the period when the current value of the overflow flag is a valid overflow value are instructions that do not need to be executed.

[0099] The outermost flag can be understood as indicating whether the loop start instruction is the loop start instruction corresponding to the outermost loop; the outermost flag includes a valid value and an invalid value; the valid value can be the value 1, and the invalid value can be the value 0; the valid value indicates that the loop start instruction is the loop start instruction corresponding to the outermost loop; the invalid value indicates that the loop start instruction is not the loop start instruction corresponding to the outermost loop.

[0100] In this context, the instructions to be executed during the period when the current value of the overflow flag is a valid overflow value are instructions that do not need to be executed. This can be understood as the instructions to be executed in the instruction queue during the period when the current value of the overflow flag of the front-end unit is set to a valid overflow value, until the loop start instruction with the current value of the outermost flag is executed.

[0101] Following the example above, in the task processing method provided in this disclosure, when it is determined that the count value of the internal loop counter is compared with a software-configured loop threshold value, and the count value exceeds the loop threshold value, the command execution unit of the front-end unit sets an overflow state to true, and sets all subsequent loop end judgment commands to end, until a loop start command is encountered in which the current value of the outermost flag is set to a valid value.

[0102] As can be seen from the above embodiments, this disclosure uses the global state of setting the overflow flag to true to uniformly control the subsequent loop termination judgment, effectively preventing loop runaway or infinite loops. Simultaneously, setting the loop execution instruction with the outermost flag as the valid value as the recovery condition ensures that the instruction execution operation of the GPU front-end unit can safely and accurately recover to the normal state, thereby improving the GPU's processing performance.

[0103] In some embodiments, the i-th instruction further includes an outermost flag, and the front-end unit further includes an overflow flag. The i-th instruction is determined to be a loop start instruction to be executed if either of the following conditions is met: the current value of the outermost flag in the i-th instruction is a valid value; or the current value of the overflow flag is an invalid overflow value. This disclosure, through the parallel conditions of the outermost flag being a valid value or the overflow flag being an invalid overflow value, can accurately determine whether the current instruction is a loop start instruction to be executed. This effectively filters out unnecessary loop start instructions, preventing loop overruns.

[0104] In some embodiments, the front-end unit further includes an internal loop counter. If the current value of the outermost flag in the i-th instruction is a valid value, the method further includes: using the instruction execution unit to reset the count value of the internal loop counter and set the current value of the overflow flag to an invalid overflow value.

[0105] The resetting of the count value of the internal loop counter includes: resetting the count value of the internal loop counter to a preset value, for example, setting the count value of the internal loop counter to the value 0, or setting the count value of the internal loop counter to the value 1.

[0106] Following the previous example, according to Figure 4 As can be seen, the loop start instruction in this disclosure has an outermost flag (this flag is used to clear the overflow flag later), an initial value of the counter, and a counter index value; Figure 5 This is a flowchart of a loop start command in a task processing method provided in this embodiment of the disclosure. When the command execution unit encounters a loop start command, its execution flow is as follows: Figure 5 As shown.

[0107] Step 1: Check its outermost markings.

[0108] Step 2: Determine if the outermost flag is true.

[0109] If the command execution unit determines that the outermost flag is true, it means that the currently executing loop start instruction is located at the outermost task of a possible nested loop. In this case, the command execution unit needs to perform step 3 to process the loop counter and overflow flag. Otherwise, it performs step 4.

[0110] Step 3: Set the overflow flag to false (i.e., invalid overflow value), reset the value of the inner loop counter to 0, and then execute step 4.

[0111] Step 4: Place the initial value of the counter into the counter specified by the counter index value.

[0112] As can be seen from the above embodiments, in the loop hardware design of related technologies, each time a loop start instruction is encountered, all loop-related states (such as overflow flags and inner loop counters) are unconditionally reset. If in a nested loop (e.g., outer loop A contains inner loop B), if the global overflow flag is reset when entering inner loop B, the state of outer loop A will be lost, thus causing a logical error (such as premature termination of the outer loop or an infinite loop). This disclosure takes this problem into consideration and solves the state management problem of GPU hardware when handling nested loops by introducing an "outermost flag" and executing conditional initialization logic accordingly. Through the outermost flag, the hardware can identify whether it is entering a completely new loop level (i.e., the outermost flag is true) or entering a nested sub-loop (i.e., the outermost flag is false); and only resets the overflow flag and inner loop counter when it is determined to be the outermost (i.e., the outermost flag is true); during the inner loop, these key states of the outer layer are retained, and only the value of the target counter required by the current layer is updated. This ensures that the control flow state of each level in a multi-layered nested loop does not interfere with each other.

[0113] In some embodiments, this disclosure provides an example of skipping instructions that do not need to be executed until the next instruction to be executed is the loop start instruction whose current value is a valid overflow value, provided that the current value of the overflow flag is a valid overflow value. Specifically, the instruction queue provided in this disclosure may include the following multiple instructions, which constitute a three-level nested loop.

[0114] {……

[0115] loop_start_1 (i.e., the outermost loop start instruction).

[0116] loop_start_2 (i.e., the loop start instruction of the second level).

[0117] loop_start_3 (i.e., the loop start instruction of the third level).

[0118] exec_part (task execution instructions).

[0119] loop_end_3 (i.e., the loop end judgment instruction of the third level).

[0120] loop_end_2 (i.e., the loop end judgment instruction of the second level).

[0121] loop_end_1 (i.e., the outermost loop end judgment instruction).

[0122] other_part (i.e., the instruction following the outermost loop termination check instruction).

[0123] loop_start_4 (i.e., the instruction to start the outermost loop of the new loop).

[0124] ...}

[0125] The overflow flag disclosed herein is to prevent loop escape. Taking the code above as an example, there are three nested loops, which are executed sequentially by the command execution unit. If a loop escape occurs during the execution of these three loops, the execution of `exec_part` will exceed the set limit. In this case, the overflow flag of the front-end unit can be set to true to indicate that an overflow has occurred. When the overflow flag is set to true, the command execution unit will skip the subsequent `loop_start_1 / 2 / 3` and `loop_end_1 / 2 / 3` loops, thus escaping the infinite loop.

[0126] Furthermore, while the overflow flag is set to true, the other_part (i.e., instructions that do not need to be executed) in the above code is skipped until the next instruction to be executed by the command execution unit is the loop start instruction (i.e., loop_start_4) where the current value of the outermost flag is valid. That is to say, this disclosure sets a special flag on loop_start_4 where the current value of the outermost flag is valid, telling the hardware that this is a brand new loop start (not the nested loop in the above code).

[0127] When the command execution unit executes looo_start_4, it sets the current value of the overflow flag to an invalid overflow value, thereby clearing the overflow state and enabling the command execution unit to execute the instructions in the instruction queue normally.

[0128] It's important to note that the command stream sent from the CPU to the GPU may contain multiple loop start commands carrying an outermost flag, with the outermost flag currently having a valid value. For example, these could be loop start commands within two independent large loops. One large loop might be a three-level nested loop as shown in the code above. During the execution of this three-level nested loop, if the inner loop counter's count does not exceed the loop threshold, the inner loop counter continues counting. If it exceeds the loop threshold, an overflow has occurred, and the overflow flag's current value is set to a valid overflow value. Subsequent commands within this large loop are skipped based on the overflow flag, and instructions within this large loop are executed until a new loop with an outermost flag set to a valid value (loop4, i.e., the loop corresponding to loop_start_4) is reached. At this point, the inner loop counter's count is reset (e.g., cleared to 0), and the overflow flag is set to an invalid overflow value.

[0129] As can be seen from the above embodiments, when the count value of the internal loop counter exceeds the loop threshold, the overflow flag is directly set to true, and all subsequent loop end judgment commands are forcibly set to end. This allows the front-end unit to quickly exit the loop without having to execute complex comparison instructions one by one. Furthermore, this disclosure continuously identifies the current instruction until it accurately identifies a loop start command with the outermost flag and the current value of the outermost flag is valid before continuing to execute the instruction. This ensures that the command execution unit can quickly exit the loop, making this disclosure more adaptable to complex scenarios with multiple nested loops.

[0130] In some embodiments, the front-end unit further includes an overflow flag; the method further includes: using the instruction execution unit, when the (i+j)th instruction being executed is a loop termination instruction and the overflow flag is an invalid overflow value, determining that the (i+j)th instruction is a loop termination judgment instruction to be executed.

[0131] Following the previous example, the format of the loop termination judgment instruction (also known as the loop termination judgment command) in this disclosure can be as follows: Figure 6 As shown; Figure 6 This is a schematic diagram of a loop termination judgment instruction in a task processing method provided in this embodiment of the present disclosure. Figure 6 It can be seen that when the command execution unit executes an instruction, if the opcode in the instruction is the loop end judgment command (loop chk) code, it can be determined that the currently executed instruction is the loop end judgment command.

[0132] The loop end judgment command can include "opcode=loop_chk (encoding)", "value / address flag", "counter operation mode", "counter operation value", "comparison mode", "counter index value", "comparison value / comparison address", "jump address offset", etc.

[0133] Based on this Figure 7 This diagram illustrates the determination of whether to execute a loop termination judgment instruction in a task processing method provided in this embodiment of the present disclosure. When the loop termination judgment instruction is executed, that is, when the command execution unit encounters an opcode for a loop termination judgment instruction (loop chk), this disclosure requires the following... Figure 7 The process is as follows to determine whether to execute the loop end judgment instruction.

[0134] Step 1: The command execution unit first checks the overflow flag.

[0135] Step 2: Determine if the overflow flag is true. If yes, proceed to step 3; otherwise, proceed to step 4.

[0136] Step 3: Skip the current loop chk instruction and execute the next instruction.

[0137] Specifically, if the overflow flag is true, it indicates that the previous loop has been executed too many times (exceeding the set loop threshold), and the hardware may enter an infinite loop. At this time, the command execution unit will skip this loop end judgment instruction (loopchk) and skip instructions that do not need to be executed until the next instruction to be executed is the loop start instruction where the current value of the outermost flag is valid.

[0138] Step 4: Execute the loop chk command.

[0139] Specifically, if the overflow flag is false at this time, it means that the number of loops executed by the hardware has not exceeded the set loop threshold value, and the command execution unit will execute this loop end judgment command.

[0140] It should be noted that during the execution of the loop end judgment command, the current value of the target counter needs to be obtained from the counter unit based on the counter index value of the target counter in the loop end judgment command, for subsequent judgment.

[0141] As can be seen from the above embodiments, this disclosure can force the hardware to exit via an overflow flag even when there are flaws in the loop logic (e.g., the loop condition can never be satisfied), ensuring the robustness of the GPU and avoiding serious failures that require resetting the GPU. Furthermore, upon detecting an overflow, it can immediately exit the loop task with minimal delay, minimizing time wasted in the overflow state.

[0142] In some embodiments, the method further includes: using the instruction execution unit to obtain the comparison value from the (i+j)th instruction; or, using the instruction execution unit to determine the comparison value storage address from the (i+j)th instruction, and obtaining the comparison value from the storage unit corresponding to the graphics processor according to the comparison value storage address.

[0143] The comparison value storage address can be understood as the storage address corresponding to the comparison value, through which the comparison value can be retrieved from the storage unit. Therefore, this disclosure achieves fast retrieval of the comparison value and improves instruction processing efficiency by carrying the comparison value in the loop end judgment instruction; alternatively, the comparison value storage address (i.e., ...) can also be carried in the loop end judgment instruction. Figure 6 The comparison address in the loop reduces the data volume and size of the loop termination judgment instruction.

[0144] In some embodiments, updating the current value of the target counter includes: using the instruction execution unit to update the current value of the target counter according to the counter operation mode in the (i+j)th instruction and the counter operation value corresponding to the counter operation mode.

[0145] The counter operation mode can be understood as a way to update the current value of the target counter. This counter operation mode and counter operation value can be set according to the actual application scenario. For example, if the comparison passes and the count value of the inner loop counter does not exceed the loop threshold, the command execution unit can update the given target counter based on the counter operation mode and counter operation value carried by the loop end judgment unit. The counter operation modes proposed in this disclosure include, but are not limited to: increment, decrement, multiplication, arithmetic left shift, arithmetic right shift, logical left shift, and logical right shift.

[0146] The counter operation value provides another piece of information required for the aforementioned counter operation. For example, if the counter operation mode is set to increment, the counter operation value can be set to 1, so that it increments by 1 each time; the counter operation value can also be set to 2, so that it can start from the initial value and accumulate cyclically in steps of 2.

[0147] As can be seen from the above embodiments, this disclosure directly embeds the counter operation mode and counter operation value into the loop end judgment instruction, realizing data-driven dynamic iterative update. By dynamically setting the counter operation mode and counter operation value, the iteration rhythm can be flexibly adjusted, thereby improving the adaptability of this disclosure.

[0148] In some embodiments, determining a target counter from the plurality of counters and assigning a value to the target counter based on the counter index value and the initial value of the counter in the i-th instruction includes: using the instruction execution unit to determine the target counter from the plurality of counters based on the counter index value in the i-th instruction, and setting the initial value of the counter to the current value of the target counter.

[0149] Specifically, the instruction execution unit of this disclosure, when executing the loop start instruction, needs to obtain the counter index value from the loop start instruction, and determine the corresponding target counter from multiple counters based on the counter index value; then, it obtains the initial value of the counter from the loop start instruction, and assigns the initial value of the counter to the target counter.

[0150] As can be seen from the above embodiments, this disclosure implements dynamic loop count control. The loop count of the target loop execution task is no longer hard-coded at compile time or dependent on global registers, but is directly carried as an operand of the loop start instruction. In complex tasks, different tasks can use different counter index values ​​simultaneously and independently set their own counter initial values, preventing the loop states of different tasks from interfering with each other.

[0151] In connection with one or more of the above embodiments, this disclosure provides an example of executing a loop end judgment instruction. Figure 8 This is a schematic diagram illustrating the execution of a loop termination judgment instruction in a task processing method provided in this embodiment of the present disclosure, based on... Figure 8 It can be seen that when the command execution unit executes the loop end judgment instruction, it will perform the following steps.

[0152] 1. Obtain the address of the currently executing instruction.

[0153] This instruction is for determining the end of a loop.

[0154] 2. Based on the counter index value carried by the loop end judgment instruction, obtain the current value of the counter from the corresponding counter unit.

[0155] The counter in question is the target counter.

[0156] 3. Try to obtain the comparison value.

[0157] Specifically, the command execution unit begins attempting to obtain a comparison value.

[0158] 4. Determine if the value / address flag is a value.

[0159] The loop termination judgment instruction proposed in this disclosure supports two different comparison methods: an immediate value and an indirect value.

[0160] The immediate value refers to the comparison value that can be immediately obtained from the loop end judgment instruction. Specifically, when the value / address flag of the loop end judgment instruction indicates that the subsequent data is a value, the command execution unit retrieves the information from the comparison value / comparison address following the loop end judgment instruction and uses this information directly as the comparison value, thereby achieving rapid acquisition of the comparison value.

[0161] Indirect values ​​refer to comparison values ​​that need to be obtained indirectly based on the comparison address carried in the loop end judgment instruction. Specifically, if the value / address flag indicates that the subsequent data is not a value but an address (i.e., the comparison value storage address), the command execution unit will extract the information from the comparison value / comparison address following the loop end judgment instruction, use it as a comparison address (i.e., the comparison value storage address), send the read request to the storage unit based on this comparison address, and obtain the comparison value from the return data of the storage unit.

[0162] 5. Compare the comparison value with the current value of the counter according to the comparison method.

[0163] Specifically, after the command execution unit obtains the current value of the given counter and the given comparison value (immediate value or indirect value), it needs to use the comparison method in the loop end judgment instruction to compare the two.

[0164] 6. Determine whether the comparison is successful.

[0165] Specifically, if not, it means the comparison failed, then the loop end judgment instruction here can be considered as the end of the loop, and step 12 is executed.

[0166] If yes, it means the comparison passed, and the loop end judgment instruction here can be considered as the loop has not ended, so step 7 is executed.

[0167] 7. Increment the value of the inner loop counter by one.

[0168] Specifically, the command execution unit increments the value of its internal loop counter by 1 according to the increment-1 strategy.

[0169] 8. Determine if the internal loop counter is greater than the loop threshold value.

[0170] Specifically, the current count value of the loop counter is compared with the loop threshold value. If they are equal, it means that the count value of the internal loop counter is greater than the loop threshold value. In this case, the number of loop executions has exceeded the set number, and the command execution unit will treat this as a failure of the comparison and proceed to step 9.

[0171] If not, it means the comparison passed and the count value of the internal loop counter did not exceed the loop threshold value, then the command execution unit will execute step 10.

[0172] 9. Set the overflow flag to true and execute step 12.

[0173] 10. Update the counter value according to the counter operation mode and the counter operation value.

[0174] Specifically, the command execution unit updates the current value of a given target counter according to the counter operation mode and the counter operation value carried by the loop end judging unit.

[0175] 11. Add the jump address offset to the current instruction address, and set the result as the address of the instruction to be executed.

[0176] Specifically, after the command execution unit updates the current value of the given target counter, it adds the jump address offset to the current instruction address, sets the result as the address of the instruction to be executed, jumps back to the next instruction after the start of the original loop, and continues execution.

[0177] 12. Set the address of the instruction to be executed as the next instruction.

[0178] Specifically, the command execution unit sets the instruction to be executed as the next instruction after the loop end judging instruction, and then starts executing the next instruction.

[0179] Wherein, the next instruction is a loop start instruction that is located after the loop end judging instruction and whose outermost flag current value is a valid value.

[0180] 13. Execute the next instruction.

[0181] Based on the above embodiments, it can be seen that in order to efficiently support the cyclic execution of GPU commands, the present disclosure proposes a brand-new instruction design framework and a GPU frontend applying the instructions. The GPU frontend designed in the present disclosure can efficiently execute cycles for a specific command stream portion; it avoids the problem that storage and transmission of multiple tasks consume a large amount of computer resources, saves computer resources and improves task processing efficiency.

[0182] In some embodiments, said using the instruction execution unit to sequentially execute instructions in the instruction queue starting from the (i+1)-th instruction comprises: using the instruction execution unit, in a case where the (i+n)-th instruction executed is a target task execution instruction, determining the target counter according to the counter index value in the counter placeholder of the target task execution instruction, and executing the target task execution instruction according to the current value of the target counter; wherein n is an integer and 1≤n<j; using the instruction execution unit to sequentially execute instructions in the instruction queue starting from the (i+n+1)-th instruction.

[0183] Wherein, the target task execution instruction can be understood as a task execution instruction that needs to be executed according to the current value of the target counter; the target task execution instruction is located between the i-th instruction and the (i+j)-th instruction.

[0184] Specifically, the instruction queue disclosed herein includes a target task execution instruction, which is encoded with a counter placeholder. During the sequential execution of instructions in the instruction queue using the instruction execution unit, when the executed instruction is a target task execution instruction, the instruction is parsed. During instruction parsing, if the counter placeholder is identified, the counter index value within the placeholder is obtained, and the corresponding target counter is determined from multiple counters based on the counter index value. Then, the corresponding counter value (i.e., the current value) is retrieved from the target counter. This counter value replaces the corresponding part in the instruction, and the execution of the target task execution instruction continues. The corresponding part in the instruction can be an additional placeholder set by the target task execution instruction to store the counter value; alternatively, the corresponding part can also be a counter placeholder within the target task execution instruction, in which case the counter value replaces the counter index value in the placeholder.

[0185] After executing the target task execution instructions, the instruction execution unit will be used to execute the instructions in the instruction queue sequentially, starting from the (i+n+1)th instruction.

[0186] As can be seen from the above embodiments, this disclosure enables the execution of the target task instruction by pre-setting a "counter placeholder" in the instruction and obtaining the counter value during execution. This allows the instruction to dynamically adjust its execution behavior according to the real-time hardware status (such as the number of loops), thereby improving the flexibility of task processing. Furthermore, it allows the task execution instruction to be reused in different computing scenarios or loop control. This design reduces the complexity of hardware instructions.

[0187] In some embodiments, the target task execution instruction includes a batch processing identifier setting instruction. Executing the target task execution instruction based on the current value of the target counter includes: using the instruction execution unit to determine the current value of the target counter as a batch processing identifier value; and executing the batch processing identifier setting instruction based on the batch processing identifier value to set the batch processing identifier value. The batch processing identifier value is used to indicate the execution of a batch processing operation corresponding to the batch processing identifier value during the execution of the batch processing instruction. For example, the batch processing identifier value is a value 1 or a value 2, and the batch processing operation corresponding to the batch processing identifier value includes: a batch processing operation for the first batch and a batch processing operation for the second batch.

[0188] In some embodiments, the task execution instruction includes a set view identifier instruction, the set view identifier instruction including a flag bit, wherein the set view identifier instruction whose value is equal to a target value is the target task execution instruction; the step of executing the target task execution instruction according to the current value of the target counter includes: using the instruction execution unit to determine the current value of the target counter as a view identifier value, and executing the set view identifier instruction based on the view identifier value to set the view identifier value, wherein the view identifier value is used to indicate the execution of a view rendering operation corresponding to the view identifier value during the execution of the view rendering instruction.

[0189] The view identifier value can be understood as a value used to indicate the execution of the corresponding view rendering operation; for example, the view identifier value is view-id. The view identifier setting instruction can be understood as an instruction used to set the view identifier value.

[0190] Following the example above, while this disclosure provides the loop start command and loop end judgment command, other commands need to be adapted accordingly. In one implementation, when this disclosure supports view-instance, the driver can set a set-view-id command (i.e., set view identifier instruction).

[0191] Figure 9 This is a schematic diagram of a set-view-id command in a task processing method provided in an embodiment of this disclosure, as shown below. Figure 9 As shown, a flag field (i.e., a flag bit) can be added to this set-view-id command. This set-view-id command includes opcode=set view id, a counter index value, and flag=1. opcode=set view id is the encoding of the set-view-id command, used to allow the command execution unit to recognize that the currently executed command is set-view-id.

[0192] When flag=1 (i.e., the value of the flag bit equals the target value), the set-view-id command no longer encodes a usable setting value (i.e., the view identifier value), but rather a counter index value in the counter placeholder. When the command execution unit encounters the set-view-id command and flag is 1, it indexes the corresponding target counter in the counter unit according to the counter index value and retrieves the current value of the target counter; during the execution of the set-view-id command, this current value is set into the hardware as the view id (i.e., the view identifier value) that needs to be set.

[0193] Specifically, this disclosure provides the following instructions, which demonstrate how to design coded instructions inside a loop so that the set-view-id instruction can use a circular index.

[0194] {……

[0195] loop_start(from 4 to 1)

[0196] set-view-id(flag = 1, index counter)

[0197] draw()

[0198] loop_end()

[0199] ...}

[0200] In the above instructions, `loop_start(from 4 to 1)` means that the loop needs to be executed 4 times. The `set-view-id` instruction is used to set the current view-id; `set-view-id(flag = 1, index counter)` means that when `flag = 1` in the `set-view-id` command, the target counter can be indexed by the counter value. The `draw()` instruction is used to instruct the execution of view rendering operations, and the view-id is required during the view rendering process. `loop_end()` is the instruction for determining the end of the loop.

[0201] Based on the above loop instructions, it can be seen that in each loop, this disclosure executes the set-view-id command, and when flag=1, it sets the value of the specified index counter in the hardware; this allows the subsequent draw operation (i.e., view rendering operation) to be repeated 4 times. The first time, draw with view-id=4 (i.e., use view-id=4 to perform the draw operation), the second time, draw with view-id=3 (i.e., use view-id=3 to perform the draw operation), and then draw with view-id=2 (i.e., use view-id=2 to perform the draw operation) and draw with view-id=1 (i.e., use view-id=1 to perform the draw operation).

[0202] In other words, by using the set-view-id instruction mentioned above, the GPU can obtain a different view-id value each time it draws, and perform some custom operations based on this view-id value, such as selecting the viewport or selecting a different texture based on the view-id.

[0203] Once the GPU's backend execution unit obtains the view-id, it needs to determine how to execute the corresponding rendering operation based on the view-id and produce different rendering effects. This rendering operation can be user-defined. This disclosure simply provides the user with information (view-id) so that the user can distinguish between different views.

[0204] As can be seen from the above embodiments, this disclosure dynamically adjusts the view identifier value by using the current value of the counter, enabling the GPU to automatically and efficiently identify and switch rendering operations. This makes the method more suitable for multi-view rendering scenarios and improves the execution efficiency of graphics rendering.

[0205] In some embodiments, the task execution instruction includes a set view identifier instruction, which includes a flag bit and a set value placeholder. If the value of the flag bit is not equal to the target value, the set view identifier instruction is executed according to the current value of the set value placeholder.

[0206] Following the previous example, when this disclosure supports view-instance, the driver can also set another set-view-id command, the format of which is as follows: Figure 10 As shown; Figure 10 This is a schematic diagram of another set-view-id command in a task processing method provided in this disclosure embodiment, based on... Figure 10 As can be seen, this set-view-id command includes opcode=set view id, setting value, and flag=0; the setting value refers to the view identifier value that needs to be set in the task execution instruction; when flag=0 (that is, the value of the flag bit is not equal to the target value), executing this set-view-id command can set the view-id (i.e., view identifier value) of the instruction currently being executed by the hardware to the setting value carried by the set-view-id command.

[0207] It should be noted that, Figure 9 and Figure 10 Reserved bits in the command can be values ​​or placeholders used to adjust the command format or size of the view identifier command, and may not be involved in task processing.

[0208] The above embodiments demonstrate how to design encoded instructions within a loop so that specific instructions can set view identifier values, thereby improving the applicability of this disclosure. The instructions proposed in this disclosure are characterized by being programmable, easy to understand, and hardware-implementable, and the designed GPU front-end has the characteristics of flexible instruction execution and wide applicability.

[0209] In some embodiments, the graphics processor further includes a back-end execution unit, and the task execution instruction further includes a view rendering instruction, which is an instruction following the setting view identifier instruction; the method further includes: during the execution of instructions in the instruction queue sequentially starting from the (i+1)th instruction using the instruction execution unit, when the view rendering instruction is executed, sending the view rendering instruction to the back-end execution unit; the back-end execution unit is used to execute the view rendering instruction according to the view identifier value to obtain the view rendering result corresponding to the view identifier value.

[0210] The back-end execution unit can be understood as the unit in the GPU used to execute the view rendering instructions. The back-end execution unit can be a microprocessor, chip, or logic circuit in the GPU. For example, the back-end execution unit can be an execution unit, shader cores, rasterization unit, texture unit, etc. in the GPU.

[0211] It should be noted that, in some embodiments, after obtaining the view rendering result (such as the rendered view), the front-end unit in the graphics processor can send the view rendering result to the central processing unit (CPU); the CPU then processes the view rendering result. For example, after obtaining the view rendering result, the GPU front-end can send the view rendering result to the CPU; the CPU, upon receiving the view rendering result, can store the view rendering result in memory, database, cache, or other storage units; or, the CPU, upon receiving the view rendering result, can render the view rendering result to a display page (such as the application's display page, webpage, etc.), thereby displaying the rendering results from multiple different perspectives.

[0212] As can be seen from the above embodiments, this disclosure can utilize the GPU front-end to automatically distribute the view rendering instruction to the back-end execution unit for execution multiple times (corresponding to multiple views) through an internal loop mechanism, thereby reducing the command stream volume, greatly compressing the buffer size, reducing the pressure on the GPU front-end for instruction fetching and decoding, releasing storage and transmission resources, and solving the problems of high CPU overhead, bandwidth waste, and storage resource waste in multi-view rendering.

[0213] As can be seen from the embodiments, the task processing method disclosed herein is a design for a GPU front-end command that implements cyclic execution. To efficiently support the cyclic execution of GPU commands, this disclosure proposes a novel instruction design framework and a GPU front-end that applies these instructions. The GPU front-end designed in this disclosure can efficiently execute loops on specific command stream portions. The instructions proposed in this disclosure are characterized by being programmable, easy to understand, and easy to implement in hardware. The designed GPU front-end features flexible instruction execution and a wide range of applications.

[0214] Taking the application of the task processing method provided in this disclosure in a GPU front-end scenario as an example, the task processing method is described. The task processing method in this disclosure provides a GPU front-end command design for implementing cyclic execution. The GPU front-end unit consists of a command acquisition unit, a command execution unit, a counter unit, and an internal loop counter, an overflow flag, and a loop threshold value.

[0215] The task processing method disclosed herein provides a GPU front-end, which specifically performs the following steps.

[0216] Step 1: Identify the loop start command based on the loop start code.

[0217] Step 2: Upon recognizing a loop start command, the command execution unit checks its outermost flag.

[0218] Step 3: Determine if the outermost flag is true.

[0219] If the outermost flag is true, it indicates that the currently executing loop start instruction is located in the outermost task of a possible nested loop. In this case, the command execution unit needs to initialize the loop counter and overflow flag, and then proceed to step 4. If the outermost flag is false, then step 4 is executed directly.

[0220] In other words, the loop start command carries an outermost flag indicating whether the current loop task is the outermost loop; this flag is used by the GPU front-end to clear the state and the internal loop counter when the loop overflows.

[0221] The initialization operation could be: setting the overflow flag to false and resetting the value of the inner loop counter to 0.

[0222] Step 4: Place the initial value of the counter carried in this command into the counter specified by the counter index value; thus, the initial value of the counter inside the counter unit can be set according to the requirements.

[0223] Step 5: Update the multi-view rendering command that implements multi-view rendering operations.

[0224] Specifically, the set-view-id command provided in this disclosure can add an additional flag field, such as... Figure 10As shown. When flag=1, the content encoded in this command is no longer a usable setting value, but a counter index value. When the command execution unit encounters the set-view-id command and flag is 1, it indexes the corresponding counter in the counter unit from the counter index value, retrieves its current value, and sets it as the view id to be set in the hardware.

[0225] In other words, this disclosure encodes a counter placeholder (i.e., counter index value) for a specific set-view-id command. When parsing the command, if this counter placeholder is encountered, the corresponding counter value is retrieved from the internal counter and used to replace the corresponding part in the multi-view rendering command.

[0226] Step 6: Execute the multi-view rendering command.

[0227] Specifically, during the execution of a multi-view rendering task, the GPU front-end can invoke instruction execution units (such as shader and rasterizer units) to execute the multi-view rendering command. Based on this, while the loop is not yet complete, the GPU front-end can send the multi-view rendering command to the instruction execution unit, which then executes the command. The instruction execution unit can execute the multi-view rendering command multiple times to obtain rendering results from multiple different perspectives.

[0228] Step 7: Determine whether to execute the loop termination check instruction.

[0229] When the loop ends and a conditional statement is reached, this disclosure needs to be performed as follows: Figure 7 The process is as follows to determine whether to execute the loop end judgment instruction.

[0230] 1. The command execution unit will first check the overflow flag.

[0231] 2. Determine if the overflow flag is true.

[0232] 3. If the overflow flag is true, it indicates that the previous loop has been executed too many times (exceeding the set threshold), and the hardware may enter an infinite loop. In this case, the command execution unit will skip this loop termination judgment instruction (loop chk) and execute its next instruction.

[0233] 4. If the overflow flag is false at this time, it means that the number of loops executed by the hardware has not exceeded the set threshold value. At this time, the command execution unit will execute this loop end judgment command.

[0234] Step 8: Execute the loop termination judgment instruction.

[0235] When the command execution unit executes the loop end judgment instruction, it will perform the following steps.

[0236] 1. Obtain the address of the currently executing instruction.

[0237] 2. Based on the counter index value carried by the loop end judgment instruction, retrieve the counter value from the corresponding counter unit.

[0238] 3. The command execution unit will attempt to obtain the comparison value.

[0239] 4. Obtain the comparison value.

[0240] It should be noted that the loop termination judgment instruction proposed in this disclosure supports two different comparison values: one is an immediate value, and the other is an indirect value.

[0241] Immediate values ​​are comparison values ​​that can be obtained immediately from the loop end check instruction. Indirect values ​​are comparison values ​​that need to be obtained indirectly based on the comparison address carried in the loop end check instruction.

[0242] 5. Compare the comparison value with the current value of the counter according to the comparison method.

[0243] 6. Determine whether the comparison is successful.

[0244] Specifically, if the comparison fails, the loop end judgment instruction here can be considered as the end of the loop, and then step 12 is executed.

[0245] If the comparison passes, then the loop termination check instruction here can be considered as the loop has not ended, and step 7 will be executed.

[0246] 7. Increment the value of the inner loop counter by one.

[0247] 8. Determine if the internal loop counter is greater than the loop threshold value.

[0248] Specifically, the value of the internal loop counter is compared with the loop threshold. If the value of the internal loop counter is greater than the loop threshold, then the number of loop executions has exceeded the set number, and the command execution unit will treat this as a failed comparison and proceed to step 9.

[0249] If the comparison passes and the value of the internal loop counter does not exceed the loop threshold, then the command execution unit will execute step 10.

[0250] 9. Set the overflow flag to true and execute step 12.

[0251] 10. Update the counter value according to the counter operation mode and the counter operation value.

[0252] 11. Add the jump address offset to the current instruction address and set it as the address of the instruction to be executed.

[0253] 12. Set the address of the instruction to be executed as the next instruction.

[0254] The next instruction includes a loop start instruction where the current value of the outermost flag is valid.

[0255] 13. Execute the next instruction.

[0256] Based on the above steps, it can be seen that during the execution of the loop end judgment instruction, the GPU front-end of this disclosure can specify a specific end condition for the internal counter (including the comparison method and the comparison object) according to the loop end judgment command; if the end condition is not met, the internal counter is updated; and if the end condition is met, it jumps back to the command before the current command, which generally requires jumping back to the command after the loop start command.

[0257] The internal counter can be modified in various ways, including incrementing, decrementing, multiplying, arithmetic left shift, arithmetic right shift, logical left shift, and logical right shift, with another operand (default is 1). Comparison modes include not equal to, equal to, unsigned greater than, unsigned less than, signed greater than, signed less than, unsigned greater than or equal to, unsigned less than or equal to, signed greater than or equal to, and signed less than or equal to.

[0258] The comparison value used for the termination condition in the loop termination judgment command can be either immediately encoded into the current command or an address that needs to be retrieved from the corresponding memory unit.

[0259] If the loop termination check command determines that the loop has ended, then the next command following the loop termination check command is executed directly. If the loop termination check command has not ended, then the command stream offset of the loop termination check command is increased by the offset value set in the command, and then the command is executed.

[0260] When the loop start command is executed, an internal counter is cleared to zero, and this internal counter is incremented every time the loop end judgment command is executed. When the value of the internal counter exceeds a software-configured threshold, the front end sets a state, setting all subsequent loop end judgment commands to end, until a loop start command with specific settings is encountered.

[0261] The task processing method according to the embodiments of this disclosure can be applied to application scenarios where neural networks are accelerated through many-core systems. The target cyclic execution task can also be a task processed by the neural network, including but not limited to any one of image processing tasks, speech processing tasks, text processing tasks, video processing tasks, etc. The data processed by the neural network includes any one of images, speech, text, and video, and this disclosure does not limit it.

[0262] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0263] In addition, this disclosure also provides a task processing system, an electronic device, and a computer-readable storage medium, all of which can be used to implement any of the task processing methods provided in this disclosure. The corresponding technical solutions and descriptions are described in the corresponding section of the method and will not be repeated here.

[0264] Figure 11 This is a block diagram of a task processing system provided in an embodiment of the present disclosure.

[0265] Reference Figure 11 This disclosure provides a task processing system, which includes a graphics processor, a front-end unit 11, an instruction execution unit 112, an instruction fetching unit 111, and a plurality of counters 113.

[0266] The instruction acquisition unit 111 is configured to: acquire a target loop execution task generated by the central processing unit, wherein the instruction queue of the target loop execution task includes a loop start instruction, a task execution instruction, and a loop end judgment instruction;

[0267] The instruction execution unit 112 is configured to: during the execution of the instruction queue, if it is determined that the i-th instruction is a loop start instruction to be executed, determine a target counter from the plurality of counters 113 according to the counter index value and the initial value of the counter in the i-th instruction, and assign a value to the target counter; i is an integer greater than or equal to 1; execute the instructions in the instruction queue sequentially starting from the (i+1)-th instruction; if it is determined that the (i+j)-th instruction is a loop end judgment instruction to be executed, determine whether the loop end condition is met according to the comparison value in the (i+j)-th instruction and the current value of the target counter; j is an integer greater than 1; if the loop end condition is not met, update the current value of the target counter, and jump to the (i+1)-th instruction, and execute the instructions in the instruction queue sequentially starting from the (i+1)-th instruction.

[0268] In some embodiments, the instruction execution unit 112 is further configured to execute instructions in the instruction queue sequentially, starting from the (i+j+1)th instruction, when the loop termination condition is met.

[0269] In some embodiments, the instruction execution unit 112 is further configured to compare the comparison value with the current value, and determine that the loop termination condition is met if the comparison fails.

[0270] In some embodiments, the instruction execution unit 112 is further configured to: compare the comparison value with the current value; if the comparison passes, update the count value of the internal loop counter included in the front-end unit; if the updated count value is greater than the loop threshold value, set the overflow flag included in the front-end unit to a valid overflow value; and if the current value of the overflow flag is a valid overflow value, determine that the loop termination condition is met.

[0271] In some embodiments, the instruction execution unit 112 is further configured to skip instructions that do not need to be executed until the next instruction to be executed is the loop start instruction whose current value of the outermost flag is valid, wherein the instructions to be executed during the period when the current value of the overflow flag is a valid overflow value are instructions that do not need to be executed.

[0272] In some embodiments, the i-th instruction further includes an outermost flag, and the front-end unit further includes an overflow flag. The i-th instruction is determined to be a loop start instruction to be executed if any of the following conditions are met: the current value of the outermost flag in the i-th instruction is a valid value; or the current value of the overflow flag is an invalid overflow value.

[0273] In some embodiments, the front-end unit further comprises an internal loop counter, and in a case where a current value of an outermost flag in the i-th instruction is a valid value, the instruction execution unit 112 is further configured to reset a count value of the internal loop counter, and set a current value of the overflow flag to an invalid overflow value.

[0274] In some embodiments, the front-end unit further comprises an overflow flag; the instruction execution unit 112 is further configured to determine, in a case where an executed (i+j)-th instruction is a loop end instruction and the overflow flag is an invalid overflow value, that the (i+j)-th instruction is a loop end judgment instruction that needs to be executed.

[0275] In some embodiments, the instruction execution unit 112 is further configured to, in a case where an executed (i+n)-th instruction is a target task execution instruction, determine the target counter 113 according to a counter 113 index value in a counter 113 placeholder of the target task execution instruction, and execute the target task execution instruction according to a current value of the target counter 113; wherein n is an integer and 1≤n<j; instructions in the instruction queue are executed sequentially starting from the (i+n+1)-th instruction.

[0276] In some embodiments, the task execution instruction comprises a set view identification instruction, and the set view identification instruction comprises a flag bit, wherein the set view identification instruction with a value of the flag bit equal to a target value is the target task execution instruction.

[0277] The instruction execution unit 112 is further configured to determine a current value of the target counter 113 as a view identification value, and execute the set view identification instruction based on the view identification value to set the view identification value, wherein the view identification value is configured to indicate execution of a view rendering operation corresponding to the view identification value during execution of a view rendering instruction.

[0278] In some embodiments, the task execution instruction comprises a set view identification instruction, the set view identification instruction comprises a flag bit and a set value placeholder, and in a case where the value of the flag bit is not equal to a target value, the set view identification instruction is executed according to a current value of the set value placeholder.

[0279] In some embodiments, the graphics processor further comprises a back-end execution unit, the task execution instruction further comprises a view rendering instruction, and the view rendering instruction is an instruction after the set view identification instruction.

[0280] The instruction execution unit 112 is further configured to, during the sequential execution of instructions in the instruction queue starting from the (i+1)th instruction, send the view rendering instruction to the backend execution unit when the view rendering instruction is executed; the backend execution unit is used to execute the view rendering instruction according to the view identifier value to obtain the view rendering result corresponding to the view identifier value.

[0281] In some embodiments, the instruction execution unit 112 is further configured to obtain the comparison value from the (i+j)th instruction; or, the instruction execution unit 112 is further configured to determine the comparison value storage address from the (i+j)th instruction, and obtain the comparison value from the storage unit corresponding to the graphics processor according to the comparison value storage address.

[0282] In some embodiments, the instruction execution unit 112 is further configured to update the current value of the target counter 113 according to the counter 113 operation mode in the (i+j)th instruction and the counter 113 operation value corresponding to the counter 113 operation mode.

[0283] In some embodiments, the instruction execution unit 112 is further configured to determine the target counter 113 from the plurality of counters 113 according to the counter 113 index value in the i-th instruction, and set the initial value of the counter 113 to the current value of the target counter 113.

[0284] The task processing system provided in this disclosure includes a front-end unit in a graphics processing unit (GPU). The front-end unit includes an instruction execution unit, an instruction fetching unit, and multiple counters. During task processing, the instruction fetching unit acquires a target loop execution task generated by the CPU. The instruction queue of the target loop execution task includes a loop start instruction, a task execution instruction, and a loop end judgment instruction. The instruction execution unit executes the instruction queue. During the execution of the instruction queue, if the i-th instruction is determined to be a loop start instruction to be executed, a target counter is determined from the multiple counters based on the counter index value and initial counter value in the i-th instruction, and a value is assigned to it. Then, starting from the (i+1)-th instruction, the instructions in the instruction queue are executed sequentially. If the (i+j)-th instruction is determined to be a loop end judgment instruction to be executed, it is determined whether the loop end condition is met. If the loop end condition is not met, the execution jumps to the (i+1)-th instruction and continues executing the (i+1)-th instruction, thereby achieving loop execution of instructions. In this process, because this disclosure can cyclically execute the instructions in the instruction queue, it achieves the effect and purpose of executing multiple tasks by executing one target in a loop, thereby improving task processing efficiency and avoiding the problem of consuming a lot of computer resources when storing and transmitting multiple tasks, thus saving computer resources.

[0285] The above is an illustrative scheme of a task processing system according to this embodiment. It should be noted that the technical solution of this task processing system and the technical solution of the task processing method described above belong to the same concept. For details not described in detail in the technical solution of the task processing system, please refer to the description of the technical solution of the task processing method described above.

[0286] Figure 12 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0287] Reference Figure 12 This disclosure provides an electronic device, which includes: at least one processor 1201; at least one memory 1202; and one or more I / O interfaces 1203 connected between the processor 1201 and the memory 1202; wherein the memory 1202 stores one or more computer programs that can be executed by the at least one processor 1201, and the one or more computer programs are executed by the at least one processor 1201 to enable the at least one processor 1201 to perform the above-described task processing method.

[0288] This disclosure also provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the above-described task processing method. The computer-readable storage medium may be volatile or non-volatile.

[0289] This disclosure also provides a computer program product, including computer-readable code, which, when executed in the processor of an electronic device, causes the processor in the electronic device to perform the aforementioned task processing method.

[0290] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0291] As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable program instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable program instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0292] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0293] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0294] The computer program product described herein can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0295] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0296] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0297] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0298] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0299] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A task processing method, characterized in that, A front-end unit applied in a graphics processing unit, the front-end unit including an instruction execution unit, an instruction fetching unit, and multiple counters, the method comprising: Using the instruction acquisition unit, a target loop execution task generated by the central processing unit is acquired, wherein the instruction queue of the target loop execution task includes a loop start instruction, a task execution instruction, and a loop end judgment instruction; During the execution of the instruction queue using the instruction execution unit, if the i-th instruction is determined to be the loop start instruction to be executed, a target counter is determined from the plurality of counters and assigned a value to the target counter based on the counter index value and the initial value of the counter in the i-th instruction; i is an integer greater than or equal to 1; Using the instruction execution unit, the instructions in the instruction queue are executed sequentially, starting from the (i+1)th instruction; Using the instruction execution unit, when it is determined that the (i+j)th instruction is a loop termination judgment instruction to be executed, it is determined whether the loop termination condition is met based on the comparison value in the (i+j)th instruction and the current value of the target counter; j is an integer greater than 1. Using the instruction execution unit, if the loop termination condition is not met, the current value of the target counter is updated, and the process jumps to the (i+1)th instruction, starting from the (i+1)th instruction, to execute the instructions in the instruction queue sequentially.

2. The method according to claim 1, characterized in that, The method further includes: Using the instruction execution unit, if the loop termination condition is met, the instructions in the instruction queue are executed sequentially starting from the (i+j+1)th instruction.

3. The method according to claim 1, characterized in that, The step of determining whether the loop termination condition is met based on the comparison value in the (i+j)th instruction and the current value of the target counter includes: The instruction execution unit compares the comparison value with the current value, and determines that the loop termination condition is met if the comparison fails.

4. The method according to claim 1, characterized in that, The step of determining whether the loop termination condition is met based on the comparison value in the (i+j)th instruction and the current value of the target counter includes: The instruction execution unit compares the comparison value with the current value, and if the comparison passes, updates the count value of the internal loop counter included in the front-end unit. Using the instruction execution unit, if the updated count value is greater than the loop threshold value, the overflow flag included in the front-end unit is set to a valid overflow value; Using the instruction execution unit, if the current value of the overflow flag is a valid overflow value, it is determined that the loop termination condition is met.

5. The method according to claim 4, characterized in that, The method further includes: Using the instruction execution unit, instructions that do not need to be executed are skipped until the next instruction to be executed is the loop start instruction whose current value of the outermost flag is valid. Instructions to be executed during the period when the current value of the overflow flag is a valid overflow value are instructions that do not need to be executed.

6. The method according to claim 1, characterized in that, The i-th instruction also includes an outermost flag, and the front-end unit also includes an overflow flag. The i-th instruction is determined to be a loop start instruction to be executed if any of the following conditions are met: The current value of the outermost flag in the i-th instruction is a valid value; The current value of the overflow flag is an invalid overflow value.

7. The method according to claim 6, characterized in that, The front-end unit further includes an internal loop counter. If the current value of the outermost flag in the i-th instruction is valid, the method further includes: Using the instruction execution unit, the count value of the internal loop counter is reset, and the current value of the overflow flag is set to an invalid overflow value.

8. The method according to claim 1, characterized in that, The front-end unit further includes an overflow flag; the method further includes: Using the instruction execution unit, if the (i+j)th instruction being executed is a loop termination instruction and the overflow flag is an invalid overflow value, the (i+j)th instruction is determined to be a loop termination judgment instruction that needs to be executed.

9. The method according to claim 1, characterized in that, The step of using the instruction execution unit to sequentially execute the instructions in the instruction queue, starting from the (i+1)th instruction, includes: Using the instruction execution unit, when the (i+n)th instruction being executed is a target task execution instruction, the target counter is determined based on the counter index value in the counter placeholder of the target task execution instruction, and the target task execution instruction is executed based on the current value of the target counter; where n is an integer and 1 ≤ n <j; Using the instruction execution unit, the instructions in the instruction queue are executed sequentially, starting from the (i+n+1)th instruction.

10. The method according to claim 9, characterized in that, The task execution instruction includes a view identifier setting instruction, which includes a flag bit, wherein the view identifier setting instruction whose value is equal to the target value is the target task execution instruction; The step of executing the target task execution instruction based on the current value of the target counter includes: Using the instruction execution unit, the current value of the target counter is determined as the view identifier value. Based on the view identifier value, the view identifier setting instruction is executed to set the view identifier value. The view identifier value is used to indicate the execution of the view rendering operation corresponding to the view identifier value during the execution of the view rendering instruction.

11. The method according to claim 1, characterized in that, The task execution instruction includes a set view identifier instruction, which includes a flag bit and a set value placeholder. If the value of the flag bit is not equal to the target value, the set view identifier instruction is executed according to the current value of the set value placeholder.

12. The method according to claim 10 or 11, characterized in that, The graphics processor further includes a back-end execution unit, and the task execution instructions further include view rendering instructions, which are instructions following the view identifier setting instructions; the method further includes: During the execution of instructions in the instruction queue sequentially starting from the (i+1)th instruction using the instruction execution unit, when the view rendering instruction is executed, the view rendering instruction is sent to the backend execution unit; The backend execution unit is used to execute the view rendering instruction according to the view identifier value, and obtain the view rendering result corresponding to the view identifier value.

13. The method according to claim 1, characterized in that, The method further includes: The comparison value is obtained from the (i+j)th instruction using the instruction execution unit; or, Using the instruction execution unit, the comparison value storage address is determined from the (i+j)th instruction, and the comparison value is obtained from the storage unit corresponding to the graphics processor according to the comparison value storage address.

14. The method according to claim 1, characterized in that, Updating the current value of the target counter includes: Using the instruction execution unit, the current value of the target counter is updated according to the counter operation mode in the (i+j)th instruction and the counter operation value corresponding to the counter operation mode.

15. The method according to claim 1, characterized in that, The step of determining the target counter from the plurality of counters and assigning a value to the target counter based on the counter index value and the initial value of the counter in the i-th instruction includes: Using the instruction execution unit, the target counter is determined from the plurality of counters according to the counter index value in the i-th instruction, and the initial value of the counter is set as the current value of the target counter.

16. A task processing system, characterized in that, The task processing system includes a graphics processor, the graphics processor includes a front-end unit, the front-end unit includes an instruction execution unit, an instruction fetching unit and multiple counters; The instruction acquisition unit is configured as follows: Obtain the target loop execution task generated by the central processing unit, wherein the instruction queue of the target loop execution task includes a loop start instruction, a task execution instruction, and a loop end judgment instruction; The instruction execution unit is configured as follows: During the execution of the instruction queue, if the i-th instruction is determined to be the loop start instruction to be executed, a target counter is determined from the plurality of counters and assigned a value based on the counter index value and the initial value of the counter in the i-th instruction; i is an integer greater than or equal to 1. Execute the instructions in the instruction queue sequentially, starting from the (i+1)th instruction. If the (i+j)th instruction is determined to be the loop termination judgment instruction to be executed, the loop termination condition is determined based on the comparison value in the (i+j)th instruction and the current value of the target counter; j is an integer greater than 1. If the loop termination condition is not met, update the current value of the target counter and jump to the (i+1)th instruction, and execute the instructions in the instruction queue sequentially starting from the (i+1)th instruction.

17. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs that can be executed by the at least one processor, the one or more computer programs being executed by the at least one processor to enable the at least one processor to perform the method as described in any one of claims 1-15.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer program, when executed by a processor, implements the method as described in any one of claims 1-15.

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