A method for high-speed data synchronization transmission between boards

Abstract

The application discloses a method for high-speed data synchronization transmission between boards, which adopts high-speed transceivers to realize high-speed data transmission between boards in a many-to-one mode; the data transmission time delay of each sub-board to the main board is tested, and the maximum value T0 is obtained; meanwhile, the data transmission buffer of each sub-board and the data receiving buffer of the main board are reset; after the resetting, each sub-board starts to send data, and the main board starts to receive the data of each sub-board from the local buffer after waiting for a time T greater than T0. The application realizes high-speed data transmission between boards, effectively controls the time delay of high-speed data transmission between boards, and realizes the synchronization transmission of data, which is very important in a system with complex data interaction and high data synchronization requirement.

Description

Technical Field

[0001] This invention relates to a method for synchronizing high-speed data transmission between boards, particularly using a timed transmit / receive approach to achieve delay control and synchronization processing for high-speed data transmission between boards, for systems requiring high-speed data transmission and demanding stable and controllable delay. Background Technology

[0002] Inter-board data transmission primarily employs methods such as LVDS transmission and high-speed transceiver GTX transmission. Traditional inter-board data transmission typically uses LVDS, which offers controllable data latency but suffers from limited data transfer capacity and low data transmission rates, generally only reaching a few hundred Mbps, insufficient for high-speed data transmission. High-speed transceivers (GTX) can achieve speeds up to 6.5 Gbps, but their drawback is inconsistent data transmission latency after each logic reload, affecting data synchronization. Summary of the Invention

[0003] The technical problem solved by this invention is to overcome the shortcoming that the data transmission delay of the high-speed transceiver GTX is not fixed each time it is powered on, and to achieve delay control and synchronization processing of high-speed data transmission between boards by adopting a timed transmission and reception method.

[0004] The technical solution of this invention is: a method for high-speed data synchronous transmission between boards, wherein the board involved in the method includes a motherboard and at least two daughterboards, the motherboard is the data receiver, the daughterboards are the data transmitters, and data transmission between the motherboard and each daughterboard is performed using an independent high-speed transceiver GTX; the method includes the following steps:

[0005] (1) Make the working clock of the daughter board and the motherboard the same; set a transmit buffer in front of the high-speed transceiver GTX of each daughter board, and each daughter board continuously stores the data to be transmitted into the local transmit buffer. The high-speed transceiver GTX reads the data from the transmit buffer and transmits it.

[0006] (2) Test the data transmission delay from each daughterboard to the motherboard and obtain the maximum data transmission delay T0;

[0007] (3) Based on the maximum data transmission delay T0 in step (2), set up a data receiving buffer for each daughterboard after the high-speed transceiver GTX on the motherboard.

[0008] (4) Simultaneously reset the data transmission buffer of each daughterboard and the data reception buffer of the motherboard;

[0009] (5) The high-speed transceiver GTX of each daughterboard reads data from the local transmit buffer and sends it. The high-speed transceiver GTX of the motherboard receives the data sent by the daughterboard and stores it in the corresponding data receive buffer. After the motherboard waits for T>T0, it continuously reads the data of each daughterboard from the local buffer corresponding to each daughterboard to complete the high-speed data synchronization transmission between boards.

[0010] The unit of the maximum data transmission delay measured in step (2) is the number of clock cycles, that is, a delay of T0 clock cycles;

[0011] In step (3), the size of the data receiving buffer set for each sub-board is greater than T0.

[0012] The beneficial effects of this invention compared to the prior art are:

[0013] To solve the problem of large-scale data synchronization between boards, this invention uses a high-speed transceiver GTX for large-scale high-speed data transmission. Because the data transmission delay of the high-speed transceiver GTX is inconsistent after each power-on loading, this invention, under the condition that the clocks of the motherboard and each daughterboard are from the same source, first measures the maximum value T0 (the delay unit is the number of clock cycles) of the data transmission delay between each daughterboard and the motherboard. Then, the motherboard sends a reset signal to each daughterboard. This reset signal only resets the data transmission buffer of the daughterboard and the corresponding data reception buffer of each daughterboard on the motherboard, and cannot reset the GTX, because after the GTX is reset, the working clock of the high-speed transceiver GTX will be reconfigured, which requires a long time to re-establish the data transmission link. The delay of establishing the link is much greater than the data transmission delay between the daughterboard and the motherboard, and the delay of re-establishing the link is inconsistent and not fixed each time. After the reset is completed, the high-speed transceiver of the motherboard buffers the received data into the corresponding data reception buffer of each daughterboard. After the number of clock cycles T > T0, the motherboard starts to continuously read the received data from the data reception buffer of each daughterboard simultaneously. The data read out is synchronized. This invention realizes high-speed data transmission between boards and solves the problem of data transmission synchronization. Attached Figure Description

[0014] Figure 1 This is a block diagram of the method of the present invention; Detailed Implementation

[0015] The present invention will now be described in detail with reference to the accompanying drawings and embodiments, as follows:

[0016] like Figure 1As shown, the board involved in the method of this invention includes a motherboard and at least two daughterboards (taking four daughterboards as an example below). The motherboard is the data receiver, and the daughterboards are the data transmitters. Data transmission between the motherboard and each daughterboard is performed using a high-speed transceiver GTX, and there is a one-to-one correspondence between the high-speed transceivers GTX between the motherboard and the daughterboards. The method steps are as follows:

[0017] (1) Make the working clock of the daughter board and the motherboard the same; set a transmit buffer FIFO in front of the high-speed transceiver GTX of each daughter board. Each daughter board continuously stores the data to be transmitted into the local transmit buffer. The high-speed transceiver GTX reads the data from the transmit buffer and transmits it. In order to facilitate design and implementation, the data buffer FIFO parameters of each daughter board are set the same.

[0018] (2) Test the data transmission delay t1, t2, t3, t4 from each daughterboard to the motherboard, and take the maximum value max{t1, t2, t3, t4}=T0;

[0019] The data transmission latency from each daughterboard to the motherboard refers to the delay between the FIFO input port of each daughterboard's transmit buffer and the output port of the corresponding high-speed transceiver GTX on the motherboard. Figure 1 The data transmission delay T is shown in the figure. The method for testing the actual data transmission delay between each daughterboard and the motherboard is as follows: The motherboard sends a reset signal, which simultaneously resets the transmit buffer FIFO of each daughterboard and the receive buffer FIFO of the motherboard. After the reset is complete, each daughterboard writes continuously incrementing data into the transmit buffer FIFO. The high-speed transceiver GTX of the daughterboard transmits data, and the delay counter of the motherboard starts counting. When the first data sent by the daughterboard is received from the output port of the high-speed transceiver GTX of the motherboard, the counter stops counting. This count value is the actual data transmission delay from the daughterboard to the motherboard. The data transmission delays from the four daughterboards to the motherboard are obtained in sequence. The unit of transmission delay is the number of clock cycles, and the maximum transmission delay is T0 clock cycles.

[0020] (3) Based on the maximum data transmission delay T0 in step (2), set up a data receiving buffer for each daughterboard after the high-speed transceiver GTX on the motherboard; the size of the data receiving buffer FIFO allocated by the motherboard receiver for each daughterboard must be greater than T0 to ensure that the data receiving buffer FIFO does not overflow.

[0021] (4) Simultaneously reset the data transmission buffer of each daughterboard and the data reception buffer of the motherboard;

[0022] The reset signal is generated by the motherboard, which transmits the reset signal to each daughterboard through hardware pins. If each daughterboard uses its local clock to sample the reset signal, it is difficult for the clocks to be in phase and frequency, making synchronous reset impossible. Therefore, the working clocks of the daughterboard and the motherboard must be from the same source. The motherboard sends clock signals to each daughterboard through hardware pins, and each daughterboard uses the received motherboard clock to work, thus ensuring that the clocks are from the same source.

[0023] Each daughterboard uses the same clock source to sample the reset signal, ensuring synchronization of the reset signals sampled by each daughterboard. During reset, only the data transmit buffer FIFOs of each daughterboard and the data receive buffer FIFOs of the motherboard can be reset; the high-speed transceiver GTX cannot be reset. This is because after a GTX reset, its operating clock needs to be reconfigured, requiring a long time to re-establish the data transmission link. The link establishment delay is much greater than the data transmission delay between the daughterboard and the motherboard, and the link establishment delay is inconsistent each time. Therefore, the high-speed transceiver GTX cannot be reset.

[0024] (5) The high-speed transceiver GTX of each daughterboard reads data from the local transmit buffer and sends it. The high-speed transceiver GTX of the motherboard receives the data sent by the daughterboard and stores it in the corresponding data receive buffer. After the motherboard waits for T>T0 clock cycles, it continuously reads the data of each daughterboard from the local buffer corresponding to each daughterboard to complete the high-speed data synchronization transmission between boards.

[0025] Because the daughterboard continuously stores the data to be sent into the transmit buffer FIFO, after the reset, the high-speed transceiver GTX can read data from the transmit buffer FIFO and send it. The motherboard's high-speed transceiver GTX begins receiving data and stores the received data into the corresponding data receive buffer FIFO of each daughterboard. The motherboard's local timer starts counting after the reset. When the count T > T0, it sends a data read enable signal to the data receive buffer of each daughterboard. Upon receiving the enable signal, the corresponding data buffer FIFO of each daughterboard begins to read data simultaneously from the buffer FIFO. At this time, the read data is completely synchronized.

[0026] The parts of this invention not described in detail are common knowledge to those skilled in the art.

Claims

1. A method for high-speed data synchronization transmission between boards, the method involving boards including a motherboard and at least two daughterboards, the motherboard being a data receiver and the daughterboards being data transmitters, and data transmission between the motherboard and each daughterboard using an independent high-speed transceiver (GTX); characterized in that... Includes the following steps: (1) Make the working clock of the daughter board and the motherboard the same; set a transmit buffer in front of the high-speed transceiver GTX of each daughter board, and each daughter board continuously stores the data to be transmitted into the local transmit buffer. The high-speed transceiver GTX reads the data from the transmit buffer and transmits it. (2) Test the data transmission delay from each daughterboard to the motherboard and obtain the maximum data transmission delay T0; (3) Based on the maximum data transmission delay T0 in step (2), set up a data receiving buffer for each daughterboard after the high-speed transceiver GTX on the motherboard. (4) Simultaneously reset the data transmission buffer of each daughterboard and the data reception buffer of the motherboard; (5) The high-speed transceiver GTX of each daughterboard reads data from the local transmit buffer and sends it. The high-speed transceiver GTX of the motherboard receives the data sent by the daughterboard and stores it in the corresponding data receive buffer. After the motherboard waits for T>T0, it continuously reads the data of each daughterboard from the local buffer corresponding to each daughterboard to complete the high-speed data synchronization transmission between boards.

2. The method for high-speed inter-board data synchronization transmission according to claim 1, characterized in that: The unit of the maximum data transmission delay measured in step (2) is the number of clock cycles, that is, a delay of T0 clock cycles; 3. The method for high-speed inter-board data synchronization transmission according to claim 2, characterized in that: In step (3), the size of the data receiving buffer set for each sub-board is greater than T0.

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