A dedicated interconnect device

Abstract

This invention relates to the field of chip design technology, and in particular to a dedicated interconnect device integrated within a graphics processor. The device includes a dedicated transmission channel comprising a dedicated data format conversion module, a verification and packaging module, and an alignment and allocation module cascaded in sequence, forming a unified transmission and reception path. In the transmission path, data flows sequentially through the dedicated data format conversion module, the verification and packaging module, and the alignment and allocation module. In the reception path, data flows sequentially through the alignment and allocation module, the verification and packaging module, and the dedicated data format conversion module. This dedicated interconnect device can be used for chip-to-chip communication outside of a package, as well as for direct die-to-die connections within an advanced package. It possesses good scalability and versatility, achieving low-latency, high-bandwidth communication.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a dedicated interconnect device. Background Technology

[0002] With the rapid development of artificial intelligence and big data models, the demand for computing power is increasing daily. GPU chips, possessing a vast number of computing cores and powerful instruction sets, are widely used in numerous fields such as artificial intelligence, scientific computing, and aerospace. For AI cluster training and inference tasks, a single GPU is usually insufficient, requiring multiple GPUs to collaborate; and the data needed by the computing engine may reside in the shared memory (global memory) of multiple GPUs. Large-scale model training requires massive parameter synchronization and data exchange, and the speed and efficiency of the interconnect network directly determine the computing power level of the entire computing cluster. Computing units and high-speed interconnect networks together construct supercomputing power, enabling its training efficiency; the increasingly large-scale GPU clusters are essentially designed to overcome the communication bottlenecks of ultra-large-scale AI training. GPUs use load / store operations to enhance the scale-up network within nodes to complete large-block data transmission, building powerful supernodes that minimize the consumption of computing resources while ensuring high-speed and high-efficiency data transmission and exchange. In the supernodes built in scale-up networks, a high-performance, high-speed, versatile, and flexibly configurable interconnect device is needed to tightly couple multiple GPUs and other devices to work together to form a unified and powerful computing unit, achieving extremely low latency and high bandwidth communication.

[0003] Currently, the common bus standard interconnect device, represented by PCIe, is suitable for connecting various devices and components, including graphics cards, storage devices, network cards, video devices, etc. It is widely compatible and scalable, supporting multiple devices to connect simultaneously and transmitting data through the bus architecture. This allows users to connect multiple devices in their computers and easily add or change these devices as needed. However, the common bus also has many drawbacks. First, bandwidth is limited. Because the PCIe interface is based on a bus architecture, multiple devices share the bus bandwidth, which may lead to bandwidth limitations. Especially when connecting high-performance computing devices, bandwidth limitations may have a certain impact on data transmission speed and performance. Secondly, latency is relatively high. Since data is transmitted on the bus, the PCIe interface may introduce a certain transmission latency. For scenarios requiring low latency, such as large-scale clusters or high-performance computing, PCIe may not be the best choice. In addition, PCIe adopts a centralized switching architecture, with all devices connected through a PCIe switch / root federation on the motherboard. This means that communication between PCIe devices usually needs to be forwarded through the CPU, memory, or PCIe switch, resulting in a longer path and more potential bottlenecks.

[0004] In summary, GPU chip scale-up interconnect devices cannot achieve efficient communication with low latency and high bandwidth using general-purpose standard buses. Therefore, there is an urgent need for a scale-up interconnect device suitable for low latency and high bandwidth communication. Summary of the Invention

[0005] To address the aforementioned technical problems, the present invention adopts the following technical solution: a dedicated interconnection device, which is integrated within a graphics processor and includes a dedicated transmission channel. The dedicated transmission channel includes a dedicated data format conversion module, a verification and encapsulation module, and an alignment and allocation module cascaded in sequence, which together constitute a unified transmission path and a reception path.

[0006] In the transmission path, data flows sequentially through the dedicated data format conversion module, the verification and encapsulation module, and the alignment and allocation module.

[0007] The dedicated data format conversion module reassembles the control fields, data payloads, and accompanying signals that conform to the standard bus data format according to the dedicated data format to generate the original data packet that conforms to the dedicated data format.

[0008] The verification and encapsulation module encapsulates the original data packet into a transmission data packet with the fixed transmission format. The encapsulation includes adding a type marker and a checksum to the transmission data packet.

[0009] The alignment and allocation module aligns the transmission data packets and allocates them to multiple logical channels, through which the transmission data packets are sent out via the physical layer.

[0010] In the receiving path, data flows sequentially through the alignment and allocation module, the verification and encapsulation module, and the dedicated data format conversion module.

[0011] The alignment and allocation module identifies the data on the logical channel and reassembles and restores the transmission data packet.

[0012] The verification and encapsulation module identifies the transmitted data packet based on the type marker and verifies the integrity of the original data packet through the check code.

[0013] The dedicated data format conversion module converts the raw data packet into control fields, data payloads, and associated signals that conform to the standard bus data format.

[0014] Furthermore, the present invention also provides a non-transitory computer-readable storage medium storing at least one instruction or at least one program segment, wherein the at least one instruction or the at least one program segment is loaded and executed by a processor to implement the above-described method.

[0015] In addition, the present invention provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.

[0016] The present invention has at least the following beneficial effects:

[0017] This invention provides a dedicated interconnect device that employs a layered design to achieve high-bandwidth, low-latency, and protocol-flexible interconnect capabilities. First, parallel transmit and receive paths are established to support concurrent read and write operations, improving bidirectional throughput efficiency. Second, a dedicated data format conversion module is deployed to dynamically map standard instructions from different devices to a unified dedicated command format, thereby shielding against upper-layer protocol differences. Based on this architecture, the interconnect device can be used for chip-to-chip communication outside of packages, as well as for direct die-to-die connections within advanced packages, exhibiting good scalability and versatility, and achieving low-latency, high-bandwidth communication. Through flexible address translation configuration and rich atomic operation instructions, it can support general switching architectures and expand the network according to user needs. Furthermore, the interconnect device provided by this invention can be directly integrated into chips, dies, etc., serving as a high-speed interconnect interface. It can directly realize multi-GPU integration, loading of larger memory or faster storage, improving computing density and enhancing computing power. Simultaneously, this interconnect device can also be used in conjunction with advanced packaging technologies to interconnect different dies, enabling chips to be packaged in a more economical way. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a dedicated interconnection device provided in an embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Unless otherwise defined, all technical and scientific terms used in the embodiments of this invention have the same meaning as commonly understood by those skilled in the art.

[0022] Please see Figure 1It illustrates a dedicated interconnect device integrated within a graphics processor, including a dedicated transmission channel comprising a dedicated data format conversion module, a verification and encapsulation module, and an alignment and allocation module cascaded in sequence, which together form a unified transmission and reception path.

[0023] Furthermore, in the transmission path, data flows sequentially through the dedicated data format conversion module, the verification and encapsulation module, and the alignment and allocation module.

[0024] Furthermore, the dedicated data format conversion module reassembles the control fields, data payloads, and accompanying signals that conform to the standard bus data format according to the dedicated data format to generate an original data packet that conforms to the dedicated data format;

[0025] The dedicated data format conversion module is used to reassemble and splice the data and control fields of the standard protocol according to the bit layout rules of the proprietary interface.

[0026] In one implementation, the standard bus is the AXI bus. Other types of in-chip bus protocols also fall within the scope of this invention.

[0027] In one implementation, the control field is an address, ID, opcode, etc. Other types of control fields also fall within the scope of protection of this invention.

[0028] In one implementation, the accompanying signal is a write request data control signal, such as data attributes, data length, etc. Other types of control accompanying signals also fall within the scope of protection of this invention.

[0029] The reassembly process includes: checking the accompanying signals; placing the control fields into the specified bits of the original data packet in the dedicated data format according to the definition of the dedicated data format; placing the data into the specified data field of the original data packet; and placing the accompanying signals into the specified bits of the original data packet to obtain the original data packet without verification. This dedicated data format conversion module does not change the semantics of the fields, only the physical distribution, and only performs the reassembly operation without adding a checksum.

[0030] As an example,

[0031] Furthermore, the verification and encapsulation module encapsulates the original data packet into a transmission data packet with the fixed transmission format. The encapsulation includes adding a type marker and a checksum to the transmission data packet.

[0032] The verification and encapsulation module is used to add check codes and type markers, making the generated transmission data packets more standardized, and the check codes increase reliability.

[0033] In one implementation, the verification method is as follows: CRC or Parity is calculated for the entire original data packet, and ECC verification is used for BUF access of the data packet during transmission.

[0034] In one implementation, the verification method is configured through a configuration management module.

[0035] As an example, two bits are used to represent different type markers. For instance, 00 represents the first packet type, 01 represents the second packet type, 10 represents the third packet type, and 11 represents the fourth packet type.

[0036] In one implementation, the length of the transmitted data packet is fixed. It should be noted that this is achieved by segmenting or padding the data packet to form a fixed-length transmitted data packet.

[0037] Furthermore, the alignment and allocation module aligns the transmission data packets and allocates them to multiple logical channels, through which the transmission data packets are sent out via the physical link;

[0038] The alignment and allocation module needs to package logically arbitrary commands and data streams into a serial transmission data format suitable for multiple lanes in parallel; the receiving operation is the reverse.

[0039] Each instruction or data unit has its own start and end positions, but may begin from any byte offset; that is, each instruction or data unit has its own independent data boundary. Similarly, the parallel bus of the physical interface also has its fixed width, i.e., the bus boundary. Data alignment realizes the transformation of independent data boundaries into the bus boundary of the interconnection protocol. The purpose of alignment is to align irregular data units onto the bus and avoid cross-step misalignment.

[0040] In one implementation, the alignment and allocation steps include: sequentially concatenating multiple data packets into a continuous data stream, then slicing it according to the bus width, with each slice occupying one bus cycle; and allocating the sliced ​​data byte-by-byte to each lane. It should be noted that the alignment operation is completed after slicing according to the bus width, and the allocation step is completed after allocating the sliced ​​data byte-by-byte to each lane.

[0041] Furthermore, in the receiving path, data flows sequentially through the alignment and allocation module, the verification and encapsulation module, and the dedicated data format conversion module.

[0042] Furthermore, the alignment and allocation module identifies the data on the logical channel and reassembles and restores the transmission data packet.

[0043] Specifically, the process involves identifying and reassembling data on logical channels, separating the data packet type identifier and command data, decomposing the serial data stream into independent data, and restoring the data boundaries. On the receiving side, data is first sampled in parallel from multiple logical channels and reassembled into a full-width bus data stream. From this bus data stream, the type identifier and command data are separated and decomposed into independent data, restoring the data boundaries of each data packet.

[0044] Furthermore, the verification and encapsulation module identifies the transmitted data packet based on the type marker and verifies the integrity of the original data packet using a checksum. Specifically, the verification and encapsulation module identifies the type identifier of the data packet, then performs Parity or CRC checks on the data to verify the integrity of the data packet, and forwards it to the next layer.

[0045] Furthermore, the dedicated data format conversion module converts the original data packet into control fields, data payload, and accompanying signals conforming to the standard bus data format. The receiving channel performs the reverse conversion process compared to the transmitting channel. Specifically, it extracts the checksum and control information from the data packet and places them in the accompanying signal positions conforming to the standard bus data format, converting all data in the data packet into an output conforming to the standard bus data format. This dedicated data format conversion module stores some of the control information from the output data for use in converting corresponding received data.

[0046] In summary, this invention provides a dedicated interconnect device that employs a layered design to achieve high-bandwidth, low-latency, and protocol-flexible interconnect capabilities. First, at the link layer, parallel transmit and receive paths are established to support concurrent read and write operations, improving bidirectional throughput efficiency. Second, at the transaction layer, a dedicated data format conversion module is deployed, dynamically mapping standard instructions from different devices to a unified dedicated command format, thereby shielding against upper-layer protocol differences. Thanks to this architecture, the interconnect system can be used for both chip-to-chip communication outside of packages and direct die-to-die connections within advanced packages, exhibiting excellent scalability and versatility. Flexible address translation configurations and rich atomic operation instructions support general switching architectures, allowing for network expansion according to user needs. Furthermore, the interconnect device provided by this invention can be directly integrated into chips, dies, etc., serving as a high-speed interconnect interface. It can directly enable multi-GPU integration, loading of larger memory or faster storage, increasing computing density and enhancing computing power. Simultaneously, this interconnect device can be combined with advanced packaging technologies to interconnect different dies, enabling chips to be packaged in a more economical way.

[0047] In one embodiment, the device further includes a parameter configuration module, which is used to activate the dedicated transmission channel or the standard transmission channel through channel selection parameters; the standard transmission channel is used to transmit standard data packets conforming to the standard bus protocol. It should be noted that the dedicated interconnect device provided in this embodiment can flexibly adapt to both dedicated and standard transmission channels.

[0048] In one implementation, the channel selection parameters include dedicated host mode parameters, dedicated slave mode parameters, dedicated dual-mode parameters, and standard mode parameters. When the dedicated host mode parameter is valid, the transmitting path in the dedicated transmission channel is activated; when the dedicated slave mode parameter is valid, the receiving path in the dedicated transmission channel is activated; and when the dedicated dual-mode parameter is valid, both the transmitting and receiving paths in the dedicated transmission channel are activated simultaneously. It should be noted that when both the transmitting and receiving paths are activated simultaneously, these two paths can execute in parallel.

[0049] In one embodiment, the device further includes a physical layer. In the transmission path, data flows sequentially through the dedicated data format conversion module, the verification and encapsulation module, the alignment and allocation module, and the physical layer. The physical layer, based on the mapping relationship between logical channels and physical channels, sends the transmission data packets on the logical channel out through the corresponding physical channel. In the reception path, data flows sequentially through the physical layer, the alignment and allocation module, the verification and encapsulation module, and the dedicated data format conversion module. The physical layer receives the transmission data packets in the physical channel and, based on the mapping relationship between logical channels and physical channels, sends the transmission data packets on the logical channel to the alignment and allocation module through the corresponding logical channel.

[0050] In one embodiment, the dedicated transmission channel further includes a configuration management module. In the transmission path, data flows sequentially through the configuration management module, the dedicated data format conversion module, the verification and encapsulation module, and the alignment and allocation module. The configuration management module is used to configure a set of indirect read / write registers to generate the standard data packet, and can directly send the standard data packet from the current module to the next-level module for processing. In the receiving path, data flows sequentially through the alignment and allocation module, the verification and encapsulation module, and the configuration management module. The configuration management module is used to receive the transmission data packet sent by the verification and encapsulation module, convert the transmission data packet into the standard data packet, and send the standard data packet uplink to the original command triggering unit. This configuration management module's ability to directly drive the generation of standard instructions allows for flexible device configuration and debugging, increasing user convenience. The configuration management module supports AXI and APB standard interface conversion.

[0051] In one embodiment, the device further includes: a standard data conversion module; data flows sequentially through the command conversion module and the parameter configuration module before entering the dedicated transmission channel or the standard transmission channel; the command conversion module is configured to: in the output direction, logically map the transmission address, the unique identifier of the transaction, and the accompanying signals, and encode the operation type to generate a control field conforming to the standard bus protocol. In the input direction, it identifies the received instruction encoding, remaps the address and the unique identifier of the transaction, and simultaneously parses the accompanying signals.

[0052] Specifically, this standard data conversion module handles both input and output data or commands. For the transmitting path, it receives and performs transmission address mapping, transaction unique identifier mapping, and associated signal mapping, as well as command encoding assignment. For example, the input transmission address "0x1000" is mapped to "0x8000_1000", the transaction unique identifier "03" is mapped to "0x23", the associated signal "2" is mapped to "0x8", and the command "WRITE" is mapped to "AWSIZE=2, AWLEN=0", etc. For the receiving path, it performs address remapping (re-mapping) of data or commands, transaction unique identifier remapping (re-mapping), parsing of associated signals, and command encoding recognition. Simultaneously, this standard data conversion module can serve as a universally applicable interface module for dedicated interconnect devices. Users only need to convert their proprietary commands and data transmission requirements into read / write commands conforming to the standard bus protocol and connect them to the standard data conversion module to achieve compatibility with proprietary interconnect devices, making them universal.

[0053] In one embodiment, the dedicated transmission channel further includes a classification-based active flow control management module, which is connected to both the dedicated data format conversion module and the verification and encapsulation module. For the dedicated data format conversion module, the classification-based active flow control management module generates corresponding flow control signals based on different types of data packets. These flow control signals are sent to the dedicated data format conversion module to control whether it continues to output data. For the verification and encapsulation module, the active flow control management module feeds back flow control information to the upper layer based on the flow control status generated during the data verification and encapsulation process, affecting the active flow control results of the upper layer.

[0054] In one embodiment, the device further includes a clock reset management module, which provides clock and reset signals to the physical layer, dedicated transmission channel, and standard data conversion module, respectively. The physical layer inputs the clock recovered from the serial data stream to the clock reset management module. The clock reset management module processes the reference clock, SoC clock, auxiliary clock, and DFT clock using BUF, CG (clock gating), and Mux operations to provide appropriate clocks for each module. The resets include power-on reset, button reset, sideband signal reset, configuration reset, and DFT reset. These reset signals undergo CDC and Mux operations to generate appropriate reset signals that are input to each module.

[0055] In one embodiment, the device further includes an instruction parsing and conversion module. This module includes an instruction parsing and execution module and a read / write command conversion module. The instruction parsing and execution module interprets various instructions, while the read / write command conversion module converts each instruction into commands and interfaces conforming to the standard bus data format. On the transmitting side, upon receiving various instructions from the driver, the parsing and conversion module parses the instructions into read / write commands. These commands are broadly categorized as read / write commands and encapsulated by the read / write command conversion module, including encapsulating various special instructions, and transmitting them downwards as commands conforming to the standard bus data format. Similarly, the reverse process is performed to obtain the status and result after command execution. Based on different instructions, information transmitted via accompanying signals is parsed, recorded, and available for driver querying. The instruction parsing and conversion module uniformly converts dedicated control commands that exchange or modify data and control parameters into standard read / write access to memory-mapped registers.

[0056] It should be noted that the interconnect device provided by this invention includes the functions required for GPU network scale-up interconnection, enabling interconnection between chips, between dies, between chips and memory, and between GPUs and CPUs. Furthermore, this interconnect device can be configured to use either a standard transmission channel or a dedicated transmission channel to adapt to different application scenarios. This invention employs a standard bus interface compliant with the aforementioned standard and a dedicated transmission channel, and uses a dedicated data format conversion module for format conversion, enabling rich custom instructions. It is not only suitable for dedicated chip interconnection but can also serve as a general-purpose interconnect device to provide interconnection functionality for various types of GPU chips.

[0057] Embodiments of the present invention also provide a non-transitory computer-readable storage medium that can be disposed in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiments, wherein the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiments.

[0058] Embodiments of the present invention also provide an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0059] Embodiments of the present invention also provide a computer program product including program code, which, when the program product is run on an electronic device, causes the electronic device to perform the steps of the methods described above in various exemplary embodiments of the present invention.

[0060] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0061] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A dedicated interconnection device, characterized in that, The device is integrated within the graphics processor and includes a dedicated transmission channel. This dedicated transmission channel comprises a dedicated data format conversion module, a verification and encapsulation module, and an alignment and allocation module, which are cascaded together to form a unified transmission and reception path. In the transmission path, data flows sequentially through the dedicated data format conversion module, the verification and encapsulation module, and the alignment and allocation module: The dedicated data format conversion module reassembles the control fields, data payloads, and accompanying signals that conform to the standard bus data format according to the dedicated data format to generate the original data packet that conforms to the dedicated data format. The verification and encapsulation module encapsulates the original data packet into a transmission data packet with a fixed transmission format. The encapsulation includes adding a type marker and a checksum to the transmission data packet. The alignment and allocation module aligns the transmission data packets and allocates them to multiple logical channels, through which the transmission data packets are sent out via the physical layer; In the receiving path, data flows sequentially through the alignment and allocation module, the verification and encapsulation module, and the dedicated data format conversion module: The alignment and allocation module identifies the data on the logical channel and reassembles and restores the transmitted data packets; The verification and encapsulation module identifies the transmitted data packet based on the type marker and verifies the integrity of the original data packet through the check code. The dedicated data format conversion module converts the raw data packet into control fields, data payloads, and associated signals that conform to the standard bus data format.

2. The apparatus according to claim 1, characterized in that, The device also includes a parameter configuration module, which is used to activate the dedicated transmission channel or the standard transmission channel through channel selection parameters; the standard transmission channel is used to transmit standard data packets that conform to the standard bus protocol.

3. The apparatus according to claim 1, characterized in that, The channel selection parameters include dedicated host mode parameters, dedicated slave mode parameters, dedicated dual-mode parameters, and standard mode parameters. When the dedicated host mode parameter is valid, the transmitting path in the dedicated transmission channel is activated; when the dedicated slave mode parameter is valid, the receiving path in the dedicated transmission channel is activated; when the dedicated dual-mode parameter is valid, both the transmitting path and the receiving path in the dedicated transmission channel are activated simultaneously.

4. The apparatus according to claim 1, characterized in that, The device also includes a physical layer; In the transmission path, data flows sequentially through the dedicated data format conversion module, the verification and encapsulation module, the alignment and allocation module, and the physical layer: The physical layer sends the data packets on the logical channel out through the corresponding physical channel according to the mapping relationship between the logical channel and the physical channel; In the receiving path, data flows sequentially through the physical layer, the alignment and allocation module, the verification and encapsulation module, and the dedicated data format conversion module: The physical layer receives the transmission data packets in the physical channel and, according to the mapping relationship between the logical channel and the physical channel, sends the transmission data packets on the logical channel to the alignment and allocation module through the corresponding logical channel.

5. The apparatus according to claim 1, characterized in that, The dedicated transmission channel also includes: a configuration management module; In the transmission path, data flows sequentially through the configuration management module, the dedicated data format conversion module, the verification and encapsulation module, and the alignment and allocation module, wherein: the configuration management module is used to configure a set of indirect read and write register groups to generate the standard data packet; In the receiving path, data flows sequentially through the alignment and allocation module, the verification and encapsulation module, and the configuration management module; wherein: the configuration management module is used to receive the transmission data packet sent by the verification and encapsulation module and convert the transmission data packet into the standard data packet.

6. The apparatus according to claim 1, characterized in that, The device further includes: a standard data conversion module; Data flows sequentially through the command conversion module and the parameter configuration module before entering the dedicated transmission channel or the standard transmission channel. The command conversion module is configured as follows: In the output direction, the transmission address, the unique identifier of the transaction, and the accompanying signals are logically mapped, and the operation type is encoded into instructions to generate control fields that conform to the standard bus protocol. In the input direction, the received instruction code is identified, and the unique identifier of the address and transaction is remapped, while the accompanying signals are parsed.

7. The apparatus according to claim 1, characterized in that, The dedicated transmission channel also includes a classification-based active flow control management module, which is connected to the dedicated data format conversion module and the verification and encapsulation module, respectively. The classification-based active flow control management module is configured to generate corresponding flow control signals based on different types of data packets in the dedicated data format conversion module. These flow control signals are then sent to the dedicated data format conversion module to control whether it continues to output data. The classification-based proactive flow control management module is configured to: based on the congestion status of the verification and encapsulation module, send a flow control instruction to the upper-level module to suspend or restrict its submission of new data or commands to the verification and encapsulation module.

8. The apparatus according to claim 1, characterized in that, The device also includes a clock reset management module, which provides clock and reset signals to the physical layer, the dedicated transmission channel, and the standard data conversion module, respectively.

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