Memory module
By introducing multiple master chips and DIMMs into the memory module and interconnecting with external devices using the CXL interface, the problem of insufficient memory capacity expansion of existing memory modules is solved, and higher memory capacity and system performance are achieved.
Patent Information
- Application Number
- CN202420700927.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-07
- Publication Date
- 2025-03-18
- Estimated Expiration
- 2034-04-07
AI Technical Summary
The memory capacity of existing memory modules is not very expanded, making it difficult to meet the growing computing needs.
A memory module is designed, including at least two main control chips and a dual inline memory module (DIMM). Each main control chip is connected to the DIMM through the DDR controller interface and connected to external devices through the CXL interface to realize resource sharing and memory expansion.
By increasing the number of main control chips and DIMMs, the memory capacity of the memory module is significantly improved, which meets higher computing needs, and interconnects with external devices through the CXL interface to improve system performance.
Smart Images
Figure CN222636633U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of memory chips, and in particular to a memory module. Background Art
[0002] With the continuous development of computer technology, the demand for memory capacity is increasing. Compute Express Link (CXL) is currently supported as a cache coherent interconnect protocol for memory expansion. CXL technology maintains consistency between the CPU memory space and the memory on the attached device, and allows resource sharing for higher performance. For example, a CXL accelerator card (CXL Accelerator Card, CXL AIC) typically includes a high-speed interface that supports the CXL protocol, which can be integrated into a server or computing platform that supports CXL to enhance performance in computing, storage, or networking, and is used to expand memory, accelerate GPUs, or accelerate other types of hardware. However, the memory capacity expansion degree of existing memory modules, such as CXL AIC memory modules, is not high. Utility Model Content
[0003] In view of this, it is necessary to provide a memory module to solve the technical problem of insufficient memory capacity expansion of the memory module.
[0004] An embodiment of the present application provides a memory module, which includes: at least two master control chips and a dual in-line memory module DIMM, each master control chip is connected to the DIMM through a first double data rate DDR controller interface, and a computing fast link CXL interface of one of the at least two master control chips is connected to an external device through a MCIO connector, and the CXL interface is a MCIO interface.
[0005] The technical effects of the embodiments of the present application include: each of the at least two main control chips in the memory module is connected to the DIMM through a first double data rate DDR controller interface, thereby realizing the expansion connection of the main control chip to the DIMM, and at the same time interacting with an external device through the MCIO interface of one of the at least two main control chips, thereby improving the memory capacity of the memory module.
[0006] In some embodiments of the present application, the DDR controller interface includes a first preset number of fourth-generation double data rate DDR4 controller interfaces or fifth-generation double data rate DDR5 controller interfaces.
[0007] In some embodiments of the present application, the fourth-generation double data rate DDR4 controller interface includes a fourth-generation double data rate unbuffered dual in-line memory module DDR4 UDIMM, and / or, a fourth-generation double data rate registered dual in-line memory module DDR4 RDIMM, the fourth-generation double data rate DDR4 controller interface; the fifth-generation double data rate DDR5 controller interface includes a fifth-generation double data rate unbuffered dual in-line memory module DDR5UDIMM, and / or, a fifth-generation double data rate registered dual in-line memory module DDR5 RDIMM.
[0008] In some embodiments of the present application, the bandwidth bit number of each main control chip includes 8 bits and / or 16 bits.
[0009] In some embodiments of the present application, each of the master control chips is connected to a second preset number of DIMMs via the DDR controller interface.
[0010] In some embodiments of the present application, the MCIO interface is a PCIE interface that supports the PCIE protocol of the peripheral device interconnect bus and supports an X8 channel or an X16 channel.
[0011] In some embodiments of the present application, the memory module further includes at least two non-volatile flash memories Nor flash, the main control chip is connected to the corresponding Nor flash via an SPI interface, and the Nor flash is used to store the firmware of the main control chip.
[0012] In some embodiments of the present application, the MCIO connector is plugged into the MCIO interface to provide a reset signal for the main control chip.
[0013] In some embodiments of the present application, each of the master control chips is connected to the external device via the MCIO connector, and the MCIO connector includes a MCIO X8 connector or a MCIO X16 connector.
[0014] In some embodiments of the present application, the memory module further includes a first power connector, which is connected to a second power connector of the external device and is used to provide power input to the memory module. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 A schematic diagram of the structure of a memory module in an embodiment is shown.
[0016] Figure 2 A schematic diagram of the structure of a memory module in another embodiment is shown.
[0017] Main component symbols
[0018] Memory module 10
[0019] Main control chip 101
[0020] The first main control chip 1011
[0021] The second main control chip 1012
[0022] DIMM 102
[0023] First DIMM 1021
[0024] Second DIMM 1022
[0025] MCIO connector 103
[0026] First MCIO connector 1031
[0027] Second MCIO connector 1032
[0028] Nor flash 104
[0029] First Nor flash 1041
[0030] Second Nor flash 1042
[0031] First Power Connector 105
[0032] External device 20
[0033] The third MCIO connector 201
[0034] Fourth MCIO Connector 2011
[0035] Fifth MCIO Connector 2012
[0036] Second Power Connector 202
[0037] The following specific embodiments will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION
[0038] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.
[0039] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time.
[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "or / and" used herein includes any and all combinations of one or more related listed items.
[0041] Some embodiments of the present application will be described in detail below with reference to the accompanying drawings.
[0042] Compute Express Link (CXL) is the currently supported cache coherent interconnect protocol for memory expansion. There are three types of existing CXL protocols: Type 1, Type 2, and Type 3. Type 1 is commonly used in cache devices such as network cards, and usually only supports io and cache protocols. Type 2 is a memory accelerator commonly used in applications such as GPUs and AI, and usually supports io, cahce, and memory protocols. Type 3 is commonly used in memory buffers and is used to expand memory bandwidth or memory capacity. Type 3 supports both io and memory protocols. This application involves how to increase the memory capacity of a type 3 memory expansion controller chip.
[0043] The appearance of the memory module 10 involved in the present application is a preset appearance, and the preset appearance dimensions are based on the appearance dimensions of a standard add-in card (Accelerator Card, AIC). For example, the preset appearance dimensions can be set to 3 / 4 length, equal height, and double width of an AIC card. The memory module 10 can be inserted into a PCIE slot that supports a CXL protocol platform for application.
[0044] See also Figure 1The embodiment of the present application provides a memory module 10, the memory module 10 comprising: at least two master chips 101 and a dual inline memory module (DIMM). Each master chip 101 is connected to the DIMM 102 via a first double data rate (DDR) controller interface. A compute express link (CXL) interface of one of the at least two master chips 101 is connected to an external device 20 via an MCIO connector 103, and the CXL interface is an MCIO interface.
[0045] In some embodiments of the present application, since the signal attenuation speed of the MCIO interface is slow and the signal stability is strong, each main control chip 101 of the memory module 10 is connected to the DIMM 102 through the first double data rate DDR controller interface, so that the main control chip 101 is extended to connect to the DIMM 102. At the same time, at least one of the two main control chips 101 is connected to the external device 20 through the MCIO interface for interaction, thereby improving the memory capacity of the memory module 10.
[0046] In some embodiments of the present application, the main control chip 101 is a memory expansion controller (Memory Expander Controller, MXC) chip, and the external device 20 can be a server motherboard, which is not limited in this embodiment.
[0047] In some embodiments of the present application, the DDR controller interface includes a first preset number of fourth-generation double data rate DDR4 controller interfaces or fifth-generation double data rate DDR5 controller interfaces.
[0048] In some embodiments of the present application, the first preset number of DDR controller interfaces can be set in advance according to memory expansion requirements, which is not limited in this embodiment. For example, the first preset number can be set to one or more of the following combinations: 1, 2, 4.
[0049] In some embodiments of the present application, the fourth-generation double data rate DDR4 controller interface includes a fourth-generation double data rate unbuffered dual in-line memory module DDR4 UDIMM, and / or, a fourth-generation double data rate registered dual in-line memory module DDR4 RDIMM, the fourth-generation double data rate DDR4 controller interface; the fifth-generation double data rate DDR5 controller interface includes a fifth-generation double data rate unbuffered dual in-line memory module DDR5UDIMM, and / or, a fifth-generation double data rate registered dual in-line memory module DDR5 RDIMM.
[0050] In some embodiments of the present application, the memory module 10 may include at least two main control chips 101, and at least two main control chips 101 support DDR4 and DDR5 protocols, thereby improving the adaptability of the memory module 10 and maximizing the memory capacity of the memory module 10.
[0051] In some embodiments of the present application, the bandwidth bit number of each main control chip 101 includes 8 bits and / or 16 bits.
[0052] In some embodiments of the present application, the number of bandwidth bits of each master control chip 101 is 8, indicating an 8-bit CXL signal, and the number of bandwidth bits of each master control chip 101 is 16, indicating a 16-bit CXL signal. This embodiment does not limit the number of bandwidth bits. For example, the number of bandwidth bits of each master control chip 101 can be set according to memory expansion requirements.
[0053] In some embodiments of the present application, each of the master control chips 101 is connected to a second preset number of DIMMs 102 through the DDR controller interface. This embodiment does not limit the second preset number. For example, the second preset number can be set to one of 1, 2 or 4.
[0054] In some embodiments of the present application, the MCIO interface is a PCIE interface that supports the external device interconnection bus PCIE protocol and supports X8 channel or X16 channel, which improves the adaptability of the memory module 10. At the same time, due to the high data transmission efficiency of the PCIE interface, the performance of the memory module 10 can be better improved through the PCIE interface.
[0055] In some embodiments of the present application, CXL communication between the main control chip 101 and the external device 20 is implemented through the MCIO interface.
[0056] In some embodiments of the present application, the memory module 10 further includes at least two non-volatile flash memories (Nor flash), the main control chip 101 is connected to the corresponding Nor flash 104 via an SPI interface, and the Nor flash 104 is used to store the firmware of the main control chip 101 .
[0057] In some embodiments of the present application, the MCIO connector 103 is plugged into the MCIO interface to provide a reset signal for the main control chip 101 .
[0058] In some embodiments of the present application, each of the main control chips 101 is connected to the external device 20 via the MCIO connector 103 , and the MCIO connector 103 includes a MCIO X8 connector or a MCIO X16 connector.
[0059] In some embodiments of the present application, each of the master control chips 101 is connected to the third MCIO connector 201 of the external device 20 through the MCIO connector 103 .
[0060] In some embodiments of the present application, see Figure 2 As shown, for example, the memory module 10 can select a first main control chip 1011 and a second main control chip 1012 with a 16-bit bandwidth. The first main control chip 1011 is connected to the first DIMM 1021 through the DDR controller interface, the CXL interface of the first main control chip 1011 is connected to the fourth MCIO connector 2011 of the external device through the first MCIO connector 1031, and the first main control chip 1011 is connected to the first Nor flash 1041 through the SPI interface; the second main control chip 1012 is connected to the second DIMM 1022 through the DDR controller interface, the CXL interface of the second main control chip 1012 is connected to the fifth MCIO connector 2012 of the external device through the second MCIO connector 1032, and the second main control chip 1012 is connected to the second Nor flash 1042 through the SPI interface, and the DDR controller interface can support external expansion of 16 first DIMMs 1021 and 16 second DIMMs 1022, thereby increasing the memory capacity of the memory module 10.
[0061] In some embodiments of the present application, the memory module 10 further includes a first power connector 105 , which is connected to a second power connector 202 of the external device for providing power input to the memory module 10 .
[0062] Those skilled in the art should recognize that the above embodiments are only used to illustrate the present application, and are not used as limitations on the present application. As long as they are within the spirit of the present application, appropriate changes and modifications to the above embodiments are within the scope of the present application.
Claims
1. A memory module, characterized in that: The memory module includes: at least two main control chips and a dual in-line memory module DIMM, each main control chip is connected to the DIMM through a first double data rate DDR controller interface, a computing fast link CXL interface of one of the at least two main control chips is connected to an external device through an MCIO connector, and the CXL interface is a MCIO interface.
2. The memory module according to claim 1, wherein: The DDR controller interface includes a first preset number of fourth-generation double data rate DDR4 controller interfaces or fifth-generation double data rate DDR5 controller interfaces.
3. The memory module according to claim 2, wherein: The fourth-generation double data rate DDR4 controller interface includes a fourth-generation double data rate unbuffered dual in-line memory module DDR4 UDIMM, and / or a fourth-generation double data rate registered dual in-line memory module DDR4 RDIMM, the fourth-generation double data rate DDR4 controller interface; the fifth-generation double data rate DDR5 controller interface includes a fifth-generation double data rate unbuffered dual in-line memory module DDR5 UDIMM, and / or a fifth-generation double data rate registered dual in-line memory module DDR5RDIMM.
4. The memory module according to claim 1, wherein: The bandwidth bit number of each main control chip includes 8 bits and / or 16 bits.
5. The memory module according to claim 1, wherein: Each of the main control chips is connected to a second preset number of DIMMs via the DDR controller interface.
6. The memory module according to claim 1, wherein: The MCIO interface is a PCIE interface that supports the PCIE protocol of the peripheral device interconnection bus and supports an X8 channel or an X16 channel.
7. The memory module according to claim 1, wherein: The memory module also includes at least two non-volatile flash memories Nor flash, the main control chip is connected to the corresponding Nor flash via an SPI interface, and the Nor flash is used to store the firmware of the main control chip.
8. The memory module according to claim 1, wherein: The MCIO connector is plugged into the MCIO interface and is used to provide a reset signal for the main control chip.
9. The memory module according to claim 1, wherein: Each of the main control chips is connected to the external device via the MCIO connector, and the MCIO connector includes a MCIO X8 connector or a MCIO X16 connector.
10. The memory module according to claim 1, wherein: The memory module also includes a first power connector, which is connected to a second power connector of the external device and is used to provide power input to the memory module.