Constant current source generating circuit, row driving circuit, driving chip, display panel and device

Abstract

The utility model provides a constant current source generation circuit, a row driving circuit, a driving chip, a display panel and a device. The constant current source generation circuit comprises a reference current generation unit used for switching an adjustment mode of a reference current according to a control signal, and generating and outputting the reference current with an adjustable current value according to the determined adjustment mode, the adjustment mode comprising determining the reference current according to a reference voltage and an external resistor or determining the reference current according to a built-in current source; the driving unit comprises a first current mirror group, is connected with the reference current generating unit and is used for outputting driving voltage and bias voltage of the first current mirror group; and the channel current output unit comprises a second current mirror group, the first current mirror group and the second current mirror group are matched to form a current mirror, the driving voltage and the bias voltage are provided for the second current mirror group, and the current mirror is used for carrying out mirror image processing on the reference current so as to output constant current source channel current. According to the invention, the current value adjusting range of the constant current source channel current is improved.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of integrated circuits, and particularly relates to a constant current source generating circuit, a row driving circuit, a driving chip, a display panel, and a device. Background Art

[0002] The row drive circuit of an LED display device includes a constant current source generating circuit, which is used to generate a constant current source channel current for transmission to the LED display panel through the corresponding drive channel, thereby driving the corresponding pixel unit. Most constant current source generating circuits are divided into three parts: a reference current generating circuit, a current mirror circuit, and a current output circuit. The reference current generating circuit uses a built-in reference voltage and an external resistor to generate a reference current. The current mirror circuit mirrors the reference current according to the current mirror ratio to obtain a mirror current. The current output circuit generates and drives the output constant current source channel current. Typically, in existing constant current source generating circuits, the mirror ratio of the current mirror is fixed. Often, the value of the reference current, and thus the value of the output constant current source channel current, can only be adjusted by adjusting the resistance value of the external resistor. This results in a single method for adjusting the constant current source channel current in the constant current source generating circuit, which is limited by the resistance value adjustment range of the external resistor, reducing the current value adjustment range of the constant current source channel current. Utility Model Content

[0003] In view of the above problems, the present disclosure provides a constant current source generating circuit, a row driving circuit, a driving chip, a display panel and a device, which aims to flexibly adjust the reference current by switching the reference current adjustment method and then adjust the current value of the constant current source channel current, thereby improving the current value adjustment range of the constant current source channel current.

[0004] According to a first aspect of the present disclosure, there is provided a constant current source generating circuit, comprising:

[0005] a reference current generating unit, configured to switch an adjustment mode of the reference current according to a control signal, and generate and output a reference current with an adjustable current value according to the determined adjustment mode, wherein the adjustment mode includes determining the reference current according to a reference voltage and an external resistor or determining the reference current according to a built-in current source;

[0006] a driving unit, comprising a first current mirror group, connected to the reference current generating unit, and configured to output a driving voltage and a bias voltage of the first current mirror group;

[0007] The channel current output unit includes a second current mirror group. The first current mirror group and the second current mirror group cooperate to form a current mirror, provide the driving voltage and bias voltage to the second current mirror group, and use the current mirror to mirror the reference current to output the constant current source channel current.

[0008] Optionally, the reference current generating unit includes: an adjustment module, the external resistor and the built-in current source,

[0009] The adjustment module is configured to apply the reference voltage to the external resistor and determine the reference current as a current value flowing through the external resistor when the control signal is at a first value.

[0010] When the control signal is at a second value, the reference current is determined to be a current value output by the built-in current source.

[0011] Optionally, the reference current generating unit further includes: a first transistor; the adjustment module includes a first operational amplifier, a first switch to a fifth switch;

[0012] A first end of the first switch receives the reference voltage, a first end of the second switch receives the first reference voltage, a second end of the first switch and a second end of the second switch are connected in parallel to a first input end of the first operational amplifier, a first end of the third switch is connected to a second input end of the first operational amplifier, an output end of the first operational amplifier provides the driving voltage, a second end of the third switch is connected to a first path end of the first transistor, a second path end of the first transistor is connected to a first end of the external resistor, a first end of the fourth switch is connected to a first connection node between the second path end of the first transistor and the first end of the external resistor, a second end of the fourth switch is connected to the second input end of the first operational amplifier, a first end of the fifth switch is connected to a first end of the built-in current source, and a second end of the fifth switch is connected to a second end of the third switch;

[0013] When the control signal is at a first value, the first switch and the fourth switch are closed, and the second switch, the third switch and the fifth switch are opened;

[0014] When the control signal has a second value, the first switch and the fourth switch are opened, and the second switch, the third switch, and the fifth switch are closed.

[0015] Optionally, the first current mirror group includes a plurality of second transistors, and the driving unit further includes a second operational amplifier.

[0016] The control terminals of the plurality of second transistors are all connected to the output terminal of the first operational amplifier to receive the driving voltage, the first path terminals are all connected to the power supply, and the second path terminals are all connected to the second terminal of the third switch.

[0017] The first input terminal of the second operational amplifier receives a second reference voltage, and the second input terminal of the second operational amplifier is connected to a second connection node between the second path terminals of the plurality of second transistors and the second terminal of the third switch.

[0018] Wherein, when the control signal is a first value, the second reference voltage is provided as the bias voltage to the second pass terminals of the plurality of second transistors;

[0019] When the control signal has a second value, the first reference voltage is provided as the bias voltage to the second pass terminals of the plurality of second transistors.

[0020] Optionally, the driving unit further includes a buffer, an input end of the buffer is connected to a third connection node between the control ends of the plurality of second transistors and the output end of the first operational amplifier, and an output end of the buffer outputs the driving voltage.

[0021] Optionally, the second current mirror group includes a plurality of third transistors, and the channel current output unit further includes a third operational amplifier and a fourth transistor.

[0022] The first input terminal of the third operational amplifier is connected to the second path terminals of the plurality of second transistors to receive the bias voltage.

[0023] The control terminals of the plurality of third transistors are all connected to the output terminal of the buffer to receive the driving voltage, the first path terminals are all connected to the power supply, and the second path terminals are all connected to the second input terminal of the third operational amplifier to receive the bias voltage.

[0024] The control end of the fourth transistor is connected to the output end of the third operational amplifier, the first path end is connected to the second input end of the third operational amplifier and the fourth connection node of the second path ends of the multiple third transistors, and the second path end is used to output the constant current source channel current.

[0025] According to a second aspect of the present disclosure, a row driving circuit is provided, comprising: the constant current source generating circuit as described above.

[0026] According to a third aspect of the present disclosure, a driver chip for a display panel is provided, comprising:

[0027] a reference current generating unit, configured to switch an adjustment mode of the reference current according to a control signal, and generate and output a reference current with an adjustable current value according to the determined adjustment mode, wherein the adjustment mode includes determining the reference current according to a reference voltage and an external resistor or determining the reference current according to a built-in current source;

[0028] a driving unit, comprising a first current mirror group, connected to the reference current generating unit, and configured to output a driving voltage and a bias voltage of the first current mirror group;

[0029] The channel current output unit includes a second current mirror group. The first current mirror group and the second current mirror group cooperate to form a current mirror, provide the driving voltage and bias voltage to the second current mirror group, and use the current mirror to mirror the reference current to output the constant current source channel current.

[0030] According to a fourth aspect of the present disclosure, there is provided a display panel, comprising:

[0031] A plurality of pixels are arranged in an array, wherein a constant current source channel current is generated by the constant current source generating circuit as described above and transmitted to the display panel through a corresponding driving channel, thereby driving the corresponding pixels.

[0032] According to a fifth aspect of the present disclosure, there is provided a display device, comprising:

[0033] Display panel;

[0034] Column driver circuit;

[0035] The row driving circuit as described above.

[0036] The present disclosure brings the following beneficial effects:

[0037] In the constant current source generating circuit provided by the present disclosure, the reference current generating unit switches the adjustment mode of the reference current according to a control signal, generates and outputs a reference current with an adjustable current value according to the determined adjustment mode, wherein the adjustment mode includes determining the reference current according to a reference voltage and an external resistor or determining the reference current according to a built-in current source, the driving unit outputs the driving voltage and bias voltage of the first current mirror group, the channel current output unit provides the driving voltage and bias voltage to the second current mirror group, and the current mirror formed by the first current mirror group and the second current mirror group is used to perform mirror processing on the reference current to output the constant current source channel current. In this way, the reference current is flexibly adjusted by switching the adjustment mode of the reference current, and then the current value of the constant current source channel current is adjusted. The current value adjustment range of the constant current source channel current is not limited to the resistance value adjustment range of the external resistor, thereby improving the current value adjustment range of the constant current source channel current.

[0038] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or understood by practicing the present disclosure. The objectives and other advantages of the present disclosure are realized and obtained by the structures particularly pointed out in the description and the drawings.

[0039] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0041] Figure 1 A schematic structural diagram of a display device according to an embodiment of the present disclosure;

[0042] Figure 2 A structural block diagram of a constant current source generating circuit provided according to an embodiment of the present disclosure;

[0043] Figure 3 A schematic diagram of the principle of a current mirror according to an embodiment of the present disclosure;

[0044] Figure 4 A circuit diagram of a constant current source generating circuit provided according to one embodiment of the present disclosure;

[0045] Figure 5 When the control signal provided according to one embodiment of the present disclosure is the first value Figure 4 The equivalent circuit diagram of the constant current source generating circuit shown in FIG.

[0046] Figure 6 When the control signal provided according to one embodiment of the present disclosure is the second value Figure 4 The equivalent circuit diagram of the constant current source generating circuit shown in FIG.

[0047] Figure 7 The present invention is a flowchart of a method for controlling a constant current source generating circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0048] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the drawings, identical elements are represented by identical or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0049] Figure 1 FIG. 1 is a schematic diagram showing the structure of a display device according to an embodiment of the present disclosure. Figure 1 As shown, the display device provided by the embodiment of the present disclosure includes: a display panel 110, a column driving circuit 120, a row driving circuit 130 and a timing control circuit 140. Exemplarily, the display device is, for example, an OLED display device.

[0050] In some embodiments, the display panel 110 includes a plurality of pixels Px arranged in an array. Each pixel Px is connected to the column driver circuit 120 via a data line and to the row driver circuit 130 via a scan line. In some embodiments, the timing control circuit 140 is configured to provide timing control signals, gamma voltages, and input data to the column driver circuit 120, and to input timing control signals to the row driver circuit 130. The column driver circuit 120 generates a plurality of grayscale voltages Vsrc based on the received timing control signals, gamma voltages, and input data, and transmits these grayscale voltages to each column of pixels Px via the data lines to drive the plurality of pixels Px in the display panel 110. The grayscale voltage received by each pixel Px corresponds to the grayscale to be displayed by that pixel. A scan signal Scan is generated based on the received timing control signal and provided to each row of pixels Px via the scan lines. In some embodiments, the row driver circuit 130 typically includes a plurality of row driver chips, the number of which depends on the resolution of the display panel 110 and the number of drive channels of the row driver chips. The row driver chip is provided with a constant current source generating circuit for generating a constant current source channel current to be transmitted to the display panel 110 through a corresponding driving channel, thereby driving the corresponding pixel.

[0051] Figure 2 FIG. 1 is a structural block diagram of a constant current source generating circuit according to an embodiment of the present disclosure. Figure 2 As shown, the constant current source generating circuit provided by the embodiment of the present disclosure includes: a reference current generating unit 210 , a driving unit 220 and a channel current output unit 230 .

[0052] In some embodiments, the reference current generating unit 210 switches the adjustment mode of the reference current I0 according to the control signal, and generates and outputs the reference current I0 with an adjustable current value according to the determined adjustment mode. The adjustment mode includes determining the reference current I0 according to the reference voltage Vref and the external resistor Rext (for example, I0=Vref / Rext) or determining the reference current I0 according to the built-in current source Iref (for example, I0=Iref', Iref' is the output current of the built-in current source Iref). In some embodiments, the driving unit 220 includes a first current mirror group ( Figure 2 The driving unit 220 outputs the driving voltage and bias voltage of the first current mirror group. In some embodiments, the channel current output unit 230 includes a second current mirror group ( Figure 2 The first current mirror group cooperates with the second current mirror group to form a current mirror. Figure 3 FIG. 1 is a schematic diagram showing the principle of a current mirror according to an embodiment of the present disclosure. Figure 3As shown, N-type field effect transistors (NFETs) NM0 and N-type field effect transistors NM1 have the same gate voltage Vg1. Assuming that the gate voltage of NFET NM2 is Vg2, and the drain voltages of NFETs NM0, NFET NM1, and NFET NM2 are Vd0, Vd1, and Vd2, respectively, then if the gate voltage Vg1 of NFET NM1 is equal to the gate voltage Vg2 of NFET NM2, and the drain voltage Vd1 of NFET NM1 is equal to the drain voltage Vd2 of NFET NM2, then NFETs NM1 and NFET NM2 are under the same bias conditions, so the current I2 in the branch where NFET NM1 is located is equal to the current I3 in the branch where NFET NM2 is located, that is, it can be said that current I3 mirrors current I2. In some embodiments, the channel current output unit 230 provides the driving voltage and the bias voltage to the second current mirror group so that the first current mirror group and the second current mirror group are under the same bias conditions, and the current mirror formed by the first current mirror group and the second current mirror group is used to mirror the reference current I0 to output the constant current source channel current Ich.

[0053] Figure 4 FIG. 1 is a circuit diagram of a constant current source generating circuit according to an embodiment of the present disclosure. Figure 4As shown, the constant current source generation circuit provided by the embodiments of the present disclosure includes: a reference current generation unit 210, a driving unit 220, and a channel current output unit 230. In some embodiments, the reference current generation unit 210 includes: an adjustment module 211, an external resistor Rext, a built-in current source Iref, and a first transistor (e.g., a P-type field-effect transistor) PM2. In some embodiments, when the control signal has a first value, the adjustment module 211 applies a reference voltage Vref to the external resistor Rext and determines the reference current I0 as the current value flowing through the external resistor Rext. When the control signal has a second value, the reference current I0 is determined to be the current value Iref' output by the built-in current source Iref. In some embodiments, the adjustment module 211 includes: a first operational amplifier AMP1, and first to fifth switches K1 to K5. In some embodiments, the first terminal of the first switch K1 receives the reference voltage Vref, the first terminal of the second switch K2 receives the first reference voltage Vcres1, and the second terminals of the first switch K1 and the second terminals of the second switch K2 are connected in parallel to the first input terminal (e.g., the inverting input terminal) of the first operational amplifier AMP1. The first end of the third switch K3 is connected to the second input terminal (e.g., the non-inverting input terminal) of the first operational amplifier AMP1. The output terminal of the first operational amplifier AMP1 provides the driving voltage Vg. The second end of the third switch K3 is connected to the first path terminal of the first transistor PM2. The second path terminal of the first transistor PM2 is connected to the first end of the external resistor Rext. The first end of the fourth switch K4 is connected to the first connection node between the second path terminal of the first transistor PM2 and the first end of the external resistor Rext. The second end of the fourth switch K4 is connected to the second input terminal of the first operational amplifier AMP1. The first end of the fifth switch K5 is connected to the first end of the built-in current source Iref. The second end of the fifth switch K5 is connected to the second end of the third switch K3.

[0054] In some embodiments, the driving unit 220 includes a first current mirror group 221, a second operational amplifier AMP2, and a buffer BUF. The channel current output unit 230 includes a second current mirror group 231, a third operational amplifier AMP3, and a fourth transistor PM3. The first current mirror group 221 and the second current mirror group 231 cooperate to form a current mirror. In some embodiments, the first current mirror group 221 includes a plurality of second transistors PM0 (e.g., second transistors PM01 through PM0n, where n is a positive integer greater than 1). The second current mirror group 231 includes a plurality of third transistors PM1 (e.g., second transistors PM11 through PM1m, where m is a positive integer greater than 1). In some embodiments, the control terminals (e.g., gate terminals) of the plurality of second transistors PM0 are connected to the output terminal of the first operational amplifier AMP1 to receive the driving voltage Vg, the first pass terminals (e.g., source terminals) are connected to the power supply VDD, and the second pass terminals are connected to the second terminal of the third switch K3. A first input terminal (e.g., a non-inverting input terminal) of the second operational amplifier AMP2 receives a second reference voltage Vcres2, and a second input terminal (e.g., an inverting input terminal) of the second operational amplifier AMP2 is connected to a second connection node between the second pass terminals (e.g., drain terminals) of the plurality of second transistors PM0 and the second terminal of the third switch K3.

[0055] In some embodiments, the input terminal of the buffer BUF is connected to a third connection node between the control terminals of the plurality of second transistors PM0 and the output terminal of the first operational amplifier AMP1. The output terminal of the buffer BUF outputs a driving voltage Vg. In some embodiments, the first input terminal (e.g., the non-inverting input terminal) of the third operational amplifier AMP3 is connected to the second pass terminals of the plurality of second transistors PM0 to receive a bias voltage. The control terminals (e.g., the gate terminals) of the plurality of third transistors PM1 are connected to the output terminal of the buffer BUF to receive the driving voltage Vg, the first pass terminals (e.g., the source terminals) are connected to the power supply VDD, and the second pass terminals (e.g., the drain terminals) are connected to the second input terminal (e.g., the inverting input terminal) of the third operational amplifier AMP3 to receive a bias voltage.

[0056] The control terminal (e.g., gate terminal) of the fourth transistor PM3 is connected to the output terminal of the third operational amplifier AMP3. The first channel terminal (e.g., source terminal) of the fourth transistor PM3 is connected to the second input terminal of the third operational amplifier AMP3 and a fourth connection node of the second channel terminals of the plurality of third transistors PM1. The second channel terminal (e.g., drain terminal) is used to output the constant current source channel current Ich. It should be noted that the reference voltage Vref, the first reference voltage Vcres1, and the second reference voltage Vcres2 can be generated by a bandgap reference voltage source within the chip.

[0057] In some embodiments, when the control signal is at a first value, the first switch K1 and the fourth switch K4 are closed, and the second switch K2 , the third switch K3 , and the fifth switch K5 are opened. Figure 5 When the control signal provided according to one embodiment of the present disclosure is the first value Figure 4 The equivalent circuit diagram of the constant current source generating circuit is shown in FIG. Figure 5 As shown, the first operational amplifier AMP1, the first current mirror group 221, the first transistor PM2, and the external resistor Rext form a negative feedback structure. Because the voltages at both input terminals of the amplifier are the same in steady-state, the input voltage at the second input terminal (e.g., the non-inverting input terminal) of the first operational amplifier AMP1 is equal to the reference voltage Vref. The reference current I0 is determined as the current flowing through the external resistor Rext (i.e., I0 = Vref / Rext). The second operational amplifier AMP2, the first current mirror group 221, and the first transistor PM2 form a negative feedback structure. Because the voltages at both input terminals of the amplifier are the same in steady-state, the input voltage at the second input terminal (e.g., the inverting input terminal) of the second operational amplifier AMP2 is equal to the second reference voltage Vcres2. That is, when the control signal is at the first value, the second reference voltage Vcres2 is provided as a bias voltage to the second path terminals of the plurality of second transistors PM0. The third operational amplifier AMP3, the second current mirror group 231, and the fourth transistor PM3 form a negative feedback structure. Because the voltages at both input terminals of the negative feedback system are the same in steady state, the input voltage at the second input terminal (e.g., the inverting input terminal) of the third operational amplifier AMP3 is also equal to the second reference voltage Vcres2. That is, when the control signal is at the first value, the second reference voltage Vcres2 is provided as a bias voltage to the second path terminals of the plurality of third transistors PM1. Therefore, the plurality of second transistors PM0 and the plurality of third transistors PM1 are under the same bias conditions, and the constant current source channel current Ich can be expressed as follows:

[0058] (1)

[0059] Where, Ich is the constant current source channel current, I0 is the reference current, and m / n is the mirror ratio of the current mirror.

[0060] In some embodiments, when the control signal is at the second value, the first switch K1 and the fourth switch K4 are opened, and K2 , the third switch K3 , and the fifth switch K5 are closed. Figure 6 When the control signal provided according to one embodiment of the present disclosure is the second value Figure 4 The equivalent circuit diagram of the constant current source generating circuit is shown in FIG. Figure 6As shown, the first operational amplifier AMP1, the first current mirror group 221, and the built-in current source Iref form a negative feedback structure. Because the voltages at the two input terminals of the amplifier are the same in the steady-state negative feedback system, the input voltage at the second input terminal (e.g., the non-inverting input terminal) of the first operational amplifier AMP1 is equal to the first reference voltage Vcres1. The reference current I0 is determined to be the output current Iref' of the built-in current source Iref (i.e., I0 = Iref'). In other words, when the control signal is at the second value, the first reference voltage Vcres1 is provided as a bias voltage to the second path terminals of the plurality of second transistors PM0. The third operational amplifier AMP3, the second current mirror group 231, and the fourth transistor PM3 form a negative feedback structure. Because the voltages at the two input terminals of the amplifier are the same in the steady-state negative feedback system, the input voltage at the second input terminal (e.g., the inverting input terminal) of the third operational amplifier AMP3 is also equal to the first reference voltage Vcres1. In other words, when the control signal is at the second value, the first reference voltage Vcres1 is provided as a bias voltage to the second path terminals of the plurality of third transistors PM1. Therefore, the plurality of second transistors PM0 and the plurality of third transistors PM1 are under the same bias condition, and the constant current source channel current Ich can be expressed as follows:

[0061] (2)

[0062] Where, Ich is the constant current source channel current, I0 is the reference current, Iref' is the output current of the built-in current source Iref, and m / n is the mirror ratio of the current mirror.

[0063] It can be understood that the constant current source generating circuit of the embodiment of the present disclosure sets the adjustment module 211 to apply the reference voltage Vref to the external resistor Rext when the control signal is the first value, and determines the reference current I0 as the current value flowing through the external resistor Rext. When the control signal is the second value, the reference current I0 is determined to be the current value Iref' output by the built-in current source Iref. This can flexibly adjust the reference current while effectively simplifying the circuit structure and reducing the chip power consumption and area, thereby adjusting the current value of the constant current source channel current.

[0064] Figure 7 A flow chart of a control method for a constant current source generating circuit according to an embodiment of the present disclosure is shown. The constant current source generating circuit includes a first current mirror group and a second current mirror group, wherein the first current mirror group and the second current mirror group cooperate to form a current mirror. The control method includes:

[0065] In step S710, the adjustment mode of the reference current is switched according to the control signal, and a reference current with an adjustable current value is generated and output according to the determined adjustment mode, wherein the adjustment mode includes determining the reference current according to a reference voltage and an external resistor or determining the reference current according to a built-in current source.

[0066] In step S720 , the driving voltage and the bias voltage of the first current mirror group are output.

[0067] In step S730, the driving voltage and the bias voltage are provided to the second current mirror group, and the reference current is mirrored by the current mirror to output a constant current source channel current.

[0068] Since the process of controlling the constant current source generating circuit according to the embodiment of the present disclosure has been described in detail in the device embodiment above, it will not be repeated here.

[0069] In summary, in the constant current source generating circuit provided by the present invention, the reference current generating unit switches the adjustment mode of the reference current according to the control signal, generates and outputs a reference current with an adjustable current value according to the determined adjustment mode, wherein the adjustment mode includes determining the reference current according to the reference voltage and the external resistor or determining the reference current according to the built-in current source, the driving unit outputs the driving voltage and bias voltage of the first current mirror group, the channel current output unit provides the driving voltage and bias voltage to the second current mirror group, and the current mirror formed by the first current mirror group and the second current mirror group is used to mirror the reference current to output the constant current source channel current. In this way, the reference current is flexibly adjusted by switching the adjustment mode of the reference current, and then the current value of the constant current source channel current is adjusted. The current value adjustment range of the constant current source channel current can be not limited to the resistance value adjustment range of the external resistor, thereby improving the current value adjustment range of the constant current source channel current.

[0070] Finally, it should be noted that the above embodiments are merely examples for the purpose of illustrating the present disclosure and are not intended to limit the embodiments. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to provide an exhaustive list of all embodiments. Obvious variations or modifications arising therefrom remain within the scope of protection of the present disclosure.

Claims

1. A constant current source generating circuit, comprising: a reference current generating unit, configured to switch an adjustment mode of the reference current according to a control signal, and generate and output a reference current with an adjustable current value according to the determined adjustment mode, wherein the adjustment mode includes determining the reference current according to a reference voltage and an external resistor or determining the reference current according to a built-in current source; a driving unit, comprising a first current mirror group, connected to the reference current generating unit, and configured to output a driving voltage and a bias voltage of the first current mirror group; The channel current output unit includes a second current mirror group. The first current mirror group and the second current mirror group cooperate to form a current mirror, provide the driving voltage and bias voltage to the second current mirror group, and use the current mirror to mirror the reference current to output the constant current source channel current.

2. The constant current source generating circuit according to claim 1, wherein: The reference current generating unit includes: an adjustment module, the external resistor and the built-in current source, The adjustment module is configured to apply the reference voltage to the external resistor and determine the reference current as a current value flowing through the external resistor when the control signal is at a first value. When the control signal is at a second value, the reference current is determined to be a current value output by the built-in current source.

3. The constant current source generating circuit according to claim 2, wherein: The reference current generating unit further includes: a first transistor; the adjustment module includes a first operational amplifier, a first switch to a fifth switch; A first end of the first switch receives the reference voltage, a first end of the second switch receives the first reference voltage, a second end of the first switch and a second end of the second switch are connected in parallel to a first input end of the first operational amplifier, a first end of the third switch is connected to a second input end of the first operational amplifier, an output end of the first operational amplifier provides the driving voltage, a second end of the third switch is connected to a first path end of the first transistor, a second path end of the first transistor is connected to a first end of the external resistor, a first end of the fourth switch is connected to a first connection node between the second path end of the first transistor and the first end of the external resistor, a second end of the fourth switch is connected to the second input end of the first operational amplifier, a first end of the fifth switch is connected to a first end of the built-in current source, and a second end of the fifth switch is connected to a second end of the third switch; When the control signal is at a first value, the first switch and the fourth switch are closed, and the second switch, the third switch and the fifth switch are opened; When the control signal has a second value, the first switch and the fourth switch are opened, and the second switch, the third switch, and the fifth switch are closed.

4. The constant current source generating circuit according to claim 3, wherein: The first current mirror group includes a plurality of second transistors, and the driving unit further includes a second operational amplifier. The control terminals of the plurality of second transistors are all connected to the output terminal of the first operational amplifier to receive the driving voltage, the first path terminals are all connected to the power supply, and the second path terminals are all connected to the second terminal of the third switch. The first input terminal of the second operational amplifier receives a second reference voltage, and the second input terminal of the second operational amplifier is connected to a second connection node between the second path terminals of the plurality of second transistors and the second terminal of the third switch. Wherein, when the control signal is a first value, the second reference voltage is provided as the bias voltage to the second pass terminals of the plurality of second transistors; When the control signal has a second value, the first reference voltage is provided as the bias voltage to the second pass terminals of the plurality of second transistors.

5. The constant current source generating circuit according to claim 4, wherein: The driving unit further includes a buffer, an input end of the buffer is connected to a third connection node between the control ends of the plurality of second transistors and the output end of the first operational amplifier, and an output end of the buffer outputs the driving voltage.

6. The constant current source generating circuit according to claim 5, wherein: The second current mirror group includes a plurality of third transistors, and the channel current output unit also includes a third operational amplifier and a fourth transistor. The first input terminal of the third operational amplifier is connected to the second path terminals of the plurality of second transistors to receive the bias voltage. The control terminals of the plurality of third transistors are all connected to the output terminal of the buffer to receive the driving voltage, the first path terminals are all connected to the power supply, and the second path terminals are all connected to the second input terminal of the third operational amplifier to receive the bias voltage. The control end of the fourth transistor is connected to the output end of the third operational amplifier, the first path end is connected to the second input end of the third operational amplifier and the fourth connection node of the second path ends of the multiple third transistors, and the second path end is used to output the constant current source channel current.

7. A display panel comprising: A plurality of pixels are arranged in an array, wherein a constant current source channel current is generated by a constant current source generating circuit according to any one of claims 1 to 6 and transmitted to the display panel through a corresponding driving channel, thereby driving the corresponding pixels.

8. A row driving circuit comprising: The constant current source generating circuit according to any one of claims 1 to 6.

9. A display device comprising: Display panel; Column driver circuit; The row driver circuit according to claim 8.

10. A driver chip for a display panel, comprising: a reference current generating unit, configured to switch an adjustment mode of the reference current according to a control signal, and generate and output a reference current with an adjustable current value according to the determined adjustment mode, wherein the adjustment mode includes determining the reference current according to a reference voltage and an external resistor or determining the reference current according to a built-in current source; a driving unit, comprising a first current mirror group, connected to the reference current generating unit, and configured to output a driving voltage and a bias voltage of the first current mirror group; The channel current output unit includes a second current mirror group. The first current mirror group and the second current mirror group cooperate to form a current mirror, provide the driving voltage and bias voltage to the second current mirror group, and use the current mirror to mirror the reference current to output the constant current source channel current.

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