Microdisplay device with cathode wiring region

Abstract

The utility model discloses a kind of micro display devices with cathode wiring area, it is related to semiconductor technical field.The micro display device, including: drive wafer, the surface of the drive wafer includes pixel array AA area, each pixel area in the pixel array AA area includes: mutually insulated anode contact and cathode wiring area, and cathode wiring area between adjacent pixel area is linked;Display module, the display module is located on the drive wafer, the display module includes respectively corresponding light-emitting unit with each pixel area, the light-emitting unit and anode contact in corresponding pixel area are communicated, and bottom and cathode wiring area in corresponding pixel area are not contacted;Wherein, the top of cathode wiring area of each described pixel area, the top of the light-emitting unit is covered with continuous common cathode layer.Based on the above scheme, light-emitting unit and cathode metal mesh grid can be prevented from competing for horizontal space, and optical enhancement and electrical enhancement can be maximized.

Description

[0001] Priority information: This application claims priority to Chinese Patent Application No. 2024213980933, filed on June 19, 2024, entitled “A Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This utility model relates to the field of semiconductor technology, and in particular to a microdisplay device having a cathode wiring area. Background Technology

[0003] In the fields of micro-displays and micro-projections, silicon-based CMOS driving backplanes are commonly used, including Micro-OLED and Micro-LED, and they almost all employ a common cathode structure, such as... Figure 1 As shown, the design of its driver backplane includes a pixel array AA area (Active Area), a peripheral common cathode CC area, and a signal and electrode pad IO interface area (Input / Output).

[0004] Taking Micro-OLED as an example, in the electrical connection of the pixel optoelectronic devices in the AA region, there is an anode electrode corresponding to the light-emitting unit in the pixel array AA region, and a common cathode layer on top of the light-emitting unit. This common cathode layer extends to the peripheral common cathode CC region and connects with the common cathode layer to form a circuit. When the light-emitting unit develops into Micro-LED, its high brightness needs to be implemented under high current density, so the demand for current expansion increases significantly. A simple transparent conductive common cathode is difficult to meet the requirements of carrying large current and current expansion of a large display area. Therefore, a metal mesh grid is added between the light-emitting units as a cathode electrical reinforcement structure to realize the current carrying and expansion of the cathode.

[0005] The metal mesh on the light-emitting unit side competes with the light-emitting unit for horizontal space, creating a contradiction between optical and electrical aspects: when the light-emitting unit is enlarged to enhance optical performance, the width of the metal mesh on the cathode is compressed, leading to a decrease in electrical performance; conversely, when electrical performance is enhanced and the metal mesh is widened, the light-emitting unit needs to be reduced in size, resulting in a loss of optical performance. Therefore, a new common-cathode optoelectronic device structure is urgently needed to resolve the contradiction between the light-emitting unit and the cathode electrical enhancement structure in terms of both optical and electrical aspects. Utility Model Content

[0006] The purpose of this invention is to provide a micro-display device with a cathode wiring area, which can resolve the contradiction between the light-emitting unit and the cathode electrical enhancement structure in terms of optics and electricity.

[0007] To achieve the above-mentioned objectives, the present invention proposes the following technical solution:

[0008] On one hand, a microdisplay device with a cathode wiring region is provided, the microdisplay device comprising:

[0009] A driving wafer, the surface of which includes a pixel array AA region, each pixel region in the pixel array AA region including: mutually insulated anode contacts and cathode wiring regions, and the cathode wiring regions between adjacent pixel regions are interconnected;

[0010] The display module is disposed on the driving wafer. The display module includes light-emitting units corresponding to each pixel area. The light-emitting units are connected to the anode contacts in the corresponding pixel area, and their bottoms are not in contact with the cathode wiring areas in the corresponding pixel area.

[0011] In this embodiment, a continuous common cathode layer is provided on the top of the cathode wiring area of ​​each pixel region and on the top of the light-emitting unit.

[0012] In one possible implementation, the surface of the driving wafer further includes a peripheral common cathode (CC) region.

[0013] The cathode wiring area in the outer portion of the pixel array AA region is connected to the outer common cathode CC region, and the common cathode layer extends to the outer common cathode CC region, so that the cathode wiring area, the common cathode layer, and the outer common cathode CC region form a loop.

[0014] In one possible implementation, in each pixel region, the anode contact is located in the middle region of the pixel region, the cathode wiring region is located in the edge region of the pixel region, and there is an insulating region between the anode contact and the cathode wiring region.

[0015] In one possible implementation, the cathode wiring area includes a first layer of cathode wiring area in a trench pattern.

[0016] In one possible implementation, the cathode wiring region further includes a second cathode wiring region with a hole pattern, the second cathode wiring region being disposed above the first cathode wiring region, and the projection of the second cathode wiring region on the driving wafer being located within the projection of the first cathode wiring region on the driving wafer.

[0017] In one possible implementation, the plurality of said pixel regions share a second layer cathode wiring region;

[0018] or,

[0019] Each pixel region shares multiple second-layer cathode wiring regions.

[0020] In one possible implementation, the size of the cathode wiring area is between 0.1µm and 30µm, the size of the anode contact is between 0.1µm and 100µm, and the size of the insulating area is not less than 0.1µm.

[0021] In one possible implementation, the cathode wiring region is a composite stack structure, which includes: a composite metal layer and a current transmission layer;

[0022] The composite metal layer includes at least one of an adhesive layer, a barrier layer, and a seed layer.

[0023] In one possible implementation, the display module further includes:

[0024] A microlens structure is aligned with the light-emitting unit and is disposed on the common cathode layer.

[0025] In one possible implementation, the radius of the microlens structure in the horizontal direction is greater than 55% of the size of the light-emitting unit.

[0026] In one possible implementation, a passivation layer is provided between the sidewall of the light-emitting unit and the common cathode layer, and between the pixel array AA region (excluding the cathode wiring region and the region in contact with the bottom of the light-emitting unit) and the common cathode layer.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] Cathode wiring is performed on the driver wafer. For each pixel area in the pixel array AA area on the surface of the driver wafer, it is divided into an anode contact and a cathode wiring area. The anode contact and the cathode wiring area are insulated from each other. The light-emitting unit corresponding to each pixel area is connected to the anode contact in the corresponding pixel area. The bottom does not contact the cathode wiring area in the corresponding pixel area. A common cathode layer is covered on the top of the cathode wiring area and the top of the light-emitting unit in each pixel area. Through the cathode wiring below, the layout between the light-emitting unit and the cathode electrical enhancement structure is transformed from 2D horizontal layout to 3D vertical layout. This solves the problem of the light-emitting unit and the cathode electrical enhancement structure competing for horizontal space. It can maximize optical enhancement and electrical enhancement. In addition, the large area of ​​metal cathode wiring at the bottom can improve the heat dissipation capacity of the chip. Attached Figure Description

[0029] Figure 1 This is a top view of a driving wafer provided in related technologies;

[0030] Figure 2 This is a cross-sectional view of a microdisplay device with a cathode wiring area provided in an embodiment of this application;

[0031] Figure 3 This is a top view of a driving wafer with a cathode wiring region provided in an embodiment of this application;

[0032] Figure 4 This is a top view of a pixel array AA region with a cathode wiring area provided in an embodiment of this application;

[0033] Figure 5 This is a cross-sectional view of a driving wafer with a cathode wiring region provided in an embodiment of this application;

[0034] Figure 6 This is a cross-sectional view of a driving wafer with a cathode wiring region provided in an embodiment of this application;

[0035] Figure 7 This is a top view of a pixel array AA region with a cathode wiring area provided in an embodiment of this application;

[0036] Figure 8 This is a cross-sectional view of a microdisplay device with a microlens structure provided in an embodiment of this application;

[0037] Figure 9 This is a flowchart of a method for fabricating a microdisplay device provided in an embodiment of this application;

[0038] Figure 10 This is a schematic diagram illustrating a process of cathode wiring in the AA region of a pixel array provided in an embodiment of this application;

[0039] Figure 11 This is a cross-sectional view of a compound epitaxial layer prepared with a P-type ohmic contact layer provided in the embodiments of this application;

[0040] Figure 12 This is a top view of a driving wafer with a patterned bonding metal layer provided in an embodiment of this application;

[0041] Figure 13 This is a cross-sectional view of a compound epitaxial growth and driver wafer integrated bonding structure provided in the embodiments of this application;

[0042] Figure 14 This is a cross-sectional view of a compound epitaxial growth and driver wafer integrated bonding structure provided in the embodiments of this application;

[0043] Figure 15 This is a cross-sectional view of a microdisplay device in substrate removal provided in an embodiment of this application;

[0044] Figure 16 This is a cross-sectional view of a microdisplay device after substrate removal provided in an embodiment of this application;

[0045] Figure 17 This is a cross-sectional view of a microdisplay device fabricated with an N-type ohmic contact, as provided in an embodiment of this application.

[0046] Figure 18 This is a cross-sectional view of a microdisplay device with an N-type layer roughened according to an embodiment of this application;

[0047] Figure 19 This is a cross-sectional view of a microdisplay device fabricated with an N-type ohmic contact, as provided in an embodiment of this application.

[0048] Figure 20 This is a cross-sectional view of a microdisplay device after pixel fabrication, provided in an embodiment of this application;

[0049] Figure 21 This is a schematic diagram illustrating a process for fabricating photoelectric functions in a light-emitting unit, as provided in an embodiment of this application.

[0050] Figure 22 This is a schematic diagram illustrating a process for fabricating photoelectric functions in a light-emitting unit, as provided in an embodiment of this application.

[0051] Figure 23 This is a schematic diagram illustrating the process of fabricating photoelectric functions for a light-emitting unit, as provided in an embodiment of this application.

[0052] Figure label:

[0053] 100-Driver wafer, 200-Display module, 10-Anode contact, 20-Cathode wiring area, 21-First cathode wiring area, 22-Second cathode wiring area, 30-Light emitting unit, 31-Bonding metal layer, 32-P-type ohmic contact layer, 33-Active layer, 34-N-type ohmic contact layer, 35-Substrate, 40-Common cathode layer, 50-Microlens structure, 60-Passivation layer, 61-Sidewall dielectric layer, 62-Sidewall metal layer. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0055] In the description of this utility model, it should be understood that the terms "vertical," "upper," "lower," "top," "side," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the utility model. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, unless otherwise stated, "a plurality of" means two or more.

[0056] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0057] In related technologies, a method is adopted to carry and extend current by fabricating a metal mesh between the light-emitting units after completing the transparent conductive common cathode film layer.

[0058] Since both the metal mesh and the light-emitting unit require horizontal space, there is a contradiction between the electrical and optical performance of the metal mesh current. A wider metal mesh has better electrical performance, but it requires more horizontal space, which prevents the size of the light-emitting unit from being increased effectively. This sacrifices the pixel aperture ratio and limits further miniaturization of the pixel size. At the same time, in the field of micro-displays, horizontal space is limited, and when compromising optical enhancement, the width of the metal mesh is also limited. An excessively narrow metal mesh cannot effectively carry and expand current when the screen size is large. In addition, the active region of the tri- or quinary compound materials (such as GaN) used in Micro-LEDs is generally close to the anode. Correspondingly, when the size of the metal mesh or the light-emitting unit is large, the metal will ride on the sidewall of the light-emitting unit, blocking the light-emitting unit and causing brightness loss. At the same time, the thickness and width of the metal coating are limited by the patterned deposition process, and the aspect ratio generally cannot exceed 2:1.

[0059] To avoid the above problems, this application proposes a vertical chip structure with the wiring in the lower cathode wiring area. By laying out the lower metal layer, the horizontal space contradiction between the metal mesh and the electrical and optical aspects is resolved. At the same time, combined with the vertical structure light-emitting unit, the loss of the light-emitting area is avoided, and the optimal light-emitting unit size and pixel density can be achieved.

[0060] The device structure proposed in this application will be described below.

[0061] First, embodiments of this application provide a microdisplay device with a cathode wiring area, such as... Figure 2 As shown, the microdisplay device includes:

[0062] A driving wafer 100 has a surface including a pixel array AA region. Each pixel region in the pixel array AA region includes: mutually insulated anode contacts 10 and cathode wiring regions 20, and the cathode wiring regions 20 between adjacent pixel regions are interconnected. A display module 200 is disposed on the driving wafer 100. The display module 200 includes light-emitting units 30 corresponding to each pixel region. The light-emitting units 30 are connected to the anode contacts 10 in the corresponding pixel region, and their bottoms are not in contact with the cathode wiring regions 20 in the corresponding pixel region. A continuous common cathode layer 40 is provided on the top of the cathode wiring region 20 and the top of the light-emitting unit 30 in each pixel region.

[0063] In this embodiment, cathode wiring is performed on the surface of the driving wafer 100. Specifically, the surface of the driving wafer 100 includes a pixel array AA region composed of at least one pixel region. Each pixel region is divided into an anode contact 10 and a cathode wiring region 20, and the anode contact 10 and the cathode wiring region 20 are insulated from each other. A display module 200 is provided on the driving wafer 100. Each light-emitting unit 30 in the display module 200 corresponds to each pixel region. Here, we will describe it as a one-to-one correspondence. The bottom of the light-emitting unit 30 is in contact with the anode contact 10 in the corresponding pixel region, and the bottom is not in contact with the cathode wiring region 20 in the corresponding pixel region. A continuous common cathode layer 40 is provided on the top of the cathode wiring region 20 and the top of the light-emitting unit 30 in each pixel region, so that the cathode wiring region 20 can realize the functions of current carrying and expansion.

[0064] In this design, the anode contact 10 in each pixel area can be a single or multiple contacts, and its shape can be circular or polygonal. The anode contact 10 can specifically adopt a composite stacked structure, which includes: a composite metal layer and a current transport layer; wherein the composite metal layer includes at least one of an adhesion layer, a barrier layer, and a seed layer. The adhesion layer and barrier layer can include Cr, Ti, Ta, Pt, Ni, and nitrides TiN and TaN, and the seed layer and current transport layer can include Al, Cu, W, Au, and their alloys AlNi and AlCu. Generally, the metal thickness of the adhesion layer or barrier layer is 1nm~200nm, and the metal thickness of the current transport layer is 100nm~5um.

[0065] The cathode wiring region 20 in each pixel region can be a continuous single region or multiple non-continuous regions. Specifically, the cathode wiring region 20 can adopt a composite stacked structure, which includes: a composite metal layer and a current transport layer; wherein the composite metal layer includes at least one of an adhesion layer, a barrier layer, and a seed layer. The adhesion layer and barrier layer can include Cr, Ti, Ta, Pt, Ni, and nitrides TiN and TaN; the seed layer and current transport layer can include Al, Cu, W, Au, and their alloys AlNi and AlCu. Generally, the metal thickness of the adhesion layer or barrier layer is 1 nm to 200 nm, and the metal thickness of the current transport layer is 100 nm to 5 μm.

[0066] It is understood that the materials of the anode contact 10 and the cathode wiring area 20 may be the same or different, and this application does not impose any restrictions on this.

[0067] The light-emitting unit 30 may include the following stacked components along a direction away from the driving wafer 100: a bonding metal layer, a P-type ohmic contact layer, an active layer, and an N-type ohmic contact layer.

[0068] The common cathode layer 40 can be a transparent conductive film layer including indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), Al-doped zinc oxide (AZO), Al-doped indium tin oxide, Ag-doped indium tin oxide, Au-doped indium tin oxide, etc., and the thickness of the common cathode layer 40 is 50nm~500nm.

[0069] In one possible implementation, such as Figure 3 As shown, the surface of the driving wafer 100 also includes: a peripheral common cathode (CC) region; the cathode wiring region 20 of the peripheral portion of the pixel array AA region is connected to the peripheral common cathode (CC) region, and the common cathode layer 40 extends to the peripheral common cathode (CC) region, so that the cathode wiring region 20, the common cathode layer 40, and the peripheral common cathode (CC) region form a loop.

[0070] In this implementation, the cathode wiring area 20 is connected to the peripheral common cathode (CC) region on the surface of the driving wafer 100, and the common cathode layer 40 in the display module 200 is connected to this peripheral common cathode (CC) region to realize a closed-loop optoelectronic device.

[0071] In one possible implementation, in each pixel region, the anode contact 10 is located in the middle region of the pixel region, the cathode wiring region 20 is located in the edge region of the pixel region, and there is an insulating region between the anode contact 10 and the cathode wiring region 20.

[0072] In this implementation, each pixel region includes at least one anode contact 10, and the anode contact 10 is located in the middle region of the pixel region. The cathode wiring region 20 is located in the edge region of the pixel region, and the anode contact 10 and the cathode wiring region 20 are insulated from each other by an insulating region. The insulating region material includes silicon oxide, silicon nitride, silicon carbide, etc., and this application does not limit it.

[0073] In one example, the cathode wiring region 20 includes a first layer of cathode wiring region 20 in a trench pattern, which can be considered as a cathode grid, and the first layer of cathode wiring region 20 is directly connected to the surface of the driving wafer 100.

[0074] For example, a top view of the cathode wiring of the pixel area in the pixel array AA region is shown below. Figure 4 As shown, the cross-sectional view is as follows Figure 5 As shown in the figure, the anode contact 10 is located in the middle area of ​​the pixel area, the edge area is the first cathode wiring area 21, and the diagonal filling area is the insulating area. The common cathode wiring in the pixel can be circular, rectangular, hexagonal, octagonal, etc., and this application does not limit it.

[0075] In one example, the cathode wiring region 20 is a hole pattern, and the cross-sectional view of the cathode wiring in the pixel area of ​​the pixel array AA region is shown below. Figure 6 As shown, based on the first cathode wiring area 21, the cathode wiring area 20 also includes a second cathode wiring area 22 with a hole pattern. The second cathode wiring area 22 is disposed above the first cathode wiring area 21, and the projection of the second cathode wiring area 22 on the driving wafer 100 is within the projection of the first cathode wiring area 21 on the driving wafer 100. This cathode wiring area 20 can be considered as a cathode contact, which can be distributed in the middle of adjacent pixel areas or at the four corners of pixel areas. Setting the cathode wiring area 20 as a hole-type contact can increase the size of the insulating area, that is, increase the alignment and overlay distance between subsequent processes and the cathode wiring area 20, and increase the process window.

[0076] It is understandable that, based on the second cathode wiring area 22, the second cathode wiring area 22 also includes a second anode contact and a second insulation area in the horizontal direction, and the size of the second insulation area is larger than the size of the first insulation area in the same layer as the first cathode wiring area 21.

[0077] Furthermore, a top view of the cathode wiring in the pixel area of ​​the pixel array AA region is shown below. Figure 7 As shown, multiple pixel areas share a second-layer cathode wiring area 22; or, a pixel area shares multiple second-layer cathode wiring areas 22.

[0078] Furthermore, such as Figure 5 As shown, the size d1 of the cathode wiring area 20 (first cathode wiring area 20, second cathode wiring area 20) is 0.1um~30um, the size d2 of the anode contact 10 is 0.1um~100um, and the size d3 of the insulating area is not less than 0.1um.

[0079] In one possible implementation, such as Figure 2 As shown, a passivation layer 60 is provided between the sidewall of the light-emitting unit 30 and the common cathode layer 40, and between the area of ​​the pixel array AA region other than the cathode wiring area 20 and the area in contact with the bottom of the light-emitting unit 30 and the common cathode layer 40.

[0080] The passivation layer 60 is used for the passivation and insulation of the sidewall of the light-emitting unit 30. The passivation layer 60 can be a single layer or multiple layers of dielectrics such as silicon oxide, silicon nitride, aluminum oxide, and aluminum nitride. The thickness of the passivation layer 60 is in the range of 50 Å to 1.5 μm.

[0081] In one possible implementation, such as Figure 8 As shown, the display module 200 also includes a microlens structure 50, which is aligned with the light-emitting unit 30 and is disposed on the common cathode layer 40.

[0082] In this implementation, a microlens structure 50 is disposed on the light-emitting unit 30. The microlens structure 50 is a spherical or conical structure, and its entire structure protrudes in a direction away from the driving wafer 100. Optical collimation is achieved through the microlens or metasurface, thereby converging the emission angle. The microlens material includes inorganic dielectric layers such as silicon oxide, silicon nitride, and aluminum oxide, or organic dielectric layers such as SU8, silicone, and polyimide. The microlens can have a smooth curvature or a combination of multiple curvatures; this application does not impose any limitations on this.

[0083] Furthermore, the radius of the microlens structure 50 in the horizontal direction is greater than 55% of the size of the light-emitting unit 30. The height of the microlens structure 50 from bottom to top is denoted as R, with the P-type ohmic contact layer in the light-emitting unit 30 as the center, and its radius in the horizontal direction is denoted as r. The dimensions of R and r are in the range of 0.5um to 200um, and r is greater than 55% of the size of the light-emitting unit 30, 1≤R:r≤10, and the common cathode layer 40 at the bottom of the adjacent microlens structure 50 can be exposed and can be covered by the microlens material.

[0084] In summary, this application provides a microdisplay device with a cathode wiring area. Cathode wiring is performed on a driving wafer. For each pixel area in the pixel array AA region on the surface of the driving wafer, it is divided into an anode contact and a cathode wiring area. The anode contact and cathode wiring area are mutually insulated, and the light-emitting unit corresponding to each pixel area is connected to the anode contact in the corresponding pixel area. The bottom does not contact the cathode wiring area in the corresponding pixel area. A common cathode layer is covered on the top of the cathode wiring area and the top of the light-emitting unit in each pixel area. Through the lower cathode wiring, the 2D horizontal layout between the light-emitting unit and the cathode electrical enhancement structure is transformed into a 3D vertical layout, solving the problem of the light-emitting unit and the cathode electrical enhancement structure competing for horizontal space. This maximizes optical and electrical enhancement, and the large-area metal cathode wiring at the bottom improves the chip's heat dissipation capacity.

[0085] The fabrication method of the microdisplay device corresponding to the structure described in the above embodiments will be explained below. For example... Figure 9 As shown, the fabrication method of a microdisplay device may include the following steps:

[0086] Step S1: Prepare the driving wafer. The surface of the driving wafer includes the pixel array AA area.

[0087] Step S2: In each pixel region of the pixel array AA region, mutually insulated anode contacts and cathode wiring regions are prepared, and the cathode wiring regions between adjacent pixel regions are connected.

[0088] It is understandable that, if necessary, when forming the common cathode metal wiring in step S2, the metal of the IO electrode can be completed simultaneously, or part of the common cathode can be connected to the relevant electrical IO interface, such as VCOM (cathode) or GND (ground).

[0089] In one possible implementation, step S2 includes: performing a first cathode wiring on the pixel array AA area to form mutually insulated anode contacts and a first layer of cathode wiring area in a trench pattern, wherein the anode contacts and the first layer of cathode wiring area are insulated areas.

[0090] Furthermore, step S2 also includes: performing a second cathode wiring based on the first cathode wiring to form a second cathode wiring area with a hole pattern. The second cathode wiring area is disposed above the first cathode wiring area, and the projection of the second cathode wiring area on the driving wafer is located within the projection of the first cathode wiring area on the driving wafer. That is, performing two cathode wiring operations, using the second wiring to convert the anode and cathode into hole-type contacts.

[0091] The process of the first or second cathode wiring can be as follows:

[0092] (1) A patterned metal coating is applied to the AA area of ​​the pixel array to form the anode contact and cathode wiring area in each pixel area.

[0093] The patterned metal coating can be specifically applied by methods such as vapor deposition or sputtering, and this application does not impose any restrictions on this.

[0094] (2) An insulating medium is deposited on the AA area of ​​the pixel array to form an insulating layer. The top height of the insulating layer is higher than the top height of the anode contact and the cathode wiring area.

[0095] (3) The insulating layer is thinned and polished until the anode contacts and cathode wiring area are exposed, and an insulating area is formed between the anode contacts and cathode wiring area.

[0096] In one embodiment, a common cathode wiring structure of Ti 5nm, Au 500nm, and Ti 10nm sandwich structure is completed by patterned vapor deposition. The periphery of the cathode wiring area is connected to the peripheral common cathode CC area. The metal in the overlapping area connected to the peripheral common cathode CC area can be a mesh or a whole surface. The anode contacts and the cathode wiring area are arranged simultaneously in the pixel array AA area. Then, silicon oxide is deposited. After silicon oxide deposition, the surface is thinned and polished to metal Ti by chemical-mechanical planarization (CMP).

[0097] The process of the first or second cathode wiring can be as follows:

[0098] (1) An insulating dielectric is deposited in the AA region of the pixel array to form an insulating layer.

[0099] (2) The insulating layer is patterned and etched to form a filling space for the anode contacts and cathode wiring area, and to form an insulating area.

[0100] Furthermore, before patterning etching, the insulating layer can be planarized using CMP.

[0101] (3) Fill the space with metal to form the anode contact and cathode wiring area.

[0102] The metal filler can be specifically adopted by sputtering, vapor deposition, electroplating, etc., and this application does not limit it.

[0103] In one embodiment, such as Figure 10 As shown, after depositing an insulating layer on the surface of the driving wafer, the trenches corresponding to the cathode wiring area and the holes corresponding to the anode contacts are patterned and etched. Then, the metal adhesion layer and the barrier layer are sputtered and deposited. After that, the current transmission layer metal is filled by electroplating or chemical plating. After filling, the metal is thinned by metal CMP to expose the insulating layer and form the anode contact 10 and the cathode wiring area 20.

[0104] Step S3: Integrate light-emitting units on the driver wafer. Each light-emitting unit is connected to the anode contact in the corresponding pixel area, and its bottom does not contact the cathode wiring area in the corresponding pixel area.

[0105] In one possible implementation, step S3 specifically includes the following steps:

[0106] (1) such as Figure 11 As shown, a patterned P-type ohmic contact layer 32 is prepared on the compound epitaxy.

[0107] The P-type ohmic contact layer can be a transparent conductive film, such as indium tin oxide (ITO), indium zinc oxide (IZO), Al-doped zinc oxide (AZO), Al-doped indium tin oxide, Ag-doped indium tin oxide, Au-doped indium tin oxide, etc. It can also be a single layer or stack of metals with certain reflective functions, such as Pt, Au, Be, Mg, Zn, Ag, Al, Ni, etc. The area of ​​the P-type ohmic contact layer is 100um~1000um outside the overall cathode wiring area in the pixel array AA area. If necessary, the transparent conductive film can be stacked with the metal with reflective function, and an adhesive layer can be introduced in the middle.

[0108] Some of the compound materials are listed in the table below. In some practical applications, the compound films may be more complex, or materials may be used interchangeably. Typically, these mainly include a P-type ohmic contact layer, an N-type ohmic contact layer, and an MQW active quantum well (i.e., the active region) sandwiched between the two, as well as other functional layers.

[0109]

[0110] (2) A bonding metal layer is prepared on the compound epitaxy and driving wafer.

[0111] The bonding metal layer can be an element such as Al, Au, or Cu, or a stacked structure of Ni, Au, Cu, and Sn, or a bonded stack of Au with In, Ge, or Si. If necessary, an adhesion layer and a barrier layer can be introduced between the bonding metal layer and the P-type ohmic layer.

[0112] In one embodiment, such as Figure 12 As shown, the patterning of the bonding metal layer drives the area extending outward from the peripheral common cathode (CC) region on the wafer surface. The outward extension distance D of the bonding metal layer relative to the peripheral CC region is in the range of 50µm to 500µm. A bonding metal layer is fabricated within this area, with the periphery either filled with a dielectric layer or left blank. By patterning the P-type ohmic contact layer and the bonding metal layer, stress control during the film layer and bonding process is achieved, preventing excessive warpage. Furthermore, compared to a full-surface metal layer, the patterned wafer contains less metal, especially since precious metals can be recycled, resulting in lower costs. Additionally, the non-full-surface metal area allows for the pre-arrangement of alignment marks required for bonding, exposure, and other processes on the driving wafer, without metal obstruction, making the process easier to implement. Compared to pixel-level alignment bonding, this extended area allows for coarse alignment or lower alignment precision requirements, and is not limited by pixel size, making it easier to engineer.

[0113] In one embodiment, a Si-based GaN compound wafer is selected, and the P-type ohmic contact layer is 110nm ITO + 2nm Cr adhesive layer + 50nm Pt reflective layer. The bonding metal layer on the compound epitaxial layer and driving wafer may specifically include a 10nm Ti adhesive layer, a 20nm Pt barrier layer, 40nm Ni and 100nm Sn bonding metals, and a 10nm Au oxide barrier layer on the surface. The P-type ohmic contact layer and bonding metal layer extend outward by D=200um compared to the peripheral common cathode (CC) region. A dielectric layer fills the area around the bonding metal layer; this dielectric layer can be inorganic materials such as silicon oxide and silicon carbide, or organic materials such as SU8 and polyimide.

[0114] (3) Perform wafer-level heterogeneous integration bonding.

[0115] Specifically, after activating the compound epitaxial layer and the driving wafer surface with Ar or N2 plasma, the wafer contour is roughly aligned and then hot-pressed for bonding, for example, at a bonding temperature of 310℃ and a pressure of 5000Kg. The bonding metal layer and dielectric layer (if any) are then integrated together through bonding. Figure 13 This is a schematic diagram of the integrated bonding wafer corresponding to the full-surface design of the bonding metal layer 31. Figure 14 A schematic diagram of the integrated bonding wafer corresponding to the graphical design of the bonding metal layer 31.

[0116] (4) Prepare N-type ohmic contacts.

[0117] Specifically, such as Figure 15 As shown, substrate removal for the compound epitaxial layer can be performed using methods such as laser lift-off, fluorine-based plasma dry etching, or fluorine-based or amino-based wet etching to remove the substrate 35. In one embodiment, the Si substrate is removed using chemicals such as HF. After substrate removal, the compound epitaxial layer is exposed to the N-type ohmic contact layer 34 by plasma etching, resulting in the desired structure. Figure 16 The structure shown is used to prepare a transparent conductive film layer with an N-type ohmic contact, resulting in the following: Figure 17 The structure shown includes transparent conductive film layers such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), Al-doped zinc oxide (AZO), Al-doped indium tin oxide, Ag-doped indium tin oxide, and Au-doped indium tin oxide.

[0118] In one embodiment, such as Figure 18 As shown, the surface of the N-type ohmic contact layer 34 is first roughened, and then a transparent conductive film layer of the N-type ohmic contact is prepared, thereby obtaining the following... Figure 19 The structure shown can be roughened by plasma dry etching, acid or alkali wet etching. For example, using KOH solution to roughen the N-type GaN surface can obtain a hexagonal pyramidal roughened surface, and using phosphorus solution to roughen the N-type GaN surface can obtain a dodecagonal pyramidal roughened surface.

[0119] (5) Perform pixel preparation.

[0120] Specifically, such as Figure 20 As shown, the light-emitting unit 30 is fabricated by patterning the compound and bonding metal layer corresponding to the anode contact 10. The patterning etching can be plasma etching, ion beam etching, wet etching, etc. The etching angles A and B can be different, and the angle range is within 90°±45°. The distance between the compound and the bonding metal layer 31 in the light-emitting unit 30 is 0≤L1≤25um, and the distance between the bonding metal layer 31 and the cathode wiring area 20 is 0.2um≤L2≤40um. The size range of the light-emitting unit 30 is 1um~200um.

[0121] Step S4: A continuous common cathode layer is applied to the top of the cathode wiring area and the top of the pixel unit.

[0122] In one possible implementation, step S3 specifically includes the following steps:

[0123] (1) A passivation layer is prepared on the periphery of the light-emitting unit and on the surface of the driving wafer.

[0124] Specifically, after etching the light-emitting unit, an insulating dielectric film is deposited around the light-emitting unit, thereby forming a passivation layer on the surface of the driving wafer around the light-emitting unit.

[0125] (2) The N-type ohmic contact layer and cathode wiring area of ​​the light-emitting unit are exposed by plasma etching.

[0126] Specifically, plasma etching is performed on the top of the light-emitting unit and part of the passivation layer on the top of the cathode wiring area to expose the N-type ohmic contact layer and the cathode wiring area of ​​the light-emitting unit.

[0127] (3) A common cathode layer is prepared on the periphery of the display module.

[0128] Specifically, a common cathode layer is prepared on the periphery of the display module by means of transparent conductive film deposition, so that the common cathode layer is covered on the top of the cathode wiring area and the top of the pixel unit.

[0129] Furthermore, after the common cathode layer is fabricated in step S4, the following step is also included: fabricating a microlens structure aligned with the light-emitting unit and deposited on the common cathode layer. The method for forming the microlens structure can be in-situ growth, patterned etching, etc., and this application does not limit this approach.

[0130] In one embodiment, such as Figure 21 As shown, a metal is prepared on the cathode wiring region 20. This metal can be a partially bonded metal layer or it can be prepared on the cathode wiring region by metal plating. The metal is used to block abnormalities such as oxidation or migration of the exposed cathode wiring region 20. The size of L3 to which the metal belongs is greater than or equal to the size of the exposed cathode wiring region 20 below it. Then, a passivation layer 60, a common cathode layer 40, and a microlens structure 50 are prepared.

[0131] In one embodiment, such as Figure 22 As shown, the distance L1 between the compound and the bonding metal layer 31 in the light-emitting unit 30 is designed to be 0. After the passivation layer 60 is deposited, only the passivation layer 60 on the sidewall of the light-emitting unit 30 is retained by in-situ etching to expose the relevant N contact area (N-type ohmic contact layer and cathode wiring area) to the maximum extent. Then, the common cathode layer 40 and the microlens structure 50 are fabricated.

[0132] In one embodiment, such as Figure 23As shown, during the fabrication of the light-emitting unit 30, only compound etching is performed, retaining the bonding metal layer 31. Then, after depositing the dielectric layer and metal layer, in-situ etching is performed, retaining the dielectric and metal layers on the sidewalls of the light-emitting unit to form a sidewall dielectric layer 61 and a sidewall metal layer 62. This metal layer can be a single layer or multiple layers of high-reflectivity metals such as Al, Au, and Pt. The sidewall dielectric layer 61 and the sidewall metal layer 62 constitute total internal reflection, enhancing crosstalk between the light-emitting units 30 and the light extraction of the pixels. After completing the fabrication of the sidewall dielectric layer 61 and the sidewall metal layer 62, an insulating dielectric is deposited again to form a passivation layer 60, and patterned etching exposes the N-contact region (N-type ohmic contact layer and cathode wiring region). Then, the common cathode layer 40 and the microlens structure 50 are fabricated.

[0133] In summary, the fabrication method of the microdisplay device provided in this application embodiment performs cathode wiring on the driving wafer. For each pixel area in the pixel array AA area on the surface of the driving wafer, it is divided into an anode contact and a cathode wiring area. The anode contact and the cathode wiring area are mutually insulated. The light-emitting unit corresponding to each pixel area is connected to the anode contact in the corresponding pixel area. The bottom does not contact the cathode wiring area in the corresponding pixel area. A common cathode layer is covered on the top of the cathode wiring area and the top of the light-emitting unit in each pixel area. Through the cathode wiring below, the layout between the light-emitting unit and the cathode electrical enhancement structure is transformed from a 2D horizontal layout to a 3D vertical layout. This solves the problem of the light-emitting unit and the cathode electrical enhancement structure competing for horizontal space, which can maximize optical enhancement and electrical enhancement. Furthermore, the large area of ​​metal cathode wiring at the bottom can improve the heat dissipation capacity of the chip.

[0134] All the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of this utility model. That is, any number of embodiments can be combined to meet the needs of different application scenarios. All of these are within the protection scope of this application and will not be described in detail here.

[0135] It should be noted that the above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A microdisplay device having a cathode wiring area, characterized in that, The microdisplay device includes: A driving wafer, the surface of which includes a pixel array AA region, each pixel region in the pixel array AA region including: mutually insulated anode contacts and a cathode wiring region, the cathode wiring region surrounding the edge region of the pixel region, and the cathode wiring regions between adjacent pixel regions being interconnected; The display module is disposed on the driving wafer. The display module includes light-emitting units corresponding to each pixel area. The light-emitting units are connected to the anode contacts in the corresponding pixel area, and their bottoms are not in contact with the cathode wiring areas in the corresponding pixel area. In this embodiment, a continuous common cathode layer is provided on the top of the cathode wiring area of ​​each pixel region and on the top of the light-emitting unit.

2. The microdisplay device according to claim 1, characterized in that, The surface of the driving wafer also includes: a peripheral common cathode (CC) region; The cathode wiring area in the outer portion of the pixel array AA region is connected to the outer common cathode CC region, and the common cathode layer extends to the outer common cathode CC region, so that the cathode wiring area, the common cathode layer, and the outer common cathode CC region form a loop.

3. The microdisplay device according to claim 1, characterized in that, In each pixel region, the anode contact is located in the middle region of the pixel region, the cathode wiring region is located in the edge region of the pixel region, and there is an insulating region between the anode contact and the cathode wiring region.

4. The microdisplay device according to claim 3, characterized in that, The cathode wiring area includes a first layer of cathode wiring area with a trench pattern.

5. The microdisplay device according to claim 4, characterized in that, The cathode wiring area also includes a second cathode wiring area with a hole pattern. The second cathode wiring area is disposed above the first cathode wiring area, and the projection of the second cathode wiring area on the driving wafer is located within the projection of the first cathode wiring area on the driving wafer.

6. The microdisplay device according to claim 5, characterized in that, Multiple pixel regions share a single second-layer cathode wiring region; or, Each pixel region shares multiple second-layer cathode wiring regions.

7. The microdisplay device according to claim 3, characterized in that, The size of the cathode wiring area is between 0.1um and 30um, the size of the anode contact is between 0.1um and 100um, and the size of the insulating area is not less than 0.1um.

8. The microdisplay device according to claim 1, characterized in that, The cathode wiring area is a composite stacked structure, which includes: a composite metal layer and a current transmission layer; The composite metal layer includes at least one of an adhesive layer, a barrier layer, and a seed layer.

9. The microdisplay device according to claim 1, characterized in that, The display module also includes: A microlens structure is aligned with the light-emitting unit and is disposed on the common cathode layer.

10. The microdisplay device according to claim 9, characterized in that, The radius of the microlens structure in the horizontal direction is greater than 55% of the size of the light-emitting unit.

11. The microdisplay device according to claim 1, characterized in that, A passivation layer is provided between the sidewall of the light-emitting unit and the common cathode layer, and between the area of ​​the pixel array AA region other than the cathode wiring area and the area in contact with the bottom of the light-emitting unit and the common cathode layer.

Images