Array substrate and display panel

Abstract

The present application provides an array substrate and a display panel. The array substrate comprises a base, at least one pixel group arranged on the base, and three data line groups. Each pixel group comprises six subpixels spaced apart from one another along a first direction, each subpixel comprising at least one pixel electrode. Each data line group is associated with the pixel electrode of one of the subpixels, and the data line group is located on a side of the pixel electrode close to the base.Each of the data line groups comprises two data lines spaced apart from each other along the first direction, and the pixel electrode of each of the subpixels is electrically connected to one of the data lines; by arranging the data lines below the respective pixel electrodes in the present application, a DBS electrode can thus be omitted, thereby significantly increasing the aperture ratio of the subpixels to alleviate the problem of limited increase in aperture ratio in existing liquid crystal display panels.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display technology, in particular to an array substrate and a display panel. STATE OF THE ART

[0002] A liquid crystal display (LCD) panel features numerous advantages, including a thin body, low power consumption, and zero radiation. It is widely used and plays a dominant role in the field of flat-panel displays. A liquid crystal display panel works on the principle that liquid crystal molecules are filled between a thin-film transistor (TFT) array substrate and a color filter (CF) substrate. A driving voltage is applied to the two substrates to control the rotation direction of the liquid crystal molecules and thus refract light rays from a backlight module outward, creating an image.

[0003] In a conventional liquid crystal display panel, a black matrix (BM) must be provided on one side of the color filter substrate to block light. When applied to a curved liquid crystal display panel, bending the panel causes a shift in the position of the BM, which in turn leads to light leakage and color deviation. To solve this problem, a Data BM Less (DBS) design can be used, which reduces the number of black matrices on data lines. That is, a DBS electrode is provided above a data line of the array substrate, arranged on the same layer as a pixel electrode, and a state is maintained where there is no voltage difference between the DBS electrode and a common electrode on the color filter substrate.Thus, the liquid crystal between the DBS electrode and the common electrode does not rotate and thus exhibits a black state to block light instead of a black matrix. However, the presence of a DBS electrode limits the ability to increase the aperture ratio of a liquid crystal display panel.

[0004] CN 1 13 936 564 A relates to a display panel with a control unit and a sub-pixel array arranged on a substrate. The sub-pixel array comprises a plurality of pixel groups arranged in columns and rows. Furthermore, a plurality of data line groups are provided, each of the data line groups being assigned to a pixel electrode of one of the sub-pixels of the array. The data line groups comprise a plurality of data lines arranged at a distance from one another. The pixel electrode of each of the sub-pixels is electrically connected to one of the data lines.

[0005] US 2019 / 0131320 A1 relates to a display panel comprising first and second signal lines, each extending in a first direction and spaced apart from each other. The signal lines overlap with associated pixel electrodes. In a plan view, the signal lines are arranged closer to a vertical portion than to an outer edge of a pixel electrode. DISCLOSURE OF THE INVENTION

[0006] The present application is based on the object of providing an array substrate and a display panel to alleviate the technical problem of limited increase in the aperture ratio in existing liquid crystal display panels.

[0007] According to the present application, the object is achieved by an array substrate according to claim 1.

[0008] An embodiment of the present application provides an array substrate comprising: a base; at least one pixel group arranged on the base, each pixel group comprising six subpixels spaced apart from one another along a first direction, each of which subpixels comprises at least one pixel electrode; and three data line groups arranged on the base, each of the data line groups being associated with the pixel electrode of one of the subpixels, the data line group being located on a side of the pixel electrode close to the base; wherein each of the data line groups comprises two data lines arranged spaced apart from each other along the first direction, and the pixel electrode of each of the subpixels is electrically connected to one of the data lines.

[0009] In the array substrate, it is provided that each of the pixel electrodes comprises a first main electrode extending along a second direction, to which the respective data line group is assigned.

[0010] In the array substrate, it is provided that the orthogonal projection of the first main electrode onto the base covers the orthogonal projection of the associated data line group onto the base.

[0011] In the array substrate according to the embodiment of the present application, it is provided that the first main electrode comprises a first subsection and a second subsection, wherein the first subsection is assigned to one of the data lines in the respective data line group and the second subsection is assigned to the other data line in the respective data line group.

[0012] In the array substrate according to the embodiment of the present application, it is provided that the pixel electrode further comprises a second main electrode extending along the first direction, to which both the first subsection and the second subsection are electrically connected.

[0013] In the array substrate according to the embodiment of the present application, it is provided that the two data lines in the data line group each have the shape of a polygon line.

[0014] In the array substrate according to the embodiment of the present application, it is provided that each of the subpixels further comprises at least one transistor, wherein the pixel electrode of each of the subpixels is electrically connected to the associated transistor, wherein the transistor is electrically connected to the associated data line; wherein the transistors of some of the six subpixels are located on a first side of the pixel group and the transistors of the other subpixels are located on a second side of the pixel group, wherein the first side is opposite the second side.

[0015] In the array substrate according to the embodiment of the present application, the array substrate further comprises a first gate scanning line and a second gate scanning line extending along the first direction, wherein the first gate scanning line is electrically connected to the gates of the transistors of the first side and the second gate scanning line is electrically connected to the gates of the transistors of the second side.

[0016] In the array substrate according to the embodiment of the present application, the pixel group is provided in a plurality, and the plurality of pixel groups are spaced apart from each other along the second direction; the array substrate further comprises a third gate scanning line extending along the first direction, wherein two adjacent pixel groups share the third gate scanning line.

[0017] In the array substrate according to the embodiment of the present application, it is provided that the array substrate further comprises a plurality of common electrode lines extending along the second direction, which are arranged on the same layer as the data lines, wherein the common electrode lines are assigned to the spaces between each two adjacent subpixels.

[0018] In the array substrate according to the embodiment of the present application, the six subpixels comprise two first-color subpixels, two second-color subpixels, and two third-color subpixels; wherein one of the three data line groups is assigned to one of the two first-color subpixels and the other two data line groups are assigned to the two second-color subpixels, and wherein the two data lines in each of the data line groups are electrically connected to the pixel electrodes in the two subpixels of one and the same color.

[0019] In the array substrate according to the embodiment of the present application, it is provided that the polarities of the voltages on the two data lines in each of the data line groups are different.

[0020] In the array substrate according to the embodiment of the present application, the first-color subpixels are blue subpixels, the second-color subpixels are green subpixels, and the third-color subpixels are red subpixels; wherein the three data line groups comprise a first data line group, a second data line group, and a third data line group, wherein the first data line group is assigned to one of the two first-color subpixels, and the second data line group and the third data line group are assigned to the two second-color subpixels;wherein the two data lines in the first data line group are electrically connected to the pixel electrodes in the two subpixels of second color, wherein the two data lines in the second data line group are electrically connected to the pixel electrodes in the two subpixels of third color, and wherein the two data lines in the third data line group are electrically connected to the pixel electrodes in the two subpixels of first color;

[0021] In the array substrate according to the embodiment of the present application, it is provided that the first color subpixel and the second color subpixel are located between two adjacent third color subpixels, wherein the first color subpixel and the third color subpixel are located between two adjacent second color subpixels, wherein the second color subpixel and the third color subpixel are located between two adjacent first color subpixels, and wherein the first color subpixels, the second color subpixels and the third color subpixels are arranged spaced from one another in the first direction in sequence.

[0022] In the array substrate according to the embodiment of the present application, it is provided that the array substrate further comprises a fourth data line group which is assigned to the other of the two subpixels of the first color, wherein the fourth data line group and the first data line group are formed identically.

[0023] An embodiment of the present application further provides a display panel according to claim 14. It comprises the array substrate according to any one of the preceding embodiments.

[0024] Advantageous Effects of the Application: In the array substrate and the display panel according to the present application, the array substrate comprises a base, at least one pixel group arranged on the base, and three data line groups. Each pixel group comprises six subpixels spaced apart from one another along the first direction, each of which comprises at least one pixel electrode. Each of the data line groups is associated with the pixel electrode of one of the subpixels, and the data line group is located on a side of the pixel electrode close to the base.Each of the data line groups comprises two data lines arranged spaced apart from each other along the first direction, and the pixel electrode of each of the subpixels is electrically connected to one of the data lines. Thus, by arranging the data lines below the respective pixel electrodes in the present application, a DBS electrode can be eliminated, thereby significantly increasing the aperture ratio of the subpixels, thus solving the technical problem of limited aperture ratio increase in existing liquid crystal display panels. PRESENTATION OF THE REGISTRATION

[0025] To better explain the embodiments of the present invention or the prior art embodiments, the accompanying drawings used to describe the embodiments or the prior art are briefly described below. It is understood that the following drawings represent only some embodiments of the invention and that it is possible for those skilled in the art to obtain further drawings from such drawings without inventive steps. Fig. 1 is a schematic plan view of a pixel structure in related art; Fig. 2 is a schematic structural plan view of an array substrate according to an embodiment of the present application; Fig. 3 is another schematic structural plan view of the array substrate according to the embodiment of the present application; Fig. 4 a schematic structural detail drawing of a first color subpixel according to Fig. 3; Fig. 5 is another schematic structural detail drawing of the first color subpixel according to an embodiment of the present application; Fig. 6 shows a further schematic structural detail drawing of the first color subpixel according to the embodiment of the present application; Fig. 7 is another schematic structural plan view of the array substrate according to the embodiment of the present application; Fig. 8 is a schematic structural sectional view of a display panel according to an embodiment of the present application. CONCRETE EMBODIMENTS

[0026] Individual embodiments are described below with reference to the accompanying drawings in order to illustrate certain feasible embodiments of the application by way of example. Directional terms mentioned in the present application, for example "top", "bottom", "front", "back", "left", "right", "inside", "outside", "side surface", etc., are used only with reference to respective directions in the accompanying drawings. Therefore, the directional terms used serve to describe and promote understanding of the application without limiting the application. In the drawings, similarly designed units are provided with the same reference numerals. In the accompanying drawings, the thicknesses of some layers and regions may be exaggerated for better understanding and to facilitate description.This means that the dimensions and thicknesses of the individual components shown in the drawings are not necessarily shown to scale and the application is in no way limited to this.

[0027] In view of the problem of limited increase in the aperture ratio in existing liquid crystal display panels, the inventor of the present application found through investigations that due to the use of the design (Data BM less, DBS) in which the number of black matrices on data lines is reduced in the related art, a DBS electrode occupies a part of the pixel space, thereby impairing the increase in the aperture ratio of the pixels.

[0028] It is specifically aimed at Fig. 1. The DBS electrode is arranged on the same layer as a pixel electrode PE. The DBS electrode covers a dedicated data line DL. The width of the DBS electrode is larger than the width of the data line DL. A common electrode CE is provided in the space between the DBS electrode and the pixel electrode PE, and a part of the common electrode CE is further arranged below a main electrode of the pixel electrode PE. The common electrode CE is arranged on the same layer as a gate scanning line GL. The light shielding by the DBS electrode in cooperation with the common electrode CE significantly reduces the effective display area of ​​the liquid crystal display panel, thereby significantly lowering the aperture ratio. This, in turn, limits the ability to increase the aperture ratio of the liquid crystal display panel.

[0029] Therefore, the present application provides an array substrate and a display panel to solve the above problem of limited increase in the aperture ratio.

[0030] It will be Fig. 1 to 2. Fig. Figure 2 shows a schematic structural plan view of the array substrate according to an embodiment of the present application. Fig. 2. The array substrate 100 comprises a base 10, at least one pixel group 20 arranged on the base 10, and three data line groups 30. Each pixel group 20 comprises six subpixels spaced apart from one another along a first direction X (for example, R1, G1, B1, R2, G2 and B2 in Fig. 2), each of which has at least one pixel electrode 40 (for example, 40-1, 40-2, 40-3, 40-4, 40-5 and 40-6 in Fig. 2). Each of the data line groups 30 is assigned to the pixel electrode 40 of one of the subpixels and the data line 30 is located on a side of the pixel electrode 40 close to the base 10. Each of the data line groups 30 comprises two data lines arranged spaced apart from one another along the first direction X (for example 31 and 32 in Fig. 2) and the pixel electrode 40 of each of the subpixels is electrically connected to one of the data lines. Each of the data lines extends along a second direction Y, which is different from the first direction X. Optionally, the first direction X is the horizontal direction and the second direction X is the vertical direction. The first direction X is perpendicular to the second direction Y.

[0031] By arranging the data line groups 30 below the pixel electrodes 40 of the pixel group 20 in the present embodiment, the DBS electrode for light shielding the data lines in the related art can be eliminated. Thus, the pixel electrodes can be extended outward to increase the area of ​​a subpixel opening region. Thus, the aperture ratio of the subpixels can be significantly increased, thereby solving the problem of limited aperture ratio increase in existing liquid crystal display panels.

[0032] Specifically, the focus will be on Fig. 2. The pixel group 20 is arranged on the base 10. The base 10 may be a rigid substrate or a flexible substrate; if the base 10 is a rigid substrate, it may comprise a glass substrate or other hard substrate; if the base 10 is a flexible substrate, it may comprise a polyimide thin film (polyimide, PI), an ultra-thin glass thin film, or another flexible substrate.

[0033] Each pixel group 20 comprises six subpixels (for example, R1, G1, B1, R2, G2 and B2 in Fig. 2), the two subpixels of first color (for example B1 and B2 in Fig. 2), two subpixels of second color (for example G1 and G2 in Fig. 2) and two subpixels of third color (for example R1 and R2 in Fig. 2). The first-color subpixel and the second-color subpixel are located between two adjacent third-color subpixels. For example, B1 and G1 are located between R1 and R2 in Fig. 2. The first-color subpixel and the third-color subpixel are located between two adjacent second-color subpixels. For example, B1 and R2 are located between G1 and G2 in Fig. 2. The second-color subpixel and the third-color subpixel are located between two adjacent first-color subpixels. For example, G2 and R2 are located between B1 and B2 in Fig. 2. This means that every three adjacent subpixels comprise a so-called subpixel of the first color, a so-called subpixel of the second color and a so-called subpixel of the third color, so that every three adjacent subpixels can form a pixel.

[0034] The subpixels of the first color (for example B1 and B2 in Fig. 2) Blue subpixels, the subpixels of the second color (for example G1 and G2 in Fig. 2) Green subpixels and the third color subpixels (for example, R1 and R2 in Fig. 2) Red subpixels. The blue subpixels can emit blue light. The green subpixels can emit green light. The red subpixels can emit red light. Since each three adjacent subpixels contain three colors, the pixel formed by each three adjacent subpixels can emit light of different colors, thus realizing a color display.

[0035] Optionally, the first-color subpixels, the second-color subpixels, and the third-color subpixels are arranged spaced apart from each other in the first direction X. That is, the six subpixels are arranged in the first direction in the order of first-color subpixel B2, second-color subpixel G2, third-color subpixel R2, first-color subpixel B1, second-color subpixel G1, and third-color subpixel R1, as shown in Fig. 2 shown, arranged.

[0036] The three data line groups 30 are also arranged on the base 10 and are assigned to some of the subpixels of the pixel group 20. Each of the data line groups 30 comprises two data lines (for example, 31 and 32 in Fig. 2). Thus, the three data line groups 30 comprise six data lines connected to the six subpixels of the pixel group 20.

[0037] In detail, each of the subpixels comprises at least one pixel electrode 40, and each of the data lines is electrically connected to the pixel electrode 40 of an associated subpixel. The data line is located on the side of the pixel electrode 40 closest to the base 10. That is, the data line is located between the respective pixel electrode 40 and the base 10. Thus, the data line group 30 associated with the data line is also located on the side of the respective pixel electrode 40 closest to the base 10. That is, the data group 30 is also located between the respective pixel electrode 40 and the base 10. Optionally, the material of the pixel electrode 40 comprises indium tin oxide (ITO) and other transparent electrically conductive materials.

[0038] The orthogonal projection of the data line group 30 onto the base 10 at least partially overlaps with the orthogonal projection of the associated pixel electrode 40 onto the base 10. Optionally, each of the pixel electrodes 40 comprises a first main electrode 41 extending along a second direction Y, to which the respective data line group 30 is assigned. The orthogonal projection of the first main electrode 41 onto the base 10 at least partially overlaps with the orthogonal projection of the respective data line group 30 onto the base 10. The data line group 30 is assigned to the first main electrode 41.Thus, on the one hand, a DBS electrode for shielding the data line from light in related art can be omitted, so that the pixel electrode 40 is extended outward to increase the area of ​​a pixel opening region and enhance the aperture ratio of the subpixels; on the other hand, since the region associated with the first main electrode 41 is not light-transmitting, the influence of the data line groups 30 on the light emission can be reduced or eliminated, thus further increasing the aperture ratio of the subpixels.

[0039] Each of the pixel electrodes 40 further includes a second main electrode 42 extending along the first direction X, and branch electrodes 43 extending in different directions from the second main electrode 42 and / or the first main electrode 41. The second main electrode 42 intersects the first main electrode 41 and is at a predetermined angle thereto. For example, the second main electrode 42 runs perpendicular to the first main electrode 41 to divide the subpixel into four domains. The branch electrodes 43 are distributed in individual domains. Optionally, the pixel electrode 40 may further include a frame electrode 44 enclosing the first main electrode 41, the second main electrode 42, and the branch electrodes 43 over half their circumference.

[0040] It should be noted that in the drawings of the application, only some of the branch electrodes 43 of the pixel electrode 40 are shown schematically. For example, in Fig. 2 illustrates three branch electrodes 43 per domain, but the present application is by no means limited to this. The pixel electrode 40 according to the present application may further comprise more or fewer branch electrodes 43. Furthermore, embodiments of the application are described using the example of the configuration in which each of the subpixels is divided into four domains. The present application is not limited to this either; rather, subpixels in the present application may alternatively be divided into two domains, six domains, eight domains, etc.

[0041] Furthermore, one of the three data line groups 30 is assigned to one of the two subpixels of first color and the other two data line groups 30 are assigned to the two subpixels of second color.

[0042] In detail, the three data line groups 30 include a first data line group 30-1, a second data line group 30-2, and a third data line group 30-3. The first data line group 30-1 is assigned to one of the two subpixels of the first color, and the second data line group 30-2 and the third data line group 30-3 are assigned to the two subpixels of the second color. The two data lines in each of the data line groups are electrically connected to the pixel electrodes in the two subpixels of the same color to compensate for a coupling capacitor between subpixels and improve longitudinal crosstalk and color deviation.

[0043] The two data lines in the first data line group 30-1 are electrically connected to the pixel electrodes in the two subpixels of the second color. The two data lines in the second data line group 30-2 are electrically connected to the pixel electrodes in the two subpixels of the third color. The two data lines in the third data line group 30-3 are electrically connected to the pixel electrodes in the two subpixels of the first color.

[0044] Optionally, the polarities of the voltages on the two data lines in each of the data line groups 30 are different to reduce a coupling effect on the pixel voltage when a data signal changes and to reduce the risk of longitudinal crosstalk. In detail, the two data lines in each of the data line groups 30 are a first data line 31 and a second data line 32. The polarity of the voltage on the first data line 31 and the polarity of the voltage on the second data line 32 are different. For example, the voltage on the first data line 31 has a positive polarity and the voltage on the second data line 32 has a negative polarity; alternatively, the voltage on the first data line 31 has a negative polarity and the voltage on the second data line 32 has a positive polarity.

[0045] In order to better explain the connection relationship between the data lines and the associated subpixels, one of the two subpixels of the same color is defined as 1 and the other as 2. For example, one of the two first-color subpixels is B1 and the other first-color subpixel is B2. Accordingly, one of the two second-color subpixels is G1 and the other second-color subpixel is G2. One of the two third-color subpixels is R1 and the other third-color subpixel is R2. The six subpixels are arranged on the basis of 10 along the first direction X in the order of first-color subpixel B2, second-color subpixel G2, third-color subpixel R2, first-color subpixel B1, second-color subpixel G1, and third-color subpixel R1.

[0046] Furthermore, pixel electrodes 40 are defined, which are assigned to the individual subpixels. For example, the pixel electrode of the first-color subpixel B2 is 40-6. The pixel electrode of the second-color subpixel G2 is 40-5. The pixel electrode of the third-color subpixel R2 is 40-4. The pixel electrode of the first-color subpixel B1 is 40-3. The pixel electrode of the second-color subpixel G1 is 40-2. The pixel electrode of the third-color subpixel R1 is 40-1.

[0047] Each of the subpixels further includes at least one transistor. The pixel electrode 40 of each of the subpixels is electrically connected to the associated transistor. In detail, each of the pixel electrodes 40 further includes a connection electrode 45, and the pixel electrode 40 of each of the subpixels is electrically connected to the associated transistor via the connection electrode 45. The transistor is further electrically connected to the associated data line; the transistors of some of the six subpixels are located on a first side of the pixel group 20, and the transistors of the other subpixels are located on a second side of the pixel group 20, with the first side opposite the second side, in order to equalize the aperture ratios of the individual subpixels, increase display uniformity, and avoid a large deviation in the aperture ratios of the subpixels from one another due to the arrangement of the transistors on one and the same side of the pixel group 20.

[0048] The transistor of each subpixel is defined analogously. For example, the transistor of the first-color subpixel B2 is T6. The transistor of the second-color subpixel G2 is T4. The transistor of the third-color subpixel R2 is T2. The transistor of the first-color subpixel B1 is T5. The transistor of the second-color subpixel G1 is T3. The transistor of the third-color subpixel R1 is T1.

[0049] Each of the transistors comprises a gate, a source, and a drain. Using the example of transistor T1 of the third-color subpixel R1, transistor T1 comprises a gate GE, a source S1, and a drain D1. It should be understood that each of the transistors further comprises an active layer, which is not shown.

[0050] The array substrate 100 further includes a first gate scan line 51 and a second gate scan line 52 extending along the first direction X. The first gate scan line 51 is electrically connected to the gates of the transistors of the first side of the pixel group 20, and the second gate scan line 52 is electrically connected to the gates of the transistors of the second side of the pixel group 20. For example, the first gate scan line 51 is electrically connected to the gates of the transistors T3, T4, T5, and T6, while the second gate scan line 52 is electrically connected to the gates of the transistors T1 and T2.

[0051] The following is based on reference to Fig. 2 the connection relationship between the pixel group 20 and the data line groups 30 is discussed in more detail.

[0052] It will be Fig. 2. The pixel electrode 40-6 in the first-color subpixel B2 is electrically connected to the transistor T6, which is further electrically connected to the second data line 32 in the third data line group 30-3. The pixel electrode 40-3 in the first-color subpixel B1 is electrically connected to the transistor T5, which is further electrically connected to the first data line 31 in the third data line group 30-3. The pixel electrode 40-5 in the second-color subpixel G2 is electrically connected to the transistor T4, which is further electrically connected to the second data line 32 in the first data line group 30-1. The pixel electrode 40-2 in the second-color subpixel G1 is electrically connected to the transistor T3, which is further electrically connected to the first data line 31 in the first data line group 30-1.The pixel electrode 40-4 in the third-color subpixel R2 is electrically connected to the transistor T2, which is further electrically connected to the second data line 32 in the second data line group 30-2. The pixel electrode 40-1 in the third-color subpixel R1 is electrically connected to the transistor T1, which is further electrically connected to the first data line 31 in the second data line group 30-2.

[0053] An example is shown in Fig. 1 to 4. Fig. 3 shows another schematic structural plan view of the array substrate according to the embodiment of the present application. Fig. Figure 4 shows a schematic structural detail drawing of the first color subpixel according to Fig. 3. In contrast to the above embodiments, in the array substrate 101 according to the present embodiment, the first main electrode 41 comprises a first subsection 411 and a second subsection 412, and both the first subsection 411 and the second subsection 412 are electrically connected to the second main electrode 42. The first subsection 411 is assigned to one of the data lines in the respective data line group 30, and the second subsection 412 is assigned to the other data line in the respective data line group 30 in order to optimize the interaction of the liquid crystal and avoid dark stripes during alignment.

[0054] In detail, Fig. 3 and Fig. 4. For the subpixels assigned to the respective data line groups 30, the first main electrode 41 of the pixel electrode comprises two parts. Using the example of the pixel electrode 40-3 of the first color subpixel B1, the first color subpixel B1 is assigned to the first data line group 30-1. As shown in Fig. As shown in Figure 4, the first main electrode 41 includes a first subsection 411 and a second subsection 412. The first subsection 411 is associated with the first data line 31 in the first data line group 30-1. The second subsection 412 is associated with the second data line 32 in the first data line group 30-1.

[0055] Furthermore, in the present embodiment, it is provided that the array substrate 101 further comprises a plurality of common electrode lines 60 extending along the second direction Y, which are arranged on the same layer as the data line groups 30. That is, the common electrode lines 60 are arranged on the same layer as each of the data lines. Furthermore, the common electrode lines 60 are assigned to the spaces between each two adjacent subpixels. For example, the common electrode line 60 is Fig. 3 is assigned to the space between the subpixel of the third color R2 and the subpixel of the first color B1. Thus, in comparison to the pixel structure according to Fig. 1 in the application, by changing the position of the data lines, a common electrode CE, which is arranged in related art on the same layer as the gate scanning line GL, can be omitted, thus reducing the coupling effect for the common voltage when a data signal changes, reducing the risk of crosstalk in the longitudinal direction and further improving the image quality.

[0056] It should be noted that in the present application, "arrangement on the same layer" means that, during the manufacturing process, a membrane layer made of the same material is patterned, thereby obtaining at least two different structures. Thus, the at least two structures are arranged on the same layer. In the present embodiment, for example, the data lines and the common electrode lines 60 are obtained by patterning one and the same electrically conductive membrane layer. Thus, the data lines and the common electrode lines 60 are arranged on the same layer.

[0057] It will continue on Fig. 3. Optionally, the array substrate 101 further comprises a fourth data line group 30-4 associated with the other of the two first-color subpixels. For example, the fourth data line group 30-4 is associated with the first-color subpixel B2, and the first data line group 30-1 is associated with the first-color subpixel B1. The fourth data line group 30-4 and the first data line group 30-1 are identical in design to maintain a uniform aperture of the two first-color subpixels and thus reduce color deviation. The data lines in the fourth data line group 30-4 are dummy signal lines and are not electrically connected to the subpixel. Other details can be found in the above embodiments, and they are omitted here.

[0058] In order to avoid dark stripes during alignment, in another embodiment, the configurations according to Fig. 5 and Fig. 6 can be used. Fig. 5 shows another schematic structural detail drawing of the first color subpixel according to an embodiment of the present application and Fig. Figure 6 shows a further schematic structural detail drawing of the first color subpixel according to the embodiment of the present application. Fig. 5. The orthogonal projection of the first main electrode 41 onto the base 10 covers the orthogonal projection of the associated data line group 30 onto the base 10. Fig. 6. The two data lines in the data line group 30 each have the shape of a polygon line.

[0059] The following description is also based on the example of the pixel electrode 40-3 of the first color subpixel B1. The first color subpixel B1 is assigned to the first data line group 30-1. As shown in Fig. As shown in Figure 5, the orthogonal projection of the first main electrode 41 of the pixel electrode 40-3 onto the base 10 covers the orthogonal projection of the first data line group 30-1 onto the base 10. That is, the width of the first main electrode 41 is greater than the sum of the widths of the first data line 31 and the second data line 32 in the first data line group 30-1.

[0060] It will be Fig. 6. The first main electrode 41 of the pixel electrode 40-3 includes a first subportion 411 and a second subportion 412 that overlap with each other in the second direction Y. That is, the first subportion 411 and the second subportion 412 are located on the same straight line. The first data line 31 in the first data line group 30-1 has the shape of a polygonal line. A part of the first data line 31 is associated with the first subportion 411, and the other part is located between the first subportion 411 and the frame electrode 44. That is, a part of the first data line 31 is covered by the first subportion 411, and the other part is not covered by the first subportion 411. Accordingly, the second data line 32 in the first data line group 30-1 also has the shape of a polygonal line.Part of the second data line 32 is associated with the second subsection 412, and the other part is located between the second subsection 412 and the frame electrode 44. That is, part of the second data line 32 is covered by the second subsection 412, and the other part is not covered by the second subsection 412. Other details can be found in the above embodiments and are omitted here.

[0061] An example is shown in Fig. 1 to 7. Fig. 7 shows another schematic structural plan view of the array substrate according to the embodiment of the present application. Different from the above embodiments, in the array substrate 102 according to the present embodiment, the pixel group 20 is provided in a plurality, and the plurality of pixel groups 20 are spaced apart from each other along the second direction Y. The array substrate 102 further includes a third gate scanning line 53 extending along the first direction X, with two adjacent pixel groups 20 sharing the third gate scanning line 53 to reduce the number of gate scanning lines. Other details are taken from the above embodiments, and repetition is omitted here.

[0062] Based on the same basic idea, an embodiment of the application further provides a display panel. Fig. 1 to 8. Fig.Figure 8 shows a schematic structural sectional view of the display panel according to an embodiment of the present application. The display panel 1000 includes the array substrate 100 according to any one of the above embodiments. The display panel 1000 further includes a color filter substrate 200 disposed opposite the array substrate 100, and liquid crystal molecules 300 disposed between the array substrate 100 and the color filter substrate 200.

[0063] The following can be seen from the above examples: The present application provides an array substrate and a display panel. The array substrate comprises a base, at least one pixel group arranged on the base, and three data line groups. Each pixel group comprises six subpixels spaced apart from one another along the first direction, each of which comprises at least one pixel electrode. Each of the data line groups is associated with the pixel electrode of one of the subpixels, and the data line group is located on a side of the pixel electrode closest to the base.Each of the data line groups comprises two data lines arranged spaced apart from each other along the first direction, and the pixel electrode of each of the subpixels is electrically connected to one of the data lines. Thus, by arranging the data lines below the respective pixel electrodes in the present application, a DBS electrode can be eliminated, thereby significantly increasing the aperture ratio of the subpixels, thus solving the technical problem of limited aperture ratio increase in existing liquid crystal display panels.

[0064] In the above embodiments, individual embodiments are described with different focuses. For parts not explained in detail in a specific embodiment, reference can be made to the relevant descriptions of other embodiments.

[0065] So far, the embodiments of the application have been presented in detail. The principle and embodiments of the application have been explained using concrete examples, and the description of the above embodiments serves only to support the understanding of the technical embodiments of the application and their core ideas. It will be understood by those of ordinary skill in the art that modifications to the technical embodiments described in the preceding embodiments or equivalent substitutions of some or all of the technical features contained therein are still possible. However, such modifications or substitutions do not cause the main ideas of the corresponding technical embodiments to deviate from the scope of the technical embodiments of the individual embodiments of the present application.

Claims

[1] Array substrate, characterized by that it includes: a base; at least one pixel group arranged on the base, each pixel group comprising six subpixels spaced apart from one another along a first direction, each of which subpixels comprises at least one pixel electrode; and three data line groups arranged on the base, each of the data line groups being associated with the pixel electrode of one of the subpixels, the data line group being located on a side of the pixel electrode close to the base; wherein each of the data line groups comprises two data lines arranged spaced apart from each other along the first direction, and the pixel electrode of each of the subpixels is electrically connected to one of the data lines, wherein each of the pixel electrodes comprises a first main electrode extending along a second direction, to which the respective data line group is assigned, wherein the orthogonal projection of the first main electrode onto the base covers the orthogonal projection of the associated data line group onto the base. [2] Array substrate according to claim 1, characterized by that the first main electrode comprises a first subsection and a second subsection. [3] Array substrate according to claim 2, characterized by that the pixel electrode further comprises a second main electrode extending along the first direction, to which both the first subsection and the second subsection are electrically connected. [4] Array substrate according to claim 1, characterized byin that each of the subpixels further comprises at least one transistor, wherein the pixel electrode of each of the subpixels is electrically connected to the associated transistor, wherein the transistor is electrically connected to the associated data line; wherein the transistors of some of the six subpixels are located on a first side of the pixel group and the transistors of the other subpixels are located on a second side of the pixel group, wherein the first side is opposite the second side. [5] Array substrate according to claim 4, characterized by in that the array substrate further comprises a first gate scan line and a second gate scan line extending along the first direction, wherein the first gate scan line is electrically connected to the gates of the transistors of the first side and the second gate scan line is electrically connected to the gates of the transistors of the second side. [6] Array substrate according to claim 5, characterized byin that the pixel group is provided in a plurality, and the plurality of pixel groups are arranged spaced apart from each other along the second direction; wherein the array substrate further comprises a third gate scanning line extending along the first direction, wherein two adjacent pixel groups share the third gate scanning line. [7] Array substrate according to claim 1, characterized by that the array substrate further comprises a plurality of common electrode lines extending along the second direction, which are arranged on the same layer as the data lines, wherein the common electrode lines are assigned to the spaces between each two adjacent subpixels. [8] Array substrate according to one of claims 1 to 7, characterized bythat the six subpixels comprise two subpixels of first color, two subpixels of second color, and two subpixels of third color; wherein one of the three data line groups is assigned to one of the two subpixels of first color and the other two data line groups are assigned to the two subpixels of second color, and wherein the two data lines in each of the data line groups are electrically connected to the pixel electrodes in the two subpixels of one and the same color. [9] Array substrate according to claim 8, characterized by that the polarities of the voltages on the two data lines in each of the data line groups are different. [10] Array substrate according to claim 9, characterized byin that the first-color subpixels are blue subpixels, the second-color subpixels are green subpixels, and the third-color subpixels are red subpixels; wherein the three data line groups comprise a first data line group, a second data line group, and a third data line group, the first data line group being assigned to one of the two first-color subpixels, and the second data line group and the third data line group being assigned to the two second-color subpixels; wherein the two data lines in the first data line group are electrically connected to the pixel electrodes in the two second-color subpixels, the two data lines in the second data line group are electrically connected to the pixel electrodes in the two third-color subpixels, and the two data lines in the third data line group are electrically connected to the pixel electrodes in the two first-color subpixels. [11] Array substrate according to claim 10, characterized by that the subpixel of the first color and the subpixel of the second color are located between two adjacent subpixels of the third color, wherein the subpixel of the first color and the subpixel of the third color are located between two adjacent subpixels of the second color, wherein the subpixel of the second color and the subpixel of the third color are located between two adjacent subpixels of the first color, and wherein the subpixels of the first color, the subpixels of the second color and the subpixels of the third color are arranged spaced from one another in the first direction. [12] Array substrate according to claim 10, characterized by that the array substrate further comprises a fourth data line group associated with the other of the two first color subpixels, wherein the fourth data line group and the first data line group are identical. [13] Display panel, characterized by that it comprises the array substrate according to one of claims 1 to 12.

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