VOICE AND TRACKING OF DATA SAMPLES

Abstract

Methods, equipment, systems, and manufactured articles are described according to data sampling point matching and tracking. An exemplary device comprises a communication interface configurable for receiving a data signal; and processor circuits coupled to the communication interface configurable for determining a first timing for sampling the data signal for a first value of a condition; determining a second timing for sampling the data signal for a second value of the condition using the first timing and a predictive compensation model, wherein the second timing differs from the first timing; measuring the condition; selecting the first timing or the second timing using the measured condition; and programming the communication interface to use the selected timing.

Description

TECHNICAL AREA

[0001] The present description concerns circuits in general and, in particular, data sampling point tuning and tracking. BACKGROUND

[0002] An electrical device (e.g., a system-on-a-chip (SoC), an integrated circuit, a semiconductor device, etc.) can comprise components of an electronic system. These components can include, on a single substrate or microchip, a microcontroller, a microprocessor, or one or more processor cores; static and dynamic memory; coprocessor circuitry such as security circuits and GPUs (graphics processing units); serial and parallel input / output ports; and network connectivity such as Ethernet, Wi-Fi, power line, and cellular communication interfaces. A device can be coupled to external devices using synchronous half-duplex data transfer protocols, such as a quad serial peripheral interface (QSPI) or an octal serial peripheral interface (OSPI). SUMMARY

[0003] For data sampling point tuning and tracking, an exemplary device comprises processor circuitry coupled to the communication interface and configurable to determine a first timing for sampling the data signal for a first value of a condition; determine a second timing for sampling the data signal for a second value of the condition using the first timing and a predictive compensation model, wherein the second timing is different from the first timing; measure the condition; select the first timing or the second timing using the measured condition; and program the communication interface to sample using the selected timing. Further examples are described.

[0004] For tuning and tracking data sampling points, an exemplary procedure includes determining a first timing for sampling a data signal for a first value of a condition. The procedure also includes determining a second timing for sampling the data signal for a second value of the condition using the first timing and a predictive compensation model, where the second timing differs from the first. The procedure also includes measuring the state. The procedure further includes selecting either the first or the second timing based on the measured condition. The procedure also includes programming a communication interface for sampling using the selected timing. Further examples are described.

[0005] For data sampling point tuning and tracking, an exemplary system comprises a communication interface configurable for transmitting a clock signal and a first data signal based on tuning point parameters, and for sampling a second data signal based on the tuning point parameters. The system also comprises a peripheral device coupled to the communication interface, the peripheral device being configurable for receiving the clock signal and the first data signal; and transmitting the second data signal, wherein the second data signal corresponds to the first data signal.The system also includes processor circuits coupled to the communication interface, the processor circuits being configurable to determine a first timing for sampling the second data signal for a first value of a condition, where the first timing corresponds to the tuning point parameters; determine a second timing for sampling the second data signal for a second value of the condition using the first timing and a predictive compensation model, where the second timing differs from the first timing; measure the condition; select the first timing or the second timing using the measured condition; and program the communication interface to use the selected timing. Further examples are described. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block representation of a device coupled to a flash memory outside the device, according to various examples described here. Fig. Figure 2 is a block diagram of an exemplary implementation of the communication interface of Fig. 1. Fig. Figure 3 shows exemplary sampling windows for a data signal. Fig. Figure 4 is a time diagram of a read transaction according to various examples. Fig. Figure 5 is a timing diagram of a data sampling in a read transaction according to various examples (e.g., with strobes marking the sampling point as DQS and delayed DQS). Fig. Figure 6 shows the device's data paths. Fig. 1, which results in delays. Fig. Figure 7 shows a multiplexer for selecting a delay amount accordingly. Fig. 6. Fig. Figure 8 is a block diagram of an exemplary implementation of the 102 core processor. Fig. 1. Fig. 9-10 are flowcharts that represent a procedure, instructions and / or operations that can be performed to utilize the core processor of Fig. 5 to implement. Fig. 11A and Fig. Figure 11B shows an example of polygon calculation and representations of 5 successful sampling points. Fig. Figure 12 shows an example of shifted sampling. Fig. Figure 13 shows an example of shifted sample values ​​that lead to different polygon representations. Fig. Figure 14 shows different polygon representations based on shifted 10 sampling. Fig. Figure 15 shows polygon representation and sampling point adjustments based on a predictive compensation model. Fig. Figure 16 shows alternative polygon representation and sampling point adjustments based on a predictive compensation model. Fig. Figure 17 shows stability indicators for different polygon representations. Fig. Figure 18 is a block diagram of an exemplary processing platform comprising programmable circuits structured to implement the exemplary machine-readable instructions and / or the exemplary operations of Fig. 9-10 to execute, instantiate and / or perform in order to control Fig. Implement 8 to 20.

[0006] The same reference numerals or other reference symbols are used in the drawings to designate the same or similar features (with respect to function and / or structure). The drawings are not necessarily to scale. In general, identical reference numerals in the drawing(s) and in this description refer to the same or similar parts. Although the drawings show areas with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In practice, the boundaries and / or lines may be imperceptible, intersecting, and / or irregular. DETAILED DESCRIPTION

[0007] A device (e.g., a SoC, an integrated circuit, a semiconductor device, etc.) can include a communication interface, such as an SPI (Serial Peripheral Interface), which electrically couples the device to a peripheral device, such as a flash memory device. The communication interface can be of type OSPI (Octal SPI), QSPI (Quad SPI), or I2C (Inter-integrated Circuit), among others, suitable for coupling the device to the peripheral device. Timing parameters of the SPI, which control program and read transactions with the peripheral device, are called tuning point parameters (or sampling point parameters, tuning points, or sampling points). Tuning point parameters include the transmit clock PDL (programmable delay line) delay (TX delay), the receive clock PDL delay (RX delay), and the RD cycle.The RD cycle is a number of cycles used to delay (e.g., dummy cycles) an SPI reference clock to read data received by the SPI from the flash device.

[0008] Under varying die conditions (e.g., different tuning parameters, operating temperatures, age, etc.), some tuning point ranges result in successful transactions between the SPI and the flash device, while others do not. A successful tuning point allows the SPI to reliably program and read data to and from the flash device. An unsuccessful tuning point causes the SPI to fail entirely or to program and read data to and from the flash device unreliably. The ranges of successful and unsuccessful tuning points also change under varying die conditions. Traditionally, after a device is first coupled with a flash device, a tuning point for the SPI is programmed and not reprogrammed during subsequent operation of the device.Consequently, the initially programmed successful SPI tuning point can become a suboptimal (e.g., unsuccessful) tuning point during operation if factors such as operating temperature, age, humidity, ambient impedance or conductivity, clock jitter, input line crosstalk, ground connection (e.g., between board and device), parallel activity, input voltage, chip corner position on the device die wafer, etc., change. Accordingly, conventional techniques require recalibration with a long service interruption to determine a new tuning point, resulting in downtime and the consumption of power and resources.

[0009] The examples described here select communication interface tuning point parameters for transactions with a peripheral device, such as a flash device, during configuration. These parameters will successfully program to or read from the peripheral device over a wider range of die conditions than other successful tuning point parameters. Additionally, the examples described here can determine different tuning point parameters corresponding to different lines, such as environmental conditions or die conditions. Environmental conditions can include temperature, humidity, environmental impedance, or conductance, among others.A die condition can correspond to the age of the die, the age of one or more components on the die, the number or time of the die or components on the die being used, clock jitter, crosstalk on the input line, ground connection, parallel activity, input voltage, die structure, die location on the wafer, and / or any other physical condition or property of the die and / or the components on the die. In this way, examples described here can dynamically adjust tuning point parameters based on monitored conditions (e.g., environmental condition(s) and / or die condition(s)) without requiring recalibration of the tuning point parameters. Examples described here search subsets of candidate tuning point parameters by adjusting tuning point parameters (e.g., RX delay, TX delay, a reference clock, and / or a protocol configuration) and / or shifted sampling delays (e.g.,RD cycles) and determine whether the adjusted tuning point parameters and / or shifted sampling delays have resulted in successful read data from the peripheral device via the communication interface.

[0010] A set of successful tuning points (e.g., an RX delay, a TX delay, a reference clock, a protocol configuration used for sampling) can be represented as one or more polygons (e.g., one polygon for each shifted delay) on a graph of RX delay and TX delay (see, e.g., Fig. 11A, 11B, and 14-17) are represented. Although all points in the one or more polygons per specific reference clock and protocol configuration correspond to RX and TX delays that resulted in successful data reading from the peripheral device via the communication interface, tuning points closer to the edge of a polygon are less stable. For example, as described above, conditions such as environmental conditions and / or die conditions can be adjusted where the edges of the polygon occur. Accordingly, the examples described here select a sample / tuning point from the polygon of successful tuning points based on the sample / tuning point's position within the polygon (e.g., a weighted center and / or a point whose distance to any edge of the polygon is greatest).After determining the one or more initial polygons and the one or more corresponding sampling / tuning points, the examples described here can generate additional sampling / tuning points using a predictive compensation model, corresponding to various conditions (e.g., of the environment and / or the die). These examples determine the sampling / tuning points for the additional polygons and corresponding stability indicator values, which can be used to determine a final sampling / tuning point and / or for specific conditions during device operation. The examples also select one of the generated sampling / tuning points based on the stability indicator values ​​(e.g., the selected sampling / tuning point corresponds to the sampling / tuning point with the highest stability indicator value).Because the generation of the final sampling / tuning point is based on several factors and / or conditions, the final sampling / tuning point can be more robust and longer-lasting than conventionally selected sampling / tuning points. The above is defined for a specific operating profile. Different optimal sampling points may apply to different operating profiles if multiple are supported (e.g., SDR (Single Data Rate) vs. DDR (Double Data Rate), flash frequency, flash register access vs. memory access, etc.).

[0011] The techniques of this disclosure can provide rapid adjustment of a sampling point in response to changing conditions. For example, a device can store one or more pre-generated sampling points for use when a condition has changed. The selected sampling point can be more accurate, thereby increasing the probability of sampling the correct bits on a receive line.

[0012] Fig. Figure 1 is a block representation of an exemplary device 100 coupled with an exemplary flash memory 112, according to various examples. Although Fig. Where the connection to the exemplary flash memory 112 corresponds to the connection to the flash memory 112, the flash memory 112 can be replaced in some implementations by a different type of peripheral device (e.g., a different type of memory, a different microcontroller, or a display controller). The device 100 comprises an exemplary core processor 102 coupled to the exemplary memory 104. The memory 104 is designed to store instructions which, when executed by the core processor 102, cause the core processor 102 to perform the various functionalities described herein.

[0013] The 102 core processor from Fig. 1 is furthermore coupled to the flash memory 112 via an exemplary communication interface 110. Additionally, the core processor 102 can be coupled to one or more communication links via a second communication interface to enable communication with other devices. The device 100 can also include other circuits and processors that are in Fig. Figure 1 is not shown. As described below, the core processor 102 performs a sample / tune point selection protocol by transmitting instructions to the communication interface 110 to adjust parameters of the communication interface 110, send known data to the flash memory 112, sample the stored data from the flash memory 112, and compare the results with the known data to determine whether the sample was successful. The core processor 102 generates one or more polygon representations of parameters that resulted in a successful sample and selects a sample / tune point based on the one or more polygon representations, as described below. Further exemplary details of sample point selection can be found in US Patent 11,935,613, entitled "Method for Tuning an External Memory Interface," filed on July 30, 1996.2021, which is incorporated in its entirety by reference.

[0014] Fig. Figure 2 is a block diagram of the communication interface 110 with the flash memory 112. The communication interface 110 is coupled to the flash memory 112 by example data lines 202, an example SPI clock line 204, and an example data strobe / DQS line 208. The data lines 202 are bidirectional, allowing the communication interface 110 and the flash memory 112 to send data to each other in different phases of a transaction. For example, the core processor 102 controls the communication interface 110 to provide an OSPI clock to the flash memory 112. The OSPI clock is generated by delaying the reference clock using the TX-PDL 210. The flash memory 112 uses the clock to capture the instruction and address during the instruction and address phase.In some examples, the communication interface 110 is a system-based half-duplex interface, such as SPI, OSPI, QSPI, or XSPI, etc. The flash memory 112 uses the SPI clock line 204 to capture command and address information from the data lines 202 during the command and address phase of a transaction. The flash memory 112 also uses the SPI clock line 204 to capture data from the data lines 202 during the data phase of a program transaction. The communication interface 110 uses a delayed copy of the DQS line 208 to capture data from the data lines 202 during the data phase of a read transaction.

[0015] The communication interface 110 includes an internal reference clock 206 (e.g., a clock signal) which is delayed by a TX-PDL 210 to form the SPI clock line 204. The value of the delay of the TX-PDL 210 is referred to as the "TX delay." The core processor 102 can adjust the TX delay as part of the sample / tune point selection protocol. Edges of signal pulses on the DQS line 208 are aligned with data transitions on the data lines 202 from the flash memory 112 during the data phase of a read transaction. The DQS line 208 is delayed by an RX-PDL 212 to cause a receive FIFO (first-in-first-out) shift register to sample data on the data lines 202 after the values ​​have stabilized. The delay value of the RX-PDL 212 is referred to as the "RX delay". The Core 102 processor can adjust the RX delay as part of the sampling / tuning point selection protocol.

[0016] A "total runtime" of data can be defined as the time from a reference clock edge 206 until a sampling time triggered by this edge in the communication interface 110 of data from the flash memory 112. The delay of the TX-PDL 210, a clock propagation delay via the SPI clock line 204, an output delay of the flash memory 112, and the delay of the RX-PDL 212 all contribute to the total runtime. As described above, the communication interface 110 samples the data lines 202 into the RX-FIFO 214 using the DQS line 208, delayed by the RX-PDL 212. The data is read from the RX-FIFO 214 by the communication interface 110 using the reference clock 206. The read data is forwarded to core processor 102 to determine whether the reading, also known as sampling, was successful.

[0017] The communication interface 110 expects the first data byte to be captured within a specific cycle of the reference clock 206 (the target cycle or RD cycle), and all remaining data to be captured in subsequent cycles of the reference clock 206. In some cases, the total runtime is longer than the period of the reference clock 206, and the target cycle is shifted to a subsequent cycle of the reference clock 206 in order to successfully read data on the data lines 202.

[0018] As described below, the core processor 102 selects a preferred tuning point (values ​​for TX delay, RX delay, and RD cycle) for the communication interface 110 for use with the flash memory 112 based on the sample / tuning point detection protocol described herein. The sample / tuning point detection protocol includes generating one or more polygon representations of a successful data sample based on various tuning point parameters and / or condition parameters, and selecting a sample / tuning point from the one or more polygon representations based on the stability of the points in the one or more polygon representations.

[0019] Fig. Figure 3 is a timing diagram of an exemplary first data signal 300, corresponding to a minimum delay tolerance, and a second data signal 302, corresponding to a maximum delay tolerance. The first data signal corresponds to a first sampling window 304, and the second data signal 302 corresponds to a second sampling window 306. The communication interface 110 will successfully sample the first data signal 300 as long as the data is sampled within sampling window 304. Additionally, the communication interface 110 will successfully sample the second data signal 302 as long as the data is sampled within sampling window 306. However, the data can be shifted anywhere between the first data signal 300 and the second data signal 302.Thus, the effective sampling window 308 corresponds to the sampling window that results in successful sampling of the data signal, regardless of whether it corresponds to the first data signal 300, the second data signal 302, or any other data signal shifted in between. Sampling / tuning point parameters can be selected such that sampling occurs within the effective sampling window 308 or one or more estimates of the effective sampling window 308. However, such a technique for generating sampling / tuning point parameters based on the effective sampling window 308 is less robust in surviving long-term effects, causing a significant degradation in performance due to sensitivity to clock-to-data offset, narrow sampling window, limited real-time compensation / complexity of calibration logic, calibration time overhead, signal hitters, etc.

[0020] Fig. Figure 4 shows an example timing diagram 400 of a read transaction that was carried out via the communication interface 110 of Fig. 1 and Fig. 2 is performed according to the examples described here. The read transaction includes an example instruction phase 402, an example address phase 404, and an example data phase 406. In instruction phase 402, the communication interface can send 110 instruction bytes on data lines 202 and the reference clock 206, delayed by TX PDL 210, on the SPI clock line 204. The instruction bytes can correspond to an instruction to read data from a specific address, where the data stored at that specific address is known. In address phase 404, the communication interface sends 110 address bytes on data lines 202 and the reference clock 206, delayed by TX PDL 210, on the SPI clock line 204. The address bytes can point to the address of the data to be read. After the addressing phase 404, one or more dummy cycles are inserted to give the flash memory 112 hours to access the addressed memory.During instruction phase 402 and address phase 404, the flash memory 112 can sample (e.g., read) the instruction bytes and address bytes, respectively, from data lines 202. During data phase 406, the flash memory 112 can send data bytes on data lines 202 and the DQS signal on DQS line 208. As described above, the core processor 102 can compare the sampled data with the known data to determine whether the sampling was successful or unsuccessful. The core processor 102 can transmit the same instruction multiple times for different tuning parameters to generate the polygon representation of the successful samples, as described above.

[0021] Fig. Figure 5 shows an exemplary timing diagram 500 of the data sampling in the communication interface 110 during a read transaction according to various examples. The read data bytes on data lines 202 and the DQS signal on DQS line 208 are as shown in Fig. 4 shown. An example delayed DQS signal 502 is the DQS line 208 delayed by the value of the RX-PDL-212 delay, as shown in an example RX delay 504.

[0022] Fig. Figure 6 shows RX reference clock sampling options, illustrating the ability of the Core 102 processors to select between three options: A) RX-Ref A: no loopback; B) RX-Ref B: pad loopback; and C) RX-Ref C: external loopback or DQS. A different RD cycle can be selected for each of these options. Accordingly, each of the three options (times the number of RD cycles per option) results in a different polygon representation when implementing the sampling / tuning point selection protocol. To tune and track the data sampling / tuning point, ensuring that the clock sampling edge is correctly aligned with the data bits, the core processor 102 can also select a method for generating a reference RX ref clock, used to tune and track the data sampling / tuning point, based on internal (relative to the transmitted data) or external (relative to the incoming samples). Fig. 6 includes the communication interface 110 and the flash memory 112 of Fig. 1. Fig. Section 6 further includes exemplary pads 600, 602 (e.g. connectors, interfaces, etc.) which enable a line, an etching, etc. to connect the communication interface 110 to the flash memory 112.

[0023] Fig. Figure 6 shows non-linear delay variation of the TX and RX clocks. D1 and D5 represent the internal chip pad clock delay. The delay between the TX clock in the chip and the clock returning to the chip pads due to internal chip delays can vary from chip to chip.

[0024] D3 represents a clock transient to valid output. The clock transient to valid output is a property of a peripheral device. The delay between the SPI clock transition on the external peripheral clock pin and the time to valid data is determined by the peripheral device. D3 can be a non-deterministic delay (tmin to tmax) that may include the internal registers and data sectors of the peripheral device.

[0025] D2 and D4 represent board delays, for example, when both devices are coupled to a single circuit board. The impedance of the leads should match the impedance of the external peripheral inputs / outputs. Board delays D2 and D4 are caused by the length of the wires / leads. These delays can still occur even if the leads are perfectly impedance-matched to the inputs / outputs of the external peripheral.

[0026] Fig. 7 is an exemplary 700 circuit that uses an RD cycle for sampling based on the three above in conjunction with Fig. The 6 described options can be selected. The circuit 700 of Fig. Section 7 includes an example MUX (multiplexer) 702. The MUX 702 has three inputs and one output. The first input of the MUX 702 corresponds to RX-Ref A: no loopback, representing internal chip pad clock delays D1+D5. Fig. 6. The second input of the MUX 702 corresponds to B) RX-Ref B: Pad-Loopback, representing both internal chip pad clock delays and board delays D1+D2+D4+D5 in Fig. 6. The third input of the MUX 702 corresponds to RX-Ref C: external loopback or DQS, representing all delays, internal chip pad clock delays, board delays, and the delay from clock transient to valid output, i.e., D1+D2+D3+D4+D5. The output of the MUX 702 is coupled to a data point sampler, which forces the MUX 702 to sample the data with the selected delay. The Core 102 processor can apply a control signal to a selection input of the MUX 702 to control how much delay is applied during sampling. Each delay amount (referred to as shifted sampling) results in a different polygon representation when determining a sample / tune point.

[0027] Fig. Figure 8 is a block diagram of an exemplary implementation of the 102 core processor. Fig. 1. The 102 core processor of Fig. 8 includes interface circuits 800, exemplary parameter selection circuits 802, exemplary polygon representation determination circuits 804, exemplary sampling / tuning point determination circuits 806, exemplary predictive compensation model or PCM circuits 808, an exemplary comparator 810, exemplary sampling / tuning point application circuits 812 and exemplary storage 814.

[0028] The 800 series interface circuits from Fig. 8. The interface circuits activate the transaction themselves via the interface lines (e.g., clock, data). Additionally, the interface circuits transmit instructions to the TX-PDL 210 and / or the RX-PDL 212 to adjust the tuning point parameters (e.g., the TX delay, RX delay, and / or RD delay) as part of a sampling / tuning point selection protocol. Furthermore, the interface circuits 800 can send instructions (e.g., via the ENB pin of communication interface 110) to read data at a specific address. The data at the address is known data and / or known data to which data has been previously written. Additionally, after data sampling, the interface circuits 800 can receive samples from the RX-FIFO 214, which are received by the flash memory 112.

[0029] The parameter selection circuits 802 from Fig. 8. Select the tuning parameters for the application for the sample / tuning point selection protocol. For example, the parameter selection circuits 802 can select the sample-RX reference clock sample option (e.g., RD ​​cycle) and the options associated with the above. Fig. (described in section 6) determine the parameters for generating a polygon based on successful sample / tuning points for various tuning point parameters. Additionally, the parameter selection circuits 802 determine the amount of TX delay and RX delay to be applied for each sample value of the sample / tuning point selection protocol when generating the polygon representation for the selected RD cycle value.

[0030] The polygon representation determination circuits 804 of Fig. 8 generate a polygon representation of successful sample / tune points for each tunable degree of freedom (e.g., RD ​​cycle, which can be for each selected RX reference clock sample option). The polygon includes points represented by the TX delay and the RX delay that resulted in successful data sampling. To generate a polygon representation, the polygon representation determining circuits 804 select an initial TX delay and an initial RX delay and instruct the communication interface 110 to access known data from the flash memory 112 based on the initial TX delay, the initial RX delay, and the RD delay. After the communication interface 110 sends the instruction to the flash memory 112 and samples the data returned by the flash memory 112, the interface circuits 800 access the sampled data.The 804 polygon representation determination circuits determine whether the sampled data matches the expected known data. If the 804 polygon representation determination circuits determine that the sampled data matches the expected known data, they mark the tuning parameters as a success. If the 804 polygon representation determination circuits determine that the sampled data does not match the expected known data, they mark the tuning parameters as a failure. The 804 polygon representation determination circuits repeat this process for various different TX delays and RX delays until a polygon representation is determined for the RD cycle value.Once the polygon representation has been determined, the 804 polygon representation determination circuits can repeat the process for one or more different RD delay values ​​and RX reference clocks to generate one or more additional polygon representations.

[0031] The 806 sampling / tuning point determination circuits from Fig. The 8 sample / tune point selects a sample / tune point from the one or more polygon representations generated by the polygon representation selector circuits 804. As described above, the stability of all sample / tune points differs, although all sample / tune points identify the combinations of TX delay and RX delay that result in successful sampling for a given RD delay and RX reference clocks. Accordingly, the sample / tune point selector circuits 806 select a sample / tune point (e.g., one of the tune points forming a polygon representation) that represents a desirable polygon according to selected optimization and stability criteria, such as the greatest distance from the polygon representation boundaries (e.g., the tune point that has the greatest distance from the interior of the polygon to its nearest boundary).Points farther from an edge are more stable under various conditions (e.g., of the environment or the die) than points closer to the edge. In some examples, the 806 sampling / tuning point determination circuits determine a sampling / tuning point for a given polygon using the following polygon centroid formula (also called the center of mass or center of gravity) in Equations 1 and 2 below. Cx=16A∑i=0n−1(xi−xi+1)(xiji+1−xi+1ji) Cj=16A∑i=0n−1(ji+ji+1)(xiji+1−xi+1ji)

[0032] In equations 1 and 2 above, Cx is the TX delay for the selected sample / tune point, Cy is the RX delay for the selected sample / tune point, x represents an x-coordinate of the polygon representation, y represents a y-coordinate of the polygon representation, and A is the area of ​​the polygon. The 806 sample / tune point determination circuits determine the area of ​​the polygon using the following equation 6. A=12∑i=0n−1(xiji+1−xi+1ji)

[0033] In some examples, the sample / tune point determination circuits 806 calculate the selected sample / tune point (e.g., the centroid) of the polygon as the weighted sum of the centroids of a partition of the polygon into triangles. After the sample / tune point determination circuits 806 select a sample / tune point for each of the polygon representations, the sample / tune point determination circuits 806 determine the sample / tune point stability point based on the distance of the selected sample / tune point to the nearest edge of the polygon representation (e.g., using a distance formula).

[0034] The Predictive Compensation Model Circuits 808 by Fig. 8 generates additional sampling / tuning points from the selected sampling / tuning point(s) corresponding to different conditions (e.g., temperature, humidity, age, structure, die position on the wafer, etc.) by adjusting the selected sampling / tuning point(s) and the corresponding stability indicator(s) using a predictive compensation model (PCM). The PCM can be a mathematical function developed based on estimates of the effective one or more conditions for a polygon representation. For example, the Predictive Compensation Model 808 circuits can generate a PCM that extrapolates the dependence of a polygon on input condition parameters (e.g., temperature, age, etc.).The Predictive Compensation Model (PCM) circuits 808 can generate a PCM by gathering information about polygon geometry and material properties (e.g., shape, size, boundary conditions, etc.) and characterizing how the conditions modify the structure of a polygon. For example, one or more conditions may modify the polygon's structure in a uniform or disproportionate manner. After determining the effect of one or more conditions on the polygons, the PCM circuits 808 can model the effect using various modeling approaches (e.g., finite element methods, computational fluid dynamics, etc.). The PCM circuits 808 can use simulation software or a programming environment to apply the modeling approaches. The PCM circuits 808 define a mathematical model (e.g.,A mathematical formula (a function or formula) that describes the relationship between one or more conditions and their effect on a stability point and / or corresponding stability point stability indicator. The mathematical formula can be an empirical model or a mechanistic model. An empirical model is a mathematical representation derived directly from observations or experiments without explicit consideration of underlying physical principles. In other words, an empirical model is generated by analyzing data and identifying relationships between variables using statistical methods, regression analysis, or machine learning techniques. A mechanistic model is a mathematical representation that describes the underlying physical principles and mechanisms that govern the behavior of a system.These models aim to capture the intrinsic dynamics, processes, and relationships of the system under investigation. The Predictive Compensation Model (PCM) circuits 808 apply PCM to generate various sampling / tuning points and corresponding sampling / tuning point stability indicators that correspond to different conditions or trends in condition changes. PCM computation can be performed either locally by the Core Processor 102 or remotely (e.g., computed by another computational element and sent to the Core Processor 102 via an interface 110 or other interface). For example, the Predictive Compensation Model circuits 808 can generate a first sampling / tuning point and corresponding stability indicator for a first temperature range and / or age range, a second sampling / tuning point and corresponding stability indicator for a second temperature range and / or age range, and so on.

[0035] The Comparator 810 from Fig. Comparator 810 compares the stability indicators of the generated sampling / tuning points to determine which indicator is highest. The higher the stability indicator, the more stable the sampling / tuning point parameters are for the corresponding sampling / tuning points. Accordingly, Comparator 810 determines the most stable sampling / tuning point parameters based on the generated sampling / tuning point parameters with the highest stability indicator, taking into account changing environmental trend trends. Based on this comparison, Comparator 810 outputs the final selected sampling / tuning point.

[0036] The 812 sampling / tuning point application circuits from Fig. The PCM 812 program the communication interface 110 to operate based on the tuning parameters of the final selected sampling / tuning point. For example, the PCM 812 can program the communication interface 110 to operate based on the RD cycle, the amount of a TX delay, and / or the amount of an RX delay corresponding to the final selected sampling / tuning point at a given RX reference clock. Additionally, the PCM 812 monitors the conditions during operation with the selected sampling / tuning point. For example, the PCM 812 can monitor temperature, device age, and so on. As described above, the PCM 808 can generate different sampling / tuning points for different conditions.In this way, if the sampling / tuning point application circuits 812 determine that the measured condition(s) no longer correspond to the selected sampling / tuning point, the sampling / tuning point application circuits 812 can select a different sampling / tuning point generated by the predictive compensation model circuits 808 that corresponds to the measured condition(s). Accordingly, the sampling / tuning point application circuits 812 provide in-flight tuning and tracking for different conditions without requiring recalibration of the sampling / tuning point.

[0037] The exemplary storage of 814 of Fig. Memory 8 stores generated sampling / tuning points created by the sampling / tuning point determination circuits 806 and / or the PCM circuits 808, which correspond to stable sampling / tuning point parameters for various conditions (e.g., temperature ranges, age ranges, etc.). As described above, the sampling / tuning points are initially generated during calibration and stored in memory 814. This allows the sampling / tuning point application circuits 812 to access the sampling / tuning points for in-flight tuning based on changes in conditions during the application of a sampling / tuning point.

[0038] Fig. Figure 9 is a flowchart representing a procedure and / or exemplary operations 900 performed by the core processor 102 of Fig. Operations 1-8 can be executed and / or instantiated. Operations 900 can be performed by any or a combination of those listed in Fig. The circuits shown in 1-5 are executed. Although the instructions and / or operations of Fig. 9 in conjunction with the core processor 102 of Fig. 1 and Fig. As described in section 8, the instructions and / or operations associated with any type of circuit implementing processing circuitry can be described. Some in Fig. The nine processes shown can be carried out in a different order than described, and many processes can be carried out simultaneously in parallel. Furthermore, in Fig. The processes shown in some examples of the present description may be omitted or replaced.

[0039] The machine-readable instructions and / or operations 900 of Fig. The process begins in block 902, where the parameter selection circuits 802 select a sample-RX reference clock sampling option (e.g., A) RX-Ref A: no loopback; B) RX-Ref B: pad loopback; or C) RX-Ref C). After selection, the interface circuits 800 can send a control signal to the selection terminal of the MUX 702. Fig. Create 7 to apply the selected sample RX reference clock sampling option that corresponds to one RD cycle.

[0040] In block 904, the polygon representation determination circuits 804 apply various tuning / sample parameters to the selected sample-RX reference clock sampling option to generate a polygon representation of the successful sample / tuning point parameters (e.g., a two-dimensional (2D) planar polygon of successful sampling). For example, the parameter selection circuits 802 select a first set of tuning parameters (e.g., RX delay and TX delay), sample data from a location in the flash memory 112 based on the first set of tuning parameters, and determine whether the sampled data matches the known data for that location. If the sampled data matches the known data, the polygon representation determination circuits 804 mark the point corresponding to the first set as a success for inclusion in a polygon representation.If the sampled data does not match the known data, the polygon representation determination circuits 804 mark the point corresponding to the first set as a failure that should not be included in the polygon representation. This process is repeated for several sets of tuning parameters until a polygon representation of the successful points is generated.

[0041] In Block 906, the sample / tune point determination circuits 806 determine a sample / tune point and a corresponding stability indicator for the polygon representation. For example, the sample / tune point determination circuits 806 can determine the sample / tune point using Equations 1-3 above and determine the corresponding stability indicator based on a distance between the sample / tune point and the nearest point on an edge of the polygon representation. In Block 908, the PCM circuits 808 generate various sample / tune points and corresponding stability indicators using a predictive compensation model. As described above in conjunction with Fig. As described in section 8, the PCM models the effect of one or more conditions on the stability point and corresponding stability indicators. Accordingly, the PCM circuits 808 apply the PCM to the selected stability point and the corresponding stability indicator to generate different stability points and corresponding stability indicators for different condition(s).

[0042] In block 910, the parameter selection circuits 802 determine whether another polygon can be generated, depending on whether all RD cycles and RX reference clock sampling options have been used to generate a polygon. If there is another RD cycle / RX reference clock sampling option that has not been used to generate a polygon, the process is repeated for the remaining RD cycle / RX reference clock sampling option(s). If the parameter selection circuits 802 determine that the generated polygon representation is not the last polygon representation to be generated (block 910: NO), the controller returns to block 902 to repeat the process for a subsequent RD cycle / RX reference clock sampling option.

[0043] If the parameter selection circuits 802 determine that the generated polygon representation is the last polygon representation to be generated (Block 910: YES), the comparator 810 selects final stability point parameters (e.g., a TX delay, an RX delay, and an RD cycle) based on the stability indicators for the generated / selected sample / tune points for the generated polygons and / or based on the various conditions (Block 912). For example, the process of steps 902-610 may result in three polygon representations, each with one corresponding sample / tune point and several PCM-matched sample / tune points. Each sample / tune point corresponds to a stability indicator. The comparator 810 determines the largest stability indicator and selects the final sample / tune point parameters corresponding to the largest stability indicator (e.g.,(the RX delay, the TX delay, and the RD cycle, which resulted in the highest stability indicator). In some examples, the highest stability indicator can be replaced by a different optimization criterion for stability.

[0044] In block 914, the sample / tune point application circuits 812 program the communication interface 110 based on the final sample / tune point parameters. For example, the sample / tune point application circuits 812 issue instructions (e.g., via the interface circuits 800) to the communication interface 110 to operate based on the final selected RX delay, the final selected TX delay, the final selected RD cycle, and the final selected RX reference clock. The 800 interface circuits can output a first control signal to the TX-PDL 210 to set the TX delay, a second control signal to the RX-PDL 212 to set the RX delay, a third control signal to a selection port of the MUX 702 for RX reference clock, and a fourth to set the RD cycle.In block 916, normal operation takes place based on the selected sampling / tuning point parameters, as described below in conjunction with . Fig. 10 is described. If the core processor 102 receives an instruction (e.g. via the interface circuits 800) to recalibrate the sampling / tuning point parameters, the control returns to block 902.

[0045] Fig. 10 is a flowchart representing a procedure and / or exemplary operations 916 performed by the core processor 102 of Fig. 1 and Fig. 8 can be executed and / or instantiated to enable normal operation. Operations 916 can be performed by any or a combination of those in Fig. The circuits shown in 1-5 are executed. Although the instructions and / or operations of Fig. 10 in conjunction with the core processor 102 from Fig. 1 and Fig. As described in section 8, the instructions and / or operations associated with any type of circuit implementing processing circuitry can be described. Some in Fig. The 10 processes shown can be carried out in a different order than described, and many processes can be carried out simultaneously in parallel. Furthermore, in Fig. The processes shown in some examples of the present description may be omitted or replaced.

[0046] The machine-readable instructions and / or operations 916 of Fig. The 10 begin in block 1002, where the sampling / tuning point application circuits 812 monitor condition(s). For example, the sampling / tuning point application circuits 812 may include or be connected to one or more sensors, clocks, etc., to access information relating to one or more conditions (e.g., temperature or humidity data from a sensor, age data from a clock or timer or counter, accessible corner position from the die, etc.). In block 1004, the sampling / tuning point application circuits 812 determine whether the monitored condition(s) match or exceed certain sampling / tuning points stored in memory 814. As described above, the predictive compensation model circuits 808 can generate several different sampling / tuning points for one or more generated polygon representations, which correspond to different conditions (e.g.,These sampling / tuning points correspond to temperature ranges and / or operating time / age ranges, etc. Such sampling / tuning points and the conditions to which they correspond are stored in memory 814. Accordingly, the sampling / tuning point application circuits 812 can access the conditions for the stored sampling / tuning point parameters and determine whether any match or exceed the current conditions.

[0047] If the sampling / tuning point application circuits 812 determine that the condition(s) do not correspond to other sampling / tuning points stored in memory 814 (Block 1004: NO), the controller returns to Block 1002. If the sampling / tuning point application circuits 812 determine that the condition(s) correspond to other sampling / tuning points stored in memory 814 (Block 1004: YES), the sampling / tuning point application circuits 812 select and apply the sampling / tuning point parameters that correspond to the current conditions (e.g., program the communication interface 110) (Block 1006). If there are multiple sampling / tuning points that meet the current conditions, the 812 sampling / tuning point application circuits can select the sampling / tuning point parameters that correspond to a desirable (e.g., optimal) stability indicator. Thus, the flowchart of Fig. 10. Parameterization and tracking of sampling / tuning points are ready in flight without requiring recalibration. After block 1006, the control system returns to block 1002 to continue monitoring / tracking the condition(s).

[0048] Fig. Figure 11A shows an exemplary polygon representation, without needing to traverse the entire combination of TX and RX delays, 1100, generated by the core processor 102 using a fast polygon generation technique for a specific protocol and reference clock configuration based on polygon boundary detection. For example, the core processor 102 can first apply the minimum RX and TX delays for a given RD cycle and known sample data, based on the RX delay, TX delay, and RD cycle. If the sampled data matches the known data, the core processor 102 marks the sample / tune point (e.g., "A") as successful.If the sampled data does not match the known data, the core processor 102 can adjust and repeat the TX delay and / or the RX delay until the first successful "corner" sampling / tuning point of the polygon representation is found.

[0049] After the first successful sampling / tuning point ("A") is determined, core processor 102 increases the RX delay while maintaining the TX delay and continues to compare known data with sampled data until the highest successful RX delay is determined (e.g., corresponding to sample "B"). Furthermore, after the first successful sampling / tuning point ("A") is determined, core processor 102 increases the TX delay while maintaining the RX delay and continues to compare known data with sampled data until the highest successful TX delay is determined (e.g., corresponding to sample "C"). After points A, B and C have been determined, the core processor 102 can first apply the maximum RX and TX delay for a given RD cycle and sample data that are known, based on the RX delay, the TX delay, the RX reference clock and the RD cycle.If the sampled data matches the known data, Core Processor 102 marks the sample / tune point (e.g., "D") as successful. If the sampled data does not match the known data, Core Processor 102 can adjust and repeat the TX delay and / or the RX delay until the first successful "corner" sample / tune point of the polygon representation is found. Furthermore, after the maximum successful sample / tune point ("C") is determined, Core Processor 102 increases the RX delay and maintains it, continuing to compare known data with sampled data until the highest successful RX delay is determined (e.g., corresponding to sample "F").Furthermore, after the maximum successful sampling / tuning point ("D") has been determined, core processor 102 increases the TX delay while maintaining the RX delay and continues to compare known data with sampled data until the highest successful TX delay is determined (e.g., corresponding to sampling "E"). Core processor 102 can then generate a polygon representation based on the determined points A, B, C, D, E, and F.

[0050] Fig. Figure 11B shows an example polygon representation 1102 generated by the core processor 102 using a robust polygon generation technique (e.g., a rigorous brute-force polygon generation technique). For example, the core processor 102 can first apply the minimum RX and TX delays for a given RD cycle and known sample data, based on the RX delay, TX delay, and RD cycle. If the sampled data matches the known data, the core processor 102 marks the sample / tune point (e.g., "A") as successful. If the sampled data does not match the known data, the core processor 102 can adjust and repeat the TX delay and / or the RX delay until the first successful "corner" sample / tune point of the polygon representation is found.

[0051] Furthermore, after the first successful sampling / tuning point ("A") is determined, Core 102 increases the RX delay while maintaining the TX delay, continuing to compare known data with sampled data until the highest successful RX delay is determined (e.g., corresponding to sample "B"). After the second successful corner sampling / tuning point ("B") is determined, Core 102 increases the RX delay and / or the TX delay, continuing to compare known data with sampled data until the highest successful RX delay is achieved along edge "1b," until a successful corner ("C") is identified, which corresponds to the maximum RX delay.After the third successful corner sampling / tuning point (“C”) is determined, Core 102 increases the TX delay and continues to compare known data with sampled data until the maximum RX and TX delay sampling / tuning point (“D”) is determined, resulting in a successful sample. Furthermore, after the maximum successful sampling / tuning point (“C”) is determined, Core 102 decreases the RX delay while maintaining the TX delay and continues to compare known data with sampled data until the highest successful RX delay is determined (e.g., corresponding to sample “E”).After the fifth successful corner sampling / tuning point (“E”) is determined, Core 102 decreases the RX delay and / or decreases the TX delay and continues to compare known data with sampled data until the highest successful RX delay is developed along edge “1e” until a successful corner (“F”) is identified. After the sixth successful corner sampling / tuning point (“F”) is determined, Core 102 continues testing while decreasing the TX delay to verify edge 1f. Core 102 determines the polygon representation based on edges A, B, C, D, E, F and edges 1a, 1b, 1c, 1d, 1e, 1f. Although… Fig. 11A and Fig. 11B corresponds to a specially shaped polygon; the size, shape, dimensions, etc., can differ for a polygon representation. Furthermore, although Fig. 11A and Fig. Section 11B shows two techniques for testing sampling / tuning points to generate a polygon representation, and other ways of selecting sampling / tuning points to generate a polygon representation of successful sampling / tuning point parameters for a specific protocol and reference clock configuration. The polygons of Fig. 11A and Fig. 11B correspond to different delays (e.g., RX and TX delays), resulting in successful data sampling.

[0052] Fig. Figure 12 shows an example sample 1200 with various delay shifts (represented by a 4-bit shift in the QSPI protocol configuration case). A first example sample 1202 corresponds to sampling with zero delay (e.g., sampling after the dummy signal). In some examples, the first sample 1202 corresponds to the RD cycle, which is based on RX-Ref B: Pad Loopback from Fig. 3 and Fig. 4 refers to. A second example sample 1204 corresponds to sampling with a positive shift delay of one (e.g., sampling before sample 1202 by one sampling period). In some examples, the second sample 1204 corresponds to the RD cycle, which refers to RX-Ref A: no loopback of Fig. 3 and Fig. 4 refers to. A third exemplary sample 1206 corresponds to sampling with a negative shift delay of one (e.g., sampling one period after the first sample 1202). In some examples, the third sample 1206 corresponds to the RD cycle, which refers to RX-Ref C: external loopback or DQS of Fig. 3 and Fig. 4 refers to. As further below in connection with Fig. 13 and Fig. 14 described.

[0053] Fig. Figure 13 shows an example data signal 1302, which includes a dummy signal (corresponding to W7), first read data (corresponding to W8) and second read data (corresponding to W9). Fig. 13 comprises a first sample 1304 of the data signal 1302, a second sample 1306 of the data signal 1302, and a third sample 1309 of the data signal 1302. The first sample 1304 (e.g., corresponding to a first RD cycle) corresponds to the second sample 1204 of Fig. 12, the second sample value 1306 (e.g., corresponding to a second RD cycle) corresponds to the first sample 1202 of Fig. 12 and the third sample value 1308 (e.g., corresponding to a third RD cycle) corresponds to the third sample 1206 of Fig. 12. As described above, each sample corresponds to a different polygon representation, as explained further below in conjunction with Fig. 14 described. In some examples, additional staggered delays can be used to determine additional or alternative polygon representations.

[0054] Fig. Figure 14 shows an exemplary visual representation of 1400 exemplary polygon representations 1404, 1402, 1406, which represent the various shifted delays of Fig. 13 correspond. For example, the polygon representation 1402 corresponds to the RX delay and TX delay combinations that result in a successful sample for the third sample value 1306 of Fig. 13 result (e.g., an RD cycle that does not correspond to any shift delay or RX-Ref B: Pad Loopback). The polygon representation 1404 corresponds to the RX delay and TX delay combinations that result in a successful sample for the first sample value 1304 of Fig. 13 lead (e.g., an RD cycle corresponding to a positive shift delay of one or RX-Ref A: no loopback). Polygon representation 1406 corresponds to the RX delay and TX delay combinations that result in a successful sample for the third sample 1308 of Fig. 13 lead (e.g., an RD cycle corresponding to a negative shift delay of one or RX-Ref C: external loopback or DQS).

[0055] Fig. Figure 15 shows three example polygons for a specific protocol and reference clock configuration representations 1500, 1502, and 1504, and the effect of applying a PCM to a polygon. In the first polygon representation, 1500, the core processor 102 determines that the sampling / tuning point is "m", which corresponds to an amount of TX and RX delay for the RD cycle that matches polygon representation 1500. Additionally, a PCM for the RD cycle was generated, representing the effect of one or more conditions on the sampling / tuning point. The PCM can take into account and / or be tuned to a specific protocol and reference clock configuration. For example, the PCM causes the polygon representation 1500 to shrink towards the origin of the graph at a linear rate of 0.1 for a certain one or more conditions (e.g., reducing the RX and TX delay).The shrinkage is due to a worst-case PCM implementation that generates the minimum polygon representation. However, other PCMs can lead to different results, such as enlargement, displacement, etc. In the second polygon representation, 1502, core processor 102 determines that the sample / tune point is "n," which corresponds to an amount of TX and RX delay for the RD cycle that matches polygon representation 1502. Additionally, a PCM was generated for the RD cycle that represents the effect of one or more conditions on the sample / tune point. For example, the PCM causes polygon representation 1500 to shrink upwards at a linear rate of 0.5 for one or more specific conditions (e.g., enlargement, RX delay).In the third polygon representation, 1504, core processor 102 determines that the sampling / tuning point is "p", which corresponds to an amount of TX and RX delay for the RD cycle that matches polygon representation 1504. Additionally, a PCM was generated for the RD cycle that represents the effect of one or more conditions on the sampling / tuning point. For example, the PCM causes polygon representation 1500 to shrink upwards and to the right towards the origin of the graph at a linear rate of 0.1 for one or more specific conditions (e.g., decreasing the RX and TX delay). The PCM of each polygon representation 1500, 1502, 1504 is defined as follows: Fig. 15 corresponds to a magnitude and a direction (e.g., a linear, vector-based representation). However, the PCM can correspond to a different model (e.g., a nonlinear one) that causes a polygon representation to adapt based on the effect that a change in conditions has on a sampling / tuning point and / or a polygon representation.

[0056] Fig. Figure 16 shows an alternative example of a polygon representation 1600 and the effect of applying a PCM on the polygon representation 1600, and the PCM can generate a scope of possible tuning points in a non-linear way. In the example of Fig. 16. Core processor 102 generates an initial polygon representation for an RD cycle with a selected sampling / tuning point of "0". The initial polygon representation corresponds to initial conditions (e.g., a first temperature range lower than a second temperature range, a first age range, etc.). When core processor 102 applies a PCM corresponding to one or more second environmental conditions (e.g., the second temperature range, a second age range older than the first age range, etc.), core processor 102 sets the selected sampling / tuning point from "0" to "1" using the PCM. When core processor 102 applies a PCM corresponding to one or more third conditions (e.g., a third temperature range higher than the second temperature range, a third age range older than the second age range, etc.), the PCM is set to "1".), the core processor 102 sets the selected sampling / tuning point from "1" to "2" using the PCM. As in . Fig. As shown in Figure 16, the polygon representations and the sampling / tuning points change non-linearly from “0” to “1” to “2”.

[0057] Fig. Figure 17 shows generated example polygon representations 1700, 1702, and 1704 for different RD cycles and the corresponding stability indicators for the selected sampling / tuning points of each polygon representation. The first polygon representation, 1700, corresponds to a first RD cycle and has a stability indicator of X1, which is the closest distance from the selected sampling / tuning point to the nearest edge of polygon representation 1700. The second polygon representation, 1702, corresponds to a second RD cycle and has a stability indicator of X2, which is the closest distance from the selected sampling / tuning point to the nearest edge of polygon representation 1702. The third polygon representation, 1704, corresponds to a third RD cycle and has a stability indicator of X3, which is the closest distance from the selected sampling / tuning point to the nearest edge of polygon representation 1704. In the example of Fig. 17. Based on the stability indicator, core processor 102 selects one of the sampling / tuning points of the polygon representations 1700, 1702, and 1704. For example, core processor 102 determines that the stability indicator of the sampling / tuning point of the third polygon, 1704, is larger than the stability indicators of the sampling / tuning points of the first and second polygons, 1700 and 1702 (assuming that the optimization criteria continuously increase). Accordingly, core processor 102 selects the sampling / tuning point of the third polygon representation, 1704, because its corresponding stability indicator is the largest of the three polygon representations.

[0058] Fig. Figure 18 is a block representation of an exemplary programmable circuit platform 1800, which is used for the execution and / or instantiation of the exemplary machine-readable instructions and / or the exemplary operations of Fig. 9 and Fig. 10 is structured to accommodate the core processor 102 of Fig. 8 to implement. The Programmable Circuit Platform 1800 can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a mobile phone, a smartphone, a tablet such as an iPad™), a personal digital assistant (PDA), an internet device, a game console, a headset (e.g., an augmented reality headset (AR headset), a virtual reality headset (VR headset), etc.), or any other wearable device or IoT (Internet of Things) device, or any other type of computing device and / or electronic device.

[0059] The programmable circuit platform 1800 of the illustrated example comprises programmable circuits 1812. The programmable circuits 1812 of the illustrated example are hardware. For example, the programmable circuits 1812 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers of any desired family or manufacturer. The programmable circuits 1812 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuits 1812 implement the parameter selection circuits 802, the polygon representation determination circuits 804, the sampling / tuning point determination circuits 806, the predictive compensation model 808, the comparator 810, and the sampling / tuning point application circuits 812.

[0060] The programmable circuits 1812 of the illustrated example include a local memory 1813 (e.g., a cache, registers, etc.). The programmable circuits 1812 of the illustrated example communicate via a bus 1818 with a main memory 1814, 1816, which includes volatile memory 1814 and non-volatile memory 1816. The volatile memory 1814 can be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), and / or any other type of RAM. The non-volatile memory 1816 can be implemented by flash memory and / or any other desired type of storage device. Access to the main memory 1814, 1816 of the illustrated example is controlled by a memory controller 1817.In some examples, memory control 1817 can be implemented by one or more integrated circuits, logic circuits, microcontrollers of any desired family or manufacturer, or any other type of circuitry for managing the data flow to and from main memory 1814, 1816. In some examples, one of the local memory 1813, volatile memory 1814, or non-volatile memory 1816 implements the storage 814 of . Fig. 8.

[0061] The programmable circuit platform 1800 of the illustrated example also includes interface circuits 1820. The interface circuits 1820 can be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a USB (Universal Serial Bus) interface, a Bluetooth® interface, an NFC (Near Field Communication) interface, a PCI (Peripheral Component Interconnect) interface, and / or a PCIe (Peripheral Component Interconnect Express) interface. In this example, the interface circuits 1820 implement the interface circuit 800 of Fig. 8.

[0062] In the example shown, one or more input devices 1822 are connected to the interface circuits 1820. The input device(s) 1822 allows a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the programmable circuits 1812. The one or more input devices 1822 can be implemented, for example, by an audio sensor, a microphone, a camera (still image or video), a keyboard, a button, a mouse, a touchscreen, a trackpad, and / or a speech recognition system.

[0063] Furthermore, one or more output devices 1824 are connected to the interface circuits 1820 of the illustrated example. The one or more output devices 1824 can be implemented, for example, by display devices (e.g., a light-emitting diode (LED), an organic light-emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube display (CRT), a fixed switching display (IPS), a touchscreen, etc.), a tactile output device, or a loudspeaker. The interface circuits 1820 of the illustrated example therefore typically include a graphics driver card, a graphics driver chip, and / or graphics processing circuitry such as a GPU.

[0064] The interface circuitry 1820 of the illustrated example also includes a communication device, such as a transmitter, a receiver, a transceiver, a modem, a home gateway, a wireless access point, and / or a network interface, to enable data exchange with external machines (e.g., data processing devices of any kind) through a network 1826. Communication can be established, for example, via an Ethernet connection, a DSL (Digital Subscriber Line) connection, a telephone line connection, a coaxial cable system, a satellite system, a wireless beyond line-of-sight system, a wireless line-of-sight system, a mobile phone system, an optical link, etc.

[0065] The programmable circuit platform 1800 of the illustrated example also includes one or more mass storage disks or devices 1828 for storing firmware, software, and / or data. Examples of such mass storage disks or devices 1828 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices such as flash memory devices and / or SSDs.

[0066] The machine-readable instructions of 1832, which were replaced by the machine-readable instructions of Fig. 9-10 may be implemented, may be stored in the mass storage device 1828, in volatile memory 1814, in non-volatile memory 1816 or on at least one non-transient computer-readable storage medium such as a CD or DVD, which may be removable.

[0067] An exemplary way of implementing the device 100, the core processor 102 and / or the communication interface 110 of Fig. 1 is in Fig. 2-5 are shown. However, one or more of the items shown may be missing. Fig. The elements, processes and / or devices shown in 1-2 may be combined, divided, rearranged, omitted, removed and / or implemented in any other way.

[0068] Furthermore, the interface circuits 800, the parameter selection circuits 802, the polygon representation determination circuits 804, the sampling / tuning point determination circuits 806, the PCM circuits 808, the comparator 810, the sampling / tuning point application circuits 812 and / or the storage 814 can be used by Fig. 8 could be implemented by hardware, software, firmware, and / or any combination thereof. Consequently, for example, any of the interface circuits 800, parameter selection circuits 802, polygon representation determination circuits 804, sample / tuning point determination circuits 806, PCM circuits 808, comparator 810, sample / tuning point application circuits 812, and / or memory 814 could be implemented by Fig. 8. implemented by one or more analog or digital circuits, logic circuits, programmable processors, programmable controller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), application-specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)) and / or field-programmable logic device(s) (PLD(s)).

[0069] In connection with one of the device or system claims of this patent for covering a pure software and / or firmware implementation, at least one of the interface circuits 800, the parameter selection circuits 802, the polygon representation determination circuits 804, the sampling / tuning point determination circuits 806, the PCM circuits 808, the comparator 810, the sampling / tuning point application circuits 812 and / or the storage 814 of Fig. 8 is hereby expressly defined as comprising a non-volatile, computer-readable storage device or storage disk such as memory, a Digital Versatile Disc (DVD), a Compact Disc (CD), a Blu-ray Disc, etc., including the software and / or firmware. Furthermore, the interface circuits 800, the parameter selection circuits 802, the polygon representation determination circuits 804, the sample / tuning point determination circuits 806, the PCM circuits 808, the comparator 810, the sample / tuning point application circuits 812, and / or the storage 814 of Fig. 8 one or more elements, processes and / or devices in addition to or instead of those in Fig. The term "in communication" includes the elements shown in Figure 8 and / or more than one of any or all of the depicted elements, processes, and devices. In its present usage, the term "in communication," including variations thereof, encompasses direct communication and / or indirect communication via one or more intermediate components and does not require direct physical (e.g., wired) communication and / or constant communication, but rather also includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and / or one-off events.

[0070] Flowcharts, exemplary hardware logic, machine-readable instructions, hardware-implemented automata and / or any combination thereof for implementing the Core Processor 102 of Fig. 1 and Fig. 8 represent, are in Fig. Figures 9-10 show that the machine-readable instructions can be one or more executable programs or part(s) of an executable program for execution by a computer processor. The program may be implemented in software stored on a non-volatile, computer-readable storage medium such as a CD-ROM, floppy disk, hard disk, DVD, Blu-ray disc, or memory associated with the processor; however, the entire program and / or parts thereof could alternatively be executed by a device other than the processor and / or be embodied in firmware or dedicated hardware.

[0071] Although the exemplary program refers to the in Fig. As described in the flowcharts shown in Figures 9-10, many other methods for implementing the Core Processor 102 can be used as alternatives. For example, the execution order of the blocks can be changed, and / or some of the described blocks can be modified, removed, or combined. Furthermore, or alternatively, some or all of the blocks can be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuits, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a comparator, an operational amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing any software or firmware.

[0072] The machine-readable instructions described here can be in one or more formats, including compressed, encrypted, fragmented, compiled, executable, and packaged. Machine-readable instructions, as described here, can be stored as data (e.g., parts of instructions, code, code representations, etc.) that can be used to create, manufacture, and / or generate machine-executable instructions. For example, machine-readable instructions can be fragmented and stored on one or more storage devices and / or computing devices (e.g., servers). The machine-readable instructions can be subjected to one or more operations, including installation, modification, adaptation, updating, combination, augmentation, configuration, decryption, decompression, unpacking, distribution, reassignment, compilation, etc.required to make them directly readable, interpretable, and / or executable by a computing device and / or another machine. For example, the machine-readable instructions may be stored in multiple parts, each of which is individually compressed, encrypted, and stored on separate computing devices, where, when decrypted, decompressed, and combined, the parts form a set of executable instructions that implement a program such as the one described here.

[0073] In another example, the machine-readable instructions may be stored in a state where they can be read by a computer, but require the addition of a library (e.g., a Dynamic Link Library (DLL)), a Software Development Kit (SDK), an Application Programming Interface (API), etc., to execute the instructions on a specific computing device or other device. In yet another example, the machine-readable instructions may need to be configured (e.g., settings saved, data entered, network addresses recorded, etc.) before the machine-readable instructions and / or the corresponding program(s) can be executed, either fully or partially.As a result, machine-readable instructions and / or corresponding program(s) include such machine-readable instructions and / or program(s) regardless of the specific format or state of the machine-readable instructions and / or program(s) when stored or otherwise at rest or in transit.

[0074] The machine-readable instructions described here can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions can be represented using any of the following languages: assembly language, C, C++, Java, C-Sharp, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0075] As mentioned above, the exemplary processes of Fig. 6. are implemented using executable instructions (e.g., computer- and / or machine-readable instructions) stored on one or more non-volatile computer- and / or machine-readable media, such as a hard disk drive, flash memory, read-only memory, compact disk, digital versatile disk, cache, random-access memory, and / or any other storage device or disk on which information is stored for any duration (e.g., for extended periods, permanently, briefly, for temporary buffering, and / or caching of information). In this usage, the term "non-volatile computer-readable medium" is expressly defined to include any type of computer-readable storage device and / or disk and excludes propagating signals and transmission media.

[0076] Although certain exemplary processes, devices, and articles have been described herein, the scope of protection of this patent is not limited to them. On the contrary, this patent covers all processes, devices, and articles that reasonably fall within the scope of protection of the claims of this patent.

[0077] The descriptors “first,” “second,” “third,” etc., are used here when identifying multiple elements or components that can be referenced separately. Unless otherwise stated or evident from their context, such descriptors do not convey any significance of priority, physical order or arrangement in a list, or chronological sequence, but are used simply as labels to facilitate understanding of the examples described. In some examples, the descriptor “first” might be used to refer to an element in the detailed description, while the same element in a claim might be referred to by a different descriptor, such as “second” or “third.” In such cases, these descriptors are used only to simplify the reference to multiple elements or components.

[0078] In the description and claims, the terms "comprising" and "comprising" and their variants shall be understood to mean inclusive in a similar way to the term "comprising," unless otherwise specified. Unless otherwise specified, "approximately," "about," or "essentially" before a value means + / - 10% of the stated value. In another example, "approximately," "about," or "essentially" before a value means + / - 5% of the stated value. In yet another example, "approximately," "about," or "essentially" before a value means + / - 1% of the stated value.

[0079] The terms "couple," "coupled," "couples," and variations thereof, as used here, can encompass connections, communications, or signal paths that enable a functional relationship in accordance with this description. For example, if a device A generates a signal to control a device B to perform an action, then in a first example, device A is coupled to device B. In a second example, device A is coupled to device B via an intermediary component C, provided that the intermediary component C does not substantially alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A. Furthermore, the terms "couple," "coupled," "couples," and variations thereof, as used here, include any indirect or direct electrical or mechanical connection.

[0080] A device that is "designed" to perform a task or function can be configured (e.g., programmed and / or hardwired) by a manufacturer to perform that function at a point in time during manufacture, and / or can be configured (or reconfigured) by a user after manufacture to perform that function and / or other additional or alternative functions. Configuration can be achieved through firmware and / or software programming of the device, through the construction and / or layout of hardware components and interconnections of the device, or a combination thereof.

[0081] Although they are in Fig.Unless otherwise indicated, components or elements of systems and circuits depicted in Figures 1-4 have one or more conductors or terminations that allow signals to enter and / or exit the components or elements. The conductors or terminations (or parts thereof) may be referred to here as pins, pads, terminals (including, for example, input terminals, output terminals, reference terminals, and ground terminals), inputs, outputs, nodes, and connections.

[0082] In this usage, a "terminal" of a component, device, system, circuit, integrated circuit, or other electronic or semiconductor device generally refers to a conductor, such as a wire, trace, pin, pad, or other connector or connection, that allows the component, device, system, etc., to be electrically and / or mechanically connected to another component, device, system, etc. A terminal may be used, for example, to receive analog or digital electrical signals (or simply signals) or to be electrically connected to a common or ground reference. An input terminal or input, accordingly, is used to receive a signal from another component, device, system, etc.An output terminal, or output, is used to supply a signal to another component, device, system, etc. Other terminals can be used to connect to a common or ground voltage reference, such as a reference terminal or ground terminal. A terminal on an IC or PCB may also be called a pin (an elongated conductor) or pad (a planar conductor). A node refers to a connection point or intermediate link between two or more terminals. An example number of terminals and nodes may be shown; however, depending on the specific circuit or system topology, there may be more or fewer terminals and nodes. In some cases, the terms "terminal," "node," "intermediate link," "pad," and "pin" may be used interchangeably.

[0083] The expressions “or” and “and / or” refer, for example in a form such as A, B or C or A, B and / or C, to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C or (7) A with B and with C.

[0084] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of protection of the claims. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US-PS 11 935 613

[0013]

Claims

[1] Device comprising: a communication interface that can be configured to receive a data signal; and Processor circuits that are coupled with the communication interface and can be designed for Determining an initial timing for sampling the data signal for a first value of a condition; Determining a second timing to sample the data signal for a second value of the condition using the first timing and a predictive compensation model, wherein the second timing differs from the first timing; Measuring the condition; Selecting the first timing or the second timing using the measured condition; and Programming the communication interface for sampling with the selected timing. [2] Device according to claim 1, where the condition is temperature, where the first temperature value is a different temperature than the second temperature value and where the first timing has a different delay than the second timing. [3] Device according to claim 1, wherein the predictive compensation model comprises different delays for varying temperatures. [4] Device according to claim 1, wherein the communication interface comprises a serial half-duplex peripheral interface. [5] Device according to claim 1, wherein the processing circuits are configurable for Determining a third timing for sampling the data signal for a third value of the condition using the first timing or using the second timing, wherein the third timing differs from the first timing and differs from the second timing; and Selecting the first timing, the second timing, or the third timing using the measured condition. [6] Device according to claim 1, wherein the predictive compensation model adjusts the first timing using a mathematical function based on estimates of an effect of the condition on the success of the first timing. [7] Device according to claim 1, wherein the processor circuits shall determine the first timing by generating a polygon representation based on a successful sampling of data for different tuning point parameters, wherein the first timing corresponds to a point in the polygon representation. [8] Device according to claim 7, wherein the processor circuits are configurable for generating the polygon representation by Transmitting instructions to write initial data to a peripheral device based on the various tuning point parameters; Sampling of second data from the peripheral device based on the various tuning point parameters; and Determine that part of the sampling was successful, based on the fact that the first data matches the second data; and Generating the polygon representation using the portion of the various tuning point parameters that corresponds to the portion of the sampling. [9] Device according to claim 1, wherein the condition is an environmental condition and / or a die condition, wherein the environmental condition corresponds to temperature and / or humidity, and the die condition corresponds to the age of the communication interface, the structure of the communication interface and / or the location of the communication interface when implemented in a wafer. [10] Procedures, including: Determining an initial timing for sampling a data signal for a first value of a condition; Determining a second timing to sample the data signal for a second value of the condition using the first timing and a predictive compensation model, wherein the second timing differs from the first timing; Measuring the condition; Selecting the first timing or the second timing using the measured condition; and Programming a communication interface for sampling using the selected timing. [11] Method according to claim 10, where the condition is temperature, where the first temperature value is a different temperature than the second temperature value and where the first timing has a different delay than the second timing. [12] Method according to claim 10, wherein the predictive compensation model includes different delays for different temperatures. [13] Method according to claim 10, wherein the communication interface comprises a serial peripheral interface. [14] The method of claim 10, comprising: Determining a third timing for sampling the data signal for a third value of the condition using the first timing or using the second timing, wherein the third timing differs from the first timing and differs from the second timing; and Selecting the first timing, the second timing, or the third timing using the measured condition. [15] Device according to claim 10, wherein the predictive compensation model adjusts the first timing using a mathematical function based on estimates of an effect of the condition on the success of the first timing. [16] Method according to claim 10, comprising: determining the first timing by generating a polygon representation based on successful sampling of data for different tuning point parameters, wherein the first timing corresponds to a point in the polygon representation. [17] Method according to claim 16, wherein generating the polygon representation comprises: Transmitting instructions to write initial data to a peripheral device based on the various tuning point parameters; Sampling of second data from the peripheral device based on the various tuning point parameters; and Determine that part of the sampling was successful, based on the fact that the first data matches the second data; and Generating the polygon representation using the portion of the various tuning point parameters that corresponds to the portion of the sampling. [18] System, encompassing: a communication interface that can be designed for Transmission of a clock signal and an initial data signal based on tuning point parameters; and Sampling a second data signal based on the tuning point parameters; and a peripheral device coupled to the communication interface, wherein the peripheral device can be designed for Receiving the clock signal and the first data signal; and Transmission of the second data signal, wherein the second data signal corresponds to the first data signal; and Processor circuits coupled to the communication interface, wherein the processor circuits can be designed for Determining a first timing to sample the second data signal for a first value of a condition, where the first timing corresponds to the tuning point parameters; Determining a second timing to sample the second data signal for a second value of the condition using the first timing and a predictive compensation model, wherein the second timing differs from the first timing; Measuring the condition; Selecting the first timing or the second timing using the measured condition; and Programming the communication interface to use the selected timing. [19] System according to claim 18, where the condition is temperature, where the first temperature value is a different temperature than the second temperature value and where the first timing has a different delay than the second timing. [20] System according to claim 18, wherein the predictive compensation model includes different delays for different temperatures.

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