Multiplexed stacked memory device

Abstract

A multiplexed stacked memory device comprises a base die and memory stack comprising one or more memory dies supporting a set of memory banks. The memory banks are organized into bank groups each internally accessed via separate internal data buses. The internal data buses may operate as different internal pseudochannels of a set of internal channels. The base die includes bus aggregation logic to switch data between an external data bus and multiple internal data buses, thereby enabling access to multiple bank groups via the single external data bus. The memory device may be configurable between a sequential access mode to enable sequential access on the external data bus to data on the multiplexed internal data buses and an interleaved access mode that enables interleaved access between the external data bus and the multiplexed internal data buses.

Description

MULTIPLEXED STACKED MEMORY DEVICEBRIEF DESCRIPTION OF THE DRAWINGS

[0001] The teachings of the embodiments herein can be readily understood by considering the following detailed description in conjunction with the accompanying drawings.

[0002] FIG. 1 is an example embodiment of a memory system according to an embodiment.

[0003] FIG. 2 is an example embodiment of a channel architecture for a stacked memory device.

[0004] FIG. 3 illustrates a first example of bus aggregation logic on a base die for interfacing between a host device and a memory die in a stacked memory device.

[0005] FIG. 4 illustrates an example operation of a multiplexed stacked memory device in which the bus aggregation logic is configured for sequential accesses.

[0006] FIG. 5 illustrates an example operation of a multiplexed stacked memory device in which the bus aggregation logic is configured for interleaved accesses.

[0007] FIG. 6 illustrates a second example of bus aggregation logic on a base die for interfacing between a host device and a memory die in a stacked memory device.DETAILED DESCRIPTION

[0008] A multiplexed stacked memory device comprises a base die and memory stack comprising one or more memory dies supporting a set of memory banks. The memory banks are organized into bank groups each internally accessed via separate internal data buses. The internal data buses may operate as different internal pseudochannels of a set of internal channels in which internal pseudochannels within the same internal channel share an internal command / address interface. The base die includes bus aggregation logic to switch data between an external data bus of the base die and multiple internal data buses of the base die, thereby enabling the base die to internally access and aggregate data from multiple bank groups via the same external data bus. The memory device may be configurable between a sequential access mode and an interleaved access mode. In the sequential access mode, data for operations associated with different bank groups accessible via the same external data bus are sequentially communicated on the external data bus. In the interleaved access mode, data for operations associated with different bank groups accessible via the same external data bus are communicated in an interleaved manner on the external data bus. In the interleaved access mode, the external data bus may operate as twice the data rate as the internal data buses.

[0009] FIG. 1 illustrates an example embodiment of a memory system 100. The memory system1 RAMB-025WO / 11445WO01100 includes a host device 110 and one or more memory devices 130 coupled by a communication link 120. In the illustrated example, a single host device 110 and two memory devices 130 are shown. In various applications, the memory system 100 can include any number of memory devices 130 coupled to the same host device 110 (via different communication links 120 or via a shared link), and / or the memory system 100 can include multiple host devices 110 accessing the same memory device 130.

[0010] The memory device 130 may comprise a stacked memory architecture having a base die 132 and a memory stack 134. The memory stack 134 may include one or more memory die 136 that each having a set of memory banks organized into bank groups. In one implementation, the memory banks may comprise dynamic random access memory (DRAM) banks. In other examples, the memory banks may include one or more different types of memories such as static random access memory (SRAM), non-volatile core memory (such as flash), conductive bridging random core memory (CBRAM — a.k.a., programmable metallization cell — PMC), resistive random core memory (a.k.a., RRAM or ReRAM), or magneto-resistive random-access memory (MRAM).

[0011] Different sets of bank groups may be accessed via respective external channels 122 of the communication link 120, where each channel 122 comprises an independent command and data pathway. For example, in one architecture, each memory device 130 includes a group of 16 channels 122. The host device 110 may facilitate memory operations (e.g., read and write operations) with respect to each channel 122 independently. For example, operations may be performed concurrently or overlappingly using multiple channels based on commands and data sent independently over the respective channels.

[0012] The base die 132 of each memory device 130 includes interface logic for managing communications to and from the host device 110. For example, the base die 132 may include a host-side channel interface 142 for each channel 122 that receives commands from the host device 110 and facilitates communication of data to and from the host device 110. The base die 132 also includes memory-side channel interfaces 144 for transmitting commands to the memory stack 134 and for facilitating communication of data to and from the memory stack 134. The base die 132 may furthermore include logic to control routing of data and commands between the host device 110 and different bank groups of the memory stack 134 as described in further detail below.

[0013] The host device 110 may comprise a computing system that includes a host processor 112 for performing general computing functions and a memory controller 114 for controlling memory operations of the connected memory devices 130 based on instructions from the host processor 112. The host device 110 may operate as part of a cloud computing and / or storage system, an enterprise server system, a personal computer device, or any other computing environment. The2 RAMB-025WO / 11445WO01memory controller 114 may be disposed on a separate Input / Output (I / O) die along with the transmitter / receiver circuits that interface with the memory devices 130 via the communication link 120. Such an I / O die may include other types of I / O interfaces, as well as one or more chiplet interfaces that communicate with one or more respective CPU chiplet dies embodying the host processor. The I / O die and CPU chiplet dies may be co-packaged together and coupled to one-another via a silicon interposer.

[0014] The memory controller 114 may facilitate memory operations by generating and sending memory commands (e.g., read, write, etc.) to one or more of the stacked memory devices 130 and facilitating data transfers to and from the memory devices 130. The memory controller 114 may furthermore provide various control and management functions associated with the memory devices 130. For example, the memory controller 114 may send one or more control signals that control whether the memory devices 130 operate in a sequential access mode or an interleaved access mode. Furthermore, the memory controller 114 may control operating data rates associated with the external data bus and / or internal data buses of the memory devices 130 as described below.

[0015] FIG. 2 illustrates an example architecture for a single external channel 122 of a memory device 130. The base die 132 includes a host-side channel interface 142 that operates as two pseudochannels 220 (e.g., a first pseudochannel 220-1 and a second pseudochannel 220-2). Each pseudochannel 220 includes an independent external data bus (DQ) 208 (e.g., data bus 208-1, 208-2) and the two pseudochannels 220 share an external command / address (CA) bus 210. An address associated with commands from the host device 110 may include a pseudochannel select field (e.g., a bit or set of bits) indicating which pseudochannel 220 is selected for a particular command. This configuration enables the host-side channel interface 142 to communicate data for commands relating to different pseudochannels 220 concurrently or overlappingly. For example, if sequential read or write commands are received for different pseudochannels 220 of the same external channel 122, the data associated with the respective commands may be communicated concurrently over the respective external data buses 208 for the different external pseudochannel 220. In other implementations, a combined command received on the external CA bus 210 may cause concurrent memory operations to be performed using both external data buses 208 for the different external pseudochannels 220.

[0016] The base die 132 also includes bus aggregation logic 206 for controlling switching of data to and from different internal data buses 204 and corresponding bank groups 202 of the memory die 136. In one implementation, the bus aggregation logic 206 may also perform switching of command / address signals from the shared host-side CA bus 210 associated with the external channel 122 to the different bank groups 202 via one or more internal command / address buses3 RAMB-025WO / 11445WO01212. Alternatively, commands may be broadcast to all bank groups 202 within the channel 122 via a single internal command / address bus 212.

[0017] The memory die 136 includes a set of memory bank groups 202 that are each accessed via respective internal data buses 204. The bank groups 202 and corresponding internal data buses 204 are organized into two internal channels 216 (e.g., internal channel 216-1 (IC1) and internal channel 216-2 (IC2)) that are both accessible via the same external channel 122. The internal channels 216 are furthermore organized into respective pairs of internal pseudochannels 214 (e.g., a first internal pseudochannel 214-1 and second internal pseudochannel 214-2). Thus, the memory die 136 may include a first bank group 202-1 associated with the first internal channel 216-1 and first internal pseudochannel 214-1 which is accessed via a first internal data bus 204-1, a second bank group 202-2 associated with the first internal channel 216-1 and second internal pseudochannel 214-2 accessed via the second internal data bus 204-2, a third bank group 202-3 associated with the second internal channel 216-2 and the first internal pseudochannel 214-1 accessed via a third internal data bus 204-3, and a fourth bank group 202-4 associated with the second internal channel 216-2 and second internal pseudochannel 214-2 accessed via a fourth internal data bus 204-4.

[0018] The bus aggregation logic 206 may route data between the two external data buses 208 (for the two respective external pseudochannels 220) and the four internal data buses 204 (supporting each of the two internal pseudochannels 214 per each of the two internal channels 216) in different ways depending on the aggregation configuration. This aggregation configuration may be statically or dynamically configured to manage desired tradeoffs between bandwidth, capacity, power usage, complexity, or other considerations.

[0019] The single channel architecture shown in FIG. 2 may be repeated for each external channel 122 of the memory device 130. For example, in one embodiment, a memory device 130 may support 16 external channels 122 that each replicate the architecture of FIG. 2 and may operate independently. The memory device 130 may have a single memory die 136 or may have multiple stacked memory dies 136. In embodiments with multiple memory dies 136, each memory die 136 may include a set of bank groups 202, internal data buses 204, command buses 212, and other logic supporting a subset of the set of external channels 122. For example, in one implementation, a memory device may have two memory dies 136 that each support eight external channels 122. The internal data buses 204 and command buses 212 for different memory die 136 may be routed through the stack using through silicon vias (TSVs) or other technologies. In other embodiments, bank groups 202, internal data buses 204, and command buses 212 supporting the same external channel 122 may be split between multiple memory die 136 such that each memory die 136 includes only a subset of the memory banks 202, internal4 RAMB-025WO / 11445WO01data buses 204, and other supporting logic associated with the external channel 122.

[0020] FIG. 3 illustrates a first example aggregation architecture for a single external channel 122 of a memory device 130 including a base die 132 and a memory die 136. This aggregation architecture may be repeated for each external channel 122 of the memory device 130 (on the same memory die 136 or distributed across multiple memory die 136 in a stacked configuration). In this example, the bus aggregation logic 206 includes a first bidirectional multiplexer 302-1 that selectively switches data between the first external pseudochannel 220-1 (via the first external data bus 208-1) and either the first internal pseudochannel 214-1 of the first internal channel 216-1 (via the first internal data bus 204-1) or the first internal pseudochannel 214-1 of the second internal channel 216-2 (via the third internal data bus 204-3). A second bidirectional multiplexer 302-2 switches data between the second external pseudochannel 220-2 (via the second external data bus 208-2) and either the second internal pseudochannel 214-2 of the first internal channel 216-1 (via the second internal data bus 204-2) or the second internal pseudochannel 214-2 of the second internal channel 216-2 (via the fourth internal data bus 204- 4).

[0021] The multiplexers 302 may be controlled in various ways. For example, in a sequential access mode (as illustrated in FIG. 4 below), data for operations associated with different bank groups 202 (and corresponding internal data buses 204) that are accessible via the same external data bus 208 are sequentially communicated on the external data bus 208. In an interleaved access mode (as illustrated in FIG. 5 below), data for operations associated with different bank groups 202 and corresponding internal data buses 204 that are accessible via the same external data bus 208 are communicated in an interleaved manner on the external data bus 208.

[0022] FIG. 4 illustrates an operating configuration of the memory device 130 in which the memory device 130 controls the multiplexer 306 to route between the different connected internal data buses 204 based on a command address associated with a received command. For the connectivity configuration of FIG. 3 in which each multiplexer 306 switch between two different internal channels 216, the multiplexer 306 may select the first internal channel 216-1 for addresses in a first address range and select the second internal channel 216-2 for addresses in a second address range. The address range may be defined based on an extended bank address, an extended row address, or other address parameter. One or more address bits (i.e., the pseudochannel select field) of the command (set by the host device 110) controls selection of either the first or second internal pseudochannels 214-1, 214-2 within the internal channel 216 (based on connectivity of the multiplexers 302). From the host perspective, the multiplexed internal channels 216-1, 216-2 appear as a single external channel 122 (still with two available pseudochannels 220) with twice the capacity (i.e., twice the address range supporting twice the5 RAMB-025WO / 11445WO01number of memory banks) as a memory stack 134 with only a single internal channel.

[0023] In the illustrated example, the memory device 130 processes a first command 402 for reading from an address in a first address range followed by a second command 404 for reading from an address in a second address range. The commands 402, 404 may be internally broadcast to both internal channels 216-1, 216-2, or may be sequentially routed to the respective internal channels 216-1, 216-2 based on the command address. The commands 402, 404 may be directly sent by the host device 110 as two separate commands or the commands 402, 404 may be internally generated by the aggregation logic 206 in response to a single command from the host device 110. Internally, the data accesses associated with the first and second data 406, 408 may be performed in parallel, in an overlapping manner, or in a non-overlapping manner. In any case, the memory device 130 externally outputs the data 406, 408 sequentially by first configuring the internal multiplexer 306-1 to select the first internal data bus 204-1 corresponding to the first internal channel 216-1 (and first internal pseudochannel 214-1) for outputting a first full data burst 406 relating to the first command 402 and then configuring the internal multiplexer 306-1 to select the third internal data bus 204-3 corresponding to the second internal channel 216-2 (and first internal pseudochannel 214-1) for outputting a full data burst 408 relating to the second command 404. The first data burst 410 and second data burst 412 are output sequentially using the external data bus 208-1 for the first pseudochannel 220-1.

[0024] While FIG. 4 provides an example operation associated with a read command, the memory device 130 may similarly process write commands in a sequential manner. Here, the memory device 130 may sequentially receive the first and second data via the external data bus 208-1, and may then internally perform the write operations in parallel, in an overlapping manner, or in a non-overlapping manner.

[0025] The illustrated operation utilizes only the first external data bus 208-1 corresponding to the first external pseudochannel 220-1. Because the external pseudochannels 220-1, 220-2 may operate in parallel concurrently or overlappingly), operations utilizing the second external pseudochannel 220-2 may be performed in parallel with the operations of the first external pseudochannel 220-1. Operations associated with the second external pseudochannel 220-2 may similarly involve the multiplexer 306-2 facilitating sequential accesses to different memory banks (e.g., memory banks 220-2, 220-4) that are associated with different internal channels 216- 1, 216-2 and are accessible via the pair of internal data buses 204-2, 204-4 corresponding to the second internal pseudochannel 214-2.

[0026] FIG. 5 illustrates another example operation of the memory device 130 where the bus aggregation logic 206 is configured to enable interleaved accesses to multiple bank groups 202 via respective internal data buses 204 that are multiplexed with the same external data bus 208.6 RAMB-025WO / 11445WO01In this example, the memory device 130 receives a read command 502 on the CA bus 210 that has the pseudochannel select field set to pseudochannel 1 (thus indicating that data will be externally communicated via the first external data bus 208-1 associated with the first external pseudochannel 220-1). The command 502 may be internally broadcast via the internal CA bus 212 to both internal channels 216-1, 216-2, or may be routed only to the specific relevant bank groups 202-1, 202-3. In another implementation, the host device 110 may send separate commands (e.g., serially) for an address associated with the first internal channel 216-1 and an address associated with the second internal channel 216-2. The bank groups 202-1, 202-3 may process the read command 502 in parallel or with overlapping timing. The first bank group 202- 1 outputs first data 504 on its internal data bus 204-1 and the second bank group 202-3 outputs second data 506 on its internal data bus 204-3. The multiplexer 302-1 for the first external pseudochannel 220-1 interleaves the first and second data 504, 506 as it is received and outputs on the interleaved data 508 on the external data bus 208-1 for the first external pseudochannel 220-1. From the perspective of the host device 110, it accesses twice the data relative to a memory device with a single internal channel. In one configuration, the data may be output on the external data interface 208-1 at double the data rate of the internal data interfaces 204-1, 204- 3. In this case, the host device 110 may operate at twice the bandwidth compared to operations using only a single internal channel 216 (or equivalently, the internal data buses 204 may operate at half the data rate while achieving the same output bandwidth as with a single internal channel 216).

[0027] While the example of FIG. 5 pertains to a read operation, the same process may be employed in a write operation. Here, interleaved data may be received at the external data interface 208-1 of a first external pseudochannel 220-1, de-interleaved by the bus aggregation logic 206, and written in parallel to respective internal data banks 202-1, 202-3 via respective internal data buses 204-1, 204-3.

[0028] The illustrated operation utilizes only the first external data bus 208-1 corresponding to the first external pseudochannel 220-1. Because the external pseudochannels 220-1, 220-2 may operate in parallel concurrently or overlappingly), similar interleaved operations utilizing the second external pseudochannel 220-2 may be performed in parallel with the operations of the first external pseudochannel 220-1. Operations associated with the second external pseudochannel 220-2 may similarly involve the multiplexer 306-2 facilitating interleaved accesses to different memory banks (e.g., memory banks 220-2, 220-4) that are associated with different internal channels 216-1, 216-2 and are accessible via the pair of internal data buses 204- 2, 204-4 corresponding to the second internal pseudochannel 214-2.

[0029] In one embodiment, the bus aggregation logic 206 may be dynamically configurable to7 RAMB-025WO / 11445WO01operate according to the sequential operation of FIG. 4 or the interleaved operations of FIG. 5. For example, the bus aggregation logic 206 may be configured via a switch set at manufacture time, via a physical toggle switch, or via a register value configurable by the host device 110. Similarly, the output data rate of the external data buses 208 may be dynamically configurable to operate at the same speed as the internal data buses 204 or double the speed (as described above with respect to FIG. 5).

[0030] FIG. 6 illustrates a second example connectivity configuration for a single external channel 122 of a memory device 130 including a base die 132 and a memory die 136. This connectivity configuration may be repeated for each external channel 122 of the memory device 130 (on the same memory die 136 or distributed across multiple memory die 136 in a stacked configuration). In this example, the first bidirectional multiplexer 302-1 switches data between the first external data bus 208-1 (corresponding to the first external pseudochannel 220-1) and either the first internal data bus 204-1 (corresponding first internal pseudochannel 214-1 of the first internal channel 216-1) or the second internal data bus 204-2 (corresponding to the second internal pseudochannel 214-2 of the first internal channel 216-1). The second bidirectional multiplexer 302-2 switches data between the second external data interface 208-2 (corresponding to the second external pseudochannel 220-2) and either the third internal data bus 204-3 (corresponding pseudochannel 214-1 of the second internal channel 216-2) or the fourth internal data bus 204-4 (corresponding to the second internal pseudochannel 214-2 of the second internal channel 216-2).

[0031] In one such configuration, one or more address bits (i.e., the pseudochannel select field of the command) (set by the host device 110) controls selection between the first or second internal channels 216 and the command address is used by the bus aggregation logic 206 to internally control routing to the first or second internal pseudochannel 214. In this configuration, the memory device 130 of FIG. 6 may perform operations similarly to those describe above with respect to FIG. 4, except that the switching associated with the sequential accesses is performed with respect to the bank groups 202-1, 202-2 and internal data buses 204-1, 204-2 corresponding to different internal pseudochannels 214-1, 214-2 of the same internal channel 216-1 (or bank groups 202-3, 202-4 and internal data buses 204-3, 204-4 corresponding to different internal pseudochannels 214-3, 214-4 of the same internal channel 216-2).

[0032] In another configuration, an interleaved data access may be performed in which the multiplexers 306 operate to interleave (or de-interleave) data from two different internal banks 202 corresponding to different internal pseudochannels 214 in response to a command. Thus, the memory device 130 of FIG. 6 may perform operations similarly to those described above with respect to FIG. 5, except the interleaved accesses may be performed with respect to the bank8 RAMB-025WO / 11445WO01groups 202-1, 202-2 and internal data buses 204-1, 204-2 corresponding to different internal pseudochannels 214-1, 214-2 of the same internal channel 216-1 (or bank groups 202-3, 202-4 and internal data buses 204-3, 204-4 corresponding to different internal pseudochannels 214-3, 214-4 of the same internal channel 216-2).

[0033] In another variation, the external data buses 208-1, 208-2 may correspond to pseudochannel interfaces for two different external channels 122 (e.g., the data bus 208-1 corresponds to pseudochannel 1 of channel 1 and the data bus 208-2 corresponds to pseudochannel 1 of channel 2) The corresponding pseudochannel 2 for channels 1 and 2 may be implemented on a separate memory die 136. In this embodiment, command / address buses 212 may be duplicated on both memory devices 130.

[0034] Upon reading this disclosure, those of ordinary skill in the art will appreciate still alternative structural and functional designs and processes for the described embodiments, through the disclosed principles of the present disclosure. Thus, while embodiments and applications of the present disclosure have been illustrated and described, it is to be understood that the disclosure is not limited to the precise construction and components disclosed herein. Various modifications, changes and variations which will be apparent to those skilled in the art may be made in the arrangement, operation and details of the method and apparatus of the present disclosure herein without departing from the scope of the disclosure as defined in the appended claims.9 RAMB-025WO / 11445WO01

Claims

WHAT IS CLAIMED IS:

1. A memory device comprising: at least one memory die including a first memory bank group and a second memory bank group; a base die stacked with the at least one memory die, the base die comprising: an external command / address bus for receiving commands from a host device; an internal command / address bus for internally sending the commands to the at least one memory die; a first external data bus to communicate data with the host device; a first internal data bus to communicate the data with the first memory bank group; a second internal data bus to communicate the data with the second memory bank group; and channel aggregation logic comprising at least a first bidirectional multiplexer to switch data between the first external data bus and the first internal data bus for commands associated with the first memory bank group, and to switch data between the first external data bus and the second internal data bus for memory commands associated with the second memory bank group.

2. The memory device of claim 1, wherein the at least one memory die further includes a third memory bank group and a fourth memory bank group; wherein the memory device further comprises: a second external data bus to communicate data with the host device; a third internal data bus to communicate the data with the third memory bank group; a fourth internal data bus to communicate the data with the fourth memory bank group; and wherein the channel aggregation logic further comprises a second bidirectional multiplexer to switch data between the second external data bus and the third internal data bus for commands associated with the third memory bank group, and to switch data between the second external data bus and the fourth internal data bus for memory commands associated with the fourth memory bank group.10 RAMB-025WO / 11445 WOOl3. The memory device of claim 2, wherein the first external data bus and the second external data bus operate as a pair of pseudochannels of an external channel between the host device and the memory device, wherein the pair of pseudochannels share the external command / address bus.

4. The memory device of claim 3, wherein the channel aggregation logic is configured to broadcast commands from the external command / address bus to each of the first memory bank group, the second memory bank group, the third memory bank group, and the fourth memory bank group.

5. The memory device of claim 3, wherein the channel aggregation logic is configured to selectively route the commands from the external command / address bus to one or more of the first memory bank group, the second memory bank group, the third memory bank group, and the fourth memory bank group.

6. The memory device of claim 1, wherein the first internal data bus and the first memory bank group operate as a first internal pseudochannel of a first internal channel of the memory device, and wherein the second internal data bus and the second memory bank group operate as the first internal pseudochannel of a second internal channel of the memory device.

7. The memory device of claim 1, wherein the first internal data bus and the first memory bank group operate as a first internal pseudochannel of a first internal channel of the memory device, and wherein the second internal data bus and the second memory bank group operate as a second internal pseudochannel of the first internal channel of the memory device.

8. The memory device of claim 1, wherein the channel aggregation logic is configured to sequentially facilitate a first memory command associated with the first memory bank group and a second memory command associated with the second memory bank group by sequentially routing a first full data burst associated with the first memory command between the first external data bus and the first internal data bus, and subsequently routing a second full data burst associated with the second memory command between the first external data bus and the second internal data bus.

9. The memory device of claim 1, wherein the channel aggregation logic is configured to perform interleaved access associated with the first memory bank group and the second memory bank group by alternately between routing data between the first external data bus and the first internal data bus, and routing data between the first external data bus and the second internal data bus.11 RAMB-025WO / 11445WO0110. The memory device of claim 9, wherein the first internal data bus and the second internal data bus operate at a first data rate, and wherein the first external data bus operates at a second data rate that is double the first data rate.

11. The memory device of claim 1, wherein the channel aggregation logic is statically configured to operate in a sequential access mode or an interleaved access mode, wherein in the sequential access mode, the channel aggregation logic sequentially routes full data bursts relating to different commands between the first internal data bus and the first external data bus and between the second internal data bus and the first external data bus, and wherein in the interleaved access mode, the channel aggregation logic alternates between routes data between the first internal data bus and the first external data bus and between the second internal data bus and the first external data bus.

12. The memory device of claim 1, wherein the channel aggregation logic is dynamically configurable to operate in a sequential access mode or an interleaved access mode, wherein in the sequential access mode, the channel aggregation logic sequentially routes full data bursts relating to different commands between the first internal data bus and the first external data bus and between the second internal data bus and the first external data bus, and wherein in the interleaved access mode, the channel aggregation logic alternates between routes data between the first internal data bus and the first external data bus and between the second internal data bus and the first external data bus.

13. The memory device of claim 1, wherein the first and second memory bank groups comprise dynamic random access memory (DRAM) bank groups.

14. A base die for a stacked memory device that includes at least one memory die in a stack with the base die, the memory die having a first memory bank group and a second memory bank group, the base die comprising; an external command / address bus for receiving commands from a host device; an internal command / address bus for internally sending the commands to the at least one memory die; a first external data bus to communicate data with the host device; a first internal data bus to communicate the data with the first memory bank group; a second internal data bus to communicate the data with the second memory bank group; and channel aggregation logic comprising at least a first bidirectional multiplexer to switch data between the first external data bus and the first internal data12 RAMB-025WO / 11445WO01bus for commands associated with the first memory bank group, and to switch data between the first external data bus and the second internal data bus for memory commands associated with the second memory bank group.

15. The base die of claim 14, wherein the at least one memory die further includes a third memory bank group and a fourth memory bank group; wherein the base die further comprises: a second external data bus to communicate data with the host device; a third internal data bus to communicate the data with the third memory bank group; a fourth internal data bus to communicate the data with the fourth memory bank group; and wherein the channel aggregation logic further comprises a second bidirectional multiplexer to switch data between the second external data bus and the third internal data bus for commands associated with the third memory bank group, and to switch data between the second external data bus and the fourth internal data bus for memory commands associated with the fourth memory bank group.

16. The base die of claim 15, wherein the first external data bus and the second external data bus operate as a pair of pseudochannels of an external channel between the host device and the stacked memory device, wherein the pair of pseudochannels share the external command / address bus.

17. The base die of claim 16, wherein the channel aggregation logic is configured to broadcast commands from the external command / address bus to each of the first memory bank group, the second memory bank group, the third memory bank group, and the fourth memory bank group.

18. The base die of claim 16, wherein the channel aggregation logic is configured to sequentially facilitate a first memory command associated with the first memory bank group and a second memory command associated with the second memory bank group by sequentially routing a first full data burst associated with the first memory command between the first external data bus and the first internal data bus, and subsequently routing a second full data burst associated with the second memory command between the first external data bus and the second internal data bus.13 RAMB-025WO / 11445WO0119. The base die of claim 16, wherein the channel aggregation logic is configured to perform interleaved access associated with the first memory bank group and the second memory bank group by alternately between routing data between the first external data bus and the first internal data bus, and routing data between the first external data bus and the second internal data bus.

20. A host device comprising: a host processor; a set of independent channel interfaces to respectively couple with a set of stacked memory devices over respective communication channels; at least one a memory controller to generate memory operation commands and facilitate transfer of data with the set of stacked memory devices based on instructions executed by the host processor, wherein the memory operation commands each specify an address including a pseudochannel select bit for selecting between a set of pseudochannels of a stacked memory device, and wherein the memory controller further generates a control signal to control whether the set of stacked memory devices operate in an interleaved access mode or a sequential access mode for data communicated via the selected pseudochannel.14 RAMB-025WO / 11445WO01

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