Semiconductor Device and Method for Manufacturing a Semiconductor Device

Abstract

A semiconductor package comprising a substrate comprising an insulating layer, wherein the insulating layer comprises a first upper main surface and a second lower main surface opposite the first upper main surface; a conductor frame comprising a first upper main surface and a second lower main surface opposite the first main surface; a semiconductor transistor chip arranged on the first main surface of the conductor frame; a connecting layer coupling the second lower main surface of the conductor frame to the first upper main surface of the ceramic insulating layer, the connecting layer having a melting point wholly or partly above 260 °C; and an encapsulation covering an inner section of the conductor frame, the semiconductor transistor chip and the ceramic insulating layer, the connecting layer having a thickness in the range of 40 µm to 200 µm, in particular 100 µm to 200 µm, in particular 50 µm to 150 µm, or the connecting layer having a thickness in the range of 1 µm to 50 µm, in particular 10 µm to 30 µm.

Description

BACKGROUND

[0001] Semiconductor devices, particularly power semiconductor devices, may be required to meet stringent electrical performance requirements. For example, such semiconductor devices may be needed to carry high electrical currents, operate at high voltages, or have low RDS(on) values. (on) etc. These requirements also apply to connections that electrically couple different parts of a semiconductor device. Soldered connections, in particular, often do not necessarily meet these requirements in every application. Furthermore, another major problem is the efficient dissipation of excess heat generated by the semiconductor power transistor, to which the electrical interconnect layers must also make a significant contribution.

[0002] Improved semiconductor devices and improved methods for manufacturing semiconductor devices can help solve these and other problems. Further background information can be found in DE 10 2010 044 709 A1, US 2011 / 0074010 A1, US 5767573 and US 2008 / 0230905 A1.

[0003] For these and other reasons, there is a need for the present disclosure. SUMMARY

[0004] A first aspect of the present disclosure relates to a semiconductor package comprising a substrate comprising an insulating layer, wherein the insulating layer comprises a first upper main surface and a second lower main surface opposite the first upper main surface, a conductor frame comprising a first upper main surface and a second lower main surface opposite the first main surface, a semiconductor transistor chip arranged on the first main surface of the conductor frame, a connecting layer coupling the second lower main surface of the conductor frame to the first upper main surface of the ceramic insulating layer, wherein the connecting layer has a melting point, in whole or in part, of more than 260 °C, and an encapsulation covering an inner section of the conductor frame, the semiconductor transistor chip, and the ceramic insulating layer;wherein the compound layer comprises a thickness in the range of 40 µm to 200 µm, in particular from 100 µm to 200 µm, in particular from 50 µm to 150 µm; or wherein the compound layer comprises a thickness in the range of 1 µm to 50 µm, in particular from 10 µm to 30 µm.

[0005] The high melting point of the bonding layer (BLT) exceeding 260 °C, as described in the first aspect, allows the customer to utilize a heat sink with high temperatures, still below 260 °C. Generally, the bonding layer can be a bond line thickness (BLT) ranging from more than 20 µm to 200 µm. Specifically, the BLT can be in the range of more than 40 µm to 200 µm. In this range and its subranges, tin-based soldering systems incorporating high-melting-point core materials are used. However, BLTs in the range of 1 µm to 50 µm are also possible. Within this range, a subrange of 10 µm to 30 µm has proven advantageous.

[0006] A second aspect of the present disclosure relates to a method for manufacturing a semiconductor package, wherein the method comprises: providing a substrate comprising an insulating layer, the insulating layer comprising a first upper main surface and a second lower main surface opposite the first upper main surface; providing a conductor frame comprising a first upper main surface and a second lower main surface opposite the first main surface; arranging a semiconductor transistor chip on the first main surface of the conductor frame; depositing an interconnect layer on one or both of the second lower main surfaces of the conductor frame or the first upper main surface of the insulating layer, wherein the interconnect layer is formed by diffusion soldering or diffusion sintering from at least one starting material having at least one first transition temperature.wherein, after formation, the interconnect layer has a second transition temperature which is higher than the first transition temperature, connecting the conductor frame to the substrate by carrying out a melting and subsequent remelting process and applying an encapsulation which covers an inner section of the conductor frame, the semiconductor transistor chip and the insulating layer, wherein the interconnect layer has a thickness in the range of 40 µm to 200 µm, in particular from 100 µm to 200 µm, in particular from 50 µm to 150 µm; or wherein the interconnect layer has a thickness in the range of 1 µm to 50 µm, in particular from 10 µm to 30 µm.

[0007] According to one embodiment of the semiconductor package of the first aspect, the interconnect layer comprises one or more materials from the group consisting of a lead-free material, an SnSb material, a NiSn material, an Sn material, a Cu material, an Ag material, an Ag adhesive material, or a hybrid sintering paste. Soldering systems based on SnSb materials have proven advantageous, but systems based on Cu materials, i.e., Cu alloys, can also be used.

[0008] In particular, the interconnect layer of the semiconductor package of the first aspect may comprise a diffusion-active layer system or a diffusion-active particle system, wherein the diffusion-active layer system and / or the diffusion-active particle system comprises sintered particles, metals, or intermetallic compounds. In the context of this disclosure, the term "diffusion-active layer systems" may refer to Sn-Cu-Sn layer systems, but also to solder paste systems with high melting points.

[0009] The bonding layer can, in particular, comprise a sintering paste, a sintering layer, or a sintering foil.

[0010] According to the second aspect method, the second transition temperature can be higher than 260 °C.

[0011] According to one embodiment of the semiconductor package of the first aspect, the Pb-free material of the compound layer, as one of the embodiments described above, does not exclude the possibility that trace elements of lead may be present, which may inevitably occur in the manufacturing process.

[0012] According to one embodiment of the semiconductor package of the first aspect, the interconnect layer is based on or comprises a metal. With regard to the method according to the second aspect, the at least one starting metal used to produce the interconnect layer could comprise a metal.

[0013] According to one embodiment of the semiconductor package of the first aspect, the interconnect layer comprises a thickness in the range of 40 µm to 200 µm, in particular from 100 µm to 200 µm, and in particular from 50 µm to 150 µm.

[0014] According to one embodiment of the semiconductor package of the first aspect, the interconnect layer comprises a material with a thermal conductivity of more than 15 W / mK.

[0015] According to one embodiment of the semiconductor package of the first aspect, the interconnect layer comprises a material from one or more of the group consisting of a Pb-free material, a CuSn material, a Transition liquid phase soldering material, an SnSb material, a NiSn material, an Sn material, an Ag material, an Ag adhesive material, a Cu material, a Cu adhesive material or a hybrid sintering paste.

[0016] According to one embodiment of the semiconductor package of the first aspect, the ceramic insulating layer is a central layer of the substrate, wherein the substrate is a direct copper bond (DCB), an active metal bond (AMB), or an insulated metal substrate (IMS). Furthermore, the ceramic insulating layer can be a layer comprising sputtered ceramics or directly plated copper ceramics. In particular, the ceramic insulating layer can be a layer comprising a metallization layer, wherein the metallization layer has a thickness in the range of 1 to 50 µm.

[0017] According to one embodiment of the semiconductor package of the first aspect, the substrate comprises a central layer, a first upper metal layer, and a second lower metal layer.

[0018] According to one example, the first top metal layer comprises a thickness of less than 2000 / 1000 / 800 / 300 / 250 / 125 / 75 / 50 / 20 / 10 µm or less, and even down to 1 µm. The first top metal layer can be a sputtered seed layer or an organic seed layer. In particular, the thickness of the first top metallization layer can be in the range of 500 µm to 10 µm. Specifically, the first top metal layer can have a thickness of less than 300 µm, preferably 127 µm, 20 µm, or 10 µm. A first top metallization layer with a thickness of 300 µm may be best suited for direct copper bonding substrates, while a thickness of 127 µm may be best suited for active metal solder (AMB) substrates. A thickness of 20 µm may be suitable for a direct-plated copper substrate (DPC).

[0019] According to one embodiment of the semiconductor package of the first aspect, the substrate consists of a single insulating layer with a lower surface facing outwards. On the customer side, a heat sink could be applied directly to the lower surface of the single ceramic layer. The size of the heat sink can be large compared to the semiconductor package. Alternatively, a metal layer could be applied to both sides of the ceramic layer. On the upper side, it may be required for the interconnect layer, but not at the system level, especially for high-voltage and AMD TSC applications. Asymmetrical designs tend to flex, therefore a thinner metal layer can be applied.

[0020] According to one embodiment of the semiconductor package of the first aspect, the ceramic insulating layer comprises one or more of the materials from the group consisting of Al₂O₃, Si₃N₄, H-AlN, AlN, and diamond. Other insulating layers are also conceivable instead of a ceramic insulating layer. In particular, the insulating layer can be an insulated metal substrate (IMS) or can be made of an organic insulating material. The insulating layer can be a multilayer organic substrate comprising thermally conductive layers, such as epoxy, polyimide, or silicone, which can be filled with ceramic particles, such as Al₂O₃, AlN, BN, diamond, etc.

[0021] The semiconductor transistor chip can be a wide bandgap semiconductor transistor chip, in particular a GaN, a SiC or a gallium oxide Ga2O3 transistor chip.

[0022] Furthermore, the semiconductor transistor chip can be configured as a power semiconductor transistor chip. A power transistor is a switching device rated to accept voltages of at least 20 V (volts) and more commonly on the order of 100 V, 600 V, 1200 V, 2 kV, 3.3 kV or higher, and / or rated to accept currents of at least 1 A (ampere) and more commonly on the order of 10 A, 50 A, 100 A, 500 A, 1000 A or even higher. The power transistor chip can be part of a multi-chip configuration and / or a multi-chip pad configuration.

[0023] The joining technologies described in this disclosure include soldering, including remelt and vapor phase soldering, sintering, in particular Ag and Cu sintering, as well as pressure and pressureless sintering. Furthermore, additional thermal interface materials could be used, such as phase change materials, thermal grease materials, gap pads, gap fillers, thermally conductive adhesives, and graphite pads.

[0024] The present disclosure provides an optimal solution for both electrically isolating and efficiently dissipating the excessive heat generated by the semiconductor power transistor chip when the semiconductor device is in operation.

[0025] One embodiment of connecting the conductor frame to the substrate according to the method of the second aspect includes a soldering process, in particular a diffusion soldering process.

[0026] Furthermore, one embodiment of the second aspect of the method consists in using either diffusion brazing or sintering in the manufacturing process of the compound layer, i.e. producing a material which, through sintering or intermetallic compounding, has a melting point higher than that of the starting material.

[0027] Further embodiments can be formed according to embodiments of the semiconductor package of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated into and form part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of these embodiments. Other embodiments and many of the intended advantages of embodiments are immediately appreciated, as they are better understood with reference to the detailed description that follows.

[0029] The elements in the drawings are not necessarily to scale relative to each other. Identical reference symbols denote corresponding similar parts. Fig. Figure 1 shows a cross-sectional view of a semiconductor package that includes a direct copper connection as a substrate. Fig. Figure 2 shows a cross-sectional view of a semiconductor package comprising a substrate and a single insulating ceramic layer on the underside of the device. Fig. 3 includes Fig. 3A and Fig. 3B and shows cross-sectional views of semiconductor devices exhibiting different effects of warping. Fig. 4 includes Fig. 4A and Fig. 4B and shows cross-sectional views of semiconductor devices that include additional copper blocks within the interconnect layer. Fig. Figure 5 shows a cross-sectional view of a semiconductor device for focusing on the chip mounting layer. Fig. Figure 6 shows a flowchart of an embodiment of the method according to the second aspect. DETAILED DESCRIPTION

[0030] In the following detailed description, directional terminology, such as "above," "below," "left," "right," "top," "bottom," etc., is used with reference to the orientation of the described figure(s). Since components of the revelation may be positioned in a number of different orientations, the directional terminology is used for illustrative purposes only.

[0031] Although a particular feature or aspect of an example may be disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desirable and advantageous for a given or particular application, unless expressly stated otherwise or technically restricted. Furthermore, to the extent that the terms "comprise," "include," "with," or other variants thereof are used either in the detailed description or the claims, such terms shall be understood to mean inclusive in a manner similar to the term "comprise." The terms "coupled" and "connected" may be used together with derivatives thereof.It is understood that these terms can be used to indicate that two elements, regardless of whether they are in direct physical or electrical contact or not, work together or interact; intermediary elements or layers may be provided between the "bonded," "attached," or "connected" elements. However, it is also possible for the "bonded," "attached," or "connected" elements to be in direct contact with each other. Furthermore, the term "exemplary" is meant merely as an example and not as the best or optimal solution.

[0032] The semiconductor devices described below can comprise one or more semiconductor dies. For example, they can contain one or more power semiconductor dies. Furthermore, one or more integrated logic circuits can be included in the semiconductor devices. The integrated logic circuits can be configured to control the integrated circuits of other semiconductor dies, such as the integrated circuits of power semiconductor dies. The integrated logic circuits can be implemented within logic dies.

[0033] The semiconductor dies can have contact pads that allow electrical contact with the integrated circuits contained within them. These pads can comprise one or more metal layers deposited onto the semiconductor material. The metal layers can be manufactured with any desired geometric shape and material composition. For example, they can be made of, or comprised of, a material selected from the group consisting of Cu, Ni, NiSn, Au, Ag, Pt, Pd, W, or an alloy of one or more of these metals.W (tungsten) could be used particularly in the so-called LTTC process (Low Temperature Cofired Ceramics) by applying temperatures around 500 °C and also in an HTTC (High Temperature Cofired Ceramics) by applying temperatures around 1000 °C together with “cofired ceramic” substrates and multilayer ceramic substrates.

[0034] Fig. Figure 1 shows a cross-sectional view of a semiconductor package that includes a direct copper connection as a substrate.

[0035] In particular, the semiconductor package comprises 10, as shown in Fig. Figure 1 shows a substrate 11, which may comprise a DCB, AMB, or IMS, and in each case an insulating layer 11A, which may be an organic insulating layer or an inorganic insulating layer, in particular a ceramic insulating layer, and may even be a multilayer insulation. The insulating layer 11A comprises a first upper main surface and a second lower main surface opposite the first upper main surface.The package 10 further comprises a conductor frame 12, which includes a first upper main surface and a second lower main surface opposite the first main surface, a semiconductor transistor chip 13, which is arranged on the first main surface of the conductor frame 12, a connecting layer 14, which couples the second lower main surface of the conductor frame 12 to the first upper main surface of the ceramic insulating layer 11A, wherein the connecting layer 14 has a melting point wholly or partly of more than 260 °C, and an encapsulation 15, which covers an inner section of the conductor frame 12, the semiconductor transistor chip 13 and the ceramic insulating layer 11 of the substrate 11.

[0036] It should be noted that instead of a direct copper bond (DCB), an active metal bond (AMB) or an insulated metal substrate (IMS) and also the aforementioned “cofired ceramic” LTTC or HTTC substrates could be used.

[0037] Fig. Figure 2 shows a cross-sectional view of a semiconductor package comprising a substrate and a single insulating layer on the underside of the device.

[0038] In particular, it shows Fig. 2 a semiconductor package 20 comprising a substrate 21 comprising a single insulating layer 21, wherein the insulating layer 21 comprises a first upper main surface and a second lower main surface opposite the first upper main surface, a conductor frame 22 comprising a first upper main surface and a second lower main surface opposite the first main surface, a semiconductor transistor chip 23 arranged on the first main surface of the conductor frame 22, a connecting layer 24 coupling the second lower main surface of the conductor frame 22 to the first upper main surface of the insulating layer 21, wherein the connecting layer 24 has a melting point, in whole or in part, of more than 260 °C, and an encapsulation 25 covering an inner section of the conductor frame 22, the semiconductor transistor chip 23 and the insulating layer 21.

[0039] It should be noted that the present disclosure can be applied to various types of packages. One of them is in the Fig. 1 and Fig. Figure 2 shows a TO247 package. However, other package types are also conceivable. For example, surface-mount devices with top-side cooling (SMD TSC) or packages comprising a surface-mount device with bottom-side cooling (SMD BSC) are possible, with the device potentially soldered onto a heat sink. Additionally, power modules are conceivable, either single-sided or double-sided. Further so-called intelligent power modules, which include a driver chip, can also be considered, either single-sided or double-sided.

[0040] Fig. 3 includes Fig. 3A and Fig. 3B and shows cross-sectional views of semiconductor devices exhibiting different effects of warping.

[0041] Different results of the process can be observed depending on different material parameters.

[0042] The curvature of the conductor frame plus semiconductor chip is determined in this case by the "chip" itself or by the different coefficients of thermal expansion (CTE) of the various materials (SiC, Cu). At room temperature, a "sad area" should always be present, as shown in Fig. As shown in 3A, Cu has a higher CTE than SiC. At higher soldering temperatures (~300 °C), it becomes almost planar and can even orient itself towards the "smiling face", as shown in Fig. As shown in Figure 3B, the insulator can tip over. Additionally, the insulator can also warp due to the design and manufacturing process. The interposer can also warp, so both directions are possible as a result.

[0043] Fig. 4 includes Fig. 4A and Fig. 4B and shows cross-sectional views of semiconductor devices that include additional copper blocks within the interconnect layer.

[0044] In particular, it shows Fig. 4A a semiconductor package 30, which in conjunction with Fig. 1 and Fig. It is similar to the two semiconductor packages shown and described. The only difference is the specific configuration of the junction layer 34.

[0045] In this case, the compound layer 34 comprises additional copper blocks 34A. These copper blocks 34A are integrated into the compound layer 34. These copper blocks 34A are a special type of solder material into which, in addition to the actual SnSb preform, so-called high-melting-point copper metal cores are incorporated to facilitate diffusion soldering and the complete formation of the intermetallic phases in the tin. Only a few copper blocks are shown in the cross-sectional view, but in reality, many more may be present. This concept can be implemented using foils, spheres, and wires.

[0046] In particular, it shows Fig. 4B a semiconductor package 40, which is used in conjunction with Fig. The semiconductor package 30 shown and described in section 4A is similar. The only difference is the specific configuration of the interconnect layer 44. In this case, the interconnect layer 44 comprises a stack of layers of a Cu intermediate layer 44A sandwiched between Sn or SnSb layers 44B on the top and bottom of the Cu intermediate layer 44A. The layers 44B are added to the actual SnSb preform to facilitate diffusion soldering and the complete formation of the intermetallic phases in the Sn.

[0047] Fig. Figure 5 shows a cross-sectional view of a semiconductor device for focusing on the attachment layer.

[0048] In particular, this includes in Fig. 5 Semiconductor package 50 shown, a substrate 11 comprising a DCB, AMB or IMS, a ceramic insulating layer 11A, wherein the ceramic insulating layer 11A comprises a first upper main surface and a second lower main surface opposite the first upper main surface, furthermore a conductor frame 12 comprising a first upper main surface and a second lower main surface opposite the first main surface, furthermore a semiconductor transistor chip 53 arranged on the first main surface of the conductor frame 12, furthermore a connecting layer 54 coupling the second lower main surface of the conductor frame 12 to the first upper main surface of the ceramic insulating layer 11A, wherein the connecting layer 54 comprises a melting point, in whole or in part, of more than 260 °C or more than 300 °C / 400 °C / 500 °C or even more, and an encapsulation comprising an inner section of the conductor frame 12,The semiconductor package 50 covers the semiconductor transistor chip 13 and the ceramic insulating layer 11 of the substrate 11. The semiconductor package 50 can also include an encapsulating means (not shown) that covers an inner section of the conductor frame 12, the semiconductor transistor chip 53, and the ceramic insulating layer 11 of the substrate 11.

[0049] The semiconductor package 50 from Fig. 5 further comprises a chip mounting layer 55, which connects the semiconductor transistor chip 53 to the upper surface of the conductor frame 12.

[0050] With regard to the semiconductor chip 53 and the interconnect layer 54, the same properties can be applied as previously described in connection with the semiconductor chip 13 and the interconnect layer 14 of the semiconductor package of Fig. 1 were described.

[0051] The semiconductor chip mounting layer 55 connects the semiconductor transistor chip 53 to the first main surface of the conductor frame 12 and can be produced by a diffusion soldering process.

[0052] Furthermore, the semiconductor chip mounting layer 55 can have a thickness that is thinner than the interconnect layer 54, particularly in a range of 1 µm to 100 µm.

[0053] Furthermore, the semiconductor chip mounting layer 55 can have a melting point of more than 260 °C in whole or in part and can in particular include one or more diffusion or sintering compound layers.

[0054] Fig. Figure 6 shows a flowchart of an embodiment of the method according to the second aspect.

[0055] In particular, the method 100 for manufacturing a semiconductor package comprises providing a substrate comprising an insulating layer, wherein the insulating layer comprises a first upper main surface and a second lower main surface opposite the first upper main surface (110), providing a conductor frame comprising a first upper main surface and a second lower main surface opposite the first main surface (120), arranging a semiconductor transistor chip on the first main surface of the conductor frame (130), and depositing an interconnect layer on one or both of the second lower main surfaces of the conductor frame or the first upper main surface of the insulating layer, wherein the interconnect layer is formed by diffusion soldering or diffusion sintering from at least one starting material having at least one first transition temperature, wherein, after formation, the interconnect layer has a second transition temperature.which is higher than the first transition temperature (140), joining the conductor frame to the substrate by performing a melting and subsequent remelting process (150) and applying an encapsulation that covers an inner section of the conductor frame, the semiconductor transistor chip and the insulating layer (160).

[0056] Although the disclosure has been illustrated and described with respect to one or more implementations, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the components or structures (assemblies, devices, circuits, systems, etc.) described above, the terms (including any reference to a "means") used to describe such components, unless otherwise specified, shall correspond to any component or structure that performs the specified function of the described component (e.g., that is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary implementations of the disclosure illustrated herein. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] DE 10 2010 044 709 A1

[0002] US 2011 / 0074010 A1

[0002] US 5,767,573

[0002] US 2008 / 0230905 A1

[0002]

Claims

[1] Semiconductor package (10; 20), comprising: a substrate (11; 21) comprising an insulating layer (11A; 21), wherein the insulating layer (11A; 21) comprises a first upper main surface and a second lower main surface opposite the first upper main surface; a ladder frame (12; 22) comprising a first upper main surface and a second lower main surface opposite the first main surface; a semiconductor transistor chip (13; 23) arranged on the first upper main surface of the conductor frame (12; 22); a bonding layer (14; 24) that couples the second lower main face of the conductor frame (12; 22) to the first upper main face of the insulating layer (11A; 21), wherein the bonding layer (14; 24) comprises a melting point wholly or partly of more than 260 °C; and an encapsulation (15; 25) covering an inner section of the conductor frame (12; 22), the semiconductor transistor chip (13; 23) and the insulating layer (11A; 21); wherein the compound layer (14; 24) comprises a thickness in the range of 40 µm to 200 µm, in particular from 100 µm to 200 µm, in particular from 50 µm to 150 µm; or wherein the compound layer (14; 24) comprises a thickness in the range of 1 µm to 50 µm, in particular from 10 µm to 30 µm. [2] Semiconductor package (10; 20) according to claim 1, wherein the insulating layer (11A) comprises a ceramic insulating layer. [3] Semiconductor package (10; 20) according to claim 1 or 2, wherein the interconnect layer (14; 24) is based on a metal. [4] Semiconductor package (10; 20) according to one of the preceding claims, wherein the interconnect layer (14; 24) comprises a material having a thermal conductivity of more than 15 W / mK. [5] Semiconductor package (10) according to one of the preceding claims, wherein the interconnect layer (14; 24) comprises a material of one or more from the group consisting of a Pb-free material, an SnSb material, a NiSn material, a CuSn material, a transition liquid phase soldering material, an Sn material, an Ag material, an Ag adhesive material or a hybrid sintering paste, in particular a Cu-based sintering paste. [6] Semiconductor package (10) according to any of the preceding claims, wherein the insulating layer (11A) is a central layer of the substrate (11), wherein the substrate (11) is a direct copper bond (DCB), an active metal solder (AMB) or an insulated metal substrate (IMS). [7] Semiconductor package (10) according to claim 6, wherein the substrate (11) comprises a central insulating layer (11A), a first upper metal layer (11B) and a second lower metal layer (11C). [8] Semiconductor package (10) according to claim 6, wherein the first upper metal layer (11B) comprises a thickness of less than 500 / 300 / 250 / 125 / 75 / 50 / 20 / 10 µm or less and even down to 1 µm, in particular the first upper metal layer may have a thickness of less than 300 µm, preferably 127 µm, 20 µm or 10 µm. [9] Semiconductor package (20) according to one of the preceding claims, wherein the substrate (21) consists of a single ceramic insulating layer (21) with a lower surface facing outwards. [10] Semiconductor package (10; 20) according to one of the preceding claims, wherein the insulating layer (11A; 21) comprises one or more of the materials from the group consisting of Al2O3, Si3N4, H-AlN and AlN. [11] Semiconductor package (50) according to one of the preceding claims, further comprising a semiconductor chip mounting layer (55) connecting the semiconductor transistor chip (53) to the first main surface of the conductor frame (12). [12] Semiconductor package (50) according to claim 11, wherein the thickness of the semiconductor chip mounting layer (55) is thinner than the thickness of the interconnect layer (54). [13] Semiconductor package (50) according to claim 11 or 12, wherein the semiconductor chip mounting layer (55) is in a range of 1 µm to 100 µm. [14] Semiconductor package (50) according to any one of claims 11 to 13, wherein the semiconductor chip mounting layer (55) comprises a melting point wholly or partly of more than 260 °C. [15] Semiconductor package (50) according to any one of claims 11 to 14, wherein the semiconductor chip mounting layer (55) is produced by a diffusion soldering process. [16] Method (100) for manufacturing a semiconductor package (10; 20), the method comprising: Providing a substrate (11; 21) comprising an insulating layer (11A; 21), wherein the insulating layer (11A; 21) comprises a first upper main surface and a second lower main surface opposite the first upper main surface (110); Providing a ladder frame (12; 22) comprising a first upper main surface and a second lower main surface opposite the first main surface (120); Arranging a semiconductor transistor chip (13; 23) on the first upper main surface of the conductor frame (12; 22) (130); Applying a compound layer (14; 24) to one or both of the second lower main faces of the conductor frame (12; 22) or the first upper main face of the insulating layer (11A; 21), wherein the compound layer (14; 24) is formed by diffusion soldering or diffusion sintering from at least one starting material having at least one first transition temperature, wherein after formation the compound layer has a second transition temperature which is higher than the first transition temperature (140); joining the conductor frame (12; 22) to the substrate (11; 21) by carrying out a melting and subsequent remelting process (150); and Applying an encapsulation (15; 25) that covers an inner section of the conductor frame (12; 22), the semiconductor transistor chip (13; 23) and the insulating layer (11A; 21) (160); wherein the compound layer (14; 24) comprises a thickness in the range of 40 µm to 200 µm, in particular from 100 µm to 200 µm, in particular from 50 µm to 150 µm; or wherein the compound layer (14; 24) comprises a thickness in the range of 1 µm to 50 µm, in particular from 10 µm to 30 µm.

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