High electron mobility transistors with heterojunction dopant diffusion barrier

Abstract

Transistor, comprehensive: an active region arranged in a III-V semiconductor fin; and a lower fin arranged between the fin and a substrate (305), the lower fin further comprising: a first sub-fin layer (307) of III-V semiconductor material arranged over the substrate (305); a second subfin layer (310) of III-V semiconductor material arranged above the first subfin layer (307); and a third subfin layer (309) of III-V semiconductor material, arranged between the first and second subfin layer (309) and closer to the substrate (305) than to the fin (320), wherein the third layer consists of a III-V alloy composition associated with a wider band gap than that of the first and second subfin layer (309).

Description

BACKGROUND OF THE INVENTION

[0001] The demand for integrated circuits (ICs) for portable electronic applications has driven the increased integration of semiconductor devices. Many advanced semiconductor devices currently under development utilize silicon-free semiconductor materials such as composite semiconductor materials (e.g., GaAs, InP, InGaAs, InAs, and III-N materials). These silicon-free material systems can be used in high-electron mobility transistors (HEMTs), some of which can be metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0002] One method for fabricating high-electron-mobility transistors involves forming a silicon-free crystalline component region (e.g., a transistor channel region) over a crystalline silicon substrate. However, a problem arises because silicon atoms from the underlying substrate can act as impurities in silicon-free component regions. Therefore, methods and structures to mitigate the problem of silicon contamination are advantageous in the fabrication of HEMTs on silicon substrates.

[0003] US 2015 / 0255545A1 discloses a method for manufacturing a semiconductor device comprising the formation of an AlInAsSb barrier material over a substrate and the formation of a transistor channel material over the barrier layer.

[0004] US 2014 / 0329376A1 discloses a method for fabricating a component structure with elements of Group III-V on a substrate. <111> A surface can be formed on a substrate, and a group III-V material can be derived from the <111> The surface is grown to form a group III-V device structure in a trench insulated between a dielectric layer. A critical final dimension of the device structure can be trimmed to obtain a node structure of suitable size. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The material described in this patent application is shown in the accompanying figures by way of example, but not as a limitation. For the sake of simplicity and clarity, the elements illustrated in the figures are not necessarily shown to scale. For example, the dimensions of some elements may be exaggerated in relation to other elements for clarity. Furthermore, where appropriate, reference numerals have been used repeatedly in the various figures to identify corresponding or analogous elements. The following applies to the illustrations: Fig. Figure 1 is an atom probe tomogram illustrating the effect of inserting a heterojunction into a III-V material stack according to some embodiments on the silicon impurity in the stack; Fig. Figure 2 is a flowchart illustrating a method for forming a III-V transistor with a heterojunction-based underfin dopant diffusion barrier according to some embodiments; Fig. 3A, Fig. 3B, Fig. 3C, Fig. 3D and Fig. Figure 3E are isometric views illustrating a pair of fin structures according to some embodiments that arise when the in Fig. The two operations shown are performed; Fig. Figure 4A shows a cross-sectional view through the length of a channel region and source / drain regions of a high-mobility finFET according to some embodiments, in which the Fig. The III-V structure shown in 3E is applied; Fig. 4B shows a cross-sectional view through the width of a channel region and a gate electrode of the in Fig. 4A High-mobility finFETs shown according to some embodiments; Fig. Figure 5 illustrates a mobile computing platform and a data server machine in which a system-on-a-chip (SoC) with a transistor with localized subfin insulation according to embodiments of the present invention is used; and Fig. Figure 6 is a functional block diagram of an electronic computing device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0006] One or more embodiments are described with reference to the accompanying figures. Although specific configurations and arrangements are presented and discussed in detail, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements are possible without deviating from the essence and scope of protection of the description. It is obvious to those skilled in the art that the methods and / or arrangements described in this patent specification can be used in a multitude of other systems or applications than those described in detail here.

[0007] The following detailed description refers to the accompanying drawings, which form part of the description and illustrate exemplary embodiments. Furthermore, it should be assumed that other embodiments can be used and structural and / or logical modifications can be made without deviating from the scope of protection of the claimed invention. It should also be noted that directional terms and references such as "upwards," "downwards," "above," "below," etc., are used solely to facilitate the description of features in the drawings. The following detailed description is therefore not to be interpreted in a restrictive sense, and the scope of protection of the claimed invention is defined exclusively by the accompanying claims and their equivalents.

[0008] The following description contains a number of details. However, it will be clear to a person skilled in the art that the present invention can be carried out without these specific details. In some cases, known methods and devices are not presented in detail but in the form of block diagrams in order to illustrate the present invention as clearly as possible. The reference in the patent specification to "one embodiment," "a single embodiment," or "some embodiments" means that a particular feature, function, or characteristic described in connection with the embodiment occurs in at least one embodiment of the invention. The expression "in one embodiment," "in a single embodiment," or "in some embodiments" at various points in the patent specification therefore does not necessarily always refer to the same embodiment.Furthermore, the specified features, structures, functions, or properties can be combined in any suitable way in one or more embodiments. For example, a first embodiment can always be combined with a second embodiment if the specified features, structures, functions, or properties of the two embodiments are not mutually exclusive.

[0009] The use of the singular forms "ein / einer / eines", "einen / eine / eines", and "der / die / das" in the description and in the attached patent claims is intended to include the plural forms as well, unless the context clearly indicates otherwise. It is also understood that the expression "and / or" as used here refers to and includes any possible combination of one or more of the corresponding listed items.

[0010] The terms "coupled" and "connected," as well as derivatives thereof, may be used in this patent specification to describe functional or structural relationships between components. It should be noted that these terms are not intended to be synonymous. Rather, in certain embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with one another. "Coupled" may be used to indicate that two or more elements are in direct or indirect (with other intermediate elements in between) physical or electrical contact with one another, and / or that the two or more elements work together or interact with one another (such as in a functional relationship).

[0011] The terms "above," "below," "between," and "on," as used here, refer to the relative position of a component or material with respect to other components or materials, insofar as such physical relationships are significant. For example, in the context of materials, a (specific) material positioned above or below another may be in direct contact with it or may have one or more intermediate materials. Furthermore, a material positioned "between" (two) materials may be in direct contact with both layers or may have one or more intermediate layers. In contrast, a (first) material is located "on top" of a (second) material and is in direct contact with the (second) material. Similar distinctions apply in the context of arrangements of components.

[0012] As used in the present description and in the claims, a list of items joined by the expressions "at least one" or "one or more" can mean any combination of the listed items. For example, the phrase "at least one of A, B or C" means (A); (B); (C); (A and B); (A and C); (B and C) or (A, B and C).

[0013] Exemplary embodiments of heteroepitaxial structures are described here, including a raised crystalline III-V structure extending over a crystalline silicon substrate. Using heteroepitaxial growth methods to form the III-V structures, silicon-free devices (e.g., III-V channel field-effect transistors) can be formed in raised structures extending over a first region of a silicon substrate. Silicon devices (e.g., silicon channel field-effect transistors) can be formed in other regions of the silicon substrate.

[0014] Particularly in III-V devices on silicon substrates, thermal transitions associated with various semiconductor manufacturing processes tend to drive silicon atoms from the underlying substrate into the silicon-free region of the device. Silicon atoms are an amphoteric dopant in most III-V materials and often preferentially dope them in an n-type manner. Under certain circumstances, such unintentional doping of III-V material via solid-state diffusion can be acceptable or even advantageous. For example, the presence of an n-doped III-V material between the active region and the substrate in a PMOS transistor can be desirable, as it improves the electrical insulation of the active region.However, in a III-V NMOS transistor, an unintentionally n-doped sublayer due to silicon impurities could create an electrical path between source and drain, leading to a very high reverse current I. off This leads to the problem that, as the critical dimensions of transistors become ever smaller, even a slight unintentional n-doping of III-V material next to the active area (e.g., the channel and / or source / drain area) can drastically impair the performance of NMOS devices.

[0015] Even though counter-doping a III-V material between an active device region and the silicon substrate with acceptor impurities that promote p-type conductivity could prevent the presence of a silicon impurity from determining the type of electrical conductivity of the III-V material (i.e., reducing the silicon impurity to a background level), such an effort poses a considerable risk of thermal diffusion of the various impurities into the channel region, ultimately reducing channel mobility. Therefore, such a counter-doping strategy can only be successful for long-channel devices.

[0016] The inventors have discovered that thermal diffusion of dopant atoms, such as silicon donors, can be halted or at least significantly delayed by introducing one or more heterojunctions in the III-V material located between an active transistor region and the substrate. In some embodiments, therefore, a portion of the III-V material distal to the active region is compositionally modulated to form a dopant diffusion barrier. In exemplary embodiments with a band offset of type I, a narrower bandgap material is arranged between a wider bandgap III-V material and the silicon dopant source (e.g., a silicon substrate).The heterojunction between the narrower and wider bandgap III-V material has been shown to act as a diffusion barrier, delaying the diffusion of silicon atoms from the substrate into essentially undoped regions of the III-V material located on one side of the wider bandgap III-V material opposite the substrate. Silicon atoms diffusing from the substrate are then present in a higher concentration in the narrower bandgap material. III-V material on one side of the heterojunction opposite the substrate has a significantly lower dopant atom concentration and can be essentially undoped (i.e., below the detection limit).In particular, with the III-V heterojunction acting as a diffusion barrier, the III-V heterojunction is advantageously located close to the substrate and ideally closer to the substrate than to the active region to confine silicon impurities to a smaller portion of the III-V material stack thickness. Instead of attempting to counteract the electrical effects of silicon diffusion proximal to an active region, a heterojunction design is employed to delay silicon diffusion at a point distal to the active region, thus keeping the remainder of the III-V material purer. The end result is a highly mobile active region and a device with a lower blocking leakage current.

[0017] In some embodiments, a silicon diffusion barrier comprises a III-V heterojunction between a first III-V material associated with a first band gap and a second III-V material associated with a second band gap. In some advantageous embodiments, the band gap difference further introduces a conduction band offset (CBO) of at least 250 meV, wherein the second III-V material has a conduction band or higher energy than the first III-V material and is physically separated from the substrate by the first III-V material. Larger offsets are also possible (e.g., 350 meV or more).

[0018] Fig. Figure 1 is an atom probe tomogram illustrating a reduction in silicon impurity by inserting a heterojunction into the stack according to the effects of some embodiments. Fig. Figure 1 illustrates the point density as the silicon concentration, with a higher point density representing a higher silicon concentration. Two III-V material stacks 101 and 102 are shown side by side with approximately matched z-heights (associated with material thicknesses), and each of these stacks undergoes the same thermal treatment. The reference III-V material stack 101 has a first III-V material layer 310 arranged over a silicon substrate 305. A second III-V material layer 320, with a different III-V alloy composition than the III-V material layer 310, forms a heterojunction 111. In the III-V material stack 101, the III-V material layer 310 has an alloy composition with a conduction band energy greater than that of the III-V material layer 320, and in some examples, a wider bandgap material is present.The III-V material layer 310 can exhibit a CBO of a few hundred meV or more compared to the III-V material layer 320. Although such an arrangement may offer certain advantages in relation to the containment of charge carriers (e.g., electrons) in an active region located in the III-V material layer 320, it is evident that a significant silicon concentration (e.g., 1–1.5 e^19 silicon atoms / cm²) is not feasible. 3 ) extends through all material layers in stack 101, with a silicon atom cluster 110 near heterojunction 111. Since silicon impurities in the III-V material layer 320 potentially decrease the carrier mobility and silicon impurities in the III-V material layer 310 potentially increase leakage currents upon electrical activation as n-donors, a transistor using a III-V material stack 101 may exhibit less than ideal properties (e.g., I off and I on ).

[0019] In comparison, an exemplary III-V material stack 102 features a heterojunction-based dopant diffusion barrier according to some embodiments. Stack 102 has a first III-V material layer 307 arranged over a silicon substrate 305. In some embodiments, the III-V material layer 307 is a first of: GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP. A second III-V material layer 309 with a different III-V alloy composition than the III-V material layer 307 forms a heterojunction 112. In some embodiments, the III-V material layer 309 is a second of: GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP. In a III-V material stack 102, the III-V material layer 309 consists of an alloy composition with a conduction band energy higher than that of the material layer 307.In some exemplary embodiments with a band offset of type I, the material layer 309 has a wider band gap than that of the III-V material layer 307. For example, an AlAs or an AlGaAs material layer 309 can be arranged on a GaAs material layer 307. In another example, the InP material layer 309 is arranged on an InGaAs material layer 307. In exemplary embodiments, the III-V material layer 309 consists of an alloy with a CBO of the III-V material layer 307 of at least 250 meV and advantageously 350 meV or more. Relative to the substrate 305, the heterojunction 112 is therefore inverted compared to the heterojunction 111. In particular, the silicon concentration at heterojunction 112 decreases abruptly. For example, if the concentration of silicon impurities in the III-V material layer 307 is around 19 silicon atoms / cm. 3This involves reducing the concentration of silicon impurities to a low value of e18 silicon atoms / cm². 3 in the III-V material layer 309.

[0020] With proper selection of the III-V material layer 307, the desired conduction band offset can be provided in combination with other heterojunctions. For example, the material stack 102 further comprises a third III-V material layer 310 with a different III-V alloy composition than that of the III-V material layer 309. In some embodiments, the III-V material layer 310 is one of: GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP. In some advantageous embodiments, the III-V material layer 310 consists of an alloy composition with a lower conduction band energy than that of the III-V material layer 309 and may furthermore have a narrower band gap than that of the III-V material layer 309. For example, an AlGaAs or GaAs material layer 310 may be arranged on an AlAs material layer 309, or an InGaAs material layer 310 may be arranged on an InP material layer 309.In the exemplary embodiment, the III-V material layer 310 has a CBO of a few hundred meV or more compared to that of the III-V material layer 309. In some embodiments, the III-V material layer 310 has the same III-V alloy composition as the III-V material layer 307. For example, a GaAs material layer 310 is arranged on top of an AlAs material layer 309, which is arranged on top of a GaAs material layer 307, and an AlGaAs material layer 310 is arranged on top of an AlAs material layer 309, which is further arranged on top of an AlGaAs material layer 307. As another example, an InGaAs material layer 310 can be arranged on top of an InP material layer 309, which is further arranged on top of an InGaAs material layer 307.

[0021] A fourth III-V material layer 320, with a different III-V alloy composition than the III-V material layer 310, forms a heterojunction 111. In some embodiments, the III-V material layer 320 is one of: GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP. In exemplary embodiments, the III-V material layer 320 consists of a material with high charge carrier mobility and with a CBO relative to the III-V material layer 310 that prevents charge carriers from migrating towards the substrate. In some embodiments, the III-V material layer 320 consists of an alloy composition with a lower conduction band energy than that of the III-V material layer 310. Furthermore, the III-V material layer may have a narrower band gap than that of the III-V material layer 310. For example, an InGaAs fin (e.g., In0.53Ga0.47As) is well suited for an InP / InGaAs lower fin and can also be suitable for a GaAs / AlAs lower fin, etc. Thus, the III-V material stack 102 can have a III-V material stack 101 arranged above the additional heterojunctions 112 and 113 inserted below material stack 101. For embodiments in which the III-V material layer 310 has the same III-V alloy composition as the III-V material layer 307, the III-V material stack 102 can be described as a material stack that encloses the III-V material stack 101 with a wide band gap material 309 inserted into the III-V material layer 310.

[0022] As in Fig. As shown in Figure 1, the silicon contamination of the III-V material layers 310 and 320 is below the detection limit of the APT measurement method (e.g., less than 1 e18 silicon atoms / cm²). 3In particular, even at the heterojunction 111, in connection with the silicon accumulation 110 in the material stack 101, there is a silicon atom concentration in the material stack 102 which is below 1e18 atoms / cm². 3 remains.

[0023] Fig. Figure 1 illustrates the effectiveness of bandgap construction of silicon diffusion barriers. The method or methodology can further be combined with other techniques, for example, to support the diffusion barrier and / or to reduce the overall thickness of a III-V material stack required to implement a suitable barrier. While not bound to any specific theory, it is currently assumed that silicon donor atoms can diffuse through III-V semiconductor material via negatively charged defects, the amount of which can be reduced by counter-doping with acceptor impurities (e.g., C, Zn, Be, or Mg). In some embodiments, therefore, only a base portion of the III-V material, located far from the active region, is counter-doped.This counter-doped region acts as an additional diffusion barrier, further delaying the diffusion of silicon from the substrate into essentially undoped regions of the III-V material near the active region. In some embodiments, a first III-V material layer is associated with the heterojunction diffusion barrier (e.g., the III-V material layer 307 in ). Fig. 1) counter-doped up to an impurity concentration above 1e18 atoms / cm³ 3 and advantageously at least 5e18 atoms / cm² 3 In some exemplary NMOS finFET implementations, the counter-doping is no more than 1e19 atoms / cm². 3These counter-doping levels should prevent a degradation of short-channel transistor performance if the counter-doping species thermally diffuses from the diffusion barrier into an active (channel) region. Therefore, either the counter-doped III-V material thickness is increased or the position of the barrier relative to the channel is increased to accommodate device scaling, etc.

[0024] The thicknesses of III-V material layers for implementing a heterojunction-based diffusion barrier can vary. In advantageous embodiments, the heterojunction for implementing the diffusion barrier (e.g., heterojunction 112 in Fig. 1) closer to the source of the dopant contamination (e.g., silicon substrate) than the barrier at the active region. At such a position, the diffusion barrier can retain a large portion of the III-V material stack at lower dopant contamination levels, which promotes high carrier mobility and low leakage.

[0025] The embodiments described above are applicable to a wide range of electronic devices and integrated circuits implemented in a III-V material system grown on a silicon substrate. Similar strategies can also be applied to other material systems grown heteroepitactically on a silicon substrate (e.g., GaN-on-silicon, etc.). The principles and methodologies introduced above are further illustrated below in the context of exemplary field-effect transistor (FET) implementations using semiconductor fin structures (i.e., finFETs). However, an average person can easily and equally well apply these teachings to other transistor designs (e.g., heterojunction bipolar transistors) and other transistor geometries (e.g., planar transistors or nanowire transistors).The principles and methodologies introduced above and explained here for finFET implementations can also be applied to other microelectronic components such as, but not limited to, electro-optical components (e.g., III-V photodetectors).

[0026] Various methods and / or techniques can be used to fabricate finFETs in III-V material on a silicon substrate to incorporate a heterojunction-based silicon diffusion barrier according to one or more embodiments. Fig. Figure 2 is a flowchart illustrating an exemplary method for forming a III-V transistor with an underfin silicon diffusion barrier according to some embodiments. Fig. 3A, Fig. 3B, Fig. 3C, Fig. 3D and Fig. Figure 3E are isometric views which, according to some embodiments, illustrate a pair of fin structures that arise when the operations described in Method 201 are performed.

[0027] In some exemplary embodiments, aspect ratio trapping (ART) is performed to achieve acceptable crystal quality in the heteroepitaxial III-V fin material. The prior art method described here in the context of Method 201 is an example of additive heteroepitaxial fin fabrication, which can advantageously reduce the effects of lattice mismatch across different heterojunctions in a given III-V material stack. In alternative embodiments, a conventional subtractive method can be used, in which an epitaxial cover sheet stack is grown over a silicon substrate, and a heterojunction is introduced as a silicon diffusion barrier at a suitable point in the growth of the cover sheet stack. The cover material would then be structured into transistor structures (e.g., finFETs) using a known method.

[0028] With reference to Fig. In Operation 210, a trench is formed in a dielectric material positioned above the silicon substrate. The trench can be structured entirely by a z-thickness of the dielectric material, thereby exposing a crystalline silicon substrate surface that is prepared for the nucleation of subsequent epitaxial growth of III-V material. In the Fig. In the embodiment shown, operation 210 further involves the formation of fins on a crystalline silicon substrate. Any silicon fin structuring process can be applied to obtain multiple silicon fins 306 extending away from the silicon substrate 305. Although not shown here, in some advantageous embodiments, the silicon substrate 305 is also used in the fabrication of any known MOSFETs with silicon channels (e.g., in PMOS devices for the monolithic integration of III-V MOS transistors to enable CMOS integrated circuits). The crystallographic orientation of an essentially monocrystalline substrate 305 in exemplary embodiments is (100), (111), or (110). However, other crystallographic orientations are also possible.For example, the substrate working surface may be miscut or cut at 2–10° in the direction

[110] to facilitate the nucleation of heteroepitaxial bottom fin material 110. Other substrate configurations are also possible; examples include silicon carbide (SiC), a silicon-on-insulator (SOI) substrate, or silicon-germanium (SiGe).

[0029] As further in Fig. As illustrated in Figure 3B, a field-dielectric material 315 is deposited over silicon fins 306 and planarized with a top surface of the fins 306. The dielectric material 315 can be any dielectric material known to be suitable as a field insulation or shallow trench insulation (STI) material, for example, but not limited to, silicon dioxide. As shown in Fig. As illustrated, the silicon fins 306 are selectively etched relative to the dielectric material 315, forming a trench 390 that exposes part of the substrate 305. In some embodiments, the exposed part of the substrate 305 is recessed. In the example shown, a depression with positively beveled sidewalls is etched into the substrate 105, which can further improve the trapping of crystalline defects (e.g., displacements) in a subsequently grown crystalline subfin material. In some embodiments where the silicon substrate 305 (100) is silicon, a crystallographic wet etching process is used to remove silicon fins 306 and / or faceted substrate 305, thereby exposing (111) planes in the etched depression.The (111) planes can provide better lattice matching with the III-V material, which improves the quality of subsequently grown crystalline III-V material and reduces defects induced by opposite-phase boundaries. However, other facet geometries are also possible.

[0030] Although the dimensions of the trench 390 can vary, the aspect ratio (z-depth : y-dimension) is advantageously at least 2:1 and even more advantageously 3:1 or greater. In some embodiments, a trench 390 has a smallest lateral critical dimension (CD) between 10 and 200 nm. However, the z-thickness of the trench material and the CD can be scaled as required to maintain a practical aspect ratio for a given fin height selected for a desired transistor current-carrying width, etc.

[0031] Reference is made again to Fig. 2; Method 201 proceeds by embedding a III-V subfin with a heterojunction diffusion barrier in a field dielectric. In Operation 220, a first thickness of an essentially monocrystalline III-V semiconductor is epitaxially grown from the silicon substrate surface (or from a seed layer grown thereon) exposed at the bottom of the trench formed in Operation 210. The term "essentially" monocrystalline is used to confirm that crystalline defects may be present in any number but tend to be trapped at the sides of the trench. In some embodiments, Operation 220 involves the epitaxial growth of a first layer of III-V semiconductor material, for example, GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP.Any epitaxial growth method, for example, but not limited to, metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE), can be used in Operation 220. In exemplary embodiments, III-V material is epitaxially grown on the substrate / nucleation surface to partially fill trench 390. In Operation 220, feed gases and potentially other epitaxial process control parameters (e.g., temperature, partial pressures, etc.) are set to provide an initial III-V alloy composition. In exemplary embodiments, the initial III-V semiconductor material is a material that can be rapidly modulated into a new composition exhibiting a significantly higher band gap and / or a significantly higher CBO.In one embodiment, a binary alloy, for example, but not limited to, GaAs, InGaAs, or AlGaAs, is grown in Operation 220. Tertiary and quaternary III-V alloys can also be grown. In some further embodiments, one or more sources of C, Zn, Be, or Mg are provided to p-type dope the epitaxial III-V material in situ to a desired impurity concentration (e.g., to reduce the silicon diffusivity in the first III-V material layer grown in Operation 220). The first underfin III-V semiconductor material grown in Operation 220 can be relatively thin to advantageously place the heterojunction diffusion barrier as close as possible to the silicon source (e.g., the substrate).For example, in some exemplary embodiments, the first underfin III-V semiconductor material is grown to a thickness of no more than 100 nm and advantageously to 50 nm or less.

[0032] In Operation 230, feed gases and potentially other process control parameters (e.g., temperature, partial pressures, etc.) are modified to compositionally modulate the III-V material composition and grow a second layer of III-V material associated with a wider band gap and / or a larger CBO than that of the first III-V material layer. In some advantageous embodiments, the wider band gap is associated with a CBO offset between the first and second sub-fin layers of at least 250 meV. The CBO offset may be larger (e.g., 350 meV or more). In some advantageous embodiments, the change in the III-V alloy composition between the first and second sub-fin layers occurs abruptly, for example, over a material thickness of no more than 10 nm.If the first III-V material layer grown in Operation 220 contained a counter-doping agent, the counter-doped source is also eliminated in Operation 230 to grow a second thickness of essentially undoped (i.e., not intentionally doped) III-V material from the surface of the first underfin III-V material contained in the trench. Operations 220 and 230 can be performed continuously with an in-situ modification of the growth parameters. In some embodiments, Operation 230 involves the epitaxial growth of a second thickness of III-V semiconductor material, for example, GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP, determined as a function of the composition of the first material layer grown in Operation 220.In an exemplary embodiment, where the first III-V material layer is GaAs, InGaAs, or AlGaAs, operation 230 involves the growth of an AlGaAs or AlAs material layer. The second subfin III-V semiconductor material can be grown to a wide range of thicknesses. The thicknesses may be restricted to a certain predetermined target to achieve a desired final heterofin height. In some exemplary embodiments, the second subfin III-V semiconductor material is grown to a thickness of no more than 100 nm, and advantageously to 50 nm or less.

[0033] If the heterojunction diffusion barrier is present, the process 201 continues with operation 240, where feed gases and potentially other process control parameters (e.g., temperature, partial pressures, etc.) are modified to epitaxially grow a third III-V underfin material layer from a surface of the second III-V underfin material layer contained in the trench. Operations 230 and 240 can be performed continuously with in-situ modification of the growth parameters. In some embodiments, operation 240 involves heteroepitaxial growth of a third thickness of III-V semiconductor material, for example, GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP. In some exemplary embodiments, the same material grown in Operation 220 is also grown in Operation 240 (e.g., GaAs, GaAs, InGaAs or AlGaAs).Thus, the multiple III-V materials form a subfin structure with at least two heterojunctions. In advantageous embodiments, Operation 240 is performed without intentional doping to grow III-V material with the lowest possible impurity doping. The third subfin III-V semiconductor material can be grown to a wide range of thicknesses, since the material can be used to provide a third heterojunction with a subsequently grown III-V fin material in which an active device region is to be located. The thickness of the third subfin III-V semiconductor material can be restricted to a certain predetermined target to achieve a desired final heterofin height. In some exemplary embodiments, the third subfin III-V semiconductor material is grown to a thickness of no more than 100 nm and advantageously to 50 nm or less.

[0034] Once the bottom fin has grown, the process 201 continues with operation 250, where feed gases and potentially other process control parameters (e.g., temperature, partial pressures, etc.) are again modified to epitaxially grow a III-V fin material from a surface of the third III-V bottom fin material layer contained within the trench. This forms the active fin material from a surface of the undoped portion of the III-V bottom fin still contained within the trench. Operations 240 and 250 can be performed continuously with in-situ modification of the growth parameters. In some embodiments, operation 250 involves epitaxial growth of a fourth thickness of III-V semiconductor material, for example, GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP.In some exemplary embodiments, the III-V material grown by Operation 250 is associated with a higher vacuum electron affinity than the III-V material grown by Operation 240, resulting in a conduction band offset. In some embodiments, the III-V material grown by Operation 250 has a narrower band gap than the III-V material grown by Operation 240 (i.e., a type I band offset). For example, where GaAs, InGaAs, AlGaAs, or InP is grown by Operation 240, an InGaAs alloy (e.g., In 0.53 Ga 0.47As) grown in Operation 250. In advantageous embodiments, Operation 250 is performed without intentional doping to grow III-V material with the lowest possible impurity doping. Such a material advantageously exhibits higher carrier mobility (electron mobility) and lower leakage current (where the charge carrier blocks the CBO from the subfin III-V material). The subfin III-V semiconductor material can be grown to a wide range of thicknesses, as the material can be used to provide a fin volume in which the active device region is to be located. The thicknesses of the fin III-V semiconductor material can be restricted to a certain predetermined target to achieve a desired final heterofin height.In some exemplary embodiments, the third subfin III-V semiconductor material is grown to a thickness of no more than 60 nm and advantageously to 50 nm or less.

[0035] Fig. 3D further illustrates an exemplary structure after epitaxial fin growth operations 220-250. As shown, the III-V heterofins 391 have a first III-V subfin layer 307, which may be counterdoped or undoped, proximal to, adjacent to, or near the substrate 305. Heterofins 391 also have a substantially undoped second III-V subfin layer 309, which is arranged above the subfin layer 307. The heterojunction between the subfin layers 307 and 309 is thus intended to act as a silicon diffusion barrier, as described above, thereby maintaining a lower silicon impurity level in the third subfin III-V material layer 310 and / or the fin III-V material layer 320.

[0036] Reference is made again to Fig. 2; Procedure 201 continues with Operation 260, where the III-V fin material is planarized with the surrounding field dielectric material using one or more known techniques. The field dielectric material is then deepened to a desired level to expose sidewalls of III-V fin material. In the Fig. In the illustrated embodiment, the following applies: In the exemplary embodiment shown, the dielectric material 315 is deeply etched to expose more or less of the heterofins 391. In the illustrative embodiment, the dielectric material 315 is sufficiently deeply etched to expose at least a large part of the fin III-V material 320 and, even more advantageously, substantially over the entire fin material 320. In further embodiments, no underfin material 310 is exposed. In exemplary embodiments, the III-V heterofins 391 have a maximum z-height of the sidewall H3 of 20-80 nm. As further illustrated, the underfin, which has III-V underfin layers 307 and 310 with a narrower band gap separated by a III-V underfin layer 309 with a wider band gap, extends the maximum z-height H2 of a contact area with the substrate 305.In some exemplary embodiments, where the lateral CD of heterofins 391 is between 10 and 50 nm, the lower fin height H2 is between 200 and 250 nm. In some further embodiments, the III-V layer 307 of the lower fin has a z-thickness H1 that is no more than 10% of the lower fin height H2. In exemplary embodiments, where the lower fin height H2 is between 200 and 250 nm, the III-V layer 307 of the lower fin has a maximum z-thickness H1 of 20–50 nm. In some further embodiments, the III-V layer 309 of the lower fin has a z-thickness H4 that is no more than 50% of the lower fin height H2. In exemplary embodiments where the lower fin height H2 is between 200 and 250 nm, the III-V layer 309 of the lower fin has a maximum z-thickness H4 of 50-100 nm.

[0037] Reference is made again to Fig. 2: Procedure 201 continues with the fabrication of one FET from each heterofin. Any known finFET process can be used, including gate-first and gate-last techniques. In an exemplary gate-last embodiment, Operation 270 involves the formation of a sacrificial gate and an exchange process. Generally, a gate stack mandrel is formed over a channel region of the exposed III-V fin. Any known sacrificial gate structure and fabrication method can be employed. For example, sacrificial gate material can be formed over III-V fin material using any conventional technique. Sacrificial gate material can be formed on at least two sidewalls of fin material and on adjacent field dielectric material. A gate spacer dielectric can also be formed using any conventional technique.After the gate mandrel is formed, doped areas are formed at the source / drain ends of the III-V semiconductor fin material.

[0038] A source / drain pair can be formed by depositing a heavily doped semiconductor of any suitable composition. In some embodiments, an epitaxial process is used to form monocrystalline source / drain regions. An interlayer dielectric (ILD) can be deposited over the source / drain regions and planarized with the gate mandrel. The gate mandrel is then selectively removed relative to the surrounding dielectric material, exposing fin material. A gate stack is then formed over at least two sidewalls of the III-V fin material. Method 201 is then completed with backend metallization, which involves source / drain contact metals connecting the multiple NMOS III-V finFETs to form an IC, for example, a CMOS IC, which further comprises PMOS transistors. In some embodiments, the PMOS transistors (e.g.,finFETs) around silicon channel devices, and there are no comparable concerns related to substrate silicon doping. In some alternative embodiments, the PMOS transistors (e.g., finFETs) each comprise a III-V semiconductor channel between a p-source / drain region and arranged over a bottom fin of III-V semiconductor material that is essentially free of non-silicon impurities, since substrate silicon doping of the bottom fin will tend to make the bottom fins n-type, which tends to improve electrical insulation.

[0039] Fig. Figure 4A shows a cross-sectional view through the length of a channel region and source / drain regions of a III-V finFET 401 along the in Fig. 3E A-A' line shown according to some embodiments. Fig. Figure 4B shows a cross-sectional view through the width of a channel region and a gate electrode of the III-V finFET 401 along the line shown in Fig. The B-B' line shown in Figure 3E is shown according to some embodiments. The transistor 401 has a monocrystalline III-V heterofin 391 with a minimal lateral CD in a first dimension (e.g., x) and a longer lateral CD in a second dimension (e.g., y). An active device area with a channel region is arranged in the fin material 320.

[0040] Transistor 401 has a channel region covered by a gate stack 470 comprising a gate dielectric 472 and a gate electrode 473. The channel region is modulated by the field effect applied by an overlying gate electrode 473. While any known gate stack material can be used, in an exemplary embodiment the gate dielectric 472 is a high-k material with a volume-based relative permittivity of 9 or more (e.g., Al₂O₃, HfO₂, etc.). The gate electrode 473 can be any metal with a working function suitable for the III-V alloy of the fin material 320. The channel region is further arranged between a pair of heavily doped III-V semiconductor source / drain regions 440.The source / drain regions of the III-V semiconductor can be made of a different alloy than that of the channel and can, for example, contain at least 1e19 donor impurity atoms / cm. 3 The doped source / drain material 440 can be any material suitable for ohmic contact with the fin material 320, for example, but not limited to, InAs. In some embodiments, the source / drain material 440 is a monocrystalline material. Metallic source / drain contacts 450 are in contact with the doped source / drain material 440 and are electrically isolated from the gate stack 470 by a dielectric interlayer 480 and / or lateral spacers of the gate dielectric 472.

[0041] Transistor 401 has a bottom fin consisting of three or more III-V semiconductor materials arranged between the fin 320 and the silicon substrate 305. Following the various thermal processes associated with the fabrication of transistor 401 (including back-end metallization), the III-V material layer 307 of the bottom fin proximal to the substrate 305 and distal to the active region contains a higher concentration of silicon impurities than the III-V material layer 310 of the bottom fin proximal to the active region and distal to the substrate 305. This is at least partially due to the fact that the intermediate III-V material layer 309 of the bottom fin has a CBO (concentrated base oxide). As shown in Fig. As shown, the silicon atoms 495 diffuse thermally from the substrate 305 and enter the III-V material of the first lower fin layer 307, where they are enclosed by the presence of the III-V material layer 309 of the lower fin.

[0042] In some embodiments, after IC fabrication, the concentration of silicon impurities at a contact surface with the substrate 305 (e.g., at least 1e19 atoms / cm3) is at least an order of magnitude higher than the concentration of silicon impurities in the sub-fin layer 310 at a contact surface of the fin 320 (e.g., less than 1e18 atoms / cm3). 3 In these exemplary embodiments, the concentration of silicon impurities in the fin material 320 is below 1e18 atoms / cm³. 3Depending on the method, the concentration of silicon impurities in the fin material 320 may be undetectable (i.e., below the detection limit of the method). For example, APT may not be able to detect silicon in the fin material 320, while SIMS (Secondary Ion Mass Spectrometry) may detect silicon at a concentration of around e17 atoms / cm³. 3 or can detect less.

[0043] As noted above, the presence of a heterojunction diffusion barrier layer in the epitaxial stack of the subfin is advantageous for many device structures beyond the finFET architecture described in the context of exemplary embodiments. For example, even if the subfin can be at least partially self-consuming in a gate-all-around (nanowire) transistor, it remains important to control the thermal diffusion of silicon into the nanowire channel during processing prior to the fin's detachment from the substrate. Therefore, a heterojunction diffusion barrier can be integrated into a subfin essentially as described, but then at least partially removed during subsequent processing.

[0044] Fig. Figure 5 illustrates a mobile computing platform and a data server machine in which a SoC with a III-V transistor having a heterojunction dopant diffusion barrier is used according to embodiments of the present invention. The server machine 506 can be any commercially available server, for example, a server with any number of high-performance computing platforms arranged in a rack and networked for electronic data processing, which in the exemplary embodiment includes a packed monolithic SoC 550. The mobile computing platform 505 can be any portable device designed for electronic data display, electronic data processing, wireless electronic data transmission, and / or the like. For example, the mobile computing platform 505 can be a tablet, a smartphone, a laptop computer, etc., and can have a display screen (e.g., a smartphone).a capacitive, inductive, resistive or optical touchscreen), a chip-level or package-level integrated system 510 and a battery 515.

[0045] Whether shown in the extended view 520 as arranged in the integrated system 510 or as an independent packed chip in the server machine 506, the packed monolithic SoC 550 comprises a memory block (e.g., RAM), a processor block (e.g., a microprocessor, a multi-core microprocessor, a graphics processor, or the like) with at least one III-V channel finFET with an underfin heterojunction diffusion barrier, for example, as described elsewhere herein. The monolithic SoC 550 may further be coupled to a circuit board, substrate, or interposer 560, together with one or more power management integrated circuits (PMICs) 530, an RF integrated circuit (RFIC) 525 with a broadband RF transmitter and / or receiver (TX / RX) (e.g., a wireless RF transmitter), a wireless RF transmitter, or a wireless RF receiver (RFIC).comprising a digital baseband and an analog front-end module, which further includes a power amplifier on a transmit path and a low-noise amplifier on a receive path) and a 535 controller.

[0046] Functionally, the PMIC 530 can perform battery power regulation, DC-to-DC conversion, etc., and thus has an input coupled to the battery 515 and an output that provides power to other functional modules. As further illustrated in the exemplary embodiment, the RFIC 525 has an output coupled to an antenna (not shown) to implement a number of wireless standards and protocols, including Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and all other wireless transmission protocols referred to as 3G, 4G, 5G, and beyond. In alternative implementations, each of these board-level modules can be integrated on separate ICs or integrated into a monolithic SoC 550.

[0047] Fig.Figure 6 is a functional block diagram of an electronic computing device according to an embodiment of the present invention. The computing device 600 may, for example, be located in the platform 505 or the server machine 506. The device 600 further comprises a mainboard 602 on which a number of components are housed, for example, but not limited to, a processor 604 (e.g., an application processor), which may further include at least one III-V semiconductor channel finFET with an underfin heterojunction diffusion barrier according to embodiments of the present invention. The processor 604 may be physically and / or electrically coupled to the mainboard 602. In some examples, the processor 604 has an IC die packed inside the processor 604.In general, the term "processor" or "microprocessor" can refer to any device or part of a device that processes electronic data from registers and / or a memory in order to convert that electronic data into other electronic data that can be further stored in registers and / or a memory.

[0048] In various examples, the one or more communication chips 606 may also be physically and / or electrically coupled to the mainboard 602. In other implementations, the communication chips 606 may be part of the processor 604. Depending on its applications, the computer device 600 may include other components, which may or may not be physically and electrically coupled to the mainboard 602. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a loudspeaker, a camera, and a mass storage device (e.g., a hard drive).Examples include hard disk drives, solid-state drives (SSDs), compact discs (CDs), digital versatile discs (DVDs), etc.

[0049] Communication chips 606 enable wireless communication for data transmission to and from the computer device 600. The term "wireless" and related terms can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data by using modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated devices do not contain wires, although this may be the case in some embodiments. Communication chips 606 can implement any of a number of wireless standards or protocols, including, but not limited to, those described elsewhere in this patent. As discussed, the computer device 600 can include multiple communication chips 606.For example, a first communication chip may be provided for shorter-range wireless communication such as Wi-Fi and Bluetooth, and a second 906 communication chip may be provided for longer-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO and others.

[0050] Even though certain features set forth in this patent application have been described with reference to various implementations, this description is by no means to be understood as limiting. Therefore, various modifications of the implementations described herein, as well as other implementations that are obvious to those skilled in the art in the field to which this disclosure belongs, are deemed to fall within the nature and scope of protection of this disclosure.

[0051] It is evident that the invention is not limited to the embodiments described above, but can be implemented with certain modifications and alterations without departing from the scope of protection of the appended patent claims. For example, the foregoing embodiments may have certain combinations of features as detailed below: In one or more first embodiments, a transistor comprises an active region arranged in a III-V semiconductor fin and a subfin arranged between the fin and a substrate. The subfin further comprises a first subfin layer of III-V semiconductor material arranged above the substrate, a second subfin layer of III-V semiconductor material arranged above the first subfin layer, and a third subfin layer of III-V semiconductor material arranged between the first and second subfin layers and closer to the substrate than to the fin, wherein the third layer consists of a III-V alloy composition associated with a wider bandgap than that of the first and second subfin layers.

[0052] To further the first embodiments, the III-V semiconductor fin comprises a III-V semiconductor material having a different III-V alloy composition than that of the first sub-fin layer. The wider band gap is associated with a conduction band offset (CBO) between the first and second sub-fin layers of at least 250 meV.

[0053] To promote the first embodiments, the III-V alloy composition is changed between the first and the second sub-fin layer over a material thickness of no more than 10 nm.

[0054] To promote the first embodiments, the third subfin layer material has a CBO of the first and the second subfin layer materials.

[0055] To promote the immediately preceding first embodiments, the CBO is at least 250 meV.

[0056] To promote the first embodiments, the first and second sub-fin layer material have essentially the same III-V alloy composition.

[0057] To further the first embodiments, the active region comprises a channel region made of III-V semiconductor material, arranged between a pair of semiconductor source / drain regions doped to the same conductor type. A gate electrode is arranged above the channel region, and a pair of source / drain contacts is coupled to the source / drain region pair.

[0058] To promote the first embodiments, the lower fin extends a height of a contact surface with the substrate, wherein the first lower fin layer extends from the contact surface to no more than 10% of the lower fin height.

[0059] To promote the first embodiments, the lower fin extends to a z-height of 200-250 nm from the contact surface with the substrate and the lower fin layer has a z-thickness of 20-100 nm.

[0060] To promote the first embodiments, the first sub-fin layer is doped with a higher concentration of one or more acceptor impurities than is present in at least the second sub-fin layer.

[0061] To promote the first embodiments, the concentration of acceptor impurities is above 1e18 atoms / cm³. 3 in the first sub-fin layer, and the concentration of donor impurities is below 1e18 atoms / cm². 3 in the second layer of lower fins.

[0062] To further the first embodiments, at least one of the first and second sub-fin layers comprises a first layer of GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP. The third sub-fin layer comprises a second layer of GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP. The fin comprises a third layer of GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP.

[0063] In one or more second embodiments, an integrated circuit device comprises several n-transistors, each having a channel region in a III-V semiconductor fin arranged between a pair of semiconductor source / drain regions, a gate electrode arranged above the channel region, and a pair of source / drain contacts coupled to the source / drain region pair. A subfin is arranged between the fin and a silicon substrate. The subfin further comprises a first subfin layer of III-V semiconductor material arranged above the substrate, and a second subfin layer of III-V semiconductor material arranged above the first subfin layer.A third subfin layer of III-V semiconductor material is arranged between the first and second subfin layers and closer to the substrate than to the fin. The third layer consists of a III-V alloy composition linked with a band gap exhibiting a conduction band offset (CBO) from that of the first subfin layer fin proximal to the active region and distal to the substrate. The device further comprises several p-type transistors electrically coupled to the multiple n-type transistors.

[0064] To promote the second embodiments, the multiple p-transistors each have active regions comprising a group IV semiconductor material.

[0065] To promote the second embodiments, the multiple p-transistors each have an active region arranged in a III-V semiconductor fin and a sub-fin with fewer than three material layers arranged between the fin and the substrate.

[0066] In one or more third embodiments, a method for forming a transistor comprises receiving a substrate, epitaxially growing a first thickness of III-V semiconductor material over a seed surface of the substrate, epitaxially growing a second thickness of III-V semiconductor material over the first thickness, epitaxially growing a third thickness of III-V semiconductor material over the second thickness, wherein the third thickness consists of a III-V alloy composition associated with a band gap wider than that of the first thickness, and wherein the first thickness is smaller than the third thickness, and forming an active region of the transistor in a fourth thickness of III-V semiconductor material, separated from the substrate by the first, second, and third thicknesses of III-V semiconductor material.

[0067] To further the third embodiments, the method further comprises embedding the first, second and third thicknesses in a field dielectric material, structuring the fourth thickness into a fin extending over the field dielectric material, and forming a gate stack and a pair of source / drain regions in the fin.

[0068] To further the immediately preceding third embodiments, the embedding of the first, second, and third thicknesses further comprises forming a trench in the field-dielectric material, wherein the trench exposes a crystalline surface of the substrate. The growth of the first thickness of III-V semiconductor material further comprises the growth of a first III-V semiconductor material in the trench. The growth of the second thickness of III-V semiconductor material further comprises the growth of a second III-V semiconductor material in the trench, wherein there is a conduction band offset to the first III-V semiconductor material of at least 250 mV. The growth of the third thickness of III-V semiconductor material further comprises the growth of the first III-V semiconductor material in the trench.

[0069] To further the third embodiment, the growth of the first thickness of III-V semiconductor material further comprises growing the first III-V semiconductor material in the trench to a thickness of less than 50 nm. The growth of the second thickness of III-V semiconductor material further comprises growing the second III-V semiconductor material in the trench to a thickness of less than 50 nm. The growth of the third thickness of III-V semiconductor material further comprises growing the first III-V semiconductor material in the trench to a thickness of at least 50 nm.

[0070] To promote the third embodiments, the growth of the first and second thicknesses of III-V semiconductor material further comprises the compositional stepping from the first III-V semiconductor material to the second III-V semiconductor material over a material thickness of not more than 10 nm.

[0071] To further the third embodiment, the growth of the first III-V semiconductor material further comprises the growth of a first of GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP. The growth of the second III-V semiconductor material further comprises a second of GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP. The formation of the active region further comprises the growth of the fourth thickness of III-V semiconductor material comprising a third of GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP.

[0072] To further the third embodiments, forming the transistor further comprises planarizing the field dielectric material with a surface of the fourth thickness of the III-V semiconductor material, deepening the field dielectric material to expose sidewalls of the fourth thickness of III-V semiconductor material, forming a gate stack over a channel region of the fourth thickness of III-V semiconductor material, and forming a pair of source / drain regions electrically coupled to opposite ends of the channel region.

[0073] However, the foregoing embodiments are not limited with regard to these aspects, and in various implementations, the foregoing embodiments may include implementing only a subset of such features, implementing a different sequence of such features, implementing a different combination of such features, and / or implementing additional features beyond those explicitly listed. The scope of protection shall therefore be determined with reference to the attached claims, together with the entirety of all equivalents to which such claims are entitled.

Claims

[1] Transistor, comprising: an active region arranged in a III-V semiconductor fin; and a lower fin arranged between the fin and a substrate (305), the lower fin further comprising: a first sub-fin layer (307) of III-V semiconductor material arranged over the substrate (305); a second subfin layer (310) of III-V semiconductor material arranged above the first subfin layer (307); and a third subfin layer (309) of III-V semiconductor material, arranged between the first and second subfin layer (309) and closer to the substrate (305) than to the fin (320), wherein the third layer consists of a III-V alloy composition associated with a wider band gap than that of the first and second subfin layer (309). [2] Transistor according to claim 1, wherein: the III-V semiconductor fin comprises a III-V semiconductor material having a different III-V alloy composition than that of the first sub-fin layer (307); and the wider band gap is associated with a conduction band offset (CBO) between the first and second sub-fin layer (309) of at least 250 meV. [3] Transistor of claim 1, wherein the change in the III-V alloy composition between the first and the second sub-fin layer (309) is made over a material thickness of not more than 10 nm. [4] Transistor according to claim 1, wherein: the III-V semiconductor material of the third sub-fin layer (310) exhibits a CBO of the III-V semiconductor material of the first (307) and second (309) sub-fin layers. [5] Transistor according to claim 4, wherein the CBO is at least 250 meV. [6] Transistor according to claim 5, wherein: the III-V semiconductor material of the first (307) and the second sub-fin layer (309) have essentially the same III-V alloy composition. [7] Transistor according to claim 1, wherein the active region comprises a channel region of III-V semiconductor material arranged between a pair of semiconductor source / drain regions doped to the same conduction type; and wherein: a gate electrode is positioned above the channel area; and a pair of source / drain contacts are coupled to the pair of source / drain areas. [8] Transistor according to claim 1, wherein: the lower fin extends a height of a contact surface with the substrate (305); and the first lower fin layer (307) extends from the contact surface to no more than 10% of the lower fin height. [9] Transistor according to claim 1, wherein: the lower fin extends to a z-height of 200 - 250 nm from the contact surface with the substrate (305); The lower fin layer has a z-thickness of 20-100 nm. [10] Transistor according to claim 1, wherein: the first sub-fin layer (307) is doped with a higher concentration of one or more acceptor impurities than is present in at least the second sub-fin layer (309). [11] Transistor according to claim 1, wherein a concentration of acceptor impurities above 1e18 atoms / cm³ 3 in the first lower fin layer (307); and a concentration of acceptor impurities below 1e18 atoms / cm³ 3 in the second lower fin layer (309). [12] Transistor according to claim 1, wherein: at least one of the first (307) and second sub-fin layer (309) comprises a first of GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs or InGaP; the third sub-fin layer (310) comprises a second of GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs or InGaP; and the fin includes a third of GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs or InGaP. [13] Component with integrated circuit, comprising: several n-transistors, each exhibiting: a channel region in a III-V semiconductor fin, arranged between a pair of semiconductor source / drain regions; a gate electrode positioned above the channel region; and a pair of source / drain contacts coupled to the pair of source / drain regions, wherein: a lower fin is arranged between the fin and a silicon substrate (305), the lower fin further comprising: a first sub-fin layer (307) of III-V semiconductor material arranged over the substrate (305); a second subfin layer (309) of III-V semiconductor material arranged above the first subfin layer (307); and a third subfin layer (310) of III-V semiconductor material, arranged between the first and second subfin layers (309) and closer to the substrate (305) than to the fin, wherein the third layer consists of a III-V alloy composition associated with a band gap that exhibits a conduction band offset (CBO) from that of the first subfin layer fin proximal to the active area and distal to the substrate (305), wherein the conduction band offset is caused by a larger band gap of the third subfin layer (310) compared to the first subfin layer (307); and several p-transistors electrically coupled to several n-transistors. [14] Component according to claim 13, wherein the multiple p-transistors each have an active region comprising a group IV semiconductor material. [15] Component according to claim 13, wherein the multiple p-transistors each comprise: an active region arranged in a III-V semiconductor fin; and a lower fin with fewer than three layers of material arranged between the fin and the substrate (305). [16] Method for forming a transistor, the method comprising: Receiving a silicon substrate; epitaxial growth of an initial thickness of III-V semiconductor material over a nucleation surface of the substrate; epitaxial growth of a second thickness of III-V semiconductor material over the first thickness; epitaxial growth of a third thickness of III-V semiconductor material over the second thickness, wherein the third thickness consists of a III-V alloy composition associated with a band gap wider than that of the first thickness, and wherein the first thickness is smaller than the third thickness; Forming an active region of the transistor in a fourth thickness of III-V semiconductor material, separated from the substrate by the first, second and third thicknesses of III-V semiconductor material Embedding the first, second and third thicknesses in a field-dielectric material; Structuring the fourth thickness into a fin that extends over the field-dielectric material; and Forming a gate stack and a pair of source / drain areas in the fin. [17] Method according to claim 16, wherein the embedding of the first, second and third thickness further comprises: Forming a trench in the field-dielectric material, wherein the trench exposes a crystalline surface of the substrate; and wherein: the growth of the first thickness of III-V semiconductor material further includes the growth of a first III-V semiconductor material in the trench; the growth of the second thickness of III-V semiconductor material further comprises the growth of a second III-V semiconductor material in the trench, wherein there is a conduction band offset to the first III-V semiconductor material of at least 250 mV; The growth of the third thickness of III-V semiconductor material also includes the growth of the first III-V semiconductor material in the trench. [18] Method according to claim 16, wherein: the growth of the first thickness of III-V semiconductor material further includes the growth of the first III-V semiconductor material in the trench to a thickness of less than 50 nm; the growth of the second thickness of III-V semiconductor material further includes the growth of the second III-V semiconductor material in the trench to a thickness of less than 50 nm; and The growth of the third thickness of III-V semiconductor material further includes the growth of the first III-V semiconductor material in the trench to a thickness of at least 50 nm. [19] Method according to claim 18, wherein the growth of the first and second thickness of III-V semiconductor material further comprises the compositional stepping from the first III-V semiconductor material to the second III-V semiconductor material over a material thickness of not more than 10 nm. [20] Method according to claim 18, wherein: the growth of the first III-V semiconductor material further includes the growth of a first of GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs or InGaP; the growth of the second III-V semiconductor material further includes the growth of a second of GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs or InGaP; and the formation of the active region further includes the growth of the fourth thickness of III-V semiconductor material with a third of GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs or InGaP. [21] Method according to claim 16, wherein forming the transistor further comprises: Planarizing the field-dielectric material with a surface of the fourth thickness of III-V semiconductor material; Deepening of the field dielectric material to expose fourth-thickness sidewalls of III-V semiconductor material; Forming a gate stack over a channel region of the fourth thickness of III-V semiconductor material; and Forming a pair of source / drain regions that are electrically coupled to opposite ends of the channel area.

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