Semiconductor relay module and semiconductor relay circuit

Abstract

Semiconductor relay module, comprising: a first semiconductor relay (10), including a first input circuit (11) and a first output circuit (12); a second semiconductor relay (20), including a second input circuit (21) and a second output circuit (22); a third semiconductor relay (30), including a third input circuit (31) and a third output circuit (32); a fourth semiconductor relay(40), including a fourth input circuit (41) and a fourth output circuit (42); a fifth semiconductor relay (50), including a fifth input circuit (51) and a fifth output circuit (52); a sixth semiconductor relay (60), including a sixth input circuit (61) and a sixth output circuit (52); a package (70) designed to accommodate the first solid-state relay (10), the second solid-state relay (20) and the third solid-state relay (30) in the package (70); a first input terminal (71), a second input terminal (72) and a third input terminal (73) arranged in the package (70), wherein the first input terminal (71), the second input terminal (72) and the third input terminal (73) are each partially exposed to the outside of the package (70); a first output terminal (81), a second output terminal (82), a third output terminal (83), a fourth output terminal (84) and a fifth output terminal (85) arranged in the package (70), wherein the first output terminal (81), the second output terminal (82), the third output terminal (83), the fourth output terminal (84) and the fifth output terminal (85) are each partially exposed to the outside of the package (70); a first connecting line (80) for connecting the first output circuit (12) and the second output circuit (22) in the package (70), a second connecting line (86) for connecting the fourth output circuit (42) and the fifth output circuit (52) in the package (70), wherein the first input circuit (11) is connected to the first input terminal (71) and the second input terminal (72) in the package (70), wherein the second input circuit (21) is connected to the first input terminal (71) and the second input terminal (72) in the package (70), wherein the third input circuit (31) is connected to the first input terminal (71) or the second input terminal (72) in the package (70), wherein the third input circuit (31) is connected to the first input terminal (71) in the package (70), wherein the fourth input circuit (41) is connected to the first input terminal (71) and the second input terminal (72) in the package (70), wherein the fifth input circuit (51) is connected to the first input terminal (71) and the second input terminal (72) in the package (70), wherein the sixth input circuit (61) is connected to the first input terminal (71) or the second input terminal (72) in the package (70), wherein the sixth input circuit (61) is connected to the third input terminal (73) in the package (70), wherein the first output circuit (12) is connected to the first output terminal (81) and the first connecting line (80) in the package (70), wherein the second output circuit (22) is connected to the second output terminal (82) and the first connecting line (80) in the package (70), wherein the third output circuit (32) is connected to the third output terminal (83) and the first connecting line (80) in the package (70), wherein the fourth output circuit (42) is connected to the fourth output terminal (84) and the second connecting line (86) in the package (70), the fifth output circuit (52) is connected to the fifth output terminal (85) and the second connecting line (86) in the package (70); and the sixth output circuit (62) is connected to the third output terminal (83) and the second connecting line (86) in the package (70); wherein in a first state in which current flows through the first input terminal (71) and the second input terminal (72) without flowing through the third input terminal (73), the first output circuit (12) and the second output circuit (22) are designed to be switched on, the third output circuit (32) is designed to be switched off, the first output terminal (81) and the second output terminal (82) are designed to be electrically connected to each other, and the first connecting line (80) and the third output terminal (83) are designed to be electrically disconnected from each other, and wherein in a second state in which current flows through the third input terminal (73) without flowing through the first input terminal (71) and the second input terminal (72), the first output circuit (12) and the second output circuit (22) are designed to be switched off, the third output circuit (32) is designed to be switched on, the first output terminal (81) and the second output terminal (82) are designed to be electrically disconnected from each other, and the first connecting line (80) and the third output terminal (83) are designed to be electrically connected to each other.

Description

TECHNICAL AREA

[0001] This disclosure relates to a semiconductor relay module and a semiconductor relay circuit. STATE OF THE ART

[0002] JP-H07-46109 A discloses a semiconductor relay, including two output semiconductor relays and a grounding semiconductor relay. The two output semiconductor relays are connected in series. The grounding semiconductor relay is arranged between the grounding point and the connection point of the two output semiconductor relays.

[0003] In a semiconductor relay module according to WO 2019 / 043 969 A1, also published as DE 11 2017 008 005 T5, inside a housing, one input part from a pair of input parts of a first semiconductor relay is connected to a first input terminal, the other input part from the pair of input parts of the first semiconductor relay is connected to a second input terminal, one input part from a pair of input parts of a second semiconductor relay is connected to the second input terminal, the other input part from the pair of input parts of the second semiconductor relay is connected to the first input terminal, one input part from a pair of input parts of a third semiconductor relay is connected to a third input terminal, and the other input part from the pair of input parts of the third semiconductor relay is connected to the first input terminal or the second input terminal.

[0004] In this solid-state relay, each of the output relays and the ground relay has two MOSFETs connected in an anti-series configuration. A photodiode array is connected to the MOSFET. The solid-state relay includes a first input circuit and a second output circuit. The first input circuit has a first LED. The photodiode arrays of the two output relays are designed to generate an electromotive force from the light emission of the first LED to switch on the MOSFETs of the output relays. The second input circuit has a second LED. The photodiode array of the ground relay is designed to generate an electromotive force from the light emission of the second LED to switch on the MOSFET of the ground relay. SUMMARY Technical Task

[0005] In the aforementioned semiconductor relay, the common first input circuit controls the switching on / off of the two output semiconductor relays. However, with such a design, guaranteeing stable operating characteristics is not straightforward. The first and second input circuits are each connected to two input terminals. Therefore, the wiring and related aspects could prove complicated, and the circuit board design could be challenging.

[0006] Therefore, one of the purposes of this disclosure is to provide a semiconductor relay module and a semiconductor relay circuit that ensure stable operating characteristics and facilitate the design of the printed circuit board. Solution to the task

[0007] The stated problem is solved by the features of the main claim. Advantageous embodiments are described in the dependent claims. A semiconductor relay module comprises a first semiconductor relay, a second semiconductor relay, and a third semiconductor relay, a packing, a first input terminal, a second input terminal, and a third input terminal, a first output terminal, a second output terminal, and a third output terminal, as well as a first connecting line. The first semiconductor relay includes a first input circuit and a first output circuit. The second semiconductor relay includes a second input circuit and a second output circuit. The third semiconductor relay includes a third input circuit and a third output circuit.

[0008] The package contains the first, second, and third solid-state relays. The first, second, and third input terminals are arranged within the package and are partially exposed to the outside. The first, second, and third output terminals are also arranged within the package and are partially exposed to the outside. The first connecting wire connects the first and second output circuits within the package.

[0009] The first input circuit is connected to the first and second input terminals in the package. The second input circuit is connected to the first and second input terminals in the package. The third input circuit is connected to either the first or the second and third input terminals in the package. The first output circuit is connected to the first output terminal and the first connecting wire in the package. The second output circuit is connected to the second output terminal and the first connecting wire in the package. The third output circuit is connected to the third output terminal and the first connecting wire in the package.

[0010] In a first state, where a current flows through the first input terminal and the second input terminal and a current does not flow through the third input terminal, the first output circuit and the second output circuit are designed to be switched on, the third output circuit is designed to be switched off, the first output terminal and the second output terminal are designed to be electrically connected, and the first connecting line and the third output terminal are designed to be electrically disconnected.In the second state, where the current does not flow through the first input terminal and the second input terminal and the current flows through the third input terminal, the first output circuit and the second output circuit are designed to be switched off, the third output circuit is designed to be switched on, the first output terminal and the second output terminal are designed to be electrically disconnected, and the first connecting line and the third output terminal are designed to be electrically connected. Effects of the invention

[0011] According to the solid-state relay module, input circuits are provided for the first, second, and third solid-state relays. This ensures stable operating characteristics. The input circuit of each solid-state relay is also connected to the input terminal. Therefore, it is possible to implement a solid-state relay module that simplifies printed circuit board design. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows a design diagram illustrating an example of a semiconductor relay circuit according to the first embodiment. Fig. Figure 2 shows a design diagram illustrating an example of a semiconductor relay module according to the first embodiment. Fig. Figure 3 shows a timing diagram illustrating an example of the operation of the semiconductor relay module. Fig. Figure 4 shows a design diagram illustrating an example of a semiconductor relay circuit according to the second embodiment. Fig. Figure 5 shows a design diagram illustrating an example of a semiconductor relay module according to the second embodiment. Fig. Figure 6 shows a design diagram illustrating an example of the semiconductor relay module according to the second embodiment. Fig. Figure 7 shows a design diagram illustrating another example of the semiconductor relay module. Fig. Figure 8 shows a timing diagram illustrating another example of the operation of the semiconductor relay module. DETAILED DESCRIPTION

[0012] The following is an example of this disclosure described with reference to the drawings. In the following description, terms indicating a specific direction or position are used as necessary; however, their use serves to simplify the understanding of the disclosure with reference to the drawings and the meaning of these terms. The technical purpose of this disclosure is not limited to this. Furthermore, the following description serves only as an example and is not intended to limit this disclosure, its applications, or uses in any way. Moreover, the drawings are schematic representations, and the proportions of the respective dimensions and the like do not necessarily correspond to the actual values.

[0013] Fig. Figure 1 shows a layout diagram illustrating an example of a semiconductor relay circuit 1a according to the first embodiment of this disclosure. According to the illustration in Fig. 1. The semiconductor relay circuit 1a includes a semiconductor relay module 2a, a power supply terminal 3, a control terminal 4, and a control circuit 5. The semiconductor relay module 2a includes a first semiconductor relay 10, a second semiconductor relay 20, a third semiconductor relay 30, a pack 70, a first input terminal 71, a second input terminal 72, and a third input terminal 73.

[0014] Package 70 contains the first solid-state relay 10, the second solid-state relay 20, and the third solid-state relay 30. Package 70 is made, for example, of an insulating resin. However, package 70 is not limited to resin and can be made of another material such as ceramic. Package 70 has a rectangular shape in a top view. However, package 70 is not limited to a rectangular shape and can have a different shape.

[0015] The first input terminal 71, the second input terminal 72, and the third input terminal 73 are arranged within the package 70. Both the first input terminal 71, the second input terminal 72, and the third input terminal 73 are arranged such that a portion of the first input terminal, a portion of the second input terminal 72, and a portion of the third input terminal 73 are exposed to the outside of the package 70. The semiconductor relay module 2a also includes a first output terminal 81, a second output terminal 82, and a third output terminal 83. The first output terminal 81, the second output terminal 82, and the third output terminal 83 are arranged within the package 70. Both the first output terminal 81, the second output terminal 82, and the third output terminal 83 are arranged such that a portion of the first output terminal 81, a portion of the second output terminal 82, and a portion of the third output terminal 83 are exposed to the outside of the package 70.

[0016] In the semiconductor relay module 2a in the package 70, the first semiconductor relay 10, the second semiconductor relay 20, and the third semiconductor relay 30 are arranged side by side in the longitudinal direction of the package 70. The third semiconductor relay 30 is arranged between the first semiconductor relay 10 and the second semiconductor relay 20 in the longitudinal direction of the package 70.

[0017] The first solid-state relay 10 includes a first input circuit 11 and a first output circuit 12. When current flows through the first input circuit 11, the first output circuit 12 is in an ON state. When no current flows through the first input circuit 11, the first output circuit 12 is in an OFF state. The second solid-state relay 20 includes a second input circuit 21 and a second output circuit 22. When current flows through the second input circuit 21, the second output circuit 22 is in an ON state. When no current flows through the second input circuit 21, the second output circuit 22 is in an OFF state. The third solid-state relay 30 includes a third input circuit 31 and a third output circuit 32. When current flows through the third input circuit 31, the third output circuit 32 is in an ON state.If no current flows in the third input circuit 31, the third output circuit 32 is in the off state. It should be noted that an "on state" refers to a state in which current flows in the output circuit. An "off state" refers to a state in which no current flows in the output circuit.

[0018] The first input circuit 11 is connected to the first input terminal 71 and the second input terminal 72 in package 70. The second input circuit 21 is connected to the first input terminal 71 and the second input terminal 72 in package 70. The third input circuit 31 is connected to the first input terminal 71 and the third input terminal 73 in package 70.

[0019] In particular, the first input circuit 11 is connected to the first input terminal 71 via connecting cable 74. The first input circuit 11 is connected to the second input terminal 72 via connecting cable 75. The second input circuit 21 is connected to the first input terminal 71 via connecting cable 76. The second input circuit 21 is connected to the second input terminal 72 via connecting cable 77. The third input circuit 31 is connected to the first input terminal 71 via connecting cable 78. The third input circuit 31 is connected to the third input terminal 73 via connecting cable 79. The connecting cables 74 to 79 are arranged in the package 70.

[0020] The first output circuit 12 is connected to the first output terminal 81 and the first connecting line 80 in the package 70. The second output circuit 22 is connected to the second output terminal 82 and the first connecting line 80 in the package 70. The first output circuit 12 and the second output circuit 22 are connected in series in the package 70 by means of the first connecting line 80. The third output circuit 32 is connected to the third output terminal 83 and the first connecting line 80 in the package 70. The first connecting line 80 is located in the package 70.

[0021] Fig. Figure 2 is a configuration diagram showing an example of the semiconductor relay module 2a. According to the diagram in Fig. 2. The first input circuit 11 of the first solid-state relay 10 includes a first input section 13, a second input section 14, and a light-emitting element 15. The first input section 13 is connected to the first input terminal 71. The second input section 14 is connected to the second input terminal 72. The light-emitting element 15 is connected to the first input section 13 and the second output section 14. The light-emitting element 15 emits light when current flows through the first input circuit 11.

[0022] The second input circuit 21 of the second solid-state relay 20 includes a first input section 23, a second input section 24, and a light-emitting element 25. The first input section 23 is connected to the first input terminal 71. The second input section 24 is connected to the second input terminal 72. The light-emitting element 25 is connected to both the first input section 23 and the second input section 24. The light-emitting element 25 emits light when current flows through the second input circuit 21.

[0023] The third input circuit 31 of the third solid-state relay 30 includes a first input section 33, a second input section 34, and a light-emitting element 35. The first input section 33 is connected to the first input terminal 71. The second input section 34 is connected to the third input terminal 73. The light-emitting element 35 is connected to both the first input section 33 and the second input section 34. The light-emitting element 35 emits light when current flows through the third input circuit 31.

[0024] The first output circuit 12 of the first semiconductor relay 10 includes a first output section 16, a second output section 17, and two MOSFETs 18 and 19. The first output section 16 is connected to the first output terminal 81. The second output section 17 is connected to the first connecting line 80. The MOSFETs 18 and 19 are connected in series so that the parasitic diodes are oriented in opposite directions. The MOSFETs 18 and 19 are switched between an on state and an off state depending on whether the light-emitting element 15 emits light or not. When the MOSFETs 18 and 19 are in the on state, the first output section 16 and the second output section 17 are electrically connected. When MOSFETs 18 and 19 are in the off state, the first output section 16 and the second output section 17 are electrically isolated.

[0025] The second output circuit 22 of the second semiconductor relay 20 includes a first output section 26, a second output section 27, and two MOSFETs 28 and 29. The first output section 26 is connected to the first connecting line 80. The second output section 27 is connected to the second output terminal 82. The MOSFETs 28 and 29 are connected in series, such that the parasitic diodes are oppositely oriented. The MOSFETs 28 and 29 are switched between an on state and an off state depending on whether the light-emitting element 25 emits light or not. When the MOSFETs 28 and 29 are in the on state, the first output section 26 and the second output section 27 are electrically connected. When MOSFETs 28 and 29 are in the off state, the first output section 26 and the second output section 27 are electrically isolated.

[0026] The third output circuit 32 of the second semiconductor relay 30 includes a first output section 36, a second output section 37, and two MOSFETs 38 and 39. The first output section 36 is connected to the first connecting line 80. The second output section 37 is connected to the third output terminal 83. The MOSFETs 38 and 39 are connected in series, so that the parasitic diodes are oppositely oriented. The MOSFETs 38 and 39 are switched between an on state and an off state depending on whether the light-emitting element 35 emits light or not. When the MOSFETs 38 and 39 are in the on state, the first output section 36 and the second output section 37 are electrically connected. When MOSFETs 38 and 39 are in the off state, the first output section 36 and the second output section 37 are electrically isolated.

[0027] According to the representation in Fig. In this diagram, the first input terminal 71, the second input terminal 72, and the third input terminal 73 are connected to the power supply terminal 3 and the control terminal 4 via the control circuit 5. A power supply voltage is applied to the power supply terminal 3. An input signal is applied to the control terminal 4.

[0028] Control circuit 5 includes a first circuit 91, a second circuit 92, and a third circuit 93. The first circuit 91 connects the power supply terminal 3 and the first input terminal 71. The second circuit 92 connects the control terminal 4 and the second input terminal 72 via transistor 94 and resistor 95. The third circuit 93 connects the control terminal 4 and the third input terminal 73 via transistors 96 and 97 and resistor 98. Transistor 96 is connected to the power supply terminal 3 via resistor 99. The design of control circuit 5 is not limited to the representation in Fig. 1 is limited and can be changed.

[0029] The first output terminal 81 is connected to the first external output terminal 6. The second output terminal 82 is connected to the second external output terminal 7. The third output terminal 83 is connected to the grounding point GND. This means that the third output terminal 83 is a grounding terminal for grounding the first connecting line 80.

[0030] Control circuit 5 switches the excitation state of each input terminal of semiconductor module 2a between the first state and the second state, depending on the input signal supplied to control terminal 4. The first state is the state in which current flows through the first input terminal 71 and the second input terminal 72, and no current flows through the third input terminal 73. The second state is the state in which no current flows through the first input terminal 71 and the second input terminal 72, and current flows through the third input terminal 73.

[0031] Fig. Figure 3 shows a timing diagram illustrating the operation of the semiconductor relay module 2a according to the voltage control of the input signal. Fig. 3A shows a voltage change of the input signal that is supplied to control terminal 4. Fig. Figure 3B shows changes in the on / off states of the first output circuit 12 of the first semiconductor relay 10 and the second output circuit 22 of the second semiconductor relay 20. Fig. 3C shows changes in the on / off state of the third output circuit 32 of the third semiconductor relay 30. Fig. 3D shows a change in the conducting / non-conducting state between the first output terminal 81 and the second output terminal 82.

[0032] According to the representation in Fig. In 3A, control circuit 5 regulates the excitation state for each input terminal 71 to 73 of the semiconductor relay module 2a to the first state at a time T1 when an ON input signal (+) is supplied to control terminal 4. This means that current flows through the first input terminal 71 and the second input terminal 72, and that no current flows through the third input terminal 73. It follows that the current flowing through the first input circuit 11 and the second input circuit 21 causes the ON state of the first output circuit 12 and the second output circuit 22 at a time T1', which, with respect to time T1, is shown in the diagram. Fig. 3B is slightly delayed. Since no current flows in the third input circuit 31, the third output circuit 32 is located in the diagram. Fig. 3C in the off state. As shown in Fig. In 3D, the first output terminal 81 and the second output terminal 82 are electrically connected at time T1'. At this time, the first connecting line 80 and the third output terminal 83 are electrically disconnected.

[0033] If the input signal is then sent to control terminal 4 according to the diagram in Fig. When 3A is deactivated at time T2, control circuit 5 changes the excitation state to the input terminals 71 to 73 of the semiconductor relay module 2a to the second state. This means that no current flows through the first input terminal 71 and the second input terminal 72, and current flows through the third input terminal 73. It follows that, due to the fact that no current flows to the first input circuit 11 and the second input circuit 21, the off state of the first output circuit 12 and the second output circuit 22 is effected at a time T2', which, with respect to time T2, is shown in the diagram. Fig. 3B is slightly delayed. Furthermore, the third output circuit 32 is located in the diagram. Fig. 3C is in the on state at a time T2", which is slightly delayed with respect to time T2'. Therefore, the first output terminal 81 and the second output terminal 82 are in the on state after time T2' as shown in the diagram. Fig. They are electrically separated from each other in 3D. Furthermore, the first electrical connecting line 80 and the third output terminal 83 are electrically connected after time T2", so that the first connecting line 80 is grounded via the third output terminal 83. This allows for good insulation properties.

[0034] Similar to the above, the third output circuit 32 is located according to the diagram in Fig. 3C at time T3", which is slightly delayed from time T3, in the off state, when the control terminal 4 is at time T3 according to the representation in Fig. An input signal is supplied to 3A. Furthermore, the first output circuit 12 and the second output circuit 22 are located as shown in the diagram. Fig. 3B is in the on state at time T3', which is slightly delayed from time T3". This results in the first output terminal 81 and the second output terminal 82 being as shown in Fig. 3 electrically connected to each other. In addition, the first connecting line 80 and the third output terminal 83 are electrically separated from each other.

[0035] If the input signal is then sent to control terminal 4 at time T4 according to the diagram in Fig. When 3A is deactivated, the first output circuit 12 and the second output circuit 22 are located as shown in the diagram. Fig. 3B is in the off state at time T4', which is slightly delayed from time T4. Furthermore, the third output circuit 32 is in the off state according to the diagram. Fig. 3C is in the on state at a time T4", which is slightly delayed with respect to time T4'. Therefore, the first output terminal 81 and the second output terminal 82 are in the on state after time T4' as shown in the diagram. Fig. 3D electrically separated from each other. In addition, the first connecting line 80 and the third output terminal 83 are electrically connected to each other after time T4".

[0036] In the semiconductor relay module 2a according to the embodiment described above, the first output circuit 12 of the first semiconductor relay 10 and the second output circuit 22 of the second semiconductor relay 20 are connected in series and designed to switch simultaneously between the on and off states. Furthermore, if the first output terminal 81 and the second output terminal 82 are electrically isolated from each other, the first connecting line 80 is electrically connected to the third output terminal 83 and thus grounded. This ensures good insulation properties between the first output terminal 81 and the second output terminal 82.

[0037] In the solid-state relay module 2a, the input circuits 11, 21, and 31 of the solid-state relays 10, 20, and 30 are each connected to the input terminals 71, 72, and 73 in package 70. The output circuits 12, 22, and 32 of the solid-state relays 10, 20, and 30 are each connected to the output terminals 81, 82, and 83 in package 70. This simplifies the wiring by avoiding a complex wiring layout where wires cross each other on the circuit board. This makes it possible to implement the solid-state relay module 2a, which reduces the transmission loss of the high-frequency signal and simplifies the circuit board design.

[0038] The first solid-state relay 10 and the second solid-state relay 20 can be low-on-resistance solid-state relays, and the third solid-state relay 30 can be a low-terminal-capacitance solid-state relay. This means that the output on-resistance of the first solid-state relay 10 and the output on-resistance of the second solid-state relay 20 can be lower than the output on-resistance of the third solid-state relay 30, and that the output terminal capacitance of the third solid-state relay 30 can be lower than the output terminal capacitance of the first solid-state relay 10 and the output terminal capacitance of the second solid-state relay 20. This allows for good insertion loss and isolation characteristics.

[0039] Alternatively, all semiconductor relays 10, 20, 30 from the first to the third can be low-capacitance semiconductor relays, having an output capacitance of at most 12 pF. The output capacitance of the low-capacitance semiconductor relay is preferably at most 0.8 pF and even better at most 0.2 pF.

[0040] The semiconductor relay circuit 1b according to the second embodiment of this disclosure is described below. Fig. Figure 4 is a design diagram illustrating an example of the semiconductor relay circuit 1b according to the second embodiment. Fig. Section 4 describes the designs of the semiconductor relay circuit 1b according to the second embodiment, which have the same components as in the first embodiment, and are named with the same reference numerals. For example, the power supply terminal 3, the control terminal 4, the control circuit 5, the first semiconductor relay 10, the second semiconductor relay 20, the third semiconductor relay 30, the packing 70, the first input terminal 71, the second input terminal 72, the third input terminal 73, the first output terminal 81, the second output terminal 82, and the third output terminal 83 are the same as in the first embodiment, and therefore a detailed description is omitted.

[0041] The solid-state relay circuit 1b includes a solid-state relay module 2b. In addition to the configuration of the solid-state relay module 2a described above, the solid-state relay module 2b includes a fourth solid-state relay 40, a fifth solid-state relay 50, a sixth solid-state relay 60, a fourth output terminal 84, a fifth output terminal 85, and a second connecting line 86. The fourth to sixth solid-state relays 40, 50, and 60 are arranged in parallel to the direction in which the first to third solid-state relays 10, 20, and 30 are arranged. The fourth to sixth solid-state relays s 40, 50 and 60 are arranged in a direction that intersects the direction in which the first to third solid-state relays 10, 20, 30 are arranged, in comparison to the first to third solid-state relays 10, 20 and 30. However, the arrangement with the fourth to sixth solid-state relays 40, 50 and 60 can be changed.For example, the first to the sixth semiconductor relays 10, 20, 30, 40, 50 and 60 can be arranged in a line in the longitudinal direction of the pack 70.

[0042] The fourth solid-state relay 40 includes a fourth input circuit 41 and a fourth output circuit 42. When current flows through the fourth input circuit 41, the fourth output circuit 42 is in the ON state. When no current flows through the fourth input circuit 41, the fourth output circuit 42 is in the OFF state. The fifth solid-state relay 50 includes a fifth input circuit 51 and a fifth output circuit 52. When current flows through the fifth input circuit 51, the fifth output circuit 52 is in the ON state. When no current flows through the fifth input circuit 51, the fifth output circuit 52 is in the OFF state. The sixth solid-state relay 60 includes a sixth input circuit 61 and a sixth output circuit 62. When current flows through the sixth input circuit 61, the sixth output circuit 62 is in the ON state. When no current flows through the sixth input circuit 61, the sixth output circuit 62 is in the OFF state.

[0043] The fourth output terminal 84 and the fifth output terminal 85 are arranged in the package 70 such that part of the fourth output terminal 84 and part of the fifth output terminal 85 are exposed to the outside of the package 70. The second connecting line 86 connects the fourth output circuit 42 and the fifth output circuit 52 in the package 70. The fourth output terminal 84 is connected to the third external output terminal 8. The fifth output terminal 85 is connected to the fourth external output terminal 9.

[0044] The fourth input circuit 41 is connected to the first input terminal 71 and to the second input terminal 72 in package 70. The fifth input circuit 51 is connected to the first input terminal 71 and to the second input terminal 72 in package 70. The sixth input circuit 61 is connected to the first input terminal 71 and the third input terminal 73 in package 70. The sixth input circuit 61 is connected in series with the third input circuit 31 in package 70.

[0045] The fourth output circuit 42 is connected to the fourth output terminal 84 and the second connecting lead 86 in the package 70. The fifth output circuit 52 is connected to the fifth output terminal 85 and the second connecting lead 86 in the package 70. The sixth output circuit 62 is connected to the third output terminal 83 and the second connecting lead 86 in the package 70.

[0046] Fig. 5 and Fig. Figure 6 shows an example of the design of the semiconductor relay module 2b. According to the representation in Fig. The fourth input circuit 41 of the fourth solid-state relay 40 includes a first input section 43, a second input section 44, and a light-emitting element 45. The first input section 43 is connected to the first input terminal 71. The second input section 44 is connected to the second input terminal 72. The fifth input circuit 51 of the fifth solid-state relay 50 includes a first input section 53, a second input section 54, and a light-emitting element 55. The first input section 53 is connected to the first input terminal 71. The second input section 54 is connected to the second input terminal 72. The sixth input circuit 61 of the sixth solid-state relay 60 includes a first input section 63, a second input section 64, and a light-emitting element 65. The first input section 63 is connected to the first input terminal 71. The second input section 64 is connected to the third input terminal 73.The design of the light-emitting elements 45, 55, and 65 of the fourth to sixth semiconductor relays 40, 50, and 60 is similar to that of the light-emitting elements 15, 25, and 35 of the first to third semiconductor elements 10, 20, and 30, which are described above. Therefore, a detailed description is omitted.

[0047] The fourth output circuit 42 of the fourth solid-state relay 40 includes a first output section 46, a second output section 47, and two MOSFETs 48 and 49. The first output section 46 is connected to the fourth output terminal 84. The second output section 47 is connected to the second connecting line 86. The fifth output circuit 52 of the fifth solid-state relay 50 includes a first output section 56, a second output section 57, and two MOSFETs 58 and 59. The first output section 56 is connected to the second connecting line 86. The second output section 57 is connected to the fifth output terminal 85. The sixth output circuit 62 of the sixth solid-state relay 60 includes a first output section 66, a second output section 67, and two MOSFETs 68 and 69. The first output section 66 is connected to the second connecting line 86. The second output section 67 is connected to the third output terminal 83.The design of MOSFETs 48, 49, 58, 59, 68, and 69 of the fourth to sixth solid-state relays is similar to that of MOSFETs 18, 19, 28, 29, 38, and 39 of the first to third solid-state relays. Therefore, a detailed description is omitted.

[0048] In the first state, where current flows through the first input terminal 71 and the second input terminal 72, but not through the third input terminal 73, the first output circuit 12, the second output circuit 22, the fourth output circuit 42, and the fifth output circuit 52 are in the ON state at the semiconductor relay module 2b, and the third output circuit 32 and the sixth output circuit 62 are in the OFF state. Consequently, the first output terminal 81 and the second output terminal 82 are electrically connected, the fourth output terminal 84 and the fifth output terminal 85 are electrically connected, the first connecting line 80 and the third output terminal 83 are electrically disconnected, and the second connecting line 86 and the third output terminal 83 are electrically disconnected.

[0049] In the second state, where no current flows through the first input terminal 71 and the second input terminal 72, and current flows through the third input terminal 73, the first output circuit 12, the second output circuit 22, the fourth output circuit 42, and the fifth output circuit 52 are in the off state, and the third output circuit 32 and the sixth output circuit 62 are in the on state. Consequently, the first output terminal 81 and the second output terminal 82 are electrically isolated from each other, the fourth output terminal 84 and the fifth output terminal 85 are electrically isolated from each other, the first connecting line 80 and the third output terminal 83 are electrically connected to each other, and the second connecting line 86 and the third output terminal 83 are electrically connected to each other.

[0050] The semiconductor relay module 2b according to the second embodiment described above is controlled similarly to the semiconductor relay module 2a according to the first embodiment by the voltage control of the input signal supplied to the control terminal 4. In this case, the fourth output circuit 42 and the fifth output circuit 52 are switched between the on state and the off state similarly to the first output circuit 12 and the second output circuit 22, which are described in Fig. 3B are shown, switched. In addition, the sixth output circuit 62 can be switched similarly to the third, in Fig. The output circuit 32 shown in Figure 3C is switched between the on state and the off state. As a result, the fourth output terminal 84 and the fifth output terminal 85 are switched between the conducting state and the non-conducting state, just like the first output terminal 81 and the second output terminal 82, which are shown in Figure 3C. Fig. 3D representations are switched on.

[0051] In the semiconductor relay module 2b, the first output circuit 12 of the first semiconductor relay 10 and the second output circuit 22 of the second semiconductor relay 20 are connected in series, and the fourth output circuit 42 of the fourth semiconductor relay 40 and the fifth output circuit 52 of the fifth semiconductor relay 50 are connected in series. These output circuits are switched to the on state and the off state simultaneously.

[0052] The third solid-state relay 30 controls the connection of the first connecting line 80, which connects the first output circuit 12 and the second output circuit 22, to the ground point GND. The sixth solid-state relay 60 controls the connection of the second connecting line 86, which connects the fourth output circuit 42 and the fifth output circuit 52, to the ground point GND. This improves the insulation properties between the first output terminal 81 and the second output terminal 82, and between the fourth output terminal 84 and the fifth output terminal 85.

[0053] Furthermore, similar to the first embodiment of the semiconductor relay module 2a, the second embodiment of the semiconductor relay module 2b also allows for simplified wiring by avoiding a complex wiring layout where wires cross each other on a printed circuit board. This makes it possible to implement the semiconductor relay module 2b, which can reduce the transmission loss of the high-frequency signal and simplify the printed circuit board design.

[0054] Although one embodiment of this invention has been described above, this invention is not limited to the embodiment described above, and various variants are possible without deviating from the concept of the invention.

[0055] The design of the semiconductor relay circuit, the semiconductor relay module, and the semiconductor relay is not limited to the embodiment described above and can be modified. The number of semiconductor relays included in the semiconductor relay module is not limited to three or six. Four or more, or seven or more semiconductor relays, are possible.

[0056] The third input circuit 31 can be connected to the second input terminal 72 and the third input terminal 73 in package 70. The sixth input circuit 61 can be connected to the second input terminal 72 and the third input terminal 73 in package 70.

[0057] The arrangement of the first to third semiconductor relays 10, 20 and 30 in the semiconductor relay module 2a according to the first embodiment is not limited to that of the embodiment described above and can be modified. For example, the second semiconductor relay 20 can be arranged as shown in Fig. 7 between the first semiconductor relay 10 and the third semiconductor relay 30. Similarly, the arrangement of the first to sixth semiconductor relays 10, 20, 30, 40, 50 and 60 in the semiconductor relay module 2b according to the second embodiment is not limited to that of the embodiment described above and can be modified. The arrangement of the input terminals and / or the output terminals is not limited to that of the embodiment described above and can be modified.

[0058] The design of the control circuit 5 is not limited to that of the embodiment above and can be modified. For example, the control circuit 5 can be designed such that the excitation state of each input terminal of the semiconductor relay module 2a is switched between the first state and the second state by controlling the current of the input signal to the second input terminal 72 and the third input terminal 73.

[0059] Fig. Figure 8 is a timing diagram showing the operation of the semiconductor relay module 2a according to the current control of the input signal. Fig. 8A indicates a change in the current of the input signal that is supplied to the second input terminal 72. Fig. Figure 8B shows a change in the current of the input signal that is supplied to the third input terminal 73. Fig. Figure 8C shows changes in the on / off states of the first output circuit 12 of the first semiconductor relay 10 and the second output circuit 22 of the second semiconductor relay 20. Fig. 8C shows changes in the on / off state of the third output circuit 32 of the third semiconductor relay 30. Fig. 8E shows a change in the conducting / non-conducting state between the first output terminal 81 and the second output terminal 82.

[0060] If the ON input signal is as shown in Fig. 8A and Fig. When the input signal to the third input terminal 73 is deactivated at time T1, the excitation state of each input terminal of the semiconductor relay module 2a is the first state. This means that current flows through the first input terminal 71 and the second input terminal 72, and no current flows through the third input terminal 73. It follows that the current flowing through the first input circuit 11 and the second input circuit 21 causes the first output circuit 12 and the second output circuit 22 to be on at a time T1', which, with respect to time T1, is shown in the diagram. Fig. 8C is slightly delayed. Since no current flows in the third input circuit 31, the third output circuit 32 is located, according to the diagram, in Fig. 8D in the off state. According to the illustration in Fig. Thus, at time T1', the first output terminal 81 and the second output terminal 82 are electrically connected. At this time, the first connecting line 80 and the third output terminal 83 are electrically disconnected.

[0061] If the input signal at the second input terminal 72 is then present at time T2 according to the representation in Fig. 8A is deactivated and the ON input signal is active at time T3 as shown in the diagram. Fig. When current is supplied to the third input terminal 73 (8B), the excitation state of each input terminal of the semiconductor relay module 2a assumes the second state. This means that no current flows through the first input terminal 71 and the second input terminal 72, and current flows through the third input terminal 73. It follows that, due to the fact that no current flows to the first input circuit 11 and the second input circuit 21, the off state of the first output circuit 12 and the second output circuit 22 is effected at a time T2', which, with respect to time T2, is shown in the diagram. Fig. 8C is slightly delayed. Furthermore, the third output circuit 32 is located in the diagram. Fig. 8D is in the on state at a time T3', which is slightly delayed with respect to time T3. Consequently, the first output terminal 81 and the second output terminal 82 are in the on state after time T2' as shown in the diagram. Fig. 8E are electrically isolated from each other. Furthermore, the first connecting line 80 and the third output terminal 83 are electrically connected to each other after time T3'. According to the illustration in Fig. 8E therefore, the first connecting line 80 is grounded via the third output terminal 83 when the first output terminal 81 and the second output terminal 82 are electrically separated from each other.

[0062] Similar to the above, the third output circuit 32 is located at time T4', which according to the representation in Fig. 8D is slightly delayed from time T4, in the off state, when the input signal is sent to the third input terminal 73 at time T4 according to the representation in Fig. 8B is deactivated. According to the illustration in Fig. Furthermore, at time T5', which is slightly delayed from time T5, the first output circuit 12 and the second output circuit 22 are in the ON state when the ON input signal of the second input terminal 72 is received at time T5, as shown in the diagram. Fig. 8C is supplied. Consequently, the first connecting line 80 and the third output terminal 83 are electrically separated from each other after time T4'. According to the illustration in Fig. 8E the first output terminal 81 and the second output terminal 82 are also electrically connected to each other after time T5'.

[0063] If the input signal is then sent to the second input terminal 72 at time T6 according to the diagram in Fig. When 8A is deactivated, the first output circuit 12 and the second output circuit 22 are located as shown in the diagram. Fig. 8C is in the off state at time T6', which is slightly delayed from time T6. Furthermore, the third input terminal 73 is in the off state at time T7, as shown in the diagram. Fig. When an ON input signal is supplied to 8B, the third output circuit 32 is located at time T7', which is slightly different from time T7 according to the representation in Fig. 8D is delayed, in the on state. Consequently, the first output terminal 81 and the second output terminal 82 are after time T6' according to the representation in Fig. 8E are electrically separated from each other. In addition, the first connecting line 80 and the third output terminal 83 are electrically connected to each other after time T7".

[0064] The semiconductor relay module 2b according to the second embodiment can also be controlled in the same way as above by controlling the current of the input signal to the second input terminal 72 and to the third input terminal 73. Industrial application

[0065] According to this invention, it is possible to realize a semiconductor relay module that ensures stable operating characteristics and simplifies the design of printed circuit boards. REFERENCE MARK

[0066] 3: Power supply terminal, 4: Control terminal, 5: Control circuit, 11: First input circuit, 12: First output circuit, 10: First solid-state relay, 20: Second solid-state relay, 21: Second input circuit, 22: Second output circuit, 30: Third solid-state relay, 31: Third input circuit, 32: Third output circuit, 40: Fourth solid-state relay, 41: Fourth input circuit, 42: Fourth output circuit, 50: Fifth solid-state relay, 51: Fifth input circuit, 52: Fifth output circuit, 61: Sixth input circuit, 62: Sixth output circuit, 60: Sixth solid-state relay, 70: Packing, 71: First input terminal, 72: Second input terminal, 73: Third input terminal, 80: First connecting line, 81: First output terminal, 82: Second output terminal, 83: Third output terminal 84: Fourth output terminal, 85: Fifth output terminal, 86: Second connecting line

Claims

[1] Semiconductor relay module comprising: a first semiconductor relay (10), including a first input circuit (11) and a first output circuit (12); a second semiconductor relay (20), including a second input circuit (21) and a second output circuit (22); a third semiconductor relay (30), including a third input circuit (31) and a third output circuit (32); a fourth semiconductor relay(40), including a fourth input circuit (41) and a fourth output circuit (42); a fifth semiconductor relay (50), including a fifth input circuit (51) and a fifth output circuit (52); a sixth semiconductor relay (60), including a sixth input circuit (61) and a sixth output circuit (52); a package (70) designed to accommodate the first solid-state relay (10), the second solid-state relay (20) and the third solid-state relay (30) in the package (70); a first input terminal (71), a second input terminal (72) and a third input terminal (73) arranged in the package (70), wherein the first input terminal (71), the second input terminal (72) and the third input terminal (73) are each partially exposed to the outside of the package (70); a first output terminal (81), a second output terminal (82), a third output terminal (83), a fourth output terminal (84) and a fifth output terminal (85) arranged in the package (70), wherein the first output terminal (81), the second output terminal (82), the third output terminal (83), the fourth output terminal (84) and the fifth output terminal (85) are each partially exposed to the outside of the package (70); a first connecting line (80) for connecting the first output circuit (12) and the second output circuit (22) in the package (70), a second connecting line (86) for connecting the fourth output circuit (42) and the fifth output circuit (52) in the package (70), wherein the first input circuit (11) is connected to the first input terminal (71) and the second input terminal (72) in the package (70), wherein the second input circuit (21) is connected to the first input terminal (71) and the second input terminal (72) in the package (70), wherein the third input circuit (31) is connected to the first input terminal (71) or the second input terminal (72) in the package (70), wherein the third input circuit (31) is connected to the first input terminal (71) in the package (70), wherein the fourth input circuit (41) is connected to the first input terminal (71) and the second input terminal (72) in the package (70), wherein the fifth input circuit (51) is connected to the first input terminal (71) and the second input terminal (72) in the package (70), wherein the sixth input circuit (61) is connected to the first input terminal (71) or the second input terminal (72) in the package (70), wherein the sixth input circuit (61) is connected to the third input terminal (73) in the package (70), wherein the first output circuit (12) is connected to the first output terminal (81) and the first connecting line (80) in the package (70), wherein the second output circuit (22) is connected to the second output terminal (82) and the first connecting line (80) in the package (70), wherein the third output circuit (32) is connected to the third output terminal (83) and the first connecting line (80) in the package (70), wherein the fourth output circuit (42) is connected to the fourth output terminal (84) and the second connecting line (86) in the package (70), the fifth output circuit (52) is connected to the fifth output terminal (85) and the second connecting line (86) in the package (70); and the sixth output circuit (62) is connected to the third output terminal (83) and the second connecting line (86) in the package (70); wherein in a first state in which current flows through the first input terminal (71) and the second input terminal (72) without flowing through the third input terminal (73), the first output circuit (12) and the second output circuit (22) are designed to be switched on, the third output circuit (32) is designed to be switched off, the first output terminal (81) and the second output terminal (82) are designed to be electrically connected to each other, and the first connecting line (80) and the third output terminal (83) are designed to be electrically disconnected from each other, and wherein in a second state in which current flows through the third input terminal (73) without flowing through the first input terminal (71) and the second input terminal (72), the first output circuit (12) and the second output circuit (22) are designed to be switched off, the third output circuit (32) is designed to be switched on, the first output terminal (81) and the second output terminal (82) are designed to be electrically disconnected from each other, and the first connecting line (80) and the third output terminal (83) are designed to be electrically connected to each other. [2] Semiconductor relay module according to claim 1, wherein the first output circuit (12), the second output circuit (22), the fourth output circuit (42) and the fifth output circuit (52) are designed to be switched on in the first state and the third output circuit (32) and the sixth output circuit (62) are designed to be switched off, the first output terminal (81) and the second output terminal (82) are designed to be electrically connected to each other, the fourth output terminal (84) and the fifth output terminal (85) are designed to be electrically connected to each other, the first connecting line (80) and the third output terminal (83) are designed to be disconnected from each other and the second connecting line (86) and the third output terminal (83) are designed to be disconnected from each other, and the first output circuit (12), the second output circuit (22), the fourth output circuit (42) and the fifth output circuit (52) are designed to be switched off in the second state and the third output circuit (32) and the sixth output circuit (62) are designed to be switched on, the first output terminal (81) and the second output terminal (82) are designed to be electrically separated from each other, the fourth output terminal (84) and the fifth output terminal (85) are designed to be electrically separated from each other, the first connecting line (80) and the third output terminal (83) are designed to be connected together and the second connecting line (80) and the third output terminal (83) are designed to be connected together. [3] Semiconductor relay circuit comprising: the semiconductor relay module according to claim 2; a power supply terminal (3) which is connected to the first input terminal (71); a control terminal (4) and a control circuit (5) connected to the control terminal (4), wherein the first input terminal (71), the second input terminal (72) and the third input terminal (73) and the control circuit (5) are designed to switch between the first state and the second state depending on one of the input signals supplied to the control terminal (4).

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