STORAGE DEVICE WITH RESISTIVE DIRECT ACCESS STORAGE CELL WITH A BIPOLAR SELECTOR AND METHOD FOR SYMMETRICAL READ PROCESS AND METHOD FOR MANUFACTURING

Abstract

Storage device comprising: a resistive direct access memory element electrically connected to an extrinsic base region (204) of a bipolar transistor, wherein the extrinsic base region of the bipolar transistor is a lower electrode of the resistive direct access memory element; an intrinsic base region (110) located between an emitter region (620) and a collector region (620) of the bipolar transistor; an extrinsic base layer (204) acting as an extrinsic base region above the intrinsic base region, wherein the extrinsic base region is arranged above the intrinsic base region; and an epitaxially grown material (902) above the extrinsic base layer, wherein the epitaxially grown material has a faceted epitaxial layer having a triangular shape with an upward-facing apex.

Description

BACKGROUND

[0001] The present invention relates generally to the field of storage devices and in particular to the manufacture of a resistive direct access memory bit cell with bipolar selector and symmetrical read operation.

[0002] Emerging memory applications such as resistive random-access memory (RRAM) require bidirectional selection for efficient operation. Transistor selectors enable bidirectional operation but introduce some read asymmetry because, depending on the polarity of the supply voltage, the terminal of the field-effect transistor (or bipolar transistor) connected to the memory element can be the functional drain (or emitter) or the functional source (or collector). This problem can be solved by using additional transistors in the bit cell. However, using additional transistors results in a larger bit cell area.

[0003] In this context, several documents have already been published. Document US 2016 / 0079310A1 describes a selector-resistant RAM cell. The selector has a wall of a first polarity type formed in the substrate. Additionally, a region of a second polarity type is present above the wall in the substrate. Furthermore, first and second polarity types are located adjacent to the region of the second polarity type. The memory element also features a programmable resistive layer. Document US 5134454A further describes a self-aligned integrated bipolar transistor circuit with monocrystalline contacts. This circuit uses a vertical bipolar transistor with monocrystalline emitter, base, and collector contacts.Additionally, document US 10 374 039 B1 describes a resistive bipolar RAM structure with an improved field, integrated using FDSOI technology. This involves forming a resistive RAM stack on the surface of a faceted drain-side structure, which is located on one side of a functional gate structure.

[0004] Despite these technological advances, there remains a need to effectively access RRAMs without a plurality of bipolar transistors or read asymmetry—as mentioned above. The challenge lies in solving these problems. SUMMARY

[0005] This problem is solved by the storage device according to claim 1, the method for writing a storage device according to claim 8, and the method for creating a storage device according to claim 12. Further embodiments are specified in the respective dependent claims.

[0006] There is a need for alternative designs and techniques for forming a memory bit cell that can prevent asymmetry problems while simultaneously reducing the bit cell area. Therefore, embodiments of the present invention provide a memory device comprising a bipolar junction transistor (BJT) with an RRAM element integrated into an extrinsic base region of the BJT. The proposed structure and integration method, among other advantages, can provide symmetrical read operations and enable a small device footprint.

[0007] According to one embodiment, a storage device comprises a resistive direct-access memory element electrically connected to an extrinsic base region of a bipolar transistor, wherein the extrinsic base region of the bipolar transistor consists of an epitaxially grown material forming the lower electrode of the resistive direct-access memory element. The epitaxially grown material has a high dopant concentration and a triangular upper region.

[0008] According to another embodiment, a method for writing to a memory device includes applying a first voltage to a word line of the memory device, wherein the memory device comprises a resistive random-access memory element electrically connected to an extrinsic base of a bipolar transistor, the application of the first voltage forming a filament in the resistive random-access memory element. A second voltage with a polarity opposite to the first voltage can be applied to the word line to remove a portion of the filament in the resistive random-access memory element. A third voltage can be applied between the word line and a bit line or a select line to activate a read operation in the resistive random-access memory element.

[0009] According to yet another embodiment, a method for forming a memory structure comprises forming a resistive direct-access memory element that is electrically connected to an extrinsic base region of a bipolar transistor, wherein the extrinsic base region of the bipolar transistor consists of an epitaxially grown material that forms the lower electrode of the resistive direct-access memory element. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The following detailed description, which serves as an example, is best understood in conjunction with the accompanying drawings, which show: Fig. Figure 1 shows an exemplary one-transistor-one-resistor RRAM structure with a BJT selector, designed according to embodiments of the present disclosure; Fig. 2 shows a storage device in a first step during a manufacturing process according to an embodiment of the present disclosure in a cross-sectional view; Fig. 3 shows the storage device in a cross-sectional view after forming an extrinsic base layer according to an embodiment of the present disclosure; Fig. 4 shows the storage device after forming a hard mask layer, followed by structuring the extrinsic base layer and forming sidewall spacers, according to an embodiment of the present disclosure in a cross-sectional view; Fig. 5 shows the storage device in a cross-sectional view after the removal of a semiconductor layer according to an embodiment of the present disclosure; Fig. 6 shows the storage device according to an embodiment of the present disclosure in a cross-sectional view, which represents an ion implantation process; Fig. 7 shows the storage device in a cross-sectional view after forming an emitter area and a collector area according to another embodiment of the present disclosure; Fig. 8 shows the storage device in a cross-sectional view after the formation of a first dielectric layer according to an embodiment of the present disclosure; Fig. 9 shows the storage device in a cross-sectional view after removal of the hard mask layer according to another embodiment of the present disclosure; Fig. 10 shows the storage device in a cross-sectional view after the formation of a faceted epitaxial layer according to another embodiment of the present disclosure; and Fig. 11 shows the storage device in a cross-sectional view after forming an RRAM stack according to another embodiment of the present disclosure.

[0011] The drawings are not necessarily to scale. They are merely schematic representations and are not intended to depict specific parameters of the invention. The drawings are only meant to illustrate typical embodiments of the invention. In the drawings, the same reference numerals represent the same elements. DETAILED DESCRIPTION

[0012] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is understood that the disclosed embodiments serve only to illustrate the claimed structures and methods, which can be implemented in various forms. The invention can, however, be implemented in many different forms and should not be interpreted as being limited to the exemplary embodiments presented herein. Details of known features and techniques may have been omitted from the description in order to avoid making the presented embodiments unnecessarily unclear.

[0013] For the purposes of the following description, terms such as "top," "bottom," "right," "left," "vertical," "horizontal," "above," "below," and derivatives thereof refer to the disclosed structures and methods as oriented in the drawings. Terms such as "above," "above," "on top of," "positioned on," or "positioned on top of" mean that a first element, e.g., a first structure, is located on top of a second element, e.g., a second structure, with intermediate elements, e.g., an interface structure, potentially existing between the first and second elements. The term "direct contact" means that a first element, e.g., a first structure, and a second element, e.g., a second structure, are connected at the interface of the two elements without any intervening conductive, insulating, or semiconducting layers.

[0014] It is understood that, although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be restricted by these terms. These terms are used only to distinguish one element from another. Thus, a first element discussed below could be referred to as a second element without departing from the scope of the present concept.

[0015] To avoid any ambiguity in the presentation of embodiments of the present invention, some process steps or operations known in the art may be summarized in the following detailed description for illustrative purposes and, in some cases, not described in detail. In other cases, some processing steps or operations known in the art may not be described at all. It is understood that the following description focuses primarily on the special features or elements of various embodiments of the present invention.

[0016] Resistive random-access memory (RRAM) is one of the emerging non-volatile memory technologies, characterized by its simple structure, high density, low power consumption for read and write operations, and high read and write speeds. A selector device connected in series with the RRAM device can be used to improve the leakage current of RRAM devices and to create large-format, high-density crossbar memory arrays. RRAM is a type of memory that uses the switching of resistance under an electric field to record information, with the high and low resistance states corresponding to logical 0 and 1, respectively.

[0017] In conventional memory cells (BJT / RRAM and / or FET / RRAM), the gate-source voltage V is affected due to the voltage drop across the RRAM. GS (or base-emitter voltage V) BE) and thus the transistor driver current is smaller when the transistor terminal connected to the RRAM is the functional source (or functional collector) than when it is the functional drain (or functional emitter). This leads to the well-known problem of asymmetric read operation.

[0018] To solve this problem, embodiments of the present invention provide a memory cell structure comprising an RRAM element integrated into an extrinsic base region of a BJT, enabling symmetrical circuit operation. Fig. Figure 1 shows an exemplary one-transistor-one-resistor RRAM structure (1T1R-RRAM structure) with a BJT selector, designed according to embodiments of the present invention. In particular, in the circuit shown, the RRAM element is connected to a base terminal of the BJT. Accordingly, during the write operation, a filament can be formed in the RRAM element by applying a positive (or negative) voltage to a word line (WL) with respect to a bit line (BL) or select line (SL) for an npn BJT (pnp BJT), thereby driving the pn junction forward, whereas during the erase operation, filament removal can be performed by applying a negative (positive) voltage to a WL with respect to a BL or SL for an npn BJT (or pnp BJT), thereby driving the pn junction into a forward or avalanche breakdown.Voltage polarities opposite to those described above can also be used for filament formation and removal, but are generally less efficient.

[0019] With further reference to Fig. 1. The reading process is the same as with conventional memory cells; in contrast to conventional memory cells, the amplitude of the read stream I is READ However, regardless of the polarity of the voltage applied between BL and SL, which determines the direction of the flux of I READ This is because the RRAM element is connected to the base terminal of the BJT and not to its collector or emitter. For a read voltage V READ , which is connected between the WL and the BL or the SL line of a memory cell with an npn-BJT selector, the following applies: I B = (V READ -V BE ) / R RRAM , where V BE ≈ 0.7 V for silicon, I C = βI B and IE = I C + I B ≈ I C is, where I B V stands for the base current BE R stands for the base-emitter voltage. RRAM for the resistance of the resistive storage element, I C for the collector current, I E β represents the emitter current, β represents the BJT gain, and I READ = I C or I E is. In a memory cell with a pnp-BJT, V BE in the above expressions by V EB (Emitter-base voltage) is replaced. As can be seen from the expressions above, the amplitude depends on I. READ not deviating from its direction, thus eliminating the problem of asymmetric reading.

[0020] Therefore, embodiments of the present disclosure provide a storage device and a method for its fabrication, comprising a bipolar junction transistor (BJT) with an RRAM element integrated into an extrinsic base region of the BJT, enabling symmetrical read operations. The proposed structure and integration method can also enable a small device footprint and thus denser memory cells. An embodiment in which the storage device can be formed with an RRAM element integrated into the extrinsic base region of the BJT is described below with reference to the accompanying drawings. Fig. 1-11 described in detail.

[0021] With the following reference to Fig. 2 shows a storage device 100 in a first step during a manufacturing process according to an embodiment of the present disclosure in a cross-sectional view.

[0022] In this step of the fabrication process, the storage device 100 can comprise a semiconductor-on-insulator (SOI) substrate, in which a buried dielectric layer 108 (i.e., a buried oxide or BOX layer) separates a (base) semiconductor substrate 102 from an upper semiconductor layer 110. The components of the storage device 100 can then be formed from the upper semiconductor layer 110. In other embodiments, a bulk semiconductor substrate can be used in the fabrication process.

[0023] In this embodiment, the semiconductor-on-insulator substrate, formed from the semiconductor substrate 102, the buried dielectric layer 108, and the upper semiconductor layer 110, comprises a silicon-germanium-on-insulator substrate. Accordingly, the buried dielectric layer 108 insulates the upper semiconductor layer 110 from the semiconductor substrate 102. The semiconductor substrate 102 can be made of various known semiconductor materials, such as silicon, germanium, silicon-germanium alloys, and compound semiconductor materials (e.g., III-V and II-VI semiconductor materials). Non-restrictive examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide. In this embodiment, the semiconductor substrate 102 consists of single-crystal silicon (Si). Typically, the semiconductor substrate 102 can be approximately several hundred micrometers thick.The semiconductor substrate 102, for example, can have a thickness of approximately 600 micrometers to approximately 1000 micrometers and in between.

[0024] The buried dielectric layer 108 (i.e., the BOX layer) can be made of various known dielectric materials. Non-limiting examples include oxides, nitrides, and oxynitrides of silicon. Oxides, nitrides, and oxynitrides of other elements are also conceivable. Additionally, the buried dielectric layer 108 can comprise crystalline or non-crystalline dielectric material. Furthermore, the buried dielectric layer 108 can be produced using any of the known methods. Non-limiting examples include ion implantation, thermal oxidation or plasma oxidation or nitridation, chemical vapor deposition, and physical vapor deposition. According to one embodiment, the buried dielectric layer 108 can have a thickness of approximately 20 nm to approximately 200 nm and in between.

[0025] In some embodiments, the semiconductor substrate 102 and the upper semiconductor layer 110 can comprise either identical or different semiconductor materials with respect to chemical composition, dopant concentration, and crystallographic orientation, depending on the design requirements. In this embodiment, the upper semiconductor layer 110 consists of silicon-germanium (SiGe). In particular, the upper semiconductor layer 110 has a single-crystal SiGe layer with a germanium concentration of 20%. Methods for fabricating the upper semiconductor layer 110 are known in the art. Non-limiting examples include wafer bonding or thermal mixing. The upper semiconductor layer 110 can have a thickness of approximately 6 nm to approximately 100 nm and in between.

[0026] With the following reference to Fig. Figure 3 shows a cross-sectional view of the storage device 100 according to an embodiment of the present disclosure, illustrating the formation of an extrinsic base layer 204. The extrinsic base layer 204 is formed directly above the upper semiconductor layer 110. In this embodiment, the extrinsic base layer 204 comprises an epitaxially grown single-crystal silicon (Si) layer.

[0027] The terms "epitaxial growth" and / or "epitaxial deposition," as well as "epitactically formed" and / or "epitactically grown," refer to the growth of a semiconductor material (a crystalline material) on a deposition surface of another semiconductor material (a crystalline material), whereby the growing semiconductor material (crystalline top layer) exhibits essentially the same crystalline properties as the semiconductor material of the deposition surface (seed material). In the epitaxial deposition process, the chemical reactants supplied by the source gases are controlled, and the system parameters are adjusted, so that the depositing atoms reach the deposition surface of the semiconductor substrate with sufficient energy to move across the surface in such a way that the depositing atoms align with the crystal arrangement of the atoms of the deposition surface.Therefore, an epitaxially grown semiconductor material has essentially the same crystalline properties as the deposition surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on a {100}-oriented crystalline surface adopts a {100} orientation. In some embodiments, epitaxial growth and / or deposition processes are selective for formation on a semiconductor surface and generally do not deposit material on exposed surfaces, such as silicon dioxide or silicon nitride surfaces.

[0028] In some embodiments, the gas source for the deposition of epitaxial semiconductor material is a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer (Si layer) can be deposited from a silicon gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorosilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source selected from the group consisting of monogerman, digerman, halogerman, dichlorgerman, trichlorogerman, tetrachlorogerman, and combinations thereof. An epitaxial silicon-germanium layer can be formed using a combination of the aforementioned gas sources. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used.

[0029] According to the proposed embodiments, the extrinsic base layer 204 can function as an extrinsic base region for a subsequently formed bipolar transistor, while the upper semiconductor layer 110 can function as an intrinsic base region for the same bipolar transistor, as described in more detail below.

[0030] With the following reference to Fig. 4 shows the storage device 100 after forming a hard mask layer 310, followed by structuring the extrinsic base layer 204 and forming side wall spacers 312, according to an embodiment of the present disclosure in a cross-sectional view.

[0031] The hard mask layer 310 can comprise a dielectric material such as silicon dioxide, silicon nitride, silicon carbide, and the like, and can be deposited using any suitable deposition method known in the art. The process of structuring the extrinsic base layer 204 consists of steps known in the art, which generally include forming a pattern on a photoresist layer (not shown), transferring it to the hard mask layer 310, and using it to structure the underlying extrinsic base layer 204 by means of a suitable etching technique.

[0032] Following the structuring process, a spacer material can be deposited onto the storage device 100 and subsequently etched to form sidewall spacers 312, as described in Fig. 4 are designed. The final thickness of the 310 hard mask layer can vary in a range between approximately 50 nm and approximately 150 nm, although other thicknesses above or below this range can also be used if desired for a specific application.

[0033] The spacer material forming the sidewall spacers 312 can comprise an insulator material such as an oxide, nitride, oxynitride, silicon-carbon oxynitride, silicon-boron oxynitride, a low-k dielectric, or any combination thereof. Standard deposition and etching techniques can be used to form the sidewall spacers 312. For example, the spacer material can be etched using an anisotropic etching process to form the sidewall spacers 312. As is known, the spacer material forming the sidewall spacers 312 is removed from all horizontal surfaces of the storage device 100 during the etching process.

[0034] As can be seen in the figure, the sidewall spacers 312 are located on the sidewalls of the extrinsic base layer 204 and the hard mask layer 310. According to one embodiment, the width of the sidewall spacers 312 can vary in a range between approximately 6 nm and approximately 12 nm, although other thicknesses above or below this range can also be used if desired for a particular application.

[0035] With the following reference to Fig. Figure 5 shows a storage device 100 after the removal of the upper semiconductor layer 110 according to an embodiment of the present disclosure in a cross-sectional view. Known etching techniques can be used to remove the upper semiconductor layer 110. In an exemplary embodiment, a reactive ion etching process (RIE process) can be used to remove the upper semiconductor layer 110.

[0036] As illustrated in the figure, the final width of the upper semiconductor layer 110 after etching is equal to the width of the extrinsic base layer 204 plus the width of the sidewall spacers 312. In other words, the upper semiconductor layer 110 is removed until the outer surfaces of the upper semiconductor layer 110 are coplanar with the outer surfaces of the sidewall spacers 312, perpendicular to the semiconductor substrate 102.

[0037] The embodiments described below represent the formation of a bipolar junction transistor (BJT) in the storage device 100, for which the removed upper semiconductor layer 110 forms the base region. In particular, the embodiments described in Fig. Figures 6-7 illustrated the process steps of forming emitter and collector regions on opposite sides of the removed upper semiconductor layer 110 (i.e., the base region).

[0038] With the following reference to Fig. Figure 6 shows a cross-sectional view of the storage device 100 according to an embodiment of the present disclosure, depicting an ion implantation process. The ion implantation process is carried out before the formation of the emitter and collector regions of the BJT.

[0039] As is known, BJTs are electronic devices with three terminals, comprising three semiconductor regions: an emitter, a base, and a collector. A BJT generally includes two pn junctions: a collector-base junction and an emitter-base junction. A voltage applied across the emitter-base junction of a BJT controls the movement of charge carriers, generating a charge flow between the collector and emitter regions of the BJT.

[0040] An npn bipolar transistor comprises two regions of n-type semiconductor material, forming the emitter-collector region, and a region of p-type semiconductor material located between the two n-type regions, forming the base region of an npn BJT device. A pnp bipolar transistor has two regions of p-type semiconductor material, forming the emitter-collector region, and a region of n-type semiconductor material located between the two p-type regions, forming the base region of a pnp BJT device.

[0041] For illustrative purposes only, and without any intention of limitation, the bipolar transistor formed in the storage device 100 comprises an npn bipolar transistor. Accordingly, in this embodiment, the upper semiconductor layer 110 (i.e., the base region of the BJT) comprises a p-type semiconductor material such as silicon germanium (SiGe). As is known, the method for fabricating a pnp bipolar transistor comprises similar steps.

[0042] To form the emitter / collector regions of the BJT, an angled ion implantation is performed on opposite sides of the ablated upper semiconductor layer 110, as indicated by the arrows 510 in the figure. The ion implantation process provides a suitable polarity for the emitter and collector regions that are subsequently formed (in Fig. 7 shown). As mentioned above, embodiments of the present disclosure are illustrated by means of an npn bipolar transistor comprising two regions of n semiconductor material and one region of p semiconductor material situated between the two regions of n semiconductor material.

[0043] Thus, first ions corresponding to a first polarity are implanted onto a first side surface 602 and a second side surface 604 of the semiconductor layer 110. As can be understood, the first polarity (i.e., p-type or n-type) of the implanted ions is chosen depending on the type of bipolar transistor to be formed. Since an exemplary npn bipolar transistor is formed in this configuration, p-type dopants are used for the ion implantation.

[0044] As in Fig. As described in section 7, an emitter area 620 is formed by the first side surface 602 and a collector area 640 by the second side surface 604.

[0045] The procedure for forming emitter / collector regions for a pnp bipolar transistor is similar and involves selecting second ions corresponding to a second polarity, i.e., p-dopers, for the implantation process.

[0046] In a preferred embodiment, hot angular ion implantation can be performed on the storage device 100. In some embodiments, cold ion implantation can be performed to provide a suitable polarity for the first side surface 602 and the second side surface 604 of the semiconductor layer 110.

[0047] In configurations where a p-type emitter / collector region is formed, p-type dopants such as boron (B) can be implanted into the storage device 100 by performing a hot angular BF₂ ion implantation. In configurations where an n-type emitter / collector region is formed, n-type dopants such as phosphorus (P) or arsenic (As) can be implanted into the storage device 100 by performing a hot angular As or P ion implantation. A dopant concentration of p-type dopants (i.e., boron) can be approximately 1 × 10⁻⁶. 18 ions / cm² 3 up to approximately 9 or 10 20 ions / cm² 3 vary, while the dopant concentration of n-dopers (i.e., arsenic or phosphorus) is approximately 1 × 10 18 ions / cm² 3 up to approximately 9 or 10 20 ions / cm² 3 may vary.

[0048] With the following reference to Fig. Figure 7 shows the storage device 100 in a cross-sectional view after forming an emitter region 620 and a collector region 640 of the bipolar transistor according to an embodiment of the present disclosure.

[0049] The emitter region 620 and the collector region 640 can be formed, for example, by epitaxial growth of an in-situ doped single-crystal Si or SiGe layer from the first side face 602 and the second side face 604 of the semiconductor layer 110, respectively. In some embodiments, the emitter region 620 and the collector region 640 can comprise a similar material to the material forming the base region (i.e., the removed upper semiconductor layer 110), but with a slightly higher band gap.To grow epitaxial materials forming the emitter region 620 and the collector region 640, gaseous or liquid precursors can be used with low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atmospheric-pressure chemical vapor deposition (APCVD), gas-phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), or another suitable method. Epitaxial silicon, silicon-germanium, germanium, and / or carbon-doped silicon (Si:C) can be doped (in-situ doped) by adding dopants, either n-type (e.g., phosphorus or arsenic) or p-type (e.g., boron or gallium), depending on the transistor type, during deposition.

[0050] According to an exemplary embodiment, the emitter area 620 (e.g. n) +-Si emitter), the upper (base) semiconductor layer 110 (e.g. p-SiGe) and the collector region 640 (e.g. n + -Si collector) an npn bipolar transistor in the storage device 100.

[0051] With the following reference to Fig. Figure 8 shows the storage device 100 in a cross-sectional view after the formation of a first dielectric layer 710 according to an embodiment of the present disclosure.

[0052] Following the epitaxial growth of the emitter region 620 and the collector region 640, a first dielectric layer 710 is formed on the storage device 100, as shown in the figure. The first dielectric layer 710 can be formed, for example, by chemical vapor deposition (CVD) of a dielectric material. Non-restrictive examples of dielectric materials for forming the first dielectric layer 710 include silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, low-k silicon-based dielectrics, flowable oxides, porous dielectrics, or organic dielectrics, including porous organic dielectrics.

[0053] In some embodiments, after the deposition of the first dielectric layer 710, a planarization process, such as chemical-mechanical polishing (CMP), can be carried out on the storage device 100.

[0054] With the following reference to Fig. Figure 9 shows a cross-sectional view of the storage device 100 after removal of the hard mask layer 310 according to an embodiment of the present disclosure. In this embodiment, the hard mask layer 310 is selectively removed from the storage device 100 using a suitable isotropic etching process, e.g., an SC1 solution. Removing the hard mask layer 310 exposes the top surface of the extrinsic base layer 204, as shown in the figure.

[0055] With the following reference to Fig. Figure 10 shows the storage device 100 in a cross-sectional view after the formation of a faceted epitaxial layer 902 according to an embodiment of the present disclosure. At this point in the manufacturing process, the faceted epitaxial layer 902 comprises an epitaxially grown semiconductor material formed on the exposed top surface of the extrinsic base layer 204 by an epitaxial process similar to the process described above with respect to the emitter / collector regions 620, 610. Fig. It is similar to the one described in section 7.

[0056] As is known, the triangular shape seen in an upper part of the faceted epitaxial layer 902 can be a consequence of the different growth rates during the epitaxial deposition process, which are characteristic of each crystallographic orientation plane of the material forming the faceted epitaxial layer 902. In particular, the facets of the triangular faceted epitaxial layer 902 are characterized by <111> -planes connected. Thus, the pointed feature or upward-facing tip 904 of the triangular faceted epitaxial layer 902, which forms on the extrinsic base layer 204, intensifies an electric field at the upward-facing tip 904, which can thereby enable the controllability of the location for current-conducting filaments in a subsequently formed RRAM device, as described below with reference to Fig. 11 is described in detail. However, in some embodiments, the epitaxial material grown on the extrinsic base layer 204 may have a different shape than the triangular shape shown in the figure (e.g., a flat shape above).

[0057] In one embodiment, the faceted epitaxial layer 902 can be made from a semiconductor material similar to that from which the extrinsic base layer 204 is formed (i.e., single-crystal Si). In other embodiments, the faceted epitaxial layer 902 can be made from a different semiconductor material than that from which the extrinsic base layer 204 is formed. In a preferred embodiment, both the extrinsic base layer 204 and the faceted epitaxial layer 902 are formed with a high dopant concentration, which can be the same or different.

[0058] In one embodiment, the extrinsic base layer 204 can, for example, be doped silicon with a first concentration of p-dopers (e.g. boron) of up to 2 · 10 20 ions / cm² 3 comprise, while the faceted epitaxial layer 902 SiGe with a second concentration of p-dopers (e.g. boron) of up to 8 · 10 20 ions / cm² 3 may include.

[0059] BJT structures typically comprise an extrinsic base layer made of a polycrystalline material (e.g., poly-Si or poly-SiGe). As described above, embodiments of the present disclosure provide a single-crystal extrinsic base region with a triangular upper region exhibiting improved electrical properties, which serves as both a lower electrode for a subsequently formed RRAM element ( Fig. 11) as well as an extrinsic base area for the BJT.

[0060] Accordingly, the extrinsic base layer 204 and the faceted epitaxial layer 902 form the extrinsic base region of the BJT, with a lowermost part of the extrinsic base region defined by the extrinsic base layer 204 and an uppermost part of the extrinsic base region defined by the faceted epitaxial layer 902. The proposed design of the extrinsic base region requires a higher bandgap energy level (E G ) than the underlying intrinsic base region. In the illustrated embodiment, the higher band gap in the extrinsic base region is achieved, for example, by forming a heavily doped extrinsic silicon base region (i.e., the extrinsic base layer 204 and the faceted epitaxial layer 902) and an intrinsic base region with 20% SiGe (i.e., the upper semiconductor layer 110).

[0061] In some embodiments, the extrinsic base layer 204 and the faceted epitaxial layer 902 can be formed with a stepped or staggered doping profile. In such embodiments, the doping concentration increases as the material (e.g., Si) forming the extrinsic base layer 204 and the faceted epitaxial layer 902 grows epitaxially. In this way, the lowest part of the extrinsic base region (i.e., the extrinsic base layer 204) can have a lower dopant concentration than the uppermost part of the extrinsic base region (i.e., the faceted epitaxial layer 902). For better illustration, the extrinsic base layer 204 and the faceted epitaxial layer 902 are shown as two separate layers. However, it is understood that the extrinsic base layer 204 and the faceted epitaxial layer 902 can comprise a block of the same material.

[0062] With the following reference to Fig. Figure 11 shows the storage device 100 after forming an RRAM element according to an embodiment of the present disclosure in a cross-sectional view.

[0063] In this embodiment, a simplified RRAM stack is formed on the storage device 100. The RRAM stack comprises a lower electrode formed by the faceted epitaxial region 902, a switching layer 1010, an upper electrode layer 1012 formed above the switching layer 1010, and a metal filling 1014.

[0064] As illustrated in the figure, the interfacial layer 1010 is conformally deposited directly over the faceted epitaxial layer 902 using known deposition techniques such as atomic layer deposition (ALD). The interfacial layer 1010 essentially covers the uppermost part of the extrinsic base region of the BJT, which is formed by the faceted epitaxial layer 902.

[0065] The switching layer 1010 generally comprises a material with switchable resistance. In this embodiment, the switching layer 1010 comprises a high k-resistance oxide material. The switching layer 1010 serves as the dielectric layer for the RRAM structure and separates the faceted epitaxial layer 902 from the upper electrode layer 1012. As is known to those skilled in the art, the switching layer 1010 represents the insulating resistive switching layer (RS layer), which is the main component of the RRAM structure, as it serves as the storage medium. Non-limiting examples of suitable materials for the switching layer 1010 include titanium oxide (TiOx), tantalum oxide (TaOx), and hafnium oxide (HfOx). The thickness of the switching layer 1010 can be in the range of approximately 3 nm to approximately 10 nm and in between. In a preferred embodiment, the switching layer 1010 can have a thickness of 5 nm.

[0066] The top electrode layer 1012 is conformally deposited over the switching layer 1010. The top electrode layer 1012 can be deposited using known deposition techniques, such as ALD. The top electrode layer 1012 can consist of, but is not limited to, a titanium-nickel alloy (TiN alloy), a titanium-nickel-aluminum alloy (TiN-Al alloy), or a titanium-aluminum alloy, such as a titanium-aluminum-carbon alloy (TiAlC alloy). The top electrode layer 1012 can have a thickness in the range of approximately 3 nm to approximately 10 nm, although other thicknesses above or below this range can also be used if desired for a specific application.

[0067] Once the upper electrode layer 1012 is positioned above the switching layer 1010, a metal filling 1014 is deposited over the upper electrode layer 1012 using known deposition methods. After deposition of the metal filling 1014, the storage device 100 undergoes a CMP process to obtain the smooth and flat surface shown in the figure. The metal filling 1014 can be made of suitable metals with low resistivity, such as tungsten (W) or copper (Cu). The metal filling 1014 serves as an electrical conductor between the upper electrode layer 1012 and the subsequently formed metal contacts of the RRAM structure.

[0068] As illustrated in the figure, the bottom part of the extrinsic area (i.e., the extrinsic base layer 204) acts as the extrinsic base of the BJT, while the top part (i.e., the faceted epitaxial layer 902) acts as the bottom electrode of the RRAM structure.

[0069] Therefore, embodiments of the present invention provide a storage device and a method for its fabrication, comprising an RRAM structure integrated into the extrinsic base of a BJT structure, enabling a symmetrical read operation. In the proposed embodiments, the extrinsic base of the BJT particularly comprises a heavily doped faceted epitaxial region with a triangular shape and an upward-facing tip, which can simultaneously function as the lower electrode of the RRAM element and as the extrinsic base of the BJT.

[0070] The descriptions of the various embodiments of the present invention serve for illustrative purposes, but do not claim to be exhaustive or limited to the disclosed embodiments. The terminology used herein has been chosen to explain the principles of the embodiments, their practical application, or their technical improvement over technologies available on the market as clearly as possible.

Claims

[1] Storage device comprising: a resistive direct access memory element electrically connected to an extrinsic base region (204) of a bipolar transistor, wherein the extrinsic base region of the bipolar transistor is a lower electrode of the resistive direct access memory element; an intrinsic base region (110) located between an emitter region (620) and a collector region (620) of the bipolar transistor; an extrinsic base layer (204) acting as an extrinsic base region above the intrinsic base region, wherein the extrinsic base region is arranged above the intrinsic base region; and an epitaxially grown material (902) above the extrinsic base layer, wherein the epitaxially grown material has a faceted epitaxial layer having a triangular shape with an upward-facing apex. [2] Storage device according to claim 1, wherein the epitaxially grown material is the lower electrode of the resistive direct access storage element. [3] Storage device according to claim 1, wherein the extrinsic base layer and the epitaxially grown material above the extrinsic base layer comprise an epitaxially grown single-crystal semiconductor material with a high doping profile. [4] Storage device according to claim 3, wherein the epitaxially grown material has a higher dopant concentration than the extrinsic base layer. [5] Storage device according to claim 3, wherein the high doping profile further comprises a graduated doping profile. [6] Storage device according to claim 3, wherein the high doping profile further comprises a staggered doping profile. [7] Storage device according to claim 1, wherein the resistive random access memory stack comprises: the lower electrode, which is formed by the extrinsic base region of the bipolar transistor; a switching layer (1010) directly above the extrinsic base region; an upper electrode layer (1012) above the switching layer; and a metal filling (1014) above the upper electrode layer. [8] Method for writing to a storage device according to claim 1, comprising: Applying an initial voltage to a word line (WL) of the storage device; and Formation of a filament in the resistive direct access memory element as a result of applying the first voltage. [9] Method according to claim 8, further comprising: Applying a second voltage to the word line, wherein the second voltage has a polarity opposite to the first voltage and wherein the second voltage removes a portion of the filament in the resistive direct access memory element. [10] Method according to claim 9, further comprising: Applying a third voltage between the word line and a bit line (BL) and / or a selection line, wherein the application of the third voltage activates a read operation in the resistive direct access memory element. [11] Method according to claim 8, wherein the extrinsic base of the bipolar transistor has a triangular upper region forming a lower electrode of the resistive direct access memory element. [12] Method for forming a storage structure comprising: Forming a resistive direct access memory element electrically connected to an extrinsic base region of a bipolar transistor, wherein the extrinsic base region of the bipolar transistor is a lower electrode of the resistive direct access memory element; Forming an intrinsic base region located between an emitter region and a collector region of the bipolar transistor; Forming an extrinsic base layer, which acts as an extrinsic base region, over the intrinsic base region, wherein the extrinsic base region is arranged over the intrinsic base region; and Formation of an epitaxially grown material over the extrinsic basal layer, wherein the epitaxially grown material has a faceted epitaxial layer having a triangular shape with an upward-pointing tip. [13] Method according to claim 12, wherein the epitaxially grown material is the lower electrode of the resistive direct access memory element. [14] Method according to claim 12, wherein the extrinsic base layer and the epitaxially grown material above the extrinsic base layer comprise an epitaxially grown single-crystal semiconductor material with a high doping profile. [15] Method according to claim 12, wherein the epitaxially grown material has a higher dopant concentration than the extrinsic base layer.

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