RECOMMEND CHANGES WHEN DESIGNING AN INTEGRATED CIRCUIT USING RULE-BASED FAULT ANALYSIS

Abstract

A computer-implemented method, system, and computer program product for recommending design changes when designing a digital integrated circuit. An analysis of the digital integrated circuit to be designed is performed, the result of such analysis being the identification and storage of violations. A stored violation, e.g., a cross-domain, cross-hierarchy, and / or multi-cycle violation, can then be analyzed to identify a root cause of the violation using a rule. Such a rule can be used to rank various defects in the cross-domain, cross-hierarchy, and / or multi-cycle violation of the digital integrated circuit. A design change when designing the digital integrated circuit can then be recommended based on the identified root cause of the violation.In this way, the root cause of defects in digital integrated circuit design can be effectively identified through offline analysis of cross-domain, cross-hierarchical and / or multi-cycle violations using a rule-based approach.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to designing integrated circuits, and more particularly to recommending changes in the design of an integrated circuit using rule-based failure analysis (e.g., timing, noise, power, voltage). BACKGROUND

[0002] Integrated circuit design, or IC design, is a branch of electrical engineering and encompasses the specialized logic and circuit design techniques required to design integrated circuits, or ICs. ICs consist of miniaturized electronic components that are incorporated into an electrical network on a monolithic semiconductor substrate using photolithography.

[0003] IC design can be divided into two broad categories: digital and analog IC design. Digital IC design involves the manufacture of components such as microprocessors, FPGAs, memory (RAM, ROM, and Flash), and digital ASICs. The focus of digital IC design is on logical correctness, maximizing circuit density, and arranging circuits to efficiently propagate clock and timing signals. Compared to digital IC design, analog IC design focuses on designing power ICs and RF (radio frequency) ICs. Furthermore, analog IC design is used in the design of operational amplifiers, linear regulators, phase-locked loops, oscillators, and active filters. Furthermore, analog IC design is more concerned with the physics of semiconductor devices such as amplification, matching, power dissipation, and resistance.

[0004] Modern ICs are extremely complicated. An average desktop computer chip has over 1 billion transistors. The rules governing what can and cannot be manufactured are also extremely complex. Common IC processes have over 500 rules. Furthermore, because the manufacturing process itself is not entirely predictable, designers must consider its statistical nature. The complexity of a modern IC design, along with market pressure to produce designs quickly, leads to the extensive use of automated design tools, such as electronic design automation (EDA), in the IC design process. For example, the EDA software tool can be used to design, test, and verify the instructions the IC is supposed to execute.

[0005] When designing digital integrated circuits, the design is tested and analyzed using various EDA tools to identify various violations, such as timing or noise errors. A "timing error" is a fault in a process or part of a process in a synchronous distributed or real-time system that violates specified limits for execution, message delivery, clock drift rate, or clock skew. A "noise error" is unexpected voltage fluctuations due to a variety of factors, such as signal transitions to adjacent wires, that can potentially cause interference or damage to electrical circuits.

[0006] When such simulated errors occur (e.g., timing and noise errors), the developer attempts to identify the root cause of these errors. However, such analysis (also called "triage") is time-consuming and difficult.

[0007] Furthermore, such errors (e.g., timing and noise errors) may be related to each other. However, such relationships are difficult to assess, making it difficult to identify the root cause of such errors.

[0008] Furthermore, such errors (e.g., timing and noise errors) may involve integration-level problems between components located at different hierarchical levels of the integrated circuit. For example, a multi-cycle path may span many components located at different hierarchical levels of the integrated circuit. Analyzing such problems may involve analyzing each of the multiple hierarchical components individually, which is extremely challenging, making it difficult to identify the root cause of such errors.

[0009] Consequently, there is currently no way to effectively identify the root cause of errors such as timing and noise errors when designing digital integrated circuits. SUMMARY

[0010] In one embodiment of the present disclosure, a computer-implemented method for recommending design changes when designing a digital integrated circuit comprises performing an analysis of the digital integrated circuit in which a plurality of violations are identified. The method further comprises analyzing one of the plurality of violations to identify a root cause of the one of the plurality of violations, including a cross-domain, a cross-hierarchy, and / or a multi-cycle violation, using a rule. The method further comprises recommending a design change when designing the digital integrated circuit for the one of the plurality of violations based on the identified root cause.

[0011] In this way, root causes of defects such as timing and noise errors in digital integrated circuit design are effectively identified through offline analysis of cross-domain (e.g., timing and noise errors), cross-hierarchy (at multiple levels of integrated circuit design) and / or multi-cycle (multi-cycle path spanning many components) violations of the digital integrated circuit using a rule-based approach.

[0012] Another embodiment of the present disclosure features a computer program product for recommending design changes when designing a digital integrated circuit, the computer program product comprising one or more computer-readable storage media having program code embodied therein, the program code comprising programming instructions for performing an analysis of the digital integrated circuit in which a plurality of violations are identified. The program code further includes the programming instructions for analyzing one of the plurality of violations to identify a root cause of the one of the plurality of violations, including a cross-domain, a cross-hierarchy, and / or a multi-cycle violation, using a rule.The program code additionally includes programming instructions for recommending a design change in the design of the digital integrated circuit for the one violation from the plurality of violations based on the identified root cause.

[0013] In this way, root causes of defects such as timing and noise errors in digital integrated circuit design are effectively identified through offline analysis of cross-domain (e.g., timing and noise errors), cross-hierarchy (at multiple levels of integrated circuit design) and / or multi-cycle (multi-cycle path spanning many components) violations of the digital integrated circuit using a rule-based approach.

[0014] In another embodiment of the present disclosure, a system comprises a memory for storing a computer program for recommending design changes when designing a digital integrated circuit, and a processor connected to the memory. The processor is configured to execute program instructions of the computer program that comprise performing an analysis of the digital integrated circuit in which a plurality of violations are identified. The processor is further configured to execute the programming instructions of the computer program that comprise analyzing one of the plurality of violations to identify a root cause of the one of the plurality of violations, including a cross-domain, a cross-hierarchy, and / or a multi-cycle violation, using a rule.The processor is further configured to execute the program instructions of the computer program that recommend a design change in designing the digital integrated circuit for the one violation of the plurality of violations based on the identified root cause.

[0015] In this way, root causes of defects such as timing and noise errors in digital integrated circuit design are effectively identified through offline analysis of cross-domain (e.g., timing and noise errors), cross-hierarchy (at multiple levels of integrated circuit design) and / or multi-cycle (multi-cycle path spanning many components) violations of the digital integrated circuit using a rule-based approach.

[0016] The foregoing description has outlined, rather generally, the features and technical advantages of one or more embodiments of the present disclosure in order to facilitate understanding of the following detailed description of the present disclosure. Additional features and advantages of the present disclosure are described below, which may be subject to the claims of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] A better understanding of the present disclosure can be achieved when the following detailed description is considered in conjunction with the following drawings, in which: Fig. 1 shows a data transmission system for carrying out the principles of the present disclosure according to an embodiment of the present disclosure; Fig. 2 shows a representation of the software components used by the IC design development system to identify the root cause of digital integrated circuit design defects through offline analysis of cross-domain, cross-hierarchy, and / or multi-cycle violations of the digital integrated circuit using a rule-based approach, according to an embodiment of the present disclosure; Fig. 3 shows the pseudocode of an exemplary rule according to an embodiment of the present disclosure; Fig. 4 shows the steps of an exemplary rule used to identify a root cause of a violation, e.g., a timing error, according to an embodiment of the present disclosure; Fig. 5 shows the pseudocode for an exemplary rule for identifying a root cause of a cross-domain, cross-hierarchy, and multi-cycle violation of the digital integrated circuit according to an embodiment of the present disclosure; Fig. 6 shows an embodiment of the present disclosure of the hardware configuration of the IC design development system representative of a hardware environment for carrying out the present disclosure; and Fig. 7 shows a flowchart of a method for recommending changes in the design of an integrated circuit based on effectively identifying the root cause of errors in the design of the digital integrated circuit through an offline analysis of cross-domain, cross-hierarchy and / or multi-cycle violations of the digital integrated circuit using a rule-based approach according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] As mentioned in the Background section, when designing a digital integrated circuit, the design is tested and analyzed using various EDA tools to identify various violations, such as timing or noise errors. A timing error is a fault in a process or part of a process in a synchronous distributed or real-time system that violates specified limits for execution, message delivery, clock drift rate, or clock skew. A noise error is unexpected voltage fluctuations due to a variety of factors, such as signal transitions to adjacent wires, that can potentially cause interference or damage to electrical circuits.

[0019] When such simulated errors occur (e.g., timing and noise errors), the developer attempts to identify the root cause of these errors. However, such analysis (also called "triage") is time-consuming and difficult.

[0020] Furthermore, such errors (e.g., timing and noise errors) may be related to each other. However, such relationships are difficult to assess, making it difficult to identify the root cause of such errors.

[0021] Furthermore, such errors (e.g., timing and noise errors) may involve integration-level problems between components located at different hierarchical levels of the integrated circuit. For example, a multi-cycle path may span many components located at different hierarchical levels of the integrated circuit. Analyzing such problems may involve analyzing each of the multiple hierarchical components individually, which is extremely challenging, making it difficult to identify the root cause of such errors.

[0022] Consequently, there is currently no way to effectively identify the root cause of errors such as timing and noise errors when designing digital integrated circuits.

[0023] The embodiments of the present disclosure provide a means for effectively identifying the root causes of digital integrated circuit design errors through offline analysis of cross-domain (e.g., timing and noise errors), cross-hierarchy (at multiple levels of the integrated circuit design), and / or multi-cycle (multi-cycle path spanning many components) violations of the digital integrated circuit using a rule-based approach, as described in detail below.

[0024] In some embodiments of the present disclosure, it comprises a computer-implemented method, a system, and a computer program product for recommending design changes when designing a digital integrated circuit. In one embodiment of the present disclosure, an analysis of the digital integrated circuit to be designed is performed, wherein the result of such analysis is to identify and store violations. The term "violation" as used herein refers to the performance of a component or system when designing the digital integrated circuit that does not conform to a required specification, as set by the designer, resulting in a failure (e.g., noise failure, timing failure, power failure, etc.).In one embodiment, such analysis may include verifying and simulating the design of the digital integrated circuit based on various properties or parameters, e.g., voltage transfer characteristics, noise margins, output load factor, power dissipation, propagation delays, and the interdependencies between these parameters. In one embodiment, such analysis ensures that it conforms to functional or parametric specifications that may be provided by the designer. A stored violation may then be analyzed to identify a root cause of the violation, including a cross-domain, cross-hierarchy, and / or multi-cycle violation, using a rule. The term "cross-domain" as used herein encompasses multiple fault types, e.g., timing faults and noise faults.The term "cross-hierarchy" as used herein refers to multiple levels of the integrated circuit design. The term "multi-cycle" as used herein refers to a multi-cycle path spanning many components. In one embodiment, such violations are analyzed using the rules offline. In one embodiment, such rules are parameterized. In one embodiment, the cross-domain, cross-hierarchy, and / or multi-cycle violation, e.g., caused by timing and noise errors, is identified by an offline analysis of the digital integrated circuit violation using a rule-based approach.Such a rule-based approach includes rules aimed at classifying different faults of cross-domain, cross-hierarchy and / or multi-cycle violations, which are based on analyzing the design of the digital integrated circuit using an integrated circuit design tool (e.g., Eagle). ® , KiCAD ® , Pulsonix, Multisim ® , Altium Designer ®etc.) have been identified. The term "triage" as used herein refers to analyzing errors, e.g., to determine the root cause of such errors. In one embodiment, these rules refer to cross-domain, cross-hierarchy, and / or multi-cycle violations, e.g., by using parameterized thresholds involving multiple domains. Furthermore, these rules may refer to a violation affecting a path traversing a hierarchy in the design of the digital integrated circuit. The term "hierarchy" as used herein refers to the levels of the digital integrated circuit, where each level includes one or more components of the digital integrated circuit. Furthermore, these rules may refer to a violation affecting a multi-cycle path spanning many components.A design change during design of the digital integrated circuit may then be recommended based on the identified root cause of the violation, e.g., a cross-domain violation. In one embodiment, such a recommendation is based on using a data structure (e.g., a table) that lists design recommendations based on the identified root causes. In one embodiment, such recommendations may be generated using a model (mathematical model) trained using a machine learning algorithm to provide a recommendation based on the identified root cause of the violation, e.g., a cross-domain violation. In one embodiment, the recommended design change is implemented during design of the digital integrated circuit.In this way, the root causes of defects such as timing and noise errors in digital integrated circuit design are effectively identified through offline analysis of cross-domain (e.g., timing and noise errors), cross-hierarchy (at multiple levels of the integrated circuit design) and / or multi-cycle (multi-cycle path spanning many components) violations of the digital integrated circuit using a rule-based approach.

[0025] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, one skilled in the art will recognize that the present disclosure may be practiced without these specific details. In other instances, well-known circuits have been presented in block diagram form in order to avoid obscuring the present disclosure with unnecessary detail. For the most part, details concerning aspects of timing and the like have been omitted because such details are not necessary to develop a thorough understanding of the present disclosure and would be apparent to one skilled in the art.

[0026] As for the figures in detail, Fig. 1 shows an embodiment of the present disclosure of a data transmission system 100 for carrying out the principles of the present disclosure. The data transmission system 100 comprises the data processing units 101A to 101C (in Fig. 1, respectively referred to as "data processing unit A," "data processing unit B," and "data processing unit C"), which are connected to an IC design development system 102 via a network 103. The data processing units 101A to 101C may be collectively or individually referred to as data processing units 101 and data processing unit 101, respectively.

[0027] The computing device 101 may be any type of computing device (e.g., portable computing device, personal digital assistant (PDA), laptop computer, mobile device, tablet PC, smartphone, mobile phone, navigation device, game console, desktop computer system, workstation, internet device, and the like) configured to connect to the network 103 and thus to communicate with other computing devices 101 and the IC design development system 102. It should be noted that both the computing device 101 and the user of the computing device 101 may be identified by the element number 101.

[0028] The network 103 may, for example, be a local area network, a wide area network, a wireless wide area network, a circuit-switched telephone network, a GSM (Global System for Mobile Communications) network, a WAP (Wireless Application Protocol) network, a WLAN network, a network according to the IEEE 802.11 standard, various combinations thereof, etc. Other networks, the description of which is omitted here for the sake of brevity, may also be used in connection with the system 100 of Fig. 1 without departing from the scope of the present disclosure.

[0029] The IC design development system 102 identifies the root causes of errors such as timing and noise errors in digital integrated circuit design through offline analysis of cross-domain (e.g., timing and noise errors), cross-hierarchy (at multiple levels of the integrated circuit design), and / or multi-cycle (multi-cycle path spanning many components) violations of the digital integrated circuit using a rule-based approach, as described in detail below.

[0030] In one embodiment, the IC design development system 102 is a system used, for example, by developers (e.g., users of the computing devices 101) when designing digital integrated circuits (e.g., microprocessors, memories, digital ASICs (application-specific integrated circuits), FPGAs (field programmable gate arrays), etc.). In one embodiment, the IC design development system 102 is configured to analyze the design for violations when designing integrated circuits (ICs). The term "violation" as used herein refers to the performance of a component or system when designing the digital integrated circuit that does not conform to a required specification, as specified by the designer, resulting in a failure (e.g., noise failure, timing failure, power failure, etc.).In one embodiment, such violations include "cross-domain," "cross-hierarchy," and / or "multi-cycle" violations. The term "cross-domain" as used herein encompasses multiple error types, e.g., timing errors and noise errors. The term "cross-hierarchy" as used herein refers to multiple levels of the integrated circuit design. The term "multi-cycle" as used herein refers to a multi-cycle path spanning many components. In one embodiment, such violations are stored in a database, e.g., database 104, connected to the IC design development system 102. Further description of analyzing the digital integrated circuit design for violations is provided below.

[0031] As described above, the IC design development system 102 is configured to identify the root causes of defects such as timing and noise errors in digital integrated circuit design through offline analysis of cross-domain (e.g., timing and noise errors), cross-hierarchy (at multiple levels of the integrated circuit design), and / or multi-cycle (multi-cycle path spanning many components) violations of the digital integrated circuit using a rule-based approach.Such a rule-based approach comprises rules that can be provided by a person skilled in the art and that aim at classifying different cross-domain, cross-hierarchical and / or multi-cycle violation errors based on analyzing the design of the digital integrated circuit using an integrated circuit design tool (e.g., Eagle). ® , KiCAD ® , Pulsonix, Multisim ® , Altium Designer ®etc.) have been identified. The term "triage" as used here refers to analyzing faults, e.g., to determine the root cause of such faults. In one embodiment, these rules relate to cross-domain, cross-hierarchy, and / or multi-cycle violations, e.g., by using parameterized thresholds involving multiple domains. Such rules may, for example, relate to a cross-domain, cross-hierarchy, and multi-cycle violation using parameterized thresholds involving noise and timing data. One of the rules could, for example, be a noise and timing rule for the NIOF (noise impact on function) violation.Such a rule can be used to analyze the relationship between noise and timing data, where nets (wires connecting components) failing due to a violation related to the impact of noise on a function with high aggressor coupling (noise injected from other sources) due to noise data are differently classified based on a time buffer (the margin by which a timing requirement is met or missed) determined from timing data using user-defined thresholds. Such cross-domain, cross-hierarchical, and multi-cycle triage is important because it more effectively identifies the root cause, which in turn leads to a better recommendation for resolving such a root cause.For example, the design approach to correct a noise error may change based on the timing buffer (timing data).

[0032] Furthermore, in one embodiment, the IC design development system 102 recommends a design change when designing the digital integrated circuit based on the identified root cause of a failure. For example, in one embodiment, the IC design development system 102 uses a data structure (e.g., a table) that lists design recommendations based on the identified root causes.For example, if the rule indicates that the root cause of the NIOF violation was a coupling error at the NAND logic gate identified in the design by 100122, the IC design development system 102 may recommend replacing the NAND logic gate (small NAND logic gate) identified in the design by the number 100122 with the NAND logic gate (large NAND logic gate) identified by the number 102233 and receiving digital signals identified by the numbers 122233, 132343, and 122343. In one embodiment, such a data structure is populated with data by a person skilled in the art. In one embodiment, such data structures are located in a storage unit (e.g., memory, hard disk drive) of the IC design development system 102.

[0033] In one embodiment, such recommendations may be generated using a model (mathematical model) trained using a machine learning algorithm to provide a recommendation based on the identified root cause of the violation, as described in detail below.

[0034] The following is in connection with Fig. 2 provides a description of the software components of the IC design development system 102 used to identify the root causes of errors such as timing and noise errors in the design of digital integrated circuits through an offline analysis of cross-domain (e.g., timing and noise errors), cross-hierarchy (at multiple levels of the integrated circuit design), and / or multi-cycle (multi-cycle path spanning many components) violations of the digital integrated circuit using a rule-based approach. A description of the hardware configuration of the IC design development system 102 is provided below in connection with Fig. 6 provided.

[0035] The system 100 is not limited in its scope to a specific network architecture. The system 100 may include any number of data processing units 101, IC design development systems 102, networks 103, and databases 104.

[0036] The following is in connection with Fig. 2 provides a description of the software components used by the IC design development system 102 to identify the root causes of errors such as timing and noise errors in digital integrated circuit design through an offline analysis of cross-domain (e.g., timing and noise errors), cross-hierarchy (at multiple levels of the integrated circuit design), and / or multi-cycle (multi-cycle path spanning many components) violations of the digital integrated circuit using a rule-based approach.

[0037] Fig. 2 is an illustration of the software components implemented by the IC design development system 102 ( Fig. 1) to identify the root causes of defects such as timing and noise errors in digital integrated circuit design through an offline analysis of cross-domain (e.g., timing and noise errors), cross-hierarchy (at multiple levels of the integrated circuit design) and / or multi-cycle (multi-cycle path spanning many components) violations of the digital integrated circuit using a rule-based approach.

[0038] With reference to Fig. 2 in conjunction with Fig. 1, the IC design development system 102 includes an analysis component 201 configured to perform an analysis of the digital integrated circuit design. Such an analysis may include verifying and simulating the digital integrated circuit design based on various properties or parameters, e.g., voltage transfer characteristics, noise margins, output load factor, power dissipation, propagation delays, and the interdependencies between these parameters.

[0039] In one embodiment, analysis component 201 analyzes the digital integrated circuit design to ensure that it conforms to the functional or parametric specifications that may be provided by the designer (e.g., the user of computing device 101). For example, analysis component 201 may analyze the digital integrated circuit design to determine whether each logic gate functions according to its truth table specification. In another example, analysis component 201 determines whether the electrical paths in the design are identical to those in the device.

[0040] Furthermore, in one embodiment, analysis component 201 performs parametric tests on the digital integrated circuit design based on the analysis of a continuous circuit parameter. For example, analysis component 201 may determine whether the device's steady-state power demand is excessive. In another example, analysis component 201 determines whether the effects of process variations are within a tolerance. In another example, analysis component 201 determines whether performance requirements (e.g., delay errors) are met.

[0041] Furthermore, in one embodiment, parametric testing may include analyzing continuous variables of circuits, e.g., noise margins, propagation delay, maximum clock frequencies, steady-state current, transient signal behavior, etc. In one embodiment, such parameters are checked at a range of different temperatures and supply voltages.

[0042] In one embodiment, the analysis component 201 uses various software tools (e.g., integrated circuit design (EDA) tools) to perform such analysis of the digital integrated circuit design, including, but not limited to, Cadence ® , Synopsis ® , Mentor Graphics ® , Atrenta etc.

[0043] When performing such an analysis of a digital integrated circuit design, violations may be detected. As used herein, "violation" refers to the performance of a component or system in the design of the digital integrated circuit that does not conform to a required specification, as defined by the designer, resulting in a failure (e.g., noise error, timing error, power failure, etc.). In one embodiment, such violations include "cross-domain," "cross-hierarchy," and / or "multi-cycle" violations.

[0044] The term "cross-domain" as used here encompasses several error types, such as timing errors and noise errors. A "timing error" as used here refers to a fault in a process or part of a process in a synchronous distributed or real-time system where specified limits for execution, message delivery, clock drift rate, or clock skew are not met. A "noise error" as used here refers to unexpected voltage fluctuations due to a variety of factors, such as signal transitions to adjacent wires, that can potentially cause noise or damage to electrical circuits. The term "cross-hierarchy" as used here refers to multiple levels of the integrated circuit design. The term "multi-cycle" as used here refers to a multi-cycle path spanning many components.

[0045] In one embodiment, such violations are identified as a result of the analysis performed by the software tools described above (e.g., EDA tools). EDA tools can, for example, identify logical-level errors corresponding to timing errors, noise errors, power outages, etc.

[0046] In one embodiment, such violations are stored, e.g., in database 104. In one embodiment, such stored violations also include metadata comprising parameters used by analysis component 201 to determine an occurred violation. Furthermore, such metadata includes the relevant data (e.g., noise limits, propagation delay, maximum clock frequencies, steady-state current, transient signal behavior) used by analysis component 201 to decide on a violation.

[0047] In one embodiment, the IC design development system 102 further comprises a rules control component 202 configured to analyze a stored violation to identify a root cause of the violation's failures (e.g., cross-domain, cross-hierarchy, and / or multi-cycle violation) using a rules-based approach. In one embodiment, such violations are analyzed using the rules offline. In one embodiment, such rules are parameterized, as described below.

[0048] In one embodiment, the rule control component 202 identifies the root causes of errors such as timing and noise errors in the design of digital integrated circuits by performing an offline analysis of cross-domain (e.g., timing and noise errors), cross-hierarchy (at multiple levels of the integrated circuit design), and / or multi-cycle (multi-cycle path spanning many components) violations of the digital integrated circuit using a rule-based approach. Such a rule-based approach includes rules that can be provided by a person skilled in the art and that aim to classify different errors of a violation (e.g., cross-domain, cross-hierarchy, and / or multi-cycle violation) based on analyzing the design of the digital integrated circuit using an integrated circuit design tool (e.g., Eagle® , KiCAD ® , Pulsonix, Multisim ® , Altium Designer ®etc.) have been identified. The term "triage" as used herein refers to analyzing faults, e.g., to determine the root cause of such faults. In one embodiment, these rules relate to cross-domain, cross-hierarchy, and / or multi-cycle violations, e.g., by using parameterized thresholds involving multiple domains. Such rules may, for example, relate to a cross-domain, cross-hierarchy, and multi-cycle violation using parameterized thresholds involving noise and timing data. For example, one of the rules could be a noise and timing rule for the NIOF violation.Such a rule can be used to analyze the relationship between noise and timing data, where nets (wires connecting components) that fail due to a violation related to the impact of noise on a function with high aggressor coupling (noise injected from other sources) due to noise data are differently classified based on a timing margin (the margin by which a timing requirement is met or missed) determined from timing data using user-defined thresholds. Such cross-domain, cross-hierarchical, and multi-cycle classification is important because the root cause is more effectively identified, which in turn leads to a better recommendation for resolving such a root cause. For example, the design approach for resolving a noise failure may change based on the timing margin (timing data).

[0049] In one embodiment, database 104 stores a collection of rules to identify the root cause of violations. Such rules are associated with specific violations. For example, a rule may be used to identify the root cause of a NIOF violation. Rule control component 202 then identifies a rule to determine the root cause of a violation based on the violation identified by analysis component 201. In one embodiment, such rules and their associated violations are stored in a data structure, such a data structure being stored in database 104 or in a storage unit (e.g., memory, hard disk unit) of IC design development system 102. In one embodiment, such a data structure is populated with data by a person skilled in the art.

[0050] In one embodiment, to analyze the violation using the corresponding rule, various parameters and data related to the violation may be retrieved from the rule control component 202. As explained above, in one embodiment, such violations include metadata comprising parameters used by the analysis component 201 to determine a violation that has occurred, as well as the relevant data (e.g., noise limits, propagation delay, maximum clock frequencies, steady-state current, transient signal behavior) used by the analysis component 201 to decide on a violation. These parameters and data may be used by the rule control component 202 to identify the root cause of the violation. An example of such a rule is described in Fig. 3 provided.

[0051] Fig. 3 shows the pseudocode of an exemplary rule 300 according to an embodiment of the present disclosure.

[0052] As in Fig. 3, rule 300 can be saved in a file, e.g., a JSON file (JSON - JavaScript Object Notation). Furthermore, rule 300 includes, as shown in Fig. 3, a rule name 301, the rule parameters 302, an annotation name 303, and a flag for outputting the information 304. The term "rule parameters" 302, as used herein, refers to the parameters used to identify the root cause of the violation associated with such a rule. The term "annotation name" 303, as used herein, refers to the name of the annotation corresponding to the added syntactical metadata. The term "flag" 304, as used herein, refers to a Boolean variable that indicates when a condition (identifying a root cause of the violation) is present in a program. For example, if flag 304 is set to "true," this means that the root cause of the violation has been identified by rule 300 and that a report (e.g., a text report) providing this information should be output.In one embodiment, such a report is issued to the developer, e.g., to the developer of the data processing unit 101. If, on the other hand, the flag 304 is set to "false," this means that the root cause of the violation was not identified by the rule 300 and that a report providing such information should not be issued.

[0053] Another representation of a rule that identifies a root cause of a violation such as a timing error is shown in Fig. 4 provided.

[0054] Fig. 4 shows the steps of an example rule 400 used to identify a root cause of a violation such as a timing error according to an embodiment of the present disclosure.

[0055] As in Fig. As shown in Figure 4, such a rule 400 uses the best delay, no net delay, and timing slack (BDNDS) algorithm. For example, the first step 401 involves retrieving the unit net delay (unet_dly) and the worst timing slack in the fastest clock phase (slk_fastclk) for each root net in a path. The second step 402 involves deriving the timing slack without unit net delay (nodly_unet_slk). The third step 403 involves deriving the best delay of the net (wire connecting the components) (unet_bdly). The fourth step 404 involves deriving the timing slack for the best unit net delay (bdly_unet_slk). The fifth step 405 involves the evaluation criteria, which can be provided by a user, and the classification of the nets based on the required measure.For example, based on the evaluation criteria 406a (if nodly_unet_slk < 0 & slk_fastclck < 0), and if these criteria are met, a circuit / logic is considered defective 407A (root cause of the violation). In another example, based on the evaluation criteria 406b (if unet_bdly_slk > cycle time & slk_fastclk < 0), and if these criteria are met, a floorplan / logic 407b was the root cause of the violation. In another example, based on the evaluation criteria 406c (if unet_bdly_slk < N% cycle time & slk_fastclk < -N% cycle time), and if these criteria are met, a floorplan / logic / circuit 407c was the root cause of the violation. It should be noted that the values ​​of the parameters M and N described above are determined, for example, by the developer for the respective design.

[0056] In another example, a rule can be used to eliminate a cross-domain, cross-hierarchy, and multi-cycle violation by using parameterized thresholds incorporating noise and timing data. An example of such a rule is shown in Fig. 5, which contains a noise and timing rule for the NIOF violation.

[0057] Fig. 5 shows the pseudocode for an exemplary rule for identifying a root cause of a cross-domain, cross-hierarchy, and multi-cycle violation of the digital integrated circuit according to an embodiment of the present disclosure.

[0058] As in Fig. As shown in Figure 5, rule 500 analyzes the relationship between noise and timing data, where nets (wires connecting components) that fail due to a violation related to the impact of noise on a function with high aggressor coupling (noise injected from other sources) due to noise data (see elements 501) are classified differently based on a timing margin (the margin by which a timing requirement is met or missed) determined from timing data using user-defined thresholds. Such cross-domain, cross-hierarchical, multi-cycle classification is important because the root cause is more effectively identified, which in turn leads to a better recommendation for resolving such a root cause. For example, the design approach for resolving a noise failure may change based on the timing margin (timing data).

[0059] With further reference to Fig. 2, such rules associated with violations may be entered into a data structure by a person skilled in the art as described above. Alternatively, in one embodiment, such rules are generated using a model trained by a machine learning algorithm.

[0060] In one embodiment, the control control component 202 trains a model to create an appropriate rule to identify the root cause of a particular violation (e.g., NIOF violation) based on the parameters (e.g., voltage transfer characteristics, noise limits, output load factor, power dissipation, propagation delays, and the interdependencies between these parameters) and data (e.g., noise limits, propagation delay, maximum clock frequencies, steady-state current, transient signal behavior) used by the analysis component 201 to decide on a violation.

[0061] In one embodiment, the rule control component 202 uses a machine learning algorithm (e.g., supervised learning) to build the model used to create a rule that identifies the root cause of a violation using a sample data set containing a rule and an associated violation, including the parameters (e.g., voltage transfer characteristics, noise limits, output load factor, power dissipation, propagation delays, and the interdependencies between these parameters) and data (e.g., noise limits, propagation delay, maximum clock frequencies, steady-state current, transient signal behavior) used by the analysis component 201 to decide on a violation.

[0062] Such a sample dataset is referred to here as "training data," which is used by the machine learning algorithm to make predictions or decisions about which rule to create to identify the root cause of the violation. The algorithm iteratively makes predictions on the training data regarding the rule to create to identify the root cause of the violation until the predictions reach the desired accuracy determined by a professional. Examples of such learning algorithms include nearest neighbor, naive Bayes, decision trees, linear regression, support vector machines, and neural networks.

[0063] After training the model to create a rule to identify the root cause of a violation based on the metadata of the violation (metadata of the violation, including the parameters and data), in one embodiment, such a model is used by the rule control component 202 to create a rule after the metadata (e.g., parameters and data) of the violation received from the analysis component 201 has been provided to the trained model.

[0064] In addition, the IC design development system 102 includes, as shown in Fig. 2, a recommendation control component 203 configured to recommend a design change in designing the digital integrated circuit based on the root cause of the violation identified by the rule control component 202.

[0065] For example, in one embodiment, the recommendation engine 203 uses a data structure (e.g., table) in which design recommendations are listed based on the identified root causes. For example, the recommendation engine 203 may recommend replacing the NAND logic gate (small NAND logic gate) identified in the design with the number 100122 with the NAND logic gate (large NAND logic gate) identified with the number 102233 and receiving digital signals identified with the numbers 122233, 132343, and 122343 if the rule indicates that the root cause of the NIOF violation was a coupling error at the NAND logic gate identified in the design with the number 100122. In one embodiment, such a data structure is populated with data by a person skilled in the art. In one embodiment, such data structures are located in a memory unit (e.g.,memory, hard disk drive) of the IC design development system 102.

[0066] In one embodiment, such recommendations may be generated using a model (mathematical model) trained using a machine learning algorithm to provide a recommendation based on the identified root cause of the violation, as described in detail below.

[0067] In one embodiment, the recommendation engine 203 trains a model to recommend an appropriate design change based on the root cause of the violation when designing the digital integrated circuit.

[0068] In one embodiment, the recommendation engine 203 uses a machine learning algorithm (e.g., supervised learning) to build the model to recommend the appropriate design change when designing the digital integrated circuit using a sample dataset containing the design change and the identified root cause of the violation when designing the digital integrated circuit. In one embodiment, such a dataset is provided by a person skilled in the art.

[0069] Such a sample dataset is referred to here as "training data," which is used by the machine learning algorithm to make predictions or decisions about which design changes to apply when designing the digital integrated circuit based on the root cause of the violation. The algorithm iteratively makes predictions on the training data regarding the design change until the predictions reach the desired accuracy determined by a subject matter expert. Examples of such learning algorithms include nearest neighbor, naive Bayes, decision trees, linear regression, support vector machines, and neural networks.

[0070] After training the model to make predictions or decisions regarding the design change in designing the digital integrated circuit based on the root cause of the violation, in one embodiment, such a model is used by the recommendation control component 203 to recommend a design change in designing the digital integrated circuit based on the root cause of the violation identified by the rule control component 202.

[0071] In one embodiment, the recommendation engine 203 annotates the database 104 with the recommended design change.

[0072] In one embodiment, the recommendation engine 203 implements the design change based on the recommendation. For example, if the recommendation engine 203 recommends replacing the NAND logic gate (small NAND logic gate) identified in the design by the number 100122 with the NAND logic gate (large NAND logic gate) identified by the number 102233 and receiving digital signals identified by the numbers 122233, 132343, and 122343, then the recommendation engine 203 proceeds to replace the NAND logic gate identified in the design by the number 100122 with the NAND logic gate identified in the design by the number 102233.

[0073] In one embodiment, the recommendation control component 203 simply provides a recommendation to the developer, for example, the user of the computing device 101, and allows the developer to decide whether to implement such a design change when designing the digital integrated circuit. In one embodiment, such a recommendation is in the format of a report (e.g., a text report).

[0074] A further description of these and other features is provided below in conjunction with the description of the method for recommending changes in the integrated circuit design based on effectively identifying the root cause of errors such as timing and noise errors in the digital integrated circuit design through an offline analysis of cross-domain, cross-hierarchy and / or multi-cycle violations of the digital integrated circuit using a rule-based approach.

[0075] Before describing the method for recommending changes in the design of an integrated circuit based on effectively identifying the root cause of errors such as timing and noise errors in the design of the digital integrated circuit through an offline analysis of cross-domain, cross-hierarchy and / or multi-cycle violations of the digital integrated circuit using a rule-based approach, a description of the hardware configuration of the IC design development system 102 ( Fig. 1) in connection with Fig. 6 provided.

[0076] With reference now to Fig. 6 in conjunction with Fig. 1 illustrates Fig. 6 illustrates an embodiment of the present disclosure of the hardware configuration of the IC design development system 102 representative of a hardware environment for carrying out the present disclosure.

[0077] Various aspects of the present disclosure are described by explanatory text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic in embodiments of computer program products (CPPs). In any flowchart, depending on the technology used, operations may be performed in a different order than that shown in a given flowchart. For example, again depending on the technology used, two operations shown in consecutive blocks of the flowchart may be performed in reverse order, as a single integrated step, concurrently, or in a manner that at least partially overlaps in time.

[0078] An embodiment of a computer program product ("CPP embodiment" or "CPP") is a term used in the present disclosure to describe a set of one or more storage media (also called "media") included together in a set of one or more storage units, which together contain machine-readable code corresponding to instructions and / or data for performing computer operations specified in a particular CPP claim. A "storage unit" is any physical unit capable of storing instructions for use by a computer processor.Without limitation, the computer-readable storage medium may be an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some common types of storage devices that comprise these media include: a floppy disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM).Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically encoded device (such as punched cards or pits / ridges formed in a major surface of a storage disk), and any suitable combination thereof. A computer-readable storage medium, as used in the present disclosure, is not intended to be construed as storing transient signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide, pulses of light propagating through an optical fiber, or electrical signals transmitted through a wire, and / or other transmission media.Those skilled in the art will appreciate that data is typically moved at certain times during normal operation of a storage device, such as during access, defragmentation, or garbage collection, but this does not make the storage device a volatile device because the data is not volatile during storage.

[0079] The computing environment 600 includes an example of an environment for executing at least a portion of the computer code 601 involved in performing the inventive methods of the present invention, e.g., in recommending changes in the design of an integrated circuit based on effectively identifying the root cause of errors such as timing and noise errors in the design of the digital integrated circuit through an offline analysis of cross-domain, cross-hierarchy, and / or multi-cycle violations of the digital integrated circuit using a rule-based approach. In addition to block 601, the computing environment 600 includes, for example, the IC design development system 102, the network 103, e.g., a wide area network (WAN), the end-user device (EUD) 602, the remote server 603, the public cloud 604, and the private cloud 605.In this embodiment, the IC design development system 102 includes a processor set 606 (including the processing circuitry 607 and the cache 608), a data transmission structure 609, a volatile memory 610, a persistent memory 611 (including an operating system 612 and the aforementioned block 601), the peripheral device set 613 (including the user interface device set 614, the memory 615, and the Internet of Things (IoT) sensor set 616), and the network module 617. The remote server 603 includes the remote database 618. The public cloud 604 includes the gateway 619, the cloud orchestration module 620, the set of physical host machines 621, the set of virtual machines 622, and the container set 623.

[0080] The IC design development system 102 may be in the form of a desktop computer, laptop computer, tablet computer, smartphone, smartwatch, or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device now known or developed in the future that is capable of executing a program, accessing a network, or querying a database, such as the remote database 618. As is well known in computer technology, the performance of a method implemented by a computer may be distributed across multiple computers and / or locations depending on the technology. On the other hand, the focus of this illustration of the computing environment 600 is on describing in detail a single computer, namely the IC design development system 102, in order to keep the illustration as simple as possible.The IC design development system 102 may be located in a cloud, even if it is in . Fig. 6 is not shown in a cloud. On the other hand, the IC design development system 102 need not be located in a cloud unless explicitly stated.

[0081] Processor set 606 includes one or more computer processors of any type now known or developed in the future. Processing circuitry 607 may be distributed across multiple packages, such as multiple coordinated integrated circuit chips. Processing circuitry 607 may implement multiple processor threads and / or multiple processor cores. Cache 608 is memory located within the processor chip package(s) and is typically used for data or code that should be available for rapid access by the threads or cores running on processor set 606. Caches are typically organized into multiple levels depending on their relative proximity to the processing circuitry. Alternatively, some or all of the cache for the processor set may be located off-chip.In some computing environments, the processor set 606 may be configured to work with qubits and perform quantum computing.

[0082] Computer-readable program instructions are typically loaded into the IC design development system 102 to cause a series of operations to be performed by the processor set 606 of the IC design development system 102, thereby executing a computer-implemented method, such that the so-executed instructions instantiate the methods specified in flowcharts and / or explanatory descriptions of computer-implemented methods in this document (collectively, "the inventive methods"). These computer-readable program instructions are stored in various types of computer-readable storage media, e.g., cache 608 and other storage media described below.The program instructions and associated data are accessed by processor set 606 to control and direct the execution of the inventive methods. In data processing environment 600, at least some of the instructions for performing the inventive methods may be stored in a permanent memory 611 in block 601.

[0083] The data transmission structure 609 is the signal transmission path through which the various components of the computer 102 can exchange data. This structure typically consists of switches and electrically conductive paths, such as the switches and electrically conductive paths that comprise buses, bridges, physical input / output ports, and the like. Other types of signal transmission paths may also be used, such as fiber optic data transmission paths and / or wireless data transmission paths.

[0084] The volatile memory 610 is any type of volatile memory now known or developed in the future. Examples include dynamic types of random access memory (RAM) or static types of RAM. Typically, the volatile memory is characterized by random access, but this is not required unless specifically noted. In the IC design development system 102, the volatile memory 610 is located in a single package and is integrated into the IC design development system 102; alternatively or additionally, the volatile memory may be distributed across multiple packages and / or located external to the IC design development system 102.

[0085] The persistent memory 611 is any form of non-volatile computer memory currently known or developed in the future. Non-volatile in this memory means that the stored data is retained regardless of whether power is supplied to the IC design development system 102 and / or the persistent memory 611 directly. The persistent memory 611 may be read-only memory (ROM), but typically at least a portion of the persistent memory allows data to be written, erased, and rewritten. Some known forms of persistent memory include magnetic disks and semiconductor memory devices. The operating system 612 may take a variety of forms, such as various well-known proprietary operating systems or open-source Portable Operating System Interface-type operating systems that utilize a kernel.The code contained in block 601 typically comprises at least a portion of the computer code involved in carrying out the methods of the invention.

[0086] The peripheral unit set 613 comprises the peripheral unit set of the computer 102. Data transmission connections between the peripheral units and the other components of the IC design development system 102 can be implemented in various ways, e.g., as Bluetooth connections, NFC connections (NFC - Near-Field Communication), cable connections (e.g., USB cables (USB - Universal Serial Bus), plug-in connections (e.g., SD card (SD - Secure Digital Card)), connections over local data transmission networks, and even connections over wide area networks such as the Internet. In various embodiments, the user interface unit set 614 can include components such as a display screen, a speaker, a microphone, wearable devices (e.g., glasses and smartwatches), a keyboard, a mouse, a printer, a touchpad, game controllers, and haptic devices.The memory 615 is external storage, e.g., an external hard drive, or removable storage, e.g., an SD card. The memory 615 may be permanent and / or volatile. In some embodiments, the memory 615 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where the IC design development system 102 requires a large amount of storage space (e.g., where the IC design development system 102 locally stores and manages a large database), this storage space may be provided by peripheral storage devices designed to store very large amounts of data, e.g., a storage area network (SAN) shared by multiple, geographically distributed computers. The IoT sensor set 616 consists of sensors that can be used in Internet of Things applications.For example, one sensor could be a thermometer and another a motion detector.

[0087] The network module 617 is the combination of computer software, hardware, and firmware that enables the IC design development system 102 to exchange data with other computers over a WAN 103. The network module 617 may include hardware, e.g., modems or WLAN transceivers, software for packetizing and / or depacketizing data for transmission over a data transmission network, and / or web browser software for transmission of data over the Internet. In some embodiments, network control functions and network forwarding functions of the network module 617 are performed on the same physical hardware unit. In other embodiments (e.g.,In embodiments employing SDN (Software-Defined Networking), the control functions and forwarding functions of the network module 617 are performed on physically separate units, so that the control functions manage multiple different hardware units of the network. Computer-readable program instructions for performing the inventive methods can typically be downloaded to the IC design development system 102 from an external computer or external storage device via a network adapter card or network interface included in the network module 617.

[0088] The WAN 103 is any wide area network (e.g., the Internet) capable of transmitting computer data over non-local distances using any technology for transmitting computer data now known or developed in the future. In some embodiments, the WAN may be replaced and / or supplemented by local area networks (LANs) designed to transmit data between devices within a local area, e.g., in a wireless network. The WAN and / or LANs typically include computer hardware such as copper transmission cables, fiber optic cables, wireless transmission, routers, firewalls, switches, gateway computers, and edge servers.

[0089] The end user device (EUD) 602 is a computer system used and controlled by an end user (e.g., a customer of a company operating the IC design development system 102) and may take any of the forms described above in connection with the IC design development system 102. The EUD 602 ​​typically receives helpful and useful data from the operations of the IC design development system 102. For example, in a hypothetical case where the IC design development system 102 is configured to provide a recommendation to an end user, this recommendation would typically be transmitted from the network module 617 of the IC design development system 102 to the EUD 602 ​​over the WAN 103. In this way, the EUD 602 ​​may display or otherwise present the recommendation to an end user. In some embodiments, the EUD 602 ​​may be a client device, e.g.,a thin client, heavy client, mainframe, desktop computer, etc.

[0090] The remote server 603 is any computer system that provides at least some data and / or functionality to the IC design development system 102. The remote server 603 may be controlled and used by the same entity that operates the IC design development system 102. The remote server 603 represents the machine(s) that collect and store helpful and useful data for use by other computers, e.g., the IC design development system 102. For example, in a hypothetical case where the IC design development system 102 is designed and programmed to make a recommendation based on historical data, this historical data may be provided to the IC design development system 102 from the remote database 618 of the remote server 603.

[0091] The public cloud 604 is a computer system available to multiple entities and enables on-demand availability of computer system resources and / or other computing capabilities, particularly data storage (cloud storage) and computing power, without direct, active management by the user. Cloud computing typically involves sharing resources to achieve consistency and economies of scale. The direct and active management of the computing resources of the public cloud 604 is performed by the computer hardware and / or software of the cloud orchestration module 620.The computing resources provided by the public cloud 604 are typically implemented by virtual computing environments running on various computers that make up the computers of the set of physical host machines 621, which represents the totality of the physical computers in and / or for the public cloud 604. The virtual computing environments (VCEs) typically take the form of virtual machines from the set of virtual machines 622 and / or containers from the container set 623. It should be noted that these VCEs can be stored as images and transferred between the various physical machine hosts, either as images or after instantiating the VCE.The cloud orchestration module 620 manages the transfer and storage of maps, implements new VCE instantiations, and manages active instantiations of VCE implementations. The gateway 619 is a combination of computer software, hardware, and firmware that enables the public cloud 604 to transfer data across the WAN 103.

[0092] Here is some further explanation of virtualized computing environments (VCEs). VCEs can be saved as "maps." From the map, a new active instance of the VCE can be created. Two common types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to a feature of the operating system where the kernel allows the existence of multiple isolated user-space instances, called containers. These isolated user-space instances typically behave like real computers from the perspective of the programs running within them. A computer program running on an ordinary operating system can use all of that computer's resources, such as connected devices, files and folders, shared network space, CPU power, and quantifiable hardware capabilities.However, programs running in a container can only use the contents of the container and the units assigned to the container. This feature is called containerization.

[0093] The private cloud 605 is similar to the public cloud 604, except that the computing resources are available for use by only a single enterprise. While the private cloud 605 is depicted as being in communication with the WAN 103, in other embodiments, a private cloud may be completely disconnected from the Internet and accessible only through a local / private network. A hybrid cloud is a combination of multiple clouds of different types (e.g., private, community, or public clouds), often implemented by different vendors. Each of the multiple clouds remains a separate and distinct entity, but the larger architecture of the hybrid cloud is interconnected by standardized or proprietary technology that enables orchestration, management, and / or data / application portability between the participating clouds.In this embodiment, the public cloud 604 and the private cloud 605 are both part of a larger hybrid cloud.

[0094] Block 601 further comprises the above-mentioned in connection with the Fig. 2 to 5 for recommending changes in the design of the integrated circuit based on effectively identifying the root cause of errors such as timing and noise errors in the design of the digital integrated circuit through an offline analysis of cross-domain, cross-hierarchy, and / or multi-cycle violations of the digital integrated circuit using a rule-based approach. In one embodiment, such components may be implemented in hardware. The functions performed by such components described above are not general-purpose computing functions. Therefore, the IC design development system 102 is a special-purpose machine that is the result of implementing specific, non-general-purpose computing functions.

[0095] In one embodiment, the functionality of such software components of the IC design development system 102, including functionality for recommending changes in the design of an integrated circuit based on effectively identifying the root cause of errors such as timing and noise errors in the design of the digital integrated circuit through an offline analysis of cross-domain, cross-hierarchy and / or multi-cycle violations of the digital integrated circuit using a rule-based approach, may be implemented in an application-specific integrated circuit.

[0096] As stated above, when designing digital integrated circuits, such a design is tested and analyzed using various EDA tools to identify various violations such as timing or noise errors. A "timing fault" is a fault in a process or part of a process in a synchronous distributed or real-time system where specified limits for execution, message delivery, clock drift rate, or clock skew are not met. A "noise fault" is unexpected voltage fluctuations due to a variety of factors, such as signal transitions to adjacent wires, which can potentially cause noise or damage to electrical circuits. When such simulated faults (e.g., timing and noise errors) occur, the designer attempts to identify the root cause of these faults.However, such analysis (also called "triage") is time-consuming and difficult. In addition, such faults (e.g., timing and noise faults) may be related to each other. However, such relationships are difficult to assess, making it difficult to identify the root cause of such faults. Furthermore, such faults (e.g., timing and noise faults) may involve integration-level problems between components located at different hierarchical levels of the integrated circuit. For example, a multi-cycle path may span many components located at different hierarchical levels of the integrated circuit. Analyzing such problems may involve analyzing each of the multiple hierarchical components, which is extremely difficult, making it difficult to identify the root cause of such faults.Consequently, there is currently no way to effectively identify the root cause of errors such as timing and noise errors when designing digital integrated circuits.

[0097] The embodiments of the present disclosure provide a means for effectively identifying the root cause of errors such as timing and noise errors in the design of digital integrated circuits through an offline analysis of cross-domain, cross-hierarchy and / or multi-cycle violations of the digital integrated circuit using a rule-based approach, as described below in connection with Fig. 7 is described.

[0098] Fig. 7 is a flowchart of a method 700 for recommending changes in the design of an integrated circuit based on effectively identifying the root cause of defects such as timing and noise errors in the design of the digital integrated circuit through an offline analysis of cross-domain, cross-hierarchy, and / or multi-cycle violations of the digital integrated circuit using a rule-based approach, according to an embodiment of the present disclosure.

[0099] With reference to Fig. 7 in conjunction with the Fig. 1 to 6, at operation 701, the analysis component 201 of the IC design development system 102 performs an analysis of the digital integrated circuit being designed by a developer (e.g., a user of the computing device 101). In one embodiment, such an analysis results in the identification of violations.

[0100] As described above, in one embodiment, such analysis may include verifying and simulating the design of the digital integrated circuit based on various properties or parameters, e.g., voltage transfer characteristics, noise margins, output load factor, power dissipation, propagation delays, and the interdependencies between these parameters.

[0101] In one embodiment, analysis component 201 analyzes the digital integrated circuit design to ensure that it conforms to the functional or parametric specifications that may be provided by the designer (e.g., the user of computing device 101). For example, analysis component 201 may analyze the digital integrated circuit design to determine whether each logic gate functions according to its truth table specification. In another example, analysis component 201 determines whether the electrical paths in the design are identical to those in the device.

[0102] Furthermore, in one embodiment, analysis component 201 performs parametric tests on the digital integrated circuit design based on the analysis of a continuous circuit parameter. For example, analysis component 201 may determine whether the device's steady-state power demand is excessive. In another example, analysis component 201 determines whether the effects of process variations are within a tolerance. In another example, analysis component 201 determines whether performance requirements (e.g., delay errors) are met.

[0103] Furthermore, in one embodiment, parametric testing may include analyzing continuous variables of circuits, e.g., noise margins, propagation delay, maximum clock frequencies, steady-state current, transient signal behavior, etc. In one embodiment, such parameters are checked at a range of different temperatures and supply voltages.

[0104] In one embodiment, the analysis component 201 uses various software tools (e.g., integrated circuit design (EDA) tools) to perform such analysis of the digital integrated circuit design, including, but not limited to, Cadence ® , Synopsis ® , Mentor Graphics ® , Atrenta etc.

[0105] When performing such an analysis of a digital integrated circuit design, violations may be detected. As used herein, "violation" refers to the performance of a component or system in the design of the digital integrated circuit that does not conform to a required specification, as defined by the designer, resulting in a failure (e.g., noise error, timing error, power failure, etc.). In one embodiment, such violations include "cross-domain," "cross-hierarchy," and / or "multi-cycle" violations.

[0106] The term "cross-domain" as used here encompasses several error types, such as timing errors and noise errors. A "timing error" as used here refers to a fault in a process or part of a process in a synchronous distributed or real-time system where specified limits for execution, message delivery, clock drift rate, or clock skew are not met. A "noise error" as used here refers to unexpected voltage fluctuations due to a variety of factors, such as signal transitions to adjacent wires, that can potentially cause noise or damage to electrical circuits. The term "cross-hierarchy" as used here refers to multiple levels of the integrated circuit design. The term "multi-cycle" as used here refers to a multi-cycle path spanning many components.

[0107] In one embodiment, such violations are identified as a result of the analysis performed by the software tools described above (e.g., EDA tools). EDA tools can, for example, identify logical-level errors corresponding to timing errors, noise errors, power outages, etc.

[0108] In one embodiment, such violations are stored, e.g., in database 104. In one embodiment, such stored violations also include metadata comprising parameters used by analysis component 201 to determine an occurred violation. Furthermore, such metadata includes the relevant data (e.g., noise limits, propagation delay, maximum clock frequencies, steady-state current, transient signal behavior) used by analysis component 201 to decide on a violation.

[0109] In operation 702, the analysis component 201 of the IC design development system 102 stores the violations, e.g., in the database 104.

[0110] As described above, such stored violations also include metadata containing parameters used by the analysis component 201 to determine a violation that has occurred. Furthermore, such metadata includes the relevant data (e.g., noise limits, propagation delay, maximum clock frequencies, steady-state current, transient signal behavior) used by the analysis component 201 to decide on a violation.

[0111] At operation 703, the rule control component 202 of the IC design development system 102 analyzes a stored violation using a rule to identify a root cause of the violation.

[0112] As explained above, in one embodiment, such violations are analyzed using the rules offline. In one embodiment, such rules are parameterized, as described below.

[0113] In one embodiment, the rule control component 202 identifies the root causes of errors such as timing and noise errors in the design of digital integrated circuits by performing an offline analysis of cross-domain (e.g., timing and noise errors), cross-hierarchy (at multiple levels of the integrated circuit design), and / or multi-cycle (multi-cycle path spanning many components) violations of the digital integrated circuit using a rule-based approach. Such a rule-based approach includes rules that can be provided by a person skilled in the art that aim to classify different errors of a violation (e.g., cross-domain, cross-hierarchy, and / or multi-cycle violation) based on analyzing the design of the digital integrated circuit using an integrated circuit design tool (e.g., Eagle ®, KiCAD ® , Pulsonix, Multisim ® , Altium Designer ®etc.) have been identified. The term "triage" as used herein refers to analyzing faults, e.g., to determine the root cause of such faults. In one embodiment, these rules relate to cross-domain, cross-hierarchy, and / or multi-cycle violations, e.g., by using parameterized thresholds involving multiple domains. Such rules may, for example, relate to a cross-domain, cross-hierarchy, and multi-cycle violation using parameterized thresholds involving noise and timing data. For example, one of the rules could be a noise and timing rule for the NIOF violation.Such a rule can be used to analyze the relationship between noise and timing data, where nets (wires connecting components) that fail due to a violation related to the impact of noise on a function with high aggressor coupling (noise injected from other sources) due to noise data are differently classified based on a timing margin (the margin by which a timing requirement is met or missed) determined from timing data using user-defined thresholds. Such cross-domain, cross-hierarchical, and multi-cycle classification is important because the root cause is more effectively identified, which in turn leads to a better recommendation for resolving such a root cause. For example, the design approach for resolving a noise failure may change based on the timing margin (timing data).

[0114] In one embodiment, database 104 stores a collection of rules to identify the root cause of violations. Such rules are associated with specific violations. For example, a rule may be used to identify the root cause of a NIOF violation. Rule control component 202 then identifies a rule to determine the root cause of a violation based on the violation identified by analysis component 201. In one embodiment, such rules and their associated violations are stored in a data structure, such a data structure being stored in database 104 or in a storage unit (e.g., storage unit 611, 615) of IC design development system 102. In one embodiment, such a data structure is populated with data by a person skilled in the art.

[0115] In one embodiment, to analyze the violation using the corresponding rule, various parameters and data related to the violation may be retrieved from the rule control component 202. As explained above, in one embodiment, such violations include metadata comprising parameters used by the analysis component 201 to determine a violation that has occurred, as well as the relevant data (e.g., noise limits, propagation delay, maximum clock frequencies, steady-state current, transient signal behavior) used by the analysis component 201 to decide on a violation. These parameters and data may be used by the rule control component 202 to identify the root cause of the violation. An example of such a rule is described in Fig. 3 provided.

[0116] Another representation of a rule that identifies a root cause of a violation such as a timing error is shown in Fig. 4 provided.

[0117] In another example, a rule can be used to eliminate a cross-domain, cross-hierarchy, and multi-cycle violation by using parameterized thresholds incorporating noise and timing data. An example of such a rule is shown in Fig. 5, which contains a noise and timing rule for the NIOF violation.

[0118] Furthermore, as described above, such rules associated with violations may be entered into a data structure by a person skilled in the art. Alternatively, in one embodiment, such rules are generated using a model trained by a machine learning algorithm.

[0119] In one embodiment, the control control component 202 trains a model to create an appropriate rule to identify the root cause of a particular violation (e.g., NIOF violation) based on the parameters (e.g., voltage transfer characteristics, noise limits, output load factor, power dissipation, propagation delays, and the interdependencies between these parameters) and data (e.g., noise limits, propagation delay, maximum clock frequencies, steady-state current, transient signal behavior) used by the analysis component 201 to decide on a violation.

[0120] In one embodiment, the rule control component 202 uses a machine learning algorithm (e.g., supervised learning) to build the model used to create a rule that identifies the root cause of a violation using a sample data set containing a rule and an associated violation, including the parameters (e.g., voltage transfer characteristics, noise limits, output load factor, power dissipation, propagation delays, and the interdependencies between these parameters) and data (e.g., noise limits, propagation delay, maximum clock frequencies, steady-state current, transient signal behavior) used by the analysis component 201 to decide on a violation.

[0121] Such a sample dataset is referred to here as "training data," which is used by the machine learning algorithm to make predictions or decisions about which rule to create to identify the root cause of the violation. The algorithm iteratively makes predictions on the training data regarding the rule to create to identify the root cause of the violation until the predictions reach the desired accuracy determined by a professional. Examples of such learning algorithms include nearest neighbor, naive Bayes, decision trees, linear regression, support vector machines, and neural networks.

[0122] After training the model to create a rule to identify the root cause of a violation based on the metadata of the violation (metadata of the violation, including the parameters and data), in one embodiment, such a model is used by the rule control component 202 to create a rule after the metadata (e.g., parameters and data) of the violation received from the analysis component 201 has been provided to the trained model.

[0123] In operation 704, the recommendation control component 203 of the IC design development system recommends a design change in designing the digital integrated circuit based on the root cause of the violation identified by the rule control component 202.

[0124] As described above, in one embodiment, the recommendation engine 203 uses, for example, a data structure (e.g., a table) that lists design recommendations based on the identified root causes. For example, if the rule indicates that the root cause of the NIOF violation was a coupling error at the NAND logic gate identified in the design with the number 100122, the recommendation engine 203 may recommend replacing the NAND logic gate (small NAND logic gate) identified in the design with the number 102233 with the NAND logic gate (large NAND logic gate) identified in the design with the number 102233 and receiving digital signals identified with the numbers 122233, 132343, and 122343. In one embodiment, such a data structure is populated with data by a person skilled in the art. In one embodiment, such a data structure is located in a storage unit (e.g.Storage unit 611, 615) of the IC design development system 102.

[0125] In one embodiment, such recommendations may be generated using a model (mathematical model) trained using a machine learning algorithm to provide a recommendation based on the identified root cause of the violation.

[0126] In one embodiment, the recommendation engine 203 trains a model to recommend an appropriate design change based on the root cause of the violation when designing the digital integrated circuit.

[0127] In one embodiment, the recommendation engine 203 uses a machine learning algorithm (e.g., supervised learning) to build the model to recommend the appropriate design change when designing the digital integrated circuit using a sample dataset containing the design change and the identified root cause of the violation when designing the digital integrated circuit. In one embodiment, such a dataset is provided by a person skilled in the art.

[0128] Such a sample dataset is referred to here as "training data," which is used by the machine learning algorithm to make predictions or decisions about which design changes to apply when designing the digital integrated circuit based on the root cause of the violation. The algorithm iteratively makes predictions on the training data regarding the design change until the predictions reach the desired accuracy determined by a subject matter expert. Examples of such learning algorithms include nearest neighbor, naive Bayes, decision trees, linear regression, support vector machines, and neural networks.

[0129] After training the model to make predictions or decisions regarding the design change in designing the digital integrated circuit based on the root cause of the violation, in one embodiment, such a model is used by the recommendation control component 203 to recommend a design change in designing the digital integrated circuit based on the root cause of the violation identified by the rule control component 202.

[0130] In one embodiment, the recommendation engine 203 annotates the database 104 with the recommended design change.

[0131] At operation 705, the recommendation engine 203 of the IC design development system 102 implements the design based on the recommendation. For example, if the recommendation engine 203 recommends replacing the NAND logic gate (small NAND logic gate) identified in the design by the number 100122 with the NAND logic gate (large NAND logic gate) identified by the number 102233 and receiving digital signals identified by the numbers 122233, 132343, and 122343, then the recommendation engine 203 proceeds to replace the NAND logic gate identified in the design by the number 100122 with the NAND logic gate identified in the design by the number 102233.

[0132] In one embodiment, the recommendation control component 203 simply provides a recommendation to the developer, for example, the user of the computing device 101, and allows the developer to decide whether to implement such a design change when designing the digital integrated circuit. In one embodiment, such a recommendation is in the format of a report (e.g., a text report).

[0133] Based on the foregoing, the principles of the present disclosure provide a means for effectively identifying the root cause of errors such as timing and noise errors in the design of digital integrated circuits through an offline analysis of cross-domain, cross-hierarchy and / or multi-cycle violations of the digital integrated circuit using a rule-based approach.

[0134] Furthermore, the principles of the present disclosure improve the technology or technical field to which integrated circuit design belongs. As stated above, when designing digital integrated circuits, such a design is tested and analyzed using various EDA tools to identify various violations such as timing or noise errors. A "timing error" is an error in a process or part of a process in a synchronous distributed or real-time system that violates specified limits for execution, message delivery, clock drift rate, or clock skew. A "noise error," as used herein, refers to unexpected random voltage fluctuations that can potentially cause disturbances or damage to electrical circuits. When such simulated errors occur (e.g.,Timing and noise errors), the developer attempts to identify the root cause of these errors. However, such analysis (also called "triage") is time-consuming and difficult. In addition, such errors (e.g., timing and noise errors) may be related to each other. However, such relationships are difficult to assess, making it difficult to identify the root cause of such errors. Furthermore, such errors (e.g., timing and noise errors) may involve integration-level problems between components located at different hierarchical levels of the integrated circuit. For example, a multi-cycle path may span many components located at different hierarchical levels of the integrated circuit.Analyzing such problems can involve analyzing each of the multiple hierarchical components, which is extremely challenging, making it difficult to identify the root cause of such failures. Consequently, there is currently no way to effectively identify the root cause of failures such as timing and noise errors when designing digital integrated circuits.

[0135] Embodiments of the present disclosure improve such technology by performing an analysis of the digital integrated circuit being designed, the result of such analysis being to identify and store violations. As used herein, the term "violation" refers to the performance of a component or system in the design of the digital integrated circuit that does not conform to a required specification, as defined by the designer, resulting in a failure (e.g., noise failure, timing failure, power failure, etc.). In one embodiment, such analysis may include verifying and simulating the design of the digital integrated circuit based on various properties or parameters, e.g., voltage transfer characteristics, noise margins, output load factor, power dissipation, propagation delays, and the interdependencies between these parameters.In one embodiment, such analysis ensures that it conforms to functional or parametric specifications that may be provided by the developer. A stored violation may then be analyzed to identify a root cause of the violation, including a cross-domain, cross-hierarchy, and / or multi-cycle violation, using a rule. The term "cross-domain" as used herein encompasses multiple fault types, e.g., timing faults and noise faults. The term "cross-hierarchy" as used herein refers to multiple levels of the integrated circuit design. The term "multi-cycle" as used herein refers to a multi-cycle path spanning many components. In one embodiment, such violations are analyzed using the rules offline. In one embodiment, such rules are parameterized.In one embodiment, the cross-domain, cross-hierarchical, and / or multi-cycle violation, e.g., caused by timing and noise errors, is identified by an offline analysis of the digital integrated circuit violation using a rule-based approach. Such a rule-based approach includes rules aimed at classifying various errors of the cross-domain, cross-hierarchical, and / or multi-cycle violation, which are determined based on analyzing the digital integrated circuit design using an integrated circuit design tool (e.g., Eagle). ® , KiCAD ® , Pulsonix, Multisim ® , Altium Designer ®etc.) have been identified. The term "triage" as used herein refers to analyzing errors, e.g., to determine the root cause of such errors. In one embodiment, these rules refer to cross-domain, cross-hierarchy, and / or multi-cycle violations, e.g., by using parameterized thresholds involving multiple domains. Furthermore, these rules may refer to a violation affecting a path traversing a hierarchy in the design of the digital integrated circuit. The term "hierarchy" as used herein refers to the levels of the digital integrated circuit, where each level includes one or more components of the digital integrated circuit. Furthermore, these rules may refer to a violation affecting a multi-cycle path spanning many components.A design change during design of the digital integrated circuit may then be recommended based on the identified root cause of the violation, e.g., a cross-domain violation. In one embodiment, such a recommendation is based on using a data structure (e.g., a table) that lists design recommendations based on the identified root causes. In one embodiment, such recommendations may be generated using a model (mathematical model) trained using a machine learning algorithm to provide a recommendation based on the identified root cause of the violation, e.g., a cross-domain violation. In one embodiment, the recommended design change is implemented during design of the digital integrated circuit.In this way, the root causes of errors such as timing and noise errors in digital integrated circuit design are effectively identified through offline analysis of cross-domain (e.g., timing and noise errors), cross-hierarchical (at multiple levels of the integrated circuit design), and / or multi-cycle (multi-cycle path spanning many components) violations of the digital integrated circuit using a rule-based approach. Furthermore, this leads to an improvement in the technical field that includes integrated circuit design.

[0136] The technical solution provided by the present disclosure cannot be implemented by the human mind or by a human using pen and paper. That is, the technical solution provided by the present disclosure could not be achieved in a reasonable time and with reasonable accuracy using only the human mind or by a human using pen and paper without the use of a computer.

[0137] In one embodiment of the present disclosure, a computer-implemented method for recommending design changes when designing a digital integrated circuit comprises performing an analysis of the digital integrated circuit in which a plurality of violations are identified. The method further comprises analyzing one of the plurality of violations to identify a root cause of the one of the plurality of violations, including a cross-domain, a cross-hierarchy, and / or a multi-cycle violation, using a rule. The method further comprises recommending a design change when designing the digital integrated circuit for the one of the plurality of violations based on the identified root cause.

[0138] Furthermore, in one embodiment of the present disclosure, the method further comprises that the rule eliminates the violation by using parameterized thresholds incorporating noise and timing data.

[0139] Furthermore, in one embodiment of the present disclosure, the method further comprises the rule that eliminates the violation including a path traversing a hierarchy in a design of the digital integrated circuit.

[0140] Furthermore, in one embodiment of the present disclosure, the method further comprises that the rule is parameterized.

[0141] Furthermore, in one embodiment of the present disclosure, the method further comprises analyzing the violation from the plurality of violations offline using the rule.

[0142] Furthermore, in one embodiment of the present disclosure, the method further comprises wherein the plurality of violations comprise timing and noise errors found using integrated circuit design tools.

[0143] Furthermore, in one embodiment of the present disclosure, the method further comprises implementing the design change based on the recommendation.

[0144] Other embodiments of the above-described computer-implemented method are included in a system and in a computer program product.

[0145] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments. It will be apparent to those skilled in the art that many changes and modifications are possible without departing from the scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, practical application, or technical improvement over technologies on the market, or to enable those skilled in the art to understand the embodiments described herein.

Claims

[1] A computer-implemented method for recommending design changes in the design of a digital integrated circuit, the method comprising: Conducting an analysis of the digital integrated circuit which reveals a plurality of violations; Analyzing one of the plurality of violations to identify a root cause for the one of the plurality of violations, including a cross-domain, a cross-hierarchy, and / or a multi-cycle violation, using a rule; and Recommend a design change in the design of the digital integrated circuit for the one violation from the plurality of violations based on the identified root cause. [2] The method of claim 1, wherein the rule eliminates the violation by using parameterized thresholds incorporating noise and timing data. [3] The method of claim 1, wherein the rule eliminates the violation affecting a path traversing a hierarchy in a design of the digital integrated circuit. [4] The method of claim 1, wherein the rule is parameterized. [5] The method of claim 1, wherein the one violation of the plurality of violations is analyzed offline using the rule. [6] The method of claim 1, wherein the plurality of violations comprise timing and noise errors found using integrated circuit design tools. [7] The method of claim 1, further comprising: Implement the design change based on the recommendation. [8] A computer program product for recommending design changes in the design of a digital integrated circuit, the computer program product comprising one or more computer-readable storage media having program code embodied therein, the program code comprising programming instructions to: to carry out an analysis of the digital integrated circuit which reveals a number of violations; analyze one violation from the plurality of violations to identify a root cause for the one violation from the plurality of violations, including a cross-domain, a cross-hierarchy, and / or a multi-cycle violation, using a rule; and to recommend a design change in the design of the digital integrated circuit for the one violation from the plurality of violations based on the identified root cause. [9] The computer program product of claim 8, wherein the rule eliminates the violation by using parameterized thresholds incorporating noise and timing data. [10] The computer program product of claim 8, wherein the rule eliminates the violation affecting a path traversing a hierarchy in a design of the digital integrated circuit. [11] The computer program product of claim 8, wherein the rule is parameterized. [12] The computer program product of claim 8, wherein the one violation of the plurality of violations is analyzed offline using the rule. [13] The computer program product of claim 8, wherein the plurality of violations comprise timing and noise errors found using integrated circuit design tools. [14] The computer program product of claim 8, wherein the program code further comprises program instructions to: to implement the design change based on the recommendation. [15] System that has: a memory for storing a computer program for recommending design changes when designing a digital integrated circuit; and a processor connected to the memory, the processor configured to execute program instructions of the computer program comprising: Conducting an analysis of the digital integrated circuit which reveals a plurality of violations; Analyzing one of the plurality of violations to identify a root cause for the one of the plurality of violations, including a cross-domain, a cross-hierarchy, and / or a multi-cycle violation, using a rule; and Recommend a design change in the design of the digital integrated circuit for the one violation from the plurality of violations based on the identified root cause. [16] The system of claim 15, wherein the rule eliminates the violation by using parameterized thresholds incorporating noise and timing data. [17] The system of claim 15, wherein the rule eliminates the violation affecting a path traversing a hierarchy in a design of the digital integrated circuit. [18] The system of claim 15, wherein the rule is parameterized. [19] The system of claim 15, wherein the one violation of the plurality of violations is analyzed offline using the rule. [20] The system of claim 15, wherein the plurality of violations comprise timing and noise errors found using integrated circuit design tools.

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