SEMICONDUCTOR DEVICE

Abstract

A semiconductor device is provided in which an insulating circuit substrate on which power semiconductor chips are mounted is sealed with a high-temperature resistant epoxy resin, wherein the semiconductor device has high reliability and is capable of suppressing delamination between the high-temperature resistant epoxy resin and the wiring of the insulating circuit substrate.The semiconductor device is characterized in that it comprises a power semiconductor chip; an insulating circuit substrate on which the power semiconductor chip is mounted; and a sealing resin for sealing at least the power semiconductor chip and a connecting section of the insulating circuit substrate with the power semiconductor chip, and is characterized in that the insulating circuit substrate has a ceramic substrate and a front-side wiring layer formed on a surface of the ceramic substrate, and the front-side wiring layer has a first roughened layer on a surface opposite a bonding surface with the ceramic substrate.

Description

Technical field

[0001] The present invention relates to a structure of a semiconductor device, and in particular to a power module in which an insulating circuit substrate on which a power semiconductor chip is mounted is sealed with a highly heat-resistant epoxy resin, and to a method for its production. Background technology

[0002] A potting technique was developed as a method for insulating and sealing a power module. This technique requires no mold and is capable of sealing with a high-temperature-resistant epoxy resin. The high-temperature-resistant epoxy resin exhibits an elasticity coefficient of 100 GPa or more at ordinary temperatures and can reduce thermal stress caused by differences in the linear expansion coefficient between circuit formation sections on a semiconductor chip or an insulating substrate through mechanical clamping, thus extending the lifetime of the power cycle.

[0003] As background technology in this technical field, there is, for example, the technology as described in patent literature 1. Patent literature 1 discloses “a power module comprising a semiconductor element arranged on a substrate; a plate-like electrode plate having two or more connection sections for connecting the semiconductor elements, the semiconductor element and an external connection, or the substrate and the external connection; a resin mold section in a convex shape and with an inclination on the substrate surface side between adjacent connection sections of the electrode plate; and a sealing resin section for sealing the periphery of the connection section.” List of citations from patent literature

[0004] Patent Literature 1: JP 2019-197842 A Summary of the invention: Technical problem

[0005] For the insulating substrate of an insulating circuit substrate intended for use in a power module for a power component, ceramics such as aluminum oxide (Al₂O₃), silicon nitride (Si₃N₄), or aluminum nitride (AlN) are used. Furthermore, copper (Cu) or aluminum (Al) is used for the wiring.

[0006] Traditionally, a silver soldering method was used to join the ceramic substrate, the insulating circuit substrate, and the wiring. However, recently, a DCB (Direct Bonded Copper) substrate for directly bonding copper to a ceramic substrate and an AMB (Active Metal Braze) substrate using an active metal such as titanium (Ti) for bonding copper to an insulator have been developed.

[0007] The linear coefficients of thermal expansion of ceramics are 7.2 × 10 6 / K for aluminium oxide, 2.8 × 10 -6 / K for silicon nitride and 4.6 × 10 -6 / K for aluminum nitride. On the other hand, the linear coefficient of expansion of copper is 16.5 × 10 -6 / K, and the linear coefficient of expansion of aluminium is 23.9 × 10 -6 / K.

[0008] The linear coefficient of expansion of the sealant made of highly heat-resistant epoxy resin varies depending on the resin material or the amount of filler added and is 10 to 20 × 10 -6 / K. A thermal stress is generated between the high-temperature epoxy resin seal and the wiring due to a difference in the coefficient of linear expansion between the ceramic and the high-temperature epoxy resin seal. This thermal stress may cause delamination between the high-temperature epoxy resin and the wiring. If delamination occurs, the mechanical clamping force exerted by the high-temperature epoxy resin is reduced, thus increasing the thermal stress and reducing the power cycle.

[0009] Incidentally, silicon nitride (Si3N4) is used as an insulating substrate in a power module for a power component with a withstand voltage of 750 V or 1200 V, intended for use in the inverter of an electric vehicle (EV). This is due to the following fact: its thermal conductivity is lower than that of aluminum oxide (Al2O3), and its dielectric strength is high, allowing for a reduction in substrate thickness. Consequently, the thermal resistance can be lowered.

[0010] On the other hand, for silicon nitride (Si3N4) the linear coefficient of expansion among ceramics is small, and the thermal stress between the high heat-resistant epoxy resin and the wiring is large.

[0011] In the patent literature 1 mentioned above, the thermal stress between the high heat-resistant epoxy resin and the wiring of the insulating circuit substrate is not taken into account, and there is room for improvement.

[0012] Under such circumstances, it is an object of the present invention to provide a semiconductor device in which an insulating circuit substrate on which power semiconductor chips are mounted is sealed with a high-temperature resistant epoxy resin, wherein the semiconductor device has high reliability and is able to suppress delamination between the high-temperature resistant epoxy resin and the wiring of the insulating circuit substrate. Solution to the problem

[0013] To solve the above problems, the present invention is characterized in that it comprises: a power semiconductor chip; an insulating circuit substrate on which the power semiconductor chip is mounted; and a sealing resin for sealing at least the power semiconductor chip and a connecting section of the insulating circuit substrate with the power semiconductor chip, and is characterized in that the insulating circuit substrate has a ceramic substrate and a front-side wiring layer formed on a surface of the ceramic substrate, and the front-side wiring layer has a first roughened layer on a surface opposite a bonding surface with the ceramic substrate. Advantageous effects of the invention

[0014] According to the present invention, it is possible to realize a highly reliable semiconductor device in a semiconductor device in which an insulating circuit substrate on which power semiconductor chips are mounted is sealed with a high-temperature resistant epoxy resin, which can suppress delamination between the high-temperature resistant epoxy resin and the wiring of the insulating circuit substrate.

[0015] This makes it possible to extend the service life of the power module's power cycle.

[0016] Other problems, configurations and effects than those described above are clarified by the following description of embodiments. Brief description of the drawings Fig. Figure 1 shows a perspective view of the external appearance of a power module according to Example 1 of the present invention. Fig. Figure 2 shows a view of the rear and side surfaces of the power module of Fig. 1 shows. Fig. Figure 3 shows a top view of the power module of Fig. 1 shows a removed high heat-resistant epoxy resin 3. Fig. Figure 4 shows a cross-sectional view along line AA' in Fig. 3. Fig. Figure 5 shows a view depicting a state in which part of Fig. 4 is sealed with the highly heat-resistant epoxy resin 3. Fig. Figure 6A shows a view illustrating part of the manufacturing steps for a power module according to Example 2 of the present invention. Fig. Figure 6B shows a diagram illustrating a manufacturing step that is based on Fig. 6A follows. Fig. Figure 7A shows a partial cross-sectional view of a power module according to Example 3 of the present invention. Fig. Figure 7B shows a diagram (top view) of the roughened layer 30 when viewed in the B-B' direction in Fig. 7A. Description of embodiments

[0017] Embodiments of the present invention are described below with reference to the drawings. It should be noted that the same configurations are shown in the respective drawings, with the same reference numerals and symbols, and detailed descriptions of overlapping parts are omitted. Design 1

[0018] With reference to the Fig. 1, Fig. 2, Fig. 3, Fig. 4 to Fig. 5 describes a semiconductor device according to Example 1 of the present invention.

[0019] Fig. Figure 1 shows a perspective view of the external appearance of a performance module 100 of the present example. Fig. Figure 2 shows a view of the rear and side surfaces of the 100 power module. Fig. 1 shows. Fig. Figure 3 shows a top view of the power module 100 of Fig. Figure 1 shows the removed high-temperature resistant epoxy resin 3. Fig. Figure 4 shows a cross-sectional view along line AA' in Fig. 3. Fig. Figure 5 shows a view depicting a state in which part of Fig. 4 is sealed with the highly heat-resistant epoxy resin 3.

[0020] As in Fig. As shown in Figure 1, in the power module 100 of the present example, a housing 2 is bonded to a metal base 1 by an adhesive. The housing 2 is filled by potting with a high-temperature-resistant epoxy resin 3.

[0021] Furthermore, performance module 100 of the present example, as shown in Fig. Figure 2 shows a plurality of fins 4 provided on the metal base 1. The fins 4 are provided on the back side of the metal base 1, that is, on the surface opposite the front side on which a power semiconductor chip is mounted, and the heat generated from the power semiconductor chip, which is associated with the operation of the power module 100, is dissipated by the fins 4 by mounting a water cooling device, such as a water jacket or an air cooling device, on the back side of the metal base 1.

[0022] As in Fig. As shown in Figure 3, the present example illustrates the case in which an IGBT (Insulated Gate Bipolar Transistor) and a diode connected in parallel to the IGBT are used as power components. Furthermore, the present example is a 6-in-1 type power module in which U-, V-, and W-phases, as well as a total of 6 arms consisting of upper and lower arms, are mounted on a 100 Ω power module.

[0023] An insulating circuit substrate 10 is provided on the metal base 1. An IGBT 11 and a diode 12 are provided on the insulating circuit substrate 10, and the IGBT 11 and the diode 12 are connected by a conductor frame 13.

[0024] As in Fig. As shown in Figure 4, the insulating circuit substrate 10 is provided on the metal base 1, which is connected to the lamellae 4. The insulating circuit substrate 10 comprises a ceramic substrate 14, a back-side wiring layer 21, and a front-side wiring layer 22. The insulating circuit substrate 10 is connected to the metal base 1 by a solder 20 provided between the back-side wiring layer 21 and the metal base 1. The back sides of the IGBT 11 and the diode 12 are each connected to the front-side wiring layer 22 by a solder 23.

[0025] As a result, the heat generated by the IGBT 11 and the diode 12 is transferred via the solder 23, the front-side wiring layer 22, the ceramic substrate 14, the back-side wiring layer 21, the solder 20, the metal base 1, and the fins 4 to a cooling medium such as cooling water or air, which is not shown in the drawing. This cools the IGBT 11 and the diode 12.

[0026] Furthermore, the IGBT 11 and the diode 12 are insulated from the metal base 1 by a ceramic substrate 14. The surfaces of the IGBT 11 and the diode 12 are connected to the conductor frame 13 by a solder 24.

[0027] As in Fig. As shown in Figure 5, in the power module 100 of the present example, the roughened layer 30 is provided on the surface of the front-side wiring layer 22. By providing the roughened layer 30, the clamping force between the high-temperature-resistant epoxy resin 3 and the front-side wiring layer 22 can be mechanically improved by an anchoring effect, and detachment due to thermal stress can be prevented.

[0028] The roughened layer 30 on the surface of the front-end wiring layer 22 is formed, for example, by etching the surface of the front-end wiring layer 22. Alternatively, if the front-end wiring layer 22 is made of copper (Cu), a roughened nickel plating layer can be formed as the roughened layer 30 on the front-end wiring layer 22.

[0029] As described up to this point, the power module 100 of the present example comprises power semiconductor chips (an IGBT 11 and a diode 12), an insulating circuit substrate 10 on which the power semiconductor chips are mounted, and a sealing resin (high-temperature resistant epoxy resin 3) for sealing at least the power semiconductor chip and the connection section of the insulating circuit substrate 10 with the power semiconductor chip. The insulating circuit substrate 10 has a ceramic substrate 14 and a front-side wiring layer 22 formed on the surface of the ceramic substrate 14, and the front-side wiring layer 22 has the roughened layer 30 on its surface opposite its connection area with the ceramic substrate 14.

[0030] Furthermore, the roughened layer 30 is formed on the contact surface of the front wiring layer 22 with the sealing resin (high heat resistant epoxy resin 3).

[0031] In addition, for example a silicon nitride ceramic substrate is used for ceramic substrate 14.

[0032] The roughened layer 30 allows the high-temperature-resistant epoxy resin 3 to penetrate the crevices of the roughened layer 30 during casting and solidify there. As a result, the clamping force is mechanically enhanced by an anchoring effect, similar to that resulting from the engagement of a hook's barb (also known as mechanical interlocking, anchoring effect, or fastening effect). This can prevent loosening due to thermal stress. Second embodiment

[0033] With reference to the Fig. 6A and Fig. Section 6B describes a semiconductor device according to Example 2 of the present invention and a manufacturing method thereof.

[0034] Fig. Figure 6A shows a view illustrating part of the manufacturing steps of the power module 100 of the present example. Fig. 6B shows a view that depicts a manufacturing step following Fig. 6A is shown.

[0035] During the formation of the insulating circuit substrate 10, as described in Fig. As shown in Figure 6A, the backside wiring layer 21 and the frontside wiring layer 22 are bonded to the ceramic substrate 14 and then passed through an etching agent. As a result, as shown in Fig. Figure 6B shows the roughened layer 30 formed on both surfaces of the backside wiring layer 21 and the frontside wiring layer 22.

[0036] Although it is necessary to mask the backside wiring layer 21 when the roughened layer 30 is formed only on the frontside wiring layer 22, in the present example a mask is not required, and production can be achieved at low cost by reducing the number of steps.

[0037] Incidentally, the roughened layer 30 has no effect on the soldering, and the bond strength with which the back-side wiring layer 21 and the metal base 1 are bonded to each other by the solder 20 is the same as that in the case where the roughened layer 30 is not present.

[0038] Furthermore, if the backside wiring layer 21 and the frontside wiring layer 22 are made of copper (Cu), the roughened layer 30 can be formed by applying a roughened nickel plating to the surface.

[0039] As described up to this point, in the power module 100 of the present example, the insulating circuit substrate 10 has the backside wiring layer 21 formed on the back side of the ceramic substrate 14, and the backside wiring layer 21 has the roughened layer 30 on the surface opposite its interface with the ceramic substrate 14. Example 3

[0040] With reference to the Fig. 7A and Fig. 7B describes a semiconductor device according to Example 3 of the present invention.

[0041] Fig. Figure 7A shows a partial cross-sectional view of a power module 100 of the present example and is a view that Fig. 5 corresponds to Example 1. Fig. Figure 7B shows a diagram (top view) of the roughened layer 30 when viewed in the B-B' direction in Fig. 7A.

[0042] In example 1 ( Fig. 5) A description was given of an example in which the roughened layer 30 is formed on the entire surface of the front-side wiring layer 22, including the connection surface with the IGBT 11. In the present example ( Fig. 7A and Fig. 7B) In contrast, the roughened layer 30 is not formed on the interface between the front-side wiring layer 22 and the IGBT 11, and the roughened layer 30 is only provided on the surface of the front-side wiring layer 22 that is in contact with the high-temperature epoxy resin 3. The present example differs in this respect from Example 1 ( Fig. 5).

[0043] As in the present example, by providing the roughened layer 30 in the area of ​​the front-side wiring layer 22, which is different from the connection section with the IGBT 11, the clamping force between the high-temperature resistant epoxy resin 3 and the front-side wiring layer 22 can be mechanically improved by an anchoring effect in the same way as in Example 1, so that detachment due to thermal stress can be prevented.

[0044] Incidentally, the present invention can, for example, be applied to a power module that uses a different power semiconductor chip, such as silicon carbide (SiC) or gallium nitride (GaN), than the power semiconductor chip that uses the silicon substrate.

[0045] Furthermore, the present invention is not limited to the preceding examples and includes various modifications. For example, the preceding examples have been described in detail to clearly describe the present invention, and they are not necessarily limited to those that have all the described configurations. Furthermore, it is also possible to replace part of the configuration of one example with the configuration of another example, and it is also possible to add the configuration of another example to the configuration of a particular example. It is also possible to add, delete, or replace part of the configuration of each example with another configuration. Reference symbol list 1 Metal base 2 cases 3 Highly heat-resistant epoxy resin 4 slats 10 Insulation circuit substrate 11 IGBT 12 diode 13 ladder frames 14 Ceramic substrate 20 Lot 21 Backside wiring layer 22 Front-end wiring layer 23 Lot 24 Lot 30 Roughened layer 100 power module QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2019-197842 A

[0004]

Claims

Semiconductor device comprising: a power semiconductor chip; an insulating circuit substrate on which the power semiconductor chip is mounted; and a sealing resin sealing at least the power semiconductor chip and a connecting section of the insulating circuit substrate with the power semiconductor chip, wherein the insulating circuit substrate comprises a ceramic substrate and a front-side wiring layer formed on a surface of the ceramic substrate, and the front-side wiring layer comprises a first roughened layer on a surface opposite a connecting surface with the ceramic substrate. Semiconductor device according to claim 1, wherein the first roughened layer is formed on a contact surface of the front-side wiring layer with the sealing resin. Semiconductor device according to claim 1, wherein the insulating circuit substrate has a backside wiring layer formed on a back side of the ceramic substrate, and the backside wiring layer has a second roughened layer on a surface opposite the interface with the ceramic substrate. Semiconductor device according to one of claims 1 to 3, wherein the sealing resin is a highly heat-resistant epoxy resin. Semiconductor device according to one of claims 1 to 3, wherein the ceramic substrate is a silicon nitride ceramic substrate. Semiconductor device according to one of claims 1 to 3, wherein the first roughened layer is formed by etching a surface of the front-side wiring layer. Semiconductor device according to claim 3, wherein the second roughened layer is formed by etching a surface of the backside wiring layer. Semiconductor device according to one of claims 1 to 3, wherein the front-side wiring layer is formed of copper, and the first roughened layer is a roughened nickel-plated layer formed on the front-side wiring layer. Semiconductor device according to claim 3, wherein the backside wiring layer is formed of copper, and the second roughened layer is a roughened nickel-plated layer formed on the backside wiring layer. Semiconductor device according to claim 1, wherein the first roughened layer is formed in a region of the front-side wiring layer that is other than the interconnection section with the power semiconductor chip.

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