Semiconductor Device and Method for Manufacturing a Semiconductor Device

Abstract

A semiconductor device is provided which has a structure in which both a front and a back of a semiconductor element are connected to a rigid body via a solder alloy, wherein the semiconductor device is able to mitigate the influence of thermal stress generated on both the front and back of the semiconductor element during use of the semiconductor device.This semiconductor device comprises: a semiconductor element; a conductor frame; an insulating substrate; a first interconnecting material connecting the semiconductor element and the conductor frame; a second interconnecting material connecting the semiconductor element and the insulating substrate; and a third interconnecting material connecting the insulating substrate and the conductor frame, wherein a solidus temperature of the first interconnecting material is lower than a solidus temperature of the second interconnecting material and a solidus temperature of the third interconnecting material is equal to or higher than the solidus temperature of the second interconnecting material.

Description

Technical field

[0001] The present invention relates to a semiconductor device with a structure in which both a front and a back side of a semiconductor element are connected to a rigid body via a solder alloy, and to a method for manufacturing the semiconductor device. State of the art

[0002] The semiconductor power module is known from patent literature 1 as a semiconductor device with a structure in which both a front and a back side of a semiconductor element are connected to a rigid body via a solder alloy.

[0003] For example, paragraph 0088 of patent literature 1 states: “The in Fig. The semiconductor module (semiconductor power module) 19 shown in Figure 10 has a configuration in which interconnect materials such as solder alloy 2b and solder alloy 2b are bonded to both a front and a back side of the semiconductor chip 1, a conductor frame 28 is bonded to the interconnect materials on both sides of the semiconductor chip 1, and a heat-dissipating metal plate 12 is further bonded to the conductor frame 28 via an insulating heat-dissipating grease 27. The semiconductor power module made of Fig. Paragraph 10 of patent literature 1 describes the device as having a structure in which each of the front and back faces of the semiconductor chip is connected to a conductor frame, which is a rigid body, via solder alloys arranged on both the front and back faces of the semiconductor chip. Furthermore, the abstract and paragraph 0029 et seq. of patent literature 1 show that the solder alloy is made of Sn-Cu-Sb. List of cited documents Patent literature

[0004] Patent literature 1: WO 2016 / 079881 Summary of the invention: Technical problem

[0005] In general, a solder alloy made from Sn-Cu-Sb exhibits high thermal fatigue resistance. Therefore, it allows the use of an Sn-Cu-Sb solder alloy on both the front and back faces of a semiconductor device, as in Fig. 10 of patent literature 1, to achieve a highly reliable bonding of the semiconductor element.

[0006] Although a solder made from Sn-Cu-Sb exhibits high thermal fatigue resistance, it tends to be harder than ordinary Sn-based solders. Patent literature 1 does not consider a configuration in which both the front and back faces of a semiconductor device are clamped by a hard solder alloy to be a particular problem and does not pay special attention to the thermal stress that is generated on both the front and back faces of the semiconductor device when the temperature rises during use of the semiconductor device.

[0007] Accordingly, it is an object of the present invention to provide a semiconductor device having a structure in which both a front and a back side of a semiconductor element are connected to a rigid body via a solder alloy, wherein the semiconductor device is able to mitigate the influence of thermal stress generated on both the front and back sides of the semiconductor element during use of the semiconductor device, and to provide a method for manufacturing the semiconductor device. Solution to the problem

[0008] To solve the above problem, the semiconductor device of the present invention comprises: a semiconductor element; a conductor frame; an insulating substrate; a first interconnecting material connecting the semiconductor element and the conductor frame; a second interconnecting material connecting the semiconductor element and the insulating substrate; and a third interconnecting material connecting the insulating substrate and the conductor frame, wherein the solidus temperature of the first interconnecting material is lower than the solidus temperature of the second interconnecting material and the solidus temperature of the third interconnecting material is equal to or higher than the solidus temperature of the second interconnecting material.

[0009] Furthermore, the method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device by heating, in a heating oven, a semiconductor element, a conductor frame, an insulating substrate, a first connecting material connecting the semiconductor element and the conductor frame, a second connecting material connecting the semiconductor element and the insulating substrate, and a third connecting material connecting the insulating substrate and the conductor frame, wherein the method comprises: a step of placing the insulating substrate on a support; a step of placing the second connecting material on a metal wiring section of the insulating substrate; a step of placing the semiconductor element on the second connecting material; a step of placing the first connecting material on the semiconductor element;a step of placing a plurality of the third interconnect materials onto the metal wiring section; a step of placing the conductor frame such that it spans the plurality of third interconnect materials in order to provide a gap between the conductor frame and the first interconnect material; a step of melting the first interconnect material and bonding it to an upper surface of the semiconductor element; a step of melting the second interconnect material and bonding a lower surface of the semiconductor element and the metal wiring section; and a step of melting the third interconnect material to bond the conductor frame and the metal wiring section, and bonding the upper surface of the semiconductor element and the conductor frame over the molten first interconnect material. Advantageous effects of the invention

[0010] According to the present invention, in a semiconductor device with a structure in which both a front and a back side of a semiconductor element are connected to a rigid body via a solder alloy, it is possible to mitigate the influence of thermal stress that is generated on both the front and back sides of the semiconductor element during use of the semiconductor device. Brief description of the drawings Fig. Figure 1 shows a schematic cross-sectional view of the semiconductor device of Example 1. Fig. Figure 2A shows a perspective view of the manufacturing process of the semiconductor device of Example 1 (before placement in the heating oven). Fig. Figure 2B shows a perspective view of the manufacturing process of the semiconductor device of Example 1 (before placement in the heating oven). Fig. Figure 3 shows a schematic cross-sectional view that illustrates a simplified representation of the manufacturing process of Example 1 (before placement in the heating oven). Fig. Figure 4 shows a schematic cross-sectional view that illustrates a simplified representation of the manufacturing process of Example 1 (after placement in the heating oven). Fig. Figure 5 shows a schematic cross-sectional view, which provides a simplified representation of the manufacturing process of the comparative example (after placement in the heating oven). Fig. Figure 6 shows an example of a cross-sectional view of a conductor frame of the semiconductor device from Example 2. Fig. Figure 7 shows another example of a cross-sectional view of a conductor frame of the semiconductor device from Example 2. Description of embodiments

[0011] Embodiments of the semiconductor device of the present invention are described below with reference to the drawings. Example 1

[0012] The semiconductor device 1 according to Example 1 of the present invention is described with reference to the Fig. 1, Fig. 2, Fig. 3, Fig. 4 to Fig. 5 described. It should be noted that in the following description the semiconductor device 1 is described as a semiconductor power module for delivering high power to drive motors of trains and electric vehicles; however, the semiconductor device 1 of the present invention may be a different type of semiconductor device. <Komponenten der Halbleitervorrichtung 1>

[0013] First, the components of the semiconductor device 1 of the present embodiment are described with reference to the cross-sectional view of Fig. 1 described therein. As shown therein, the semiconductor device 1 of the present embodiment comprises an insulating substrate 11, a semiconductor element 12, a conductor frame 13, a first interconnect material 14, a second interconnect material 15, a third interconnect material 16, a heat dissipation material 17, a fourth interconnect material 18, and a sealing material 19. Each of these is briefly described below. It should be noted that in the following description, the vertical direction is used as in Fig. 1 is shown and defined.

[0014] The insulating substrate 11 is a rigid body in which metal wiring sections 11b of a desired number and shape are arranged on the upper surface (front side) of an insulating plate 11a made of ceramic.

[0015] The semiconductor element 12 is a chip that corresponds to the function of the semiconductor device 1; for example, if the semiconductor device 1 is a semiconductor power module, the semiconductor element is an IGBT-embedded chip 12a, a diode-embedded chip 12b, or the like.

[0016] The conductor frame 13 is a rigid copper body for carrying high current, comprising: a plurality of terminals 13a projecting laterally to be electrically connected to the upper surface of the metal wiring section 11b of the insulating substrate 11; and a projection 13b projecting downwards to be electrically connected to the upper surface of the semiconductor element 12.

[0017] The first joining material 14 is a solder alloy for joining the upper surface of the semiconductor element 12 and the lower surface of the projection 13b of the conductor frame 13; for example, it is Sn-Cu solder with a solidus temperature T1 of 227°C. It should be noted that Sn-Cu solder is a relatively soft solder and has excellent stress relaxation properties; therefore, even if thermal stress arises from heat generated during the use of the semiconductor device 1, the Sn-Cu solder on the upper surface of the semiconductor element 12 can absorb the thermal stress, and damage to the semiconductor element 12 due to thermal stress can be suppressed.

[0018] The second bonding material 15 is a solder alloy for joining the lower surface of the semiconductor element 12 and the upper surface of a metal wiring section 11b; for example, it is Sn-Cu-Sb solder with a solidus temperature T2 of more than 227°C and less than 240°C. It should be noted that Sn-Cu-Sb solder, as described above, exhibits a property of high thermal fatigue resistance and can therefore bond the semiconductor element 12 firmly to the upper surface of the metal wiring section 11b.

[0019] The third joining material 16 is a solder alloy for joining the lower surface of the terminals 13a of the conductor frame 13 and the upper surface of the metal wiring section 11b; for example, it is Sn-Cu-Sb solder with a solidus temperature T3 of more than 227°C and less than 240°C. The solidus temperature T3 only needs to be higher than the solidus temperature T1 and equal to or higher than the solidus temperature T2.

[0020] The heat dissipation material 17 is a metal plate comprising heat dissipation fins 17a for dissipating heat generated during the use of the semiconductor device 1. It should be noted that, although Fig. Figure 1 illustrates the heat dissipation material 17 including heat dissipation fins 17a, the configuration which can omit the heat dissipation fins 17a.

[0021] The fourth joining material 18 is a solder alloy for joining the lower surface of the insulating substrate 11 and the upper surface of the heat dissipation material 17; for example, it can be Sn-Cu solder with a solidus temperature T4 of 227°C, Sn-Cu-Sb solder with a solidus temperature T4 of more than 227°C and less than 240°C, or a solder alloy containing Sn as a major component and having a solidus temperature of less than 232°C.

[0022] The sealing material 19 is a heat-resistant resin mold that seals the respective components described above. <Herstellungsprozess der Halbleitervorrichtung 1>

[0023] Next, the manufacturing process of the main parts of the semiconductor device 1 will be described with reference to the group of perspective views (which also serve as a flowchart) of the Fig. 2A and Fig. 2B and Fig. Figure 3, which is a schematic view showing a simplified cross-section of both figures, is described. It should be noted that a known chip mounting device can be used to place the respective components shown in the figures.

[0024] Step S1 is a procedure for placing the insulating substrate 11 onto a support (not shown) with the side of the metal wiring section 11b facing upwards. The support used here is formed by machining a carbon plate to conform to the shape of the insulating substrate 11. The following description outlines the procedure for placing the components on the front side of the top surface, assuming that the placement of the components on the rear side of the top surface of the insulating substrate 11 is complete.

[0025] Step S2 is a procedure for placing a sheet-shaped second connecting material 15 onto the upper surface of the metal wiring section 11b (front side) of the insulating substrate 11. This example shows a state in which a relatively large rectangular second connecting material 15a and a relatively small rectangular second connecting material 15b have been placed on the upper surface of the metal wiring section 11b (front side).

[0026] Step S3 is a procedure for placing the semiconductor element 12 onto the top surface of the second interconnect material 15. This example shows a state in which a relatively large IGBT-embedded chip 12a has been placed on the top surface of a relatively large second interconnect material 15a, and a relatively small diode-embedded chip 12b has been placed on the top surface of a relatively small second interconnect material 15b.

[0027] Step S4 is a procedure for placing a sheet-shaped first interconnect material 14 onto the top surface of the semiconductor element 12. This example shows a state in which a relatively large first interconnect material 14a has been placed onto the top surface of the relatively large IGBT-embedded chip 12a, and a relatively small first interconnect material 14b has been placed onto the top surface of the relatively small diode-embedded chip 12b.

[0028] Step S5 is a procedure for placing a sheet-shaped third connecting material 16 onto the upper surface of the metal wiring section 11b. This example shows a state in which a third connecting material 16 has been placed on each of the two metal wiring sections 11b on which the two terminals 13a of the conductor frame 13 are to be placed according to plan.

[0029] Step S6 is a procedure for positioning the ladder frame 13 such that it spans the two third connecting materials 16. In this example, by supporting the two terminals 13a of the ladder frame 13 with two third connecting materials 16a, a gap is formed between the projection 13b of the ladder frame 13 and the first connecting material 14.

[0030] Next, step S7 will be described with reference to Fig. 4 described which of the representation of Fig. Step 3 follows. This step is a procedure in which the components stacked on the jig by steps S1 to S6 (hereinafter referred to as the "element-loaded jig") are transferred to the heating furnace and heated, and each bonding material is sequentially melted and solidified to fix the respective components. It should be noted that if the ladder frame 13 is lightweight, a step of placing a ballast weight to apply a load to the ladder frame 13 prior to heating in the furnace may be provided.

[0031] Step S7a: In the period immediately after the element-loaded holder is placed in the heating oven, when the temperature of the element-loaded holder is lower than the solidus temperature T1, the terminals 13a of the conductor frame 13 are supported by the third connecting material 16, which is fixed, so that a gap exists between the projection 13b and the first connecting material 14.

[0032] Step S7b: During the time interval when the temperature of the element-loaded holder is higher than the solidus temperature T1 of the first bonding material 14 and lower than the solidus temperature T2 of the second bonding material 15, the first bonding material 14 melts and bonds to the upper surface of the semiconductor element 12; however, since a gap still exists above the first bonding material 14, the molten first bonding material 14 does not bond to the projection 13b of the conductor frame 13 at this point.

[0033] Step S7c: When the temperature of the element-loaded holder exceeds the solidus temperature T3 of the third interconnect material 16, the terminals 13a of the conductor frame 13, which have lost their support due to the melting of the third interconnect material 16, move downwards. The already molten first interconnect material 14 and the projection 13b then come into contact. Since at this time the molten first interconnect material 14 is drawn towards the projection 13b by wetting force, an upward force, attributable to the wetting force of the first interconnect material 14, also acts on the semiconductor element 12 beneath the first interconnect material 14.

[0034] On the other hand, since the already molten second compound material 15 is drawn towards the side of the insulating substrate 11 by wetting force, a downward force, attributable to the wetting force of the second compound material 15, also acts on the semiconductor element 12 above the second compound material 15. Because the upward force, attributable to the wetting force of the first compound material 14, and the downward force, attributable to the wetting force of the second compound material 15, cancel each other out, the semiconductor element 12 therefore does not float any more than necessary.

[0035] Step S7d: When the heating is stopped and the temperature of the element-loaded holder becomes lower than the solidus temperature T1 of the first interconnect material 14, the respective components of the semiconductor device 1 are fixed in the desired positions.

[0036] As described in Step S7 above, by sequentially melting and solidifying the first compound material 14 through the third compound material 16, the amount of wetting from the first compound material 14 through the third compound material 16 can be appropriately controlled, and the upper surface of the semiconductor element 12 and the projection 13b of the conductor frame 13, the lower surface of the semiconductor element 12 and the metal wiring section 11b of the insulating substrate 11, as well as the terminal 13a of the conductor frame 13 and the metal wiring section 11b of the insulating substrate 11 can be advantageously connected.

[0037] It should be noted that it goes without saying that after step S7, by attaching the heat dissipation material 17 with the fourth connecting material 18 and further resin capsules of the semiconductor element 12 and the like with the sealing material 19 by known methods, the semiconductor device 1 with the in Fig. The structure shown in the illustration can be produced. <vergleichsbeispiel>

[0038] To explain the effectiveness of step S7 here Fig. To supplement Section 4, the problems of step S7' in the manufacturing process of the semiconductor device 1' of the comparative example are outlined. It should be noted that the semiconductor device 1' of the comparative example is equivalent to the semiconductor device 1 of the present embodiment, except that the first interconnect material 14 and the third interconnect material 16 are made of the same material and their solidus temperature T13 is lower than the solidus temperature T2 of the second interconnect material 15. In step S7' of the semiconductor device 1' of this comparative example, the following phenomena occur in the heating oven.

[0039] Step S7a': In the period immediately after the element-loaded holder is placed in the heating oven, when the temperature of the element-loaded holder is lower than the solidus temperature T13 of the first connecting material 14 and the third connecting material 16, the terminals 13a of the conductor frame 13 are supported by the third connecting material 16, which is solid, so that a gap exists between the projection 13b and the first connecting material 14.

[0040] Step S7b': During the period when the temperature of the element-loaded holder is higher than the solidus temperature T13 of the first bonding material 14 and the third bonding material 16 and lower than the solidus temperature T2 of the second bonding material 15, the first bonding material 14 melts and bonds to the upper surface of the semiconductor element 12, and the terminals 13a of the conductor frame 13, which have lost their hold due to the melting of the third bonding material 16, move downwards.

[0041] When the gap above the first connecting material 14 is eliminated and the upper surface of the molten first connecting material 14 comes into contact with the projection 13b of the conductor frame 13, an upward force, attributable to the wetting force of the first connecting material 14, also acts on the semiconductor element 12 below the first connecting material 14, since the molten first connecting material 14 is drawn towards the projection 13b by wetting force.

[0042] In contrast to step S7c of Fig. However, since the second connecting material 15 is still solid, the downward force attributable to the wetting force of the second connecting material 15 does not act on the semiconductor element 12. Therefore, as shown in the figure, an undesirable phenomenon called chip floating occurs, in which the semiconductor element 12 separates from the second connecting material 15. Furthermore, the following problems also arise as a result of chip floating.

[0043] First, since the downward force attributable to the wetting force of the second compound material 15 does not act on the first compound material 14, the molten first compound material 14 rises into an area not provided for by the design (for example, the side face of the projection on the lower face of the conductor frame 13, etc.), resulting in a reduced amount of the first compound material 14 remaining between the projection 13b of the conductor frame 13 and the semiconductor element 12, and there is a risk of connection failure between the projection 13b and the semiconductor element 12.

[0044] Secondly, if chip floating occurs, the weight of the semiconductor element 12 is also transferred via the terminals 13a of the conductor frame 13 to the molten third interconnect material 16. As a result, the third interconnect material 16 protrudes below the terminals 13a into an area not provided for by the design, the amount of third interconnect material 16 remaining between the terminal 13a of the conductor frame 13 and the insulating substrate 11 is reduced, and there is a risk of interconnect failure also occurring between the terminal 13a and the insulating substrate 11.

[0045] Step S7c': If the temperature of the element-loaded holder becomes higher than the solidus temperature T2 of the second compound material 15, a downward force, attributable to the wetting force of the molten second compound material 15, also acts on the semiconductor element 12; however, since the problems encountered in step S7b' are irreversible, the various problems described above are not solved by the downward force attributable to the wetting force of the second compound material 15.

[0046] Furthermore, if the semiconductor element 12 is located at a higher position than intended due to chip floating, there is a risk of connection failure between the semiconductor element 12 and the insulating substrate 11 due to an insufficient amount of the second connecting material 15.

[0047] Step S7d': When the heating is stopped and the temperature of the element-loaded holder falls below the solidus temperature T13 of the first interconnect material 14 and the third interconnect material 16, the respective components of the semiconductor device 1' are fixed. That is, the various problems encountered in steps S7b' and S7c' are also fixed.

[0048] According to the manufacturing process of the comparative example described above, chip floating and various properties attributable to it occur; however, according to the manufacturing process of the present embodiment, chip floating does not occur, and problems attributable to it also do not occur.

[0049] Furthermore, in the semiconductor device of the present embodiment, since relatively soft Sn-Cu solder is arranged on the upper surface of the semiconductor element and Sn-Cu-Sb solder with high thermal fatigue resistance is arranged on the lower surface of the semiconductor element, it is possible to mitigate the influence of thermal stresses that are generated on both the front and back of the semiconductor element during use of the semiconductor device. Example 2

[0050] Next, semiconductor device 1 according to Example 2 of the present invention is described with reference to the Fig. 6 and Fig. 7 described. It should be noted that descriptions of points that are common to those in Example 1 are omitted.

[0051] In the Fig. In the manufacturing process shown in Example 1, no configuration exists to control the amount of wetting of the first bonding material 14 when the molten first bonding material 14 comes into contact with the lower surface of the projection 13b of the conductor frame 13; therefore, even if the sequence of melting the respective bonding materials can be adequately controlled, there is a risk that the molten first bonding material 14 may spread into an area not provided for in the design. Therefore, in the present embodiment, a configuration has been added to keep the spread area of ​​the molten first bonding material 14 within the intended area.

[0052] For example, as in Fig. Figure 6 shows a wetting spread prevention material 13c, consisting of a resin or resist material, applied to the side surface of the projection 13b of the conductor frame 13. Since this wetting spread prevention material 13c has a low affinity for the molten first bonding material 14, it is effective even in a situation where chip floating occurs, as in Figure 6. Fig. 5(b) shown, it is possible to suppress the spread of the molten first compound material 14 into the region coated with the wetting spread prevention material 13c (i.e., a region where an overflow of the first compound material 14 is not intended by design) and to keep the spread area of ​​the first compound material 14 within the lower surface of the projection 13b.

[0053] Alternatively, as in Fig. As shown in Figure 7, the material to prevent wetting spread 13c, consisting of a resin material or a resist material, can be applied to the outer circumference of the lower surface of the projection 13b of the conductor frame 13. This configuration can also have the same effect as Fig. Score 6. List of reference symbols 1 Semiconductor device 11 insulating substrate 11a insulating plate 11b Metal wiring section 12 Semiconductor element 13 ladder frames 13a connection 13b advantage 13c Material to prevent the spread of wetting 14 first connecting material 15 second connecting material 16 third connecting material 17 Heat dissipation material 18 fourth connecting material 19 Sealing material 20 metal wire QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] WO 2016 / 079881

[0004] < / vergleichsbeispiel>

Claims

Semiconductor device comprising: a semiconductor element; a conductor frame; an insulating substrate; a first interconnecting material connecting the semiconductor element and the conductor frame; a second interconnecting material connecting the semiconductor element and the insulating substrate; and a third interconnecting material connecting the insulating substrate and the conductor frame, wherein a solidus temperature of the first interconnecting material is lower than a solidus temperature of the second interconnecting material and a solidus temperature of the third interconnecting material is equal to or higher than the solidus temperature of the second interconnecting material. Semiconductor device according to claim 1, wherein the first compounding material is a Cu-Sn-based solder containing Sn and Cu, and the second compounding material is a Sn-Cu-Sb-based solder containing Sn, Cu and Sb. Semiconductor device according to claim 1, wherein the conductor frame comprises a terminal projecting laterally and a projection projecting downwards, the projection being bonded to an upper surface of the semiconductor element via the first bonding material, and the terminal being bonded to a metal wiring section of the insulating substrate via the third bonding material. Semiconductor device according to claim 3, wherein a side surface of the projection is coated with a resin material or a resist material. Semiconductor device according to claim 3, wherein an outer circumference of a lower surface of the projection is coated with a resin material or a resist material. A method for manufacturing a semiconductor device by heating in a heating oven, comprising a semiconductor element, a conductor frame, an insulating substrate, a first interconnect material connecting the semiconductor element and the conductor frame, a second interconnect material connecting the semiconductor element and the insulating substrate, and a third interconnect material connecting the insulating substrate and the conductor frame, the method comprising: a step of placing the insulating substrate on a support; a step of placing the second interconnect material on a metal wiring section of the insulating substrate; a step of placing the semiconductor element on the second interconnect material; a step of placing the first interconnect material on the semiconductor element; a step of placing a plurality of the third interconnect materials on the metal wiring section;a step of placing the conductor frame such that it spans the majority of third interconnect materials to provide a gap between the conductor frame and the first interconnect material; a step of melting the first interconnect material and bonding it to an upper surface of the semiconductor element; a step of melting the second interconnect material and bonding a lower surface of the semiconductor element and the metal wiring section; and a step of melting the third interconnect material to bond the conductor frame and the metal wiring section, and bonding the upper surface of the semiconductor element and the conductor frame over the molten first interconnect material.

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