Non-volatile memories with variable resistance, processes and associated assemblies

Abstract

NON-VOLATILE MEMORIES WITH VARIABLE RESISTANCE, METHODS AND ASSOCIATED ASSEMBLIES The invention relates to a memory (100) comprising: a main conducting electrode (120) forming a cathode; a secondary conducting electrode (130) forming an anode; and a semiconducting ferroelectric layer (110) forming an active layer, disposed between the cathode and the anode (120, 130), the active layer (110) having a ferroelectric polarization (111) having a plurality of stable states, the cathode (120) forming a main contact with the active layer (110), the resistance of the main contact varying in a strictly monotonic way as a function of the ferroelectric polarization (111), the behavior of the main contact forming, as a function of the ferroelectric polarization (111): an ohmic contact for a first stable state of the plurality of stable states;and a Schottky contact for at least a second stable state of the plurality of stable states, the active layer (110) being degenerate and exhibiting a band gap energy less than 1.5 eV. Figure to be published with the abbreviation: Figure 1;

Description

Title of the invention: Non-volatile memories with variable resistance, methods and associated assemblies TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of non-volatile variable resistance memories. The technical field also relates to methods for reading and manufacturing such memories, as well as the assembly of such memories in the form of logic gates and matrices. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] Variable resistance memories, known as "memristors," are capable of storing information at at least two levels. In some cases, these memristors are also capable of storing information that may have intermediate levels and / or perform logical operations. This latter type of memory is of particular interest in the implementation of new computing paradigms, such as analog computing or neuromorphic computing.

[0003] Memristors encompass several families of memory types, including magnetic and resistive memories. Magnetic memories store information in a relative orientation of magnetic moments. Resistive memories store information in the resistance of one of their constituent layers. The change in layer resistance is induced, for example, by a controlled breakdown of the layer or a phase change in the material from which it is composed.

[0004] Among the qualities of memristors, it is expected that a memristor will exhibit a resistance variation, known as the "on / off ratio," sufficiently high to be measured easily and quickly, for example, greater than 102, and that this on / off ratio will be measurable even with a low reading voltage. It is also expected that a memristor will exhibit high endurance, greater than 107 cycles.

[0005] The most common magnetic memories include magnetic tunnel junctions (MTJs). MTJs generally exhibit good endurance. However, they have a low on / off ratio, for example, of a few units.

[0006] Resistive memories in which one of the layers undergoes a phase change or electrostatic breakdown generally exhibit limited endurance. Other types of resistive memories, such as RRAM (Resistive Random Access Memory), also exhibit limited endurance.

[0007] There is therefore a need for a non-volatile variable resistance memory showing good endurance and a high on / off ratio, even with a low read voltage.

[0008] The document [VAROTTO, Sara, NESSI, Luca, CECCHI, Stefano, et al. “Room-temperature ferroelectric switching of spin-to-charge conversion in germanium telluride.” Nature Electronics, 2021, vol. 4, no. 10, pp. 740–747.] discloses a ferroelectric memory. This memory comprises, on the one hand, a semiconducting ferroelectric layer of GeTe, and on the other hand, a conducting electrode of Ti. In addition to exhibiting stable ferroelectric polarization, the GeTe layer is also intrinsically degenerate and has a low band gap energy, on the order of 0.7 eV. The contact between the electrode and the semiconducting ferroelectric layer forms a Schottky barrier whose height and / or width varies depending on the polarization of the GeTe layer. Summary of the invention

[0009] The invention relates to a memory comprising: • a main conducting electrode forming a cathode; • a secondary conducting electrode forming an anode; and • a semiconducting ferroelectric layer forming an active layer, disposed between the cathode and the anode, the active layer having a ferroelectric polarization (111) exhibiting a plurality of stable states, the cathode forming a principal contact with the active layer, the resistance of the principal contact varying in a strictly monotonic manner as a function of the ferroelectric polarization, the behavior of the principal contact forming, as a function of the ferroelectric polarization: • an ohmic contact for a first stable state of the plurality of stable states; and • a Schottky contact for at least one second stable state out of the plurality of stable states, the active layer being degenerate and exhibiting a band gap of less than 1.5 eV.

[0010] The semiconductor ferroelectric layer allows information to be stored in a non-volatile manner thanks to the ferroelectric polarization, which can adopt stable states. A measurement of the resistance of the main contact (for example, by measuring the total resistance between the cathode and the anode) makes it possible to determine which stable state the ferroelectric polarization is in and therefore allows the information stored in the memory to be read.

[0011] The change in behavior (from ohmic to Schottky or vice versa) for the main contact ensures that the resistance variation associated with two distinct states is large enough to be easily measurable.

[0012] Since the semiconducting ferroelectric layer is degenerate and has a small band gap, it exhibits low resistivity. The measurable resistance of the memory therefore depends primarily on the resistance of the main contact. Consequently, the ON / OFF ratio, defined as Rwr, measured for two polarization states ferroelectric, where Rq^ is the minimum resistance and Rqff is the maximum resistance, is optimal, for example greater than 102 or even greater than 105.

[0013] Thanks to the main contact, the memory can function as a Schottky diode. The primary conductive electrode forms, for example, a cathode of the Schottky diode, while the secondary conductive electrode forms an anode of the Schottky diode. The main memory can therefore be used in a circuit where a Schottky diode is needed. It can be used as a selector for a memory. The memory according to the invention is doubly advantageous in this type of circuit because the main contact can be made ohmic, making it possible to "deactivate" the equivalent Schottky diode by rendering it transparent.

[0014] Advantageously, the main contact also forms a Schottky contact for a third stable state of the plurality of stable states, the resistance of the main contact for the second stable state being less than the resistance of the main contact for the third stable state.

[0015] Thus, the memory according to the invention can maintain a Schottky behavior in which the resistance at the cathode varies according to the state of the bias of the semiconductor ferroelectric layer. The leakage currents of an array integrating memories according to the invention are therefore very low when the selected memory is forward-biased, which means that the leakage currents correspond to paths passing through reverse-biased memories and are therefore blocked.

[0016] Unlike memories in which a phase change, or breakdown, occurs in one of the layers, the memory according to the invention stores information through its electrical polarization. The electrical polarization can be switched a large number of times without inducing significant aging. Therefore, and like all ferroelectric memories, the memory according to the invention exhibits very high endurance.

[0017] In addition to the characteristics mentioned in the preceding paragraphs, the memory according to the invention may have one or more additional characteristics from among the following, considered individually or according to all technically possible combinations:

[0018] The main contact also forms a Schottky contact for a third stable state of the plurality of stable states, the resistance of the main contact for the second stable state being less than the resistance of the main contact for the third stable state.

[0019] The main contact is formed at the level of an interface between the active layer and the cathode, and in which, for each stable state, the ferroelectric polarization has, at the level of said interface, a component normal to said interface.

[0020] The anode forms an ohmic contact with the active layer, the resistance of the ohmic contact being independent of the ferroelectric polarization.

[0021] The anode is semiconductor and forms a heterojunction or a homojunction with the active layer. In this case, the anode may comprise a stack of two semiconductor sublayers, a first semiconductor sublayer being undoped and a second semiconductor sublayer being doped, the second semiconductor sublayer forming a homojunction with the active layer.

[0022] The anode forms a secondary contact with the active layer, the resistance of the secondary contact varying in a strictly monotonic way as a function of the ferroelectric polarization, the resistance of the primary contact as a function of the ferroelectric polarization exhibiting a first tendency of monotony and the resistance of the secondary contact as a function of the ferroelectric polarization exhibiting a second tendency of monotony, the two tendencies of monotony being opposite.

[0023] The stack includes an insulating layer disposed between the active ferroelectric layer and the cathode or between the active layer and the anode.

[0024] According to an advantageous embodiment, the active ferroelectric layer is made of GeTe. In this case, the active ferroelectric layer of GeTe can be co-doped with Bi and Cu, co-doped with Pb and Bi, or doped with Sn, Cu, or Sb. According to this embodiment, the cathode material is, for example, chosen from one of the following materials: Pt, Pd, Au, Fe. The anode material can be chosen from one of the following materials: Ti, TiN, Ag.

[0025] The anode material is a semiconductor material such that it forms a junction with the active layer, such as a heterojunction or a homojunction. The junction may be a homojunction forming a PN-type junction.

[0026] The cathode is made from a material chosen from: transition metals or alloys of transition metals, post-transition metals or alloys of post-transition metals, materials from columns I and II of the periodic table or alloys of these materials.

[0027] The active layer is cylindrical and is wound around the cathode or around the anode.

[0028] The invention further relates to a method for reading a memory according to the invention, in which the Schottky contact is reverse-biased. The reverse-biased reading voltage applied to the main contact is advantageously strictly less than 0.1 V.

[0029] The invention also relates to a method for manufacturing a memory according to the invention, comprising: minimize a volume energy density U; U - ) Tr+ ( 1- a)^-Tw

[0030] with a resistivity P, a read / write ratio a, a write voltage Ew, a read current E, a write time Tw, and a read time Tr and a surface area $, so as to obtain an optimal resistivity $; and form a cathode, an anode and an active layer such that the active layer is disposed between the cathode and the anode and such that the active layer has a ferroelectric polarization having a plurality of stable states, and such that the cathode forms a principal contact of optimal surface area S with the active layer, the resistance of the principal contact varying in a strictly monotonic way as a function of the ferroelectric polarization, the behavior of the principal contact forming, as a function of the ferroelectric polarization: an ohmic contact for a first stable state of the plurality of stable states; and a Schottky contact for at least a second stable state of the plurality of stable states, the active layer being degenerate and having a band gap of less than 1.5 eV.

[0031] The invention also relates to a logic gate comprising a first memory according to the invention and a second memory according to the invention, the first memory and the second memory being connected in series or in parallel.

[0032] The invention finally relates to a memory matrix comprising: a plurality of memories according to the invention; a plurality of conducting lines; and a plurality of conducting columns, For each memory, the cathode is formed by one of the conductive lines and the anode is formed by one of the conductive columns.

[0033] In the matrix according to the invention, the conducting lines can be parallel to each other, the conducting columns can be parallel to each other, the conducting lines and the conducting columns being arranged to intersect, each memory being positioned at an intersection between one of the conducting lines and one of the conducting columns.

[0034] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0035] The figures are shown for illustrative purposes only and are not intended to limit the invention. Unless otherwise specified, the same element appearing in different figures has a unique reference numeral.

[0036] Figures [Fig.1] and [Fig.2] show two embodiments of a memory according to the invention.

[0037] Figure 3 shows three additional embodiments of a memory according to the invention.

[0038] Fig. 4 shows three examples of measurable current-voltage characteristics for one memory according to the invention and for two memories according to the prior art.

[0039] Figures [Fig. 5], [Fig. 6], [Fig. 7], [Fig. 8], [Fig. 9], [Fig. 10] show five embodiments of a matrix according to the invention.

[0040] Figures [Fig. 11] and [Fig. 12] show two embodiments of a logic gate according to the invention. DETAILED DESCRIPTION

[0041] The invention aims to improve the storage of information, in particular by offering high endurance and on / off ratio.

[0042] Figures 1 and 2 show two embodiments of a memory 100 according to the invention. The memory 100 comprises two conductive electrodes 120, 130 and a semiconducting ferroelectric layer 100.

[0043] The two conducting electrodes 120, 130 form respectively a main electrode 120 and a secondary electrode 130 also called respectively cathode 120 and anode 130. In the embodiments of figures 1 and 2, the cathode 120 and the anode 130 extend parallel to a plane and are superimposed with respect to each other.

[0044] The semiconducting ferroelectric layer 110 forms a so-called "active" layer. It is intended to store information. The active layer 110 exhibits a ferroelectric polarization 111. This ferroelectric polarization 111 corresponds, for example, to a volume average of the electrostatic dipole moments of the active layer 110.

[0045] The ferroelectric polarization 111 can exhibit at least two distinct stable states. Each stable state corresponds, for example, to a particular orientation of the ferroelectric polarization 111 and / or a particular amplitude of the polarization Ferroelectric 111. From a microscopic point of view, stable states correspond, for example, to particular configurations of the dipole moments forming the ferroelectric polarization 111. When the ferroelectric polarization 111 has strictly two stable states, it allows the storage of binary information. When it has strictly more than two stable states, for example, three or more states, it allows the storage of multivalued information (that is, information that can take more than two states). In an extreme case, when the ferroelectric polarization 111 has a large number of stable states, it allows the storage of analog information, that is, information that can take a value within a range of values. This could be, for example, a number between zero and one or a standardized temperature.

[0046] According to the invention, the cathode 120 forms a first contact. This first contact is called the "primary contact." The contact can be formed by direct contact between the cathode 120 and the active layer 110. This type of contact, corresponding to a particular deformation of the energy bands of the active layer 110 (or even of the cathode when the latter is semiconducting), can form an energy barrier at the interface between these two materials. The absence of a barrier at the interface (or a negligible barrier) forms a transparent (or quasi-transparent) contact, also called an "ohmic contact," or a contact with non-negligible resistance called a "Schottky contact." An ohmic contact is distinguished from a Schottky contact by the fact that the ohmic contact exhibits a linear I-V characteristic, while the Schottky contact exhibits an exponential I-V characteristic.

[0047] The resistance at the interface between the active layer 110 and the cathode 120 (which will be called the main contact resistance) depends on the presence or absence of the energy barrier at this interface and on the height and / or width of this energy barrier. In the case of the invention, the main contact resistance is particular in that it is a function of the ferroelectric polarization 111. Indeed, the energy bands in the active layer 110 and the cathode 120 are influenced by the electric field, such as that emanating from the ferroelectric polarization. Thus, different states of the polarization 111 (i.e., different orientations or amplitudes of the associated electric field) correspond to different fields applied to the main contact which: • completely eliminate the energy barrier (thus obtaining an ohmic contact); or • modulate the height and / or width of the energy barrier (thus obtaining a Schottky contact exhibiting different resistances for different polarizations).

[0048] The invention provides that the resistance of the main contact is a strictly monotonic function of the ferroelectric polarization 111. By "strictly monotonic", we This means that the resistance exhibits a derivative with respect to the ferroelectric polarization 111 that is strictly positive or strictly negative. In other words, the resistance does not have two equal values ​​for two distinct polarization states. In practice, the monotonicity of the resistance can be achieved through the out-of-plane component of the ferroelectric polarization 111. By "out-of-plane," we mean the component that is transverse to the interface formed between the active layer 110 and the cathode 120. This out-of-plane component can be non-zero. To ensure the presence of an out-of-plane component, the cathode 120 and anode 130 are arranged so as to be aligned with a principal polarization axis of the active layer 110.

[0049] Thus, a measurement of the resistance of the main contact makes it possible to determine a projection of the state (i.e., the orientation and / or the amplitude) in which the ferroelectric biasing 111 is located. In other words, a measurement of the resistance of the main contact makes it possible to read the information stored in the memory 100. In one embodiment, the ferroelectric biasing 111 can take at least two states, of which: • a first state corresponds to a measurable Schottky barrier (i.e., one exhibiting significant resistance compared to the resistance of the active layer 110); and • a second state corresponds to an erased Schottky barrier corresponding to an ohmic contact (in other words a transparent contact, i.e. whose resistance is not significant compared to the resistance of the active layer 110).

[0050] By "significant resistance" is meant a resistance at least ten times greater than the reference resistance (here, the resistance of the active layer 110). Thus, switching the bias 111 between these two states allows the contact between the cathode 120 and the active layer 110 to change its nature, going from a Schottky contact to an ohmic contact, or vice versa.

[0051] Storing information using ferroelectric polarization 111, and in particular switching from one state to another, does not require any structural change to the active layer 110. For example, it is not necessary to modify the crystalline arrangement of the active layer to switch, for instance, from crystalline to amorphous. Nor is it necessary to form a conductive filament within this active layer 110, for example, by electrostatic breakdown. Thus, the mechanisms leading to premature aging of the active layer 110 over a large number of cycles are absent. The memory 100 according to the invention therefore offers good endurance.

[0052] Two states of the ferroelectric polarization 111 correspond, for example, to two distinct resistances (due to the strict monotonicity of the resistance). The lower resistance is denoted Rq^ and the higher resistance is denoted Rqff- In a case In the extreme case where the contact is ohmic, the resistance Rqn is zero or almost zero. Memory 100 is then said to be "passing." In another extreme case, the Schottky barrier is reinforced by the influence of the ferroelectric bias 11. The resistance Rqff is then at its maximum. Memory 100 is then said to be "blocked."

[0053] The “ON / OFF report” then corresponds to

[0054] a = ^ RON

[0055] Thus, the lower the resistance Rqn, the higher the ON / OFF ratio.

[0056] The ON / OFF ratio measurement cannot be performed solely at the main contact. This measurement is carried out, for example, by measuring the total resistance between the cathode and the anode. This measurement therefore takes into account the resistance of the active layer 110. Thus, the total ON / OFF ratio becomes

[0057] „ _ ROEf+R3 H) «- R0^Rlln

[0058] where ^ho is the total resistance of the active layer 110.

[0059] In order to reduce this resistance to the minimum necessary for it to be negligible compared to other quantities, the invention provides that the active layer 110 is degenerate and has a small band gap, in this case less than 1.5 eV. In this way, the active layer 110 is conductive, although it is semiconductor. It therefore exhibits a low resistance, maximizing the total on / off ratio of the memory 100.

[0060] In one embodiment, the active layer 110 is made of GeTe alloy, which is a ferroelectric semiconductor with a band gap of 0.7 eV and is intrinsically degenerate. The low resistance of the active layer 110 allows, for example, an on / off ratio greater than 10⁴ to be achieved. The In₂Se₃ material is also a low-band gap ferroelectric semiconductor (it has a band gap of 1.35 eV). However, it is not intrinsically degenerate. Nevertheless, when it is selected to be degenerate, it is a good candidate for forming the active layer 110.

[0061] The active layer 110 can be doped or co-doped to optimize energy consumption during the reading or writing of information within it, or to improve its ferroelectric properties. "Co-doped" means doped with two different doping materials. For example, it can be doped with Sn, Cu, or Sb. It can be co-doped with Bi and Cu, or co-doped with Pb and Bi. The active layer 110 is, for example, formed from a GeTe alloy (where 0 < x < 1), for example GeTe, doped or undoped with the aforementioned elements.

[0062] The active layer 110 may have a thickness between 1 nm and 1 pm. It may have lateral dimensions, for example a width and a length or a diameter between 1 nm and 10 nm.

[0063] In certain cases, the Schottky barrier formed at the interface between the active layer 110 and the cathode 120 can disappear completely for one state of the ferroelectric polarization 111 or be strengthened for another state of the ferroelectric polarization 111. Thus, for two polarization states 111, the nature of the principal contact between the active layer 110 and the cathode 120 changes from a Schottky barrier to an ohmic contact. The output work function 0]2O of the cathode 120 is advantageously chosen so that the contact between the active layer 110 and the cathode 120 changes its nature for two polarization states 111.

[0064] The nature of the material forming the cathode 120 is of great importance because it determines whether or not a Schottky contact is formed. Indeed, the work function 0(2O) of the cathode 120 must be chosen according to the electron affinity Zj io and the band gap A110 of the active layer 110. In particular, the work function 012O must be chosen according to:

[0065]

[0066] In one embodiment, compatible with the examples described below, the cathode 120 may be metallic. It may also be formed from a degenerate or non-degenerate semiconductor. In the case where it is metallic, it is formed, for example, from transition metals, or from post-transition metals, or from materials in columns I and II of the periodic table, or from an alloy of these metals or materials. Cathode 120, for example, is produced separately from Li, Be, Mg, Ca, Sr, Ba, Ra, Ti, Zr, Hf, Rf, V, Nb, Ta, Db, Cr, Mo, W, Sg, Mn, Te, Re, Bh, Fe, Ru, Os, Hs, Co, Rh, Ir, Ni, Pd, Pt, Cu, Ag, Au, Zn, Cd, Hg, Al, Ga, In, Sn, Bi, or At. Preferably, cathode 120 is formed from Au, Pt, Pd, or Fe.

[0067] In an embodiment compatible with the embodiments described above, the anode 130 forms an ohmic contact with the active layer 110. Thus, its resistance does not vary according to the ferroelectric bias 111 of the active layer 110 and it does not influence the on / off ratio. The choice of the material forming the anode 130 ensures ohmic contact with the active layer 110. The work function 130 of the anode 130 must be chosen according to the electron affinity Zj 10 and the band gap An0 of the active layer 110. The work function 130 must be chosen such that:

[0068] ÿB0 < ZJ10

[0069] or

[0070] > Z| ]q+ A] io

[0071] The anode 130 can be formed from one of the aforementioned materials, provided that the above inequalities are respected. In other words, the anode 130 is, for example, formed from transition metals, or from post-transition metals, or from materials from columns I and II of the periodic table, or from an alloy of these metals or materials. Anode 130, for example, is made from Li, Be, Mg, Ca, Sr, Ba, Ra, Ti, Zr, Hf, Rf, V, Nb, Ta, Db, Cr, Mo, W, Sg, Mn, Te, Re, Bh, Fe, Ru, Os, Hs, Co, Rh, Ir, Ni, Pd, Pt, Cu, Ag, Au, Zn, Cd, Hg, Al, Ga, In, Sn, Bi, or At. Preferably, anode 130 is formed from Ti or Ag.

[0072] Alternatively, the anode 130 can be semiconducting. Thus, it can form a junction with the active layer 110. For example, it forms a heterojunction with the active layer 110, for instance, for an anode 130 made of Si and an active layer 110 made of GeTe. The anode 130 can also form a homojunction with the active layer, for example, when both the anode 130 and the active layer 110 are made of In₂Se₃ but the doping within these layers varies. The homojunction can then form a PN-type junction. The element exhibits diode characteristics for all bias states of the active layer 110.

[0073] In one embodiment, the anode 130 is a stack of two semiconductor sublayers, the first sublayer being undoped and the second sublayer being doped. The junction (heterojunction or homojunction, for example PN) is then formed between the doped semiconductor sublayer and the active layer 110.

[0074] In an alternative embodiment, the anode 130 forms a secondary contact with the active layer 110. This contact can be formed by direct contact of the anode 130 with the active layer 110. Similar to the main contact, the resistance of the secondary contact is preferably a strictly monotonic function of the ferroelectric bias 111. This strictly monotonic dependence can, for example, be obtained when the ferroelectric bias 111 has a transverse component (i.e., a component normal to the interface between the active layer 110 and the anode 130).

[0075] The formation of the secondary Schottky contact aims to improve the on / off ratio of the memory 100. For this, it is preferable that the primary and secondary contacts contribute positively to each other. Indeed, the measurement of the total resistance of the memory 100 includes the sum of the resistances of the primary and secondary contacts. Thus, it is expected that for a given ferroelectric bias (for example, upwards in Figures 1 and 2), the resistances of the primary and secondary contacts will be, for example, at their maximum. And for another given ferroelectric bias (for example, downwards in Figures 1 and 2), the resistances of the primary and secondary contacts will be, for example, at their minimum.

[0076] Considering a simple case where the resistance variations of the two Schottky contacts are the same, for two distinct states, the on / off ratio becomes:

[0077] 2

[0078] Thus, the resistance of the primary contact as a function of the ferroelectric polarization 111 and the resistance of the secondary contact as a function of the ferroelectric polarization 111 exhibit two monotonic tendencies, the two tendencies being opposite. In other words, if the derivative of the resistance of the primary contact as a function of the polarization is strictly positive, then the derivative of the resistance of the secondary contact as a function of the polarization is strictly negative. For example, if the resistance of the primary contact is strictly increasing as a function of the ferroelectric polarization, the resistance of the secondary contact is strictly decreasing as a function of the ferroelectric polarization.

[0079] The embodiment of [Fig. 2] differs from the embodiment of [Fig. 1] in that the memory comprises an insulating layer 140, ferroelectric or non-ferroelectric, disposed between the active layer 110 and the anode 130. The insulating layer 140 can be viewed as a tunable resistor, allowing the minimum resistance of the memory 100 to be adjusted. The addition of this resistor has little effect on the total resistance when the resistance of the main contact (or of the main and secondary contacts) is at its maximum. This insulating layer 140 also facilitates the application of a voltage to the active layer 110 (called the "write voltage") to switch the ferroelectric bias 111 from one state to another.The insulating layer 140 can also limit the diffusion of species towards or from the active layer 110, or modulate the charge trapping at the interface between the active layer 110 and the insulating layer 140, or between the insulating layer and the anode and / or cathode.

[0080] The insulating layer is for example made of HfO2, Al2O3, SiN, PZT, BFO or BTO. It has a thickness between 0.1 nm and 10 nm.

[0081] Figure 3 partially shows three embodiments of the memory 100 according to the invention. In these embodiments, the active layer 110 and the anode 130 are cylindrical. The active layer 110 is wound around the anode 130 like a sheath around a core. The cathode 120 can also be cylindrical and surround the active layer 110. Alternatively, the active layer 110 could surround the cathode 120 instead of the anode 130. Alternatively still, the cathode 120 is only in contact with a portion, annular or otherwise, of the active layer 110 (see, for example, the embodiment in Figures 9 and 10).

[0082] In two of the illustrated modes, the memory 100 comprises an insulating layer 140 as described in [Fig. 2]. The insulating layer 140 is also cylindrical and is inserted between the active layer 110 and the anode 130 or between the active layer 110 and the cathode 120.

[0083] Figure 4 shows three curves 210, 220, 230 corresponding to the on / off ratio measured as a function of an applied voltage referred to as the "reading voltage". The first The on / off curve 210, shown in solid lines, is an example of the on / off ratio measurable across the terminals of a memory 100 according to the invention. The other two curves 220 and 230, shown in dashed lines, are measurable across the terminals of memories according to the prior art. An inset shows the direction of application of the read voltage V to the memory (100). When the applied read voltage V is positive, the memory 100 is forward biased, meaning that the voltage is higher on the anode 130 than on the cathode 120. When the applied read voltage is negative, the memory 100 is reverse biased, meaning that the voltage is higher on the cathode 120 than on the anode 130.

[0084] The second on / off curve 220 corresponds to a symmetric memory. That is, a memory with two contacts, respectively between the cathode and the active layer 110 and between the anode 130 and the active layer 110, capable of switching from Schottky to ohmic and vice versa, depending on the state of the ferroelectric biasing. While the second characteristic 220 shows a high on / off ratio for a high read voltage, it is conversely minimal around 0 V. The on / off ratio is therefore low for low read voltages.

[0085] The third curve 230 corresponds to a memory in which the contact between the cathode 120 and the active layer 110 is a Schottky-type contact whose resistance varies according to the ferroelectric bias state. In this memory, the contact between the anode 130 and the active layer 110 is ohmic and does not vary according to the ferroelectric bias. The on / off ratio remains constant, regardless of the applied read voltage. However, the on / off ratio remains low, even for high read voltages.

[0086] The first feature 210 corresponds to a memory in which the contact between the cathode and the active layer is of the Schottky type in the off state and of the ohmic type in the on state. The difference in contact type between the two states induces an asymmetric variation. In particular, it exhibits a better on / off ratio when reverse biased. Moreover, the on / off ratio is not reduced around 0 V. Thus, the memory according to the invention exhibits a high on / off ratio even for low read voltages. This is all the more true when the memory is reverse biased. For example, the on / off ratio is close to 105 at -0.1 V.

[0087] Thus, a read operation of a memory 100 according to the invention can be performed by applying a voltage, called the "read voltage," to the memory so as to reverse-bias the memory 100 (i.e., with a higher voltage on the cathode than on the anode). Since the conductivity of the active layer 110 is high, and depends little, if at all, on the ferroelectric bias 111, applying the read voltage to the memory 100 is equivalent to applying said The voltage reading is on the main contact. Therefore, it is the contact that is reverse-biased.

[0088] In order to reduce the power consumption of memory 100, while offering a high on / off ratio, the read voltage of memory 100 is preferably less than 0.1 V and preferably less than 0.01 V.

[0089] The on / off curves in Figure 4 were obtained by simulating three memories as described. The parameters considered include a cathode output work function 0f2() = 0.5 eV; an active layer output work function i() = 0.4 eV; a contact area between the cathode and the active layer S = 2.5 fim2; an active layer resistance R = 100 Q; and a temperature T = 300 K.

[0090] The mechanisms for electron conduction across the Schottky barrier include, in particular, field emission, Schottky emission, and thermionic emission. In the latter case, the effective Richardson constant considered is A = 200 A cm-2 K 2,

[0091] During the fabrication of a memory 100 according to the invention, the formation of the cathode 120 on the active layer 110 can be achieved using nanofabrication techniques derived from the so-called "CMOS" (Complementary Metal Oxide Semiconductor) technology. The cathode 120 is, for example, lithographed or etched or deposited by evaporation or sputtering.

[0092] The physical or geometric properties of the memory 100 can be adapted to meet specific operational constraints. For example, a maximum resistivity of the active layer 100 (and therefore of the memory 100 in its low state) may be required. To achieve this, the manufacturing of the memory 100 may include an optimization step aimed at adapting the physical or geometric properties of the memory 100.

[0093] For example, minimize the following equation:

[0094] (L)2 4 U = Tr+{la)— Tw

[0095] with a targeted resistivity, a volume energy density U, a read / write ratio (alpha characterizes the memory usage profile), a write voltage Ew, a read current E, a write time Tw, and a read time Tr and an area -S between the cathode 120 and the active layer 110, can allow for obtaining optimal resistivity

[0096] Assuming that the influence of doping on the write voltage Ew and on the read current L- is negligible, the optimal target resistivity is:

[0097] The target resistivity / ? can also be chosen to be minimal in order to maximize the on / off ratio. Indeed, since the resistance in the high-resistance state is dominated by the Schottky contact and the low-resistance state is ohmic, minimizing the resistivity will reduce the total resistance of the low-resistance state without affecting the resistance of the high-resistance state. The on / off ratio is therefore improved.

[0098] A memory 100 according to the invention can be implemented for a storage application, or for Boolean calculations, in particular in the context of calculations in memory (called "in-memory computing" in English), or for artificial intelligence, for example as a synapse of an artificial neural network.

[0099] To this end, figures 5 to 10 show different embodiments of a memory matrix 300 according to the invention, enabling information storage and linking memories to perform logical calculations in the memories 100.

[0100] The matrix 300 includes, in particular, a plurality of memories 100 and a connection architecture allowing each memory 100 to be addressed independently. In the illustrated examples, the connection architecture is of the "crossbar" type. A crossbar architecture comprises a plurality of intersecting conductive lines 310 and a plurality of conductive columns 320. These lines and columns 310, 320 take, for example, the form of metallic tracks. Each memory 100 is connected to one of the conductive lines 310 and one of the conductive columns 320 and is preferably located at the intersection between said conductive line 310 and said conductive column 320. In this way, applying a voltage between the conductive line 310 and the conductive column 320 biases the memory 100 located at the intersection. Thus, each memory 100 can be addressed independently of the other memories.The connection of the 100 memories according to this architecture forms a matrix arrangement.

[0101] In [Fig. 5], the rows 310 are arranged parallel to each other. The columns 320 are also arranged parallel to each other. The rows 310 are arranged in a first plane and the columns 320 are arranged in a second plane, distinct from and parallel to the first plane. The rows 310 and columns 320 intersect at a right angle in projection. Each memory 100 is located at this intersection, joining the first plane to the second plane.

[0102] In a crossbar architecture, several memories 100 (at least two) are connected to the same row 310 and several other memories 100 (also at least two) are connected to the same column 320. Thus, applying an electrical voltage between a row 310 and a column 320 can induce currents flowing in the memories 100 that are not connected to the row intersection. and the column. These currents form leakage currents. Figure 5 shows, in solid lines, a current induced by the application of a potential between a row 310 and a column 320. Figure 5 shows, in dashed lines, a leakage current that can pass through several rows 310, columns 320 and memories 100.

[0103] Thanks to the primary and secondary contacts between, respectively, the cathode 120 and the active layer 110 and the anode 130 and the active layer, the connected memories 100 can function as Schottky diodes. Unlike standard Schottky diodes, the diode's resistance level varies according to its ferroelectric bias. Connecting memories 100 that function as Schottky diodes drastically reduces leakage currents. Indeed, memories 100 whose ferroelectric bias induces a Schottky contact at both of their contacts exhibit a high impedance whether they are in the high or low state. Thus, they always present a high impedance.

[0104] The matrix 300 may include monostable or bistable devices, normally off, forming selectors. Each selector is then connected in series to one of the memories 100. The selectors normally exhibit a high impedance, blocking the flow of current, except in the memory connected to the row and column to which the read (or write) voltage is applied. Even when conducting, the selectors may exhibit a significant impedance. The large impedance variation of the memories 100 according to the invention (which corresponds in particular to the on / off ratio of the memories) makes this impedance measurable, even in series with a selector exhibiting a high impedance.

[0105] The formation of a heterojunction or a homojunction (for example of type PN) between the active layer 110 and the anode 130 (described with reference to figures 1 and 2) allows the selector function to be integrated into each memory 100.

[0106] In one embodiment, the rows 310 and columns 320 of the matrix 300 form the cathodes 120 and anodes 130 of the memories 100 they connect, respectively. Indeed, the materials presented for forming the rows 310 and columns 320 are perfectly suited to forming the rows and columns of a crossbar architecture. Thus, it is not necessary to provide multiple levels for the cathodes and anodes and for the rows and columns. The matrix 300 therefore has a reduced footprint.

[0107] [Fig.6] shows an embodiment of the 300 matrix where, unlike the 300 matrix of [Fig.5], it comprises several pluralities of rows and columns intersecting on several levels so as to form stacks of 300 memories. This type of architecture is called "crossbar 3D" because it also takes advantage of a third dimension of space to stack the matrix layers and reduce the lateral footprint of the 300 matrix.

[0108] Figures 7 and 8 show two other embodiments of the matrix 300 in perspective and top views. These matrices 300 differ from [Fig. 5] in that the columns 320 extend vertically (the vertical being represented by the Z-axis) and in that the rows 310 form layers or plates arranged vertically one above the other. Openings 321, made in each row 310, allow the columns 320 to pass through the rows. To connect each memory 100 to a column 320 and a row 310, said memory 100 extends, for example, against at least a portion of the column 320 and against an edge of the opening 311 made in the row.

[0109] Advantageously, in this embodiment, the rows 310 and columns 320 also form the cathodes 120 and anodes 130 of the memories 100. Even more advantageously, and as shown in [Fig. 7], a plurality of memories 100 connected to the same column 320 share the same active layer 110. The active layer 110 extends against the column 320, over the entire height of the column 320. Each memory 100 is then located at an intersection between the column 320 and one of the rows 310. In order to avoid any interference between the memories 100, the rows 310 are spaced at a distance greater than one ferroelectric domain length of the active layer 100 and preferably greater than ten times the ferroelectric domain length of the active layer 100. By "ferroelectric domain length," we mean a characteristic dimension of a ferroelectric domain (such as its diameter).This domain length is, for example, between a few nanometers and a few tens of nanometers.

[0110] An insulating element 330 disposed in the opening 311 of each row 310 provides mechanical support, allowing contact to be maintained between the active layer 110 and the edge of each opening 311. This insulating element 330 also allows the column 320 and the row 310 to be insulated.

[0111] The embodiments of Figures 7 and 8 differ from that of [Fig. 6] in that they allow the inclusion of the possibility of a ferroelectric material with an out-of-plane ferroelectric polarization (for [Fig. 6]) and in-plane (for Figures 7 and 8). "Out-of-plane" means a polarization along a direction perpendicular to the plane of the substrate and "in-plane" means a polarization along a direction in the plane of the substrate.

[0112] Embodiments in Figures 9 and 10 show two further embodiments of the matrix 300 in perspective and top views. These embodiments correspond to a ferroelectric material with in-plane polarization. These matrices 300 combine the embodiments of Figures 7 and 8 and of [Fig. 3]. Indeed, for these matrices as well, the rows 310 and columns 320 form the cathodes 120 and anodes 130 of the memories 100. In these embodiments of In this design, the columns 310 are cylindrical. The active layer 110, common to a plurality of memories 100, is also cylindrical and surrounds the column 320. The active layer 110 is in contact with the entire opening 311 through which the column 320 and the active layer 110 pass. The row 310 is therefore in contact with an annular portion of the active layer 110.

[0113] Figures 11 and 12 show two memory assemblies allowing the realization of an OR logic gate and an AND logic gate respectively.

[0114] The OR logic gate ([Fig. 11]) corresponds to connecting two memories in series. The total impedance of this chain of 100 memories will then be high impedance if one of the 100 memories has a high impedance. The impedance will be low impedance if all the 100 memories have low impedances. By acting on the ferroelectric bias of each memory, it is then possible to perform a binary OR operation. Connecting at least three memories in series allows a logical OR operation to be performed on at least three inputs.

[0115] The AND logic gate ([Fig. 12]) corresponds to connecting two memories in parallel. The total impedance of this chain of 100 memories will then be high impedance if all the 100 memories are high impedance. The total impedance will be low impedance if at least one of the 100 memories is low impedance. Connecting at least three memories in parallel allows an AND logic operation to be performed on at least three inputs.

Claims

Demands

1. Memory (100) comprising: - a main conducting electrode (120) forming a cathode; - a secondary conducting electrode (130) forming an anode; and - a semiconducting ferroelectric layer (110) forming an active layer, disposed between the cathode and the anode (120, 130), the active layer (110) having a ferroelectric polarization (111) having a plurality of stable states, the cathode (120) forming a main contact with the active layer (110), the resistance of the main contact varying in a strictly monotonic way as a function of the ferroelectric polarization (111), the behavior of the main contact forming, as a function of the ferroelectric polarization (111): - an ohmic contact for a first stable state of the plurality of stable states;and - a Schottky contact for at least a second stable state of the plurality of stable states, the active layer (110) being degenerate and exhibiting a band gap energy less than 1.5 eV.;

2. Memory (100) according to claim 1, wherein the principal contact also forms a Schottky contact for a third stable state of the plurality of stable states, the resistance of the principal contact for the second stable state being less than the resistance of the principal contact for the third stable state.

3. Memory (100) according to any one of claims 1 or 2, wherein the main contact is formed at an interface between the active layer (110) and the cathode (120), and wherein, for each stable state, the ferroelectric polarization has, at said interface, a component normal to said interface.

4. Memory (100) according to any one of claims 1 to 3, wherein the anode (130) forms an ohmic contact with the active layer (110), the resistance of the ohmic contact being independent of the ferroelectric biasing (111).

5. Memory (100) according to any one of claims 1 to 3, wherein the anode (130) forms a secondary contact with the active layer (110), the resistance of the secondary contact varying in a strictly monotonic manner as a function of the ferroelectric polarization (111), the resistance of the primary contact as a function of the ferroelectric polarization (111) exhibiting a first tendency of monotony and the resistance of the secondary contact as a function of the ferroelectric polarization (111) exhibiting a second tendency of monotony, the two tendencies of monotony being opposite.

6. Memory (100) according to any one of the preceding claims, wherein the stack comprises an insulating layer (140) disposed between the active ferroelectric layer (110) and the cathode (120) or between the active layer (110) and the anode (130).

7. Memory (100) according to any one of the preceding claims characterized in that the active ferroelectric layer is made of GeTe.

8. Memory according to the preceding claim, wherein the active ferroelectric layer in GeTe is co-doped with Bi and Cu, co-doped with Pb and Bi or doped with Sn, Cu or Sb.

9. Memory according to any one of claims 7 to 8 wherein the cathode material (120) is selected from one of the following materials: Pt, Pd, Au, Fe.

10. Memory according to any one of claims 7 to 9 wherein the anode material (130) is selected from one of the following materials: Ti, TiN, Ag.

11. Memory according to any one of claims 1 to 9 wherein the anode material (130) is a semiconductor material so as to form a junction with the active layer (110) such as a heterojunction or a homojunction.

12. Memory according to the preceding claim in which the junction is a homojunction forming a PN type junction.

13. Memory (100) according to any one of the preceding claims, wherein the cathode (120) is made from a material selected from: transition metals or alloys of transition metals, post-transition metals or alloys of post-transition metals, materials from columns I and II of the periodic table or alloys of these materials.

14. Memory (100) according to any one of the preceding claims, wherein the active layer (110) is cylindrical and is wound around the cathode (120) or around the anode (130).

15. Reading a memory (100) according to any one of claims 1 to 14, wherein the Schottky contact is reverse polarized.

16. Method of manufacturing a memory (100) according to any one of claims 1 to 14, comprising: - minimizing a volume energy density: U = ap\f ) Tr + ( 1-a)~^TW with a resistivity P,, a read / write ratio a, a write voltage Ew, a read current E, a write time and a read time Tr and a surface $, so as to obtain an optimal resistivity 5';and - form a cathode (120), an anode (130) and an active layer (110) such that the active layer (110) is disposed between the cathode (120) and the anode (130) and such that the active layer (110) has a ferroelectric polarization (111) having a plurality of stable states, and such that the cathode (120) forms a principal contact of optimal surface area >5 with the active layer (110), the resistance of the principal contact varying in a strictly monotonic way as a function of the ferroelectric polarization (111), the behavior of the principal contact forming, as a function of the ferroelectric polarization (111): an ohmic contact for a first stable state of the plurality of stable states; and a Schottky contact for at least a second stable state of the plurality of stable states, the active layer (110) being degenerate and exhibiting a band gap energy less than 1.5 eV.;

17. Memory matrix (300) comprising: - a plurality of memories (100) according to any one of claims 1 to 14; - a plurality of conductive lines (310); and - a plurality of conductive columns (320), for each memory (100), the cathode (120) is formed by one of the conducting lines (310) and the anode (130) is formed by one of the conducting columns (320).

18. Matrix (300) according to the preceding claim, wherein the conducting lines (310) are parallel to each other, the conducting columns (320) are parallel to each other, the conducting lines and the conducting columns being arranged to cross each other, each memory (100) being disposed at an intersection between one of the conducting lines (310) and one of the conducting columns (320).

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