Semiconductor device

Abstract

To provide a semiconductor device including a resistor capable of obtaining a large resistance value adjustment amount with a low voltage in relative to the prior arts.SOLUTION: A semiconductor device comprises: at least one first resistor of which a resistance value can be changed by applying a voltage from a power source or causing a current to flow, the first resistor being connected between two terminals; a pair of switch elements to be simultaneously turned on and turned off on the basis of a predetermined switch control signal, the pair of switch elements being connected between both ends of the first resistor and the power source. Each of the first resistors is formed from polycrystal silicon containing predetermined impurity. The pair of switch elements is provided for selecting on the basis of the switch control signal the first resistor in changing the resistance value by applying a voltage from the power source or causing a current to flow.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including, for example, a polycrystalline silicon resistor (polysilicon resistor). [Background technology]

[0002] Conventionally, the trimming method for semiconductor devices has been to coat a polycrystalline silicon layer on a field oxide film that coats the surface of a semiconductor substrate, form multiple polycrystalline silicon resistors in this polycrystalline silicon layer, and then cut off the unnecessary portions with a laser beam. However, this conventional laser trimming method for polycrystalline silicon resistors requires trimming in wafer form, which can cause a shift in characteristics due to subsequent resin packaging.

[0003] In order to solve the problems with the conventional method for trimming polycrystalline silicon resistors, for example, Patent Document 1 discloses a semiconductor device according to Conventional Example 1, to which a trimming method for adjusting electrical characteristics can be applied after the device is completed. This semiconductor device is characterized by having a polycrystalline silicon layer grown on a semiconductor device on which a semiconductor element is formed, and an electrode covering the polycrystalline silicon layer so as to form a series resistor between both ends of the polycrystalline silicon, and by applying a potential difference between unit parts of the series resistor via the electrode, the resistivity between both ends of the polycrystalline silicon layer is changed.

[0004] Furthermore, Non-Patent Document 1 discloses a method according to Conventional Example 2, in which the resistance value is adjusted by applying a current pulse to a polycrystalline silicon resistor to which an impurity is added. Figure 33 is a graph showing the normalized resistance value of the polycrystalline silicon resistor with respect to the power consumption of the applied voltage disclosed in Non-Patent Document 1. Here, C T indicates the dose of impurity addition. Also, Fig. 34 is a circuit diagram of a digital-analog conversion circuit including a polycrystalline silicon resistor disclosed in Non-Patent Document 1. In the digital-analog conversion circuit of Fig. 34, a polycrystalline silicon resistor is used as a resistor for generating a reference voltage during AD conversion. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 64-61046 [Patent Document 2] Japanese Patent Application Publication No. 6-153934 [Non-patent literature]

[0006] [Non-Patent Document 1] Kotaro Kato, "Study on Electrical Trimming of Polycrystalline Silicon Resistors in Integrated Circuits," Doctoral Dissertation, Shizuoka University, November 1996, National Diet Library Summary of the Invention [Problem to be solved by the invention]

[0007] In the circuit configuration shown in Figure 34 of the present application, which is Figure 5.12 of the above-mentioned conventional example 2, the resistance adjustment element and the external terminal cannot be opened after trimming, which poses a problem that an unintended resistance change may occur due to a signal input from the external terminal after trimming is completed.

[0008] SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to provide a semiconductor device that, compared with the prior art, is free from unintended resistance changes. [Means for solving the problem]

[0009] A semiconductor device according to one aspect of the present invention includes: At least one first resistor connected between two terminals, the resistance value of which can be changed by applying a voltage from a power supply or by passing a current therethrough; The power supply includes a pair of switch elements respectively connected between both ends of each of the first resistors and the power supply, the pair of switch elements being simultaneously turned on and off based on a predetermined switch control signal. [Effects of the Invention]

[0010] Therefore, according to one aspect of the power conversion circuit device of the present disclosure, a pair of switch elements can be used to select the resistor to which current or voltage is applied depending on the intended amount of resistance adjustment, thereby providing a semiconductor device that does not cause unintended resistance changes. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a circuit diagram showing an example of the configuration of a resistor semiconductor device 10 according to a first embodiment. [Figure 2] 2 is a perspective view showing the appearance of a semiconductor wafer including chips of the resistor semiconductor device 10 of FIG. 1. FIG. [Figure 3] FIG. 3 is a perspective view showing pads in the semiconductor chip of FIG. 2. [Figure 4] 1 is a graph showing an example of a change in the rate of resistance change with respect to voltage of a polycrystalline silicon resistor. [Figure 5] 1 is a graph showing changes in sheet resistance when the impurity concentration (dose) of a polycrystalline silicon resistor is changed. [Figure 6] 10 is a circuit diagram showing a configuration example of a resistor semiconductor device 10A according to a second embodiment. FIG. [Figure 7A] 10 is a circuit diagram showing a configuration example of a resistor semiconductor device 10B according to a third embodiment. FIG. [Figure 7B] 10 is a circuit diagram showing a configuration example of a resistor semiconductor device 10C according to a fourth embodiment. FIG. [Figure 7C] FIG. 10 is a circuit diagram showing a configuration example of a resistor semiconductor device 10D according to a fifth embodiment. [Figure 8] 10 is a circuit diagram showing a configuration example of a resistor semiconductor device 100 according to a sixth embodiment. FIG. [Figure 9] 10 is a circuit diagram showing a configuration example of a resistor semiconductor device 100A according to a seventh embodiment. FIG. [Figure 10] 13 is a circuit diagram showing a configuration example of a resistor semiconductor device 100B according to an eighth embodiment. FIG. [Figure 11] 11 is a plan view showing an example of the layout of a part of the resistor semiconductor device 100B of FIG. 10. FIG. [Figure 12] 13 is a circuit diagram showing a configuration example of a resistor semiconductor device 100C according to a ninth embodiment. FIG. [Figure 13] FIG. 20 is a circuit diagram showing a configuration example of a resistor semiconductor device 100D according to a tenth embodiment. [Figure 14A] 14 is a plan view showing a partial layout example 1 of the resistor semiconductor device 100D of FIG. 13. FIG. [Figure 14B] 14 is a plan view showing a second partial layout example of the resistor semiconductor device 100D of FIG. 13. FIG. [Figure 15] FIG. 20 is a circuit diagram showing a configuration example of a resistor semiconductor device 100E according to an eleventh embodiment. [Figure 16] 4 is a timing chart of signals and a voltage VR1 showing a first control method for adjusting the resistance value of a resistor R1 in the resistor semiconductor device 10 of FIG. [Figure 17] 10 is a timing chart of signals and a voltage VR1 showing a second control method for adjusting the resistance value of a resistor R1 in the resistor semiconductor device 10 of FIG. [Figure 18] FIG. 20 is a circuit diagram showing an example of the configuration of a voltage detection circuit 120 according to a twelfth embodiment. [Figure 19] FIG. 22 is a circuit diagram showing an example of the configuration of a voltage detection circuit 120A according to a thirteenth embodiment. [Figure 20] FIG. 20 is a circuit diagram showing a configuration example of an error amplifier circuit 120B according to a fourteenth embodiment. [Figure 21] 21 is a timing chart of signals and a voltage V21 showing a control method for the voltage detection circuits 120 and 120A of FIGS. 18 and 19 and the error amplifier circuit 120B of FIG. 20. [Figure 22] 1 is a flowchart showing a semiconductor device manufacturing process including resistor generation and resistance value adjustment processes for the resistor semiconductor devices according to the first to eleventh embodiments and the voltage detection circuits according to the twelfth to fourteenth embodiments. [Figure 23] FIG. 20 is a circuit diagram showing an example of the configuration of a voltage detection circuit 120C according to a fifteenth embodiment. [Figure 24] FIG. 20 is a circuit diagram showing an example of the configuration of a voltage detection circuit 120D according to a sixteenth embodiment. [Figure 25] 25 is a flowchart showing a process for adjusting the resistance value of a resistor in a voltage detection circuit 120D of FIG. 24. [Figure 26] FIG. 20 is a circuit diagram showing an example of the configuration of a voltage detection circuit 120E according to a seventeenth embodiment. [Figure 27] 27 is a flowchart showing a process for adjusting the resistance value of a resistor in a voltage detection circuit 120E of FIG. 26. [Figure 28] FIG. 22 is a circuit diagram showing an example of the configuration of a voltage detection circuit 120F according to an eighteenth embodiment. [Figure 29] 29 is a flowchart showing a process for adjusting the resistance value of a resistor in a voltage detection circuit 120F of FIG. 28. [Figure 30] FIG. 20 is a circuit diagram showing a configuration example of a resistor semiconductor device 10E according to a nineteenth embodiment. [Figure 31] FIG. 26 is a circuit diagram showing a configuration example of a resistor semiconductor device 100F according to a twentieth embodiment. [Figure 32] FIG. 23 is a circuit diagram showing a configuration example of a resistor semiconductor device 100G according to a twenty-first embodiment. [Figure 33] 1 is a graph showing the normalized resistance value of a polycrystalline silicon resistor versus power consumption at an applied voltage disclosed in Non-Patent Document 1. [Figure 34] FIG. 1 is a circuit diagram of a digital-to-analog conversion circuit including a polycrystalline silicon resistor disclosed in Non-Patent Document 1. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments and modifications of the present invention will be described with reference to the drawings, in which the same or similar components are designated by the same reference numerals.

[0013] (Inventor's Knowledge) Patent Document 1 discloses a method for adjusting the resistance of a polycrystalline silicon resistor in a polysilicon layer of a semiconductor device by applying a predetermined voltage to the resistor. However, although an example is given in which a voltage of 10 V or more is applied for 1 microsecond, there is no detailed description of the conditions for applying the voltage. Patent Document 1 also describes an example in which an electrode is formed between three resistors and a voltage is applied to one resistor, thereby reducing the resistance to 1 / 1000 and lowering the overall resistance, and an example in which the overall resistance is increased by combining a parallel resistor and a series resistor, cutting the polysilicon, and reducing the resistance value according to the present invention.

[0014] Furthermore, Non-Patent Document 1 discloses a method for adjusting the resistance value by applying a current pulse to a polycrystalline silicon resistor doped with an impurity. In this conventional example 2, as shown in Fig. 33, a resistance value adjustment process for a polycrystalline silicon resistor is tried under various conditions of elements, pulse application time, and applied current, and a theoretical model for the resistance value adjustment process is created. An example is also described in which the offset voltage of a digital-analog conversion circuit shown in Fig. 34 is canceled using a circuit including a polycrystalline silicon resistor.

[0015] The manufacturing process of a semiconductor device having a circuit including the polycrystalline silicon resistor is carried out in the following manner. (1) Wafer manufacturing process (2) First test process (3) Packaging process (4) Second test process

[0016] The first test process after the wafer manufacturing process, which is the initial process, is completed will be described below with reference to FIGS.

[0017] Fig. 2 is a perspective view showing the appearance of a semiconductor wafer including the semiconductor chip of the resistor semiconductor device 10 of Fig. 1. Fig. 3 is a perspective view showing a pad in the semiconductor chip of Fig. 2.

[0018] After the wafer manufacturing process known as the pre-processing, the semiconductor wafer 1 takes the form shown in FIG. 2. Next, the semiconductor wafer 1 is diced into semiconductor chips 2, which, as shown in FIG. 3, have a plurality of pads 3 for electrical connection during packaging. In the first test process, the undiced semiconductor wafer 1 shown in FIG. 2 is placed on a tester device, and test needles are connected to predetermined pads 3. Typically, in this first test process, a power supply voltage is supplied from the power supply pads 3 to evaluate the product's functionality, and the voltage of the signal pads 3 is measured with the tester device to test whether the product specifications are met. Next, after the semiconductor chips 2 are diced, they are packaged and completed as products. The completed products undergo electrical characteristic tests in the second test process.

[0019] However, various factors can cause variations in the electrical characteristics of products, hindering the ability to meet the electrical characteristic specifications. One of these is variations introduced during the wafer manufacturing process, a front-end process. Analog product electronic circuits use MOS transistors as active nonlinear elements and resistors and capacitors as passive elements. To achieve high product precision, not only transistor variations but also resistor variations in particular are crucial factors. One method for reducing these variations is to adjust the electrical characteristics using a laser after the first test process. Resistors with equivalent electrical characteristics and laser-removable fuses are pre-assembled into a ladder-like structure in the circuit. The fuses are then cut with a laser based on the results of the first test process, adjusting the electrical characteristics (see, for example, Patent Document 2). This improves the electrical characteristics of the semiconductor wafer 1.

[0020] On the other hand, after the semiconductor chip 2 is packaged, various factors can cause fluctuations in characteristics. Possible factors that can cause fluctuations in characteristics include the packaging itself, heating due to solder reflow during board mounting, X-ray exposure, and deterioration over time. After packaging, the above-mentioned laser-based fuse cutting method cannot be used. For this reason, a practical method has been developed in which memory is installed inside the product, and the parts that should be shorted out by resistors are tested and then the write resistance value is adjusted.

[0021] However, this method has the drawback of increasing the chip area of ​​the product. Therefore, an object of the embodiment of the present invention is to provide a means for improving product characteristics by adjusting the resistance value of the resistor in a packaged state without significantly increasing costs.

[0022] The electronic circuits of analog products use MOS transistors as active nonlinear elements, and resistors and capacitors as passive elements. In order to achieve high precision in products, not only the variation of transistors but also the variation of resistors in particular is a very important factor.

[0023] Below we will explain how to create resistors from silicon wafer semiconductor substrates (single crystal), or polycrystalline silicon or polysilicon (high-purity polycrystalline silicon). There are several ways to create resistors with the desired resistance value in semiconductor elements on silicon semiconductor substrates. One method is to add impurities to the silicon semiconductor to increase the carriers compared to intrinsic semiconductor silicon and adjust the resistance value. There are N-type resistors that are doped with phosphorus (P), arsenic (As), or antimony (Sb) as impurities, and P-type resistors that are doped with boron (B) or indium (In) as impurities.

[0024] Most of the polysilicon used in product electronic circuits is made by adding impurities to polysilicon, but polysilicon has a much larger variation in the finished resistance value than single crystal. Therefore, as mentioned in the prior art section, a method has been put into practical use to correct the resistance value of the entire resistor using laser trimming. However, as mentioned as a problem, this method does not allow for correction of the resistance value after packaging.

[0025] Therefore, a technique has been known in the past that can change the resistance value by directly passing a current through polysilicon (see, for example, Patent Document 1). Patent Document 1 reports a technique for adjusting the resistance value by combining a technique for reducing the resistance to 1 / 1000 by applying a voltage to polysilicon with a technique for cutting the polysilicon. However, the invention disclosed in Patent Document 1 does not describe the principle behind the reduction in the resistance value of polysilicon. The principle behind the reduction in the resistance value of polysilicon is described in detail in Non-Patent Document 1. The contents of Non-Patent Document 1 will be explained below.

[0026] Not all of the impurities that make up the polysilicon resistor mentioned above are activated, and some segregation occurs. When current is passed through a polysilicon resistor, the current flows concentratedly at the interfaces between the various sizes of crystal grains that make up the polysilicon, causing local melting due to Joule heat. When the current is stopped and the polysilicon solidifies, the segregated impurities are activated, resulting in a resistor with a localized high concentration of impurities. As the impurity concentration of the polysilicon resistor increases, the electrical conductivity of the polysilicon resistor also increases, resulting in a decrease in the resistance value of the resistor as a whole.

[0027] In the embodiment of the present invention, an embodiment will be described in which both N-type impurities and P-type impurities are added to obtain a resistance value higher than the initial resistance value. When a voltage pulse is applied to the resistor element, the resistance value can not only be decreased but also increased.

[0028] Figure 4 is a graph showing an example of the change in resistance change rate with voltage for a polycrystalline silicon resistor. As is clear from Figure 4, the increase in the resistance value of this polycrystalline silicon resistor is largely influenced by the difference in activation rate of the elements implanted as N-type or P-type impurities. Both boron and phosphorus are inactive at the time of implantation. When voltage is applied, boron, which activates at a lower temperature than phosphorus, is activated first, and the resistance value of the polycrystalline silicon resistor decreases. Then, as voltage is applied again and the temperature increases, phosphorus is activated, and the resistance value increases. If voltage is continued to be applied, the carrier concentration of phosphorus and the carrier concentration of boron approach the same amount, resulting in extremely high resistance and thermal breakdown.

[0029] Figure 5 is a graph showing the change in sheet resistance when the impurity concentration (dose) of a polycrystalline silicon resistor is changed. That is, Figure 5 shows the change in sheet resistance when the carrier concentration is changed by changing the amount of boron implanted while keeping the amount of phosphorus implanted constant. As is clear from Figure 5, increasing the implantation amount increases the resistance as an N-type resistor up to a certain value, but once that value is exceeded, the resistance decreases as a P-type resistor. This represents the phenomenon in which the resistance of polycrystalline silicon changes from a decrease to an increase due to a change in the carrier concentration ratio, similar to the embodiment of the present invention.

[0030] That is, as mentioned above, in the circuit configuration shown in Figure 34 of the present application, which is Figure 5.12 of the above-mentioned conventional example 2, when an attempt is made to increase the resistance value and obtain a larger resistance value adjustment amount, the voltage becomes high and the incorporated semiconductor device is destroyed, which is a problem.

[0031] In order to solve the above problems, the embodiments according to the present invention will be explained below by dividing them into three groups of embodiments.

[0032] (First embodiment group) The purpose of this first embodiment group is to solve the above problems and to provide a semiconductor device or the like including a resistor that can obtain a large amount of resistance adjustment at a lower voltage than in the prior art.

[0033] The following describes a specific circuit and its layout relating to the resistance value adjusting means using the polycrystalline silicon resistor described above. Here, various combinations of switch elements are possible for the switch elements constituting this embodiment.

[0034] (Embodiment 1) FIG. 1 is a circuit diagram showing a configuration example of a resistor semiconductor device (hereinafter referred to as a semiconductor device) 10 according to a first embodiment. In FIG. 1, the semiconductor device 10 has three pads P10, P21, and P22, each of which serves as a terminal, and two nodes P1 and P2, which are connection points with an internal circuit (an electronic circuit formed on the same silicon as the resistor R1 and including the resistor R1). The semiconductor device 10 is also configured with a polycrystalline silicon resistor (resistor) R1, the resistance of which can be adjusted by a predetermined voltage or current, as disclosed in Patent Document 1 or Non-Patent Document 1, a P-channel MOS field-effect transistor Q1, an N-channel MOS field-effect transistor Q2, and an inverter INV1. Hereinafter, a MOS field-effect transistor will be referred to as a MOS transistor, a P-channel MOS transistor as a PMOS transistor, and an N-channel transistor as an NMOS transistor. PMOS transistors and NMOS transistors will be collectively referred to as MOS transistors. Furthermore, while a pad is generally a connection point to the outside of a semiconductor chip, the pads P10, P21, P22, etc. in this embodiment may function as nodes for other signals within the semiconductor chip, and may input equivalent signals.

[0035] 1, nodes P1 and P2 are terminals at both ends of resistor R1 for use as a resistive element, and are provided for drawing the resistor R1 out of the chip of semiconductor device 10. Pad P21 is connected to power supply voltage VDD, and pad P22 is grounded to ground voltage VSS. Pad P10 receives a switch control signal Sc for turning MOS transistors Q1 and Q2 on or off from an external circuit. Pads P21 and P22 are not limited to terminals connected to power supply voltage VDD and ground voltage VSS, and may be other signals as long as they can input the required signals.

[0036] A resistor R1 is connected between nodes P1 and P2, the source and drain of a MOS transistor Q1 are connected between pad P21 and node P1, and the source and drain of a MOS transistor Q2 are connected between pads P22 and P2. A switch control signal Sc input to pad P10 from an IC tester device or an external voltage generator is input to the gate of the MOS transistor Q2 and also input to the gate of the MOS transistor Q1 via an inverter INV1.

[0037] In the semiconductor device 10 configured as described above, in a normal mode in which the resistor R1 is used, a switch control signal Sc of L level is input, and at this time, the pair of switch elements, MOS transistors Q1 and Q2, are simultaneously turned off, and the resistor R1 connected between nodes P1 and P2 is used. On the other hand, in a resistance value adjustment mode in which the resistance value of the resistor R1 is adjusted, a switch control signal Sc of H level is input, and at this time, the pair of switch elements, MOS transistors Q1 and Q2, are simultaneously turned on, and a predetermined power supply voltage VDD or the like is applied from a power supply device such as an IC tester device or an external voltage generator to both ends of the resistor R1 connected between nodes P1 and P2, and the resistance value of the resistor R1 is adjusted to a predetermined resistance value.

[0038] According to the first embodiment described above, in the resistance adjustment mode, the MOS transistors Q1 and Q2 are turned off, thereby selecting only the resistor R1, and a predetermined power supply voltage VDD or the like is applied only to the resistor R1, thereby adjusting the resistance of the resistor R1 to a predetermined resistance value. On the other hand, in the normal mode, the MOS transistors Q1 and Q2 are turned off, thereby disconnecting the resistor R1 from the power supply voltage VDD or the like and providing the resistor R1 for use. In other words, by providing the MOS transistors Q1 and Q2, the resistor R1 can be disconnected from the external terminal, thereby preventing unintended changes in the resistance value.

[0039] (Embodiment 2) Fig. 6 is a circuit diagram showing a configuration example of a semiconductor device 10A according to embodiment 2. In Fig. 6, the semiconductor device 10A differs from the semiconductor device 10 of Fig. 1 in the following points. (1) The nodes P1 and P2 connected to both ends of the resistor R1 are deleted. (2) Voltages V1 and V2 are applied to the pads P21 and P22, respectively. Here, for example, the voltage V1 is a power supply voltage VDD, and the voltage V2 is a ground voltage VSS that is lower than the voltage V1.

[0040] The semiconductor device 10A configured as above operates in the same manner as the semiconductor device 10 of FIG. 1, and has the same effects.

[0041] As modifications of the second embodiment, configuration examples of the third to fifth embodiments are shown.

[0042] (Embodiment 3) Fig. 7A is a circuit diagram showing a configuration example of a semiconductor device 10B according to embodiment 3. In Fig. 7A, the semiconductor device 10B differs from the semiconductor device 10A in Fig. 6 in the following points. (1) An inverter INV2 is provided instead of the inverter INV1. That is, the insertion position of the inverter INV1 is short-circuited, and the inverter INV2 is connected between the pad P10 and the gate of the MOS transistor Q2. (2) A predetermined voltage such as a power supply voltage VDD is applied to the pad P21, and a predetermined voltage such as a ground voltage VSS that is lower than the predetermined voltage applied to the pad P21 is applied to the pad P22.

[0043] In the semiconductor device 10B configured as described above, in a normal mode in which the resistor R1 is used, an H-level switch control signal Sc is input, at which time the MOS transistors Q1 and Q2 are turned off and the resistor R1 connected between the nodes P1 and P2 is used. On the other hand, in a resistance value adjustment mode in which the resistance value of the resistor R1 is adjusted, an L-level switch control signal Sc is input, at which time the MOS transistors Q1 and Q2 are turned on and a predetermined power supply voltage VDD or the like is applied across the resistor R1 connected between the nodes P1 and P2, thereby adjusting the resistance value of the resistor R1 to a predetermined resistance value.

[0044] The semiconductor device 10B configured as above operates in the same manner as the semiconductor device 10A of FIG. 6, and has the same effects.

[0045] (Embodiment 4) 7B is a circuit diagram showing a configuration example of a semiconductor device 10C according to embodiment 4. In FIG. 7B, the semiconductor device 10C differs from the semiconductor device 10A in FIG. 6 in the following respects. (1) An NMOS transistor Q1A is provided in place of the PMOS transistor Q1. (2) Inverter INV1 has been deleted. (3) A predetermined voltage, such as a voltage close to the ground voltage VSS, is applied to the pads P21 and P22, and the voltage of the pad P21 is set higher or lower than the voltage of the pad P22.

[0046] The semiconductor device 10C configured as above operates in the same manner as the semiconductor device 10 of FIG. 1, and has the same effects.

[0047] (Embodiment 5) Fig. 7C is a circuit diagram showing a configuration example of a semiconductor device 10D according to embodiment 5. In Fig. 7C, the semiconductor device 10D differs from the semiconductor device 10B in Fig. 7A in the following respects. (1) A PMOS transistor Q2A is provided in place of the NMOS transistor Q2. (2) Inverter INV2 has been deleted. (3) A predetermined voltage, such as a voltage close to the power supply voltage VDD, is applied to the pads P21 and P22, and the voltage of the pad P21 is set higher or lower than the voltage of the pad P22.

[0048] The semiconductor device 10D configured as above operates in the same manner as the semiconductor device 10B of FIG. 7A, and has the same effects.

[0049] (Embodiment 6) 8 is a circuit diagram showing a configuration example of a semiconductor device 100 according to a sixth embodiment. The semiconductor device 100 of FIG. 8 is characterized in that it includes three semiconductor devices 10 of FIG. 1 (here, the three semiconductor devices 10 are collectively designated by the reference numerals 10-1, 10-2, and 10-3), which are connected in series, and the series circuit is connected between nodes P1 and P2. In addition, (1) the switch control signal for the semiconductor device 10-1 is designated as Sc1 and is input from a pad P11, (2) the switch control signal for the semiconductor device 10-2 is designated as Sc2 and is input from a pad P12, and (3) the switch control signal for the semiconductor device 10-3 is designated as Sc3 and is input from a pad P13.

[0050] In the semiconductor device 100 configured as described above, in a normal mode using a series circuit (one resistor) in which three resistors R1 are connected in series, an L-level switch control signal Sc is input, and at this time, the MOS transistors Q1 and Q2 of each semiconductor device 10-1, 10-2, and 10-3 are turned off, and the series circuit in which three resistors R1 are connected in series between nodes P1 and P2 is used.

[0051] on the other hand, (1) In the semiconductor device 10-1, in a resistance value adjustment mode for adjusting the resistance value of the resistor R1, an H-level switch control signal Sc is input. At this time, the MOS transistors Q1 and Q2 are turned on, and a predetermined power supply voltage VDD or the like is applied from an IC tester device or an external voltage generator to both ends of the resistor R1 connected between the nodes P1 and P2, thereby adjusting the resistance value of the resistor R1 to a predetermined resistance value. (2) In the semiconductor device 10-2, in a resistance value adjustment mode for adjusting the resistance value of the resistor R1, an H-level switch control signal Sc is input. At this time, the MOS transistors Q1 and Q2 are turned on, and a predetermined power supply voltage VDD or the like is applied from an IC tester device or an external voltage generator to both ends of the resistor R1 connected between the nodes P1 and P2, thereby adjusting the resistance value of the resistor R1 to a predetermined resistance value. (3) In the semiconductor device 10-3, in a resistance value adjustment mode for adjusting the resistance value of the resistor R1, an H-level switch control signal Sc is input. At this time, the MOS transistors Q1 and Q2 are turned on, and a predetermined power supply voltage VDD or the like is applied from an IC tester device or an external voltage generator to both ends of the resistor R1 connected between the nodes P1 and P2, thereby adjusting the resistance value of the resistor R1 to a predetermined resistance value.

[0052] As described above, according to the semiconductor device 100 configured with three semiconductor devices 10-1, 10-2, and 10-3 of embodiment 1, one resistor is configured with a series circuit of three resistors R1, so that the resistance adjustment amount can be accumulated, and when attempting to obtain an equivalent resistance adjustment amount, this can be achieved by applying a lower voltage to each resistor R1 (because the current to each resistor R1 can be reduced) compared to the prior art.

[0053] In the sixth embodiment, the normal mode is described in which a series circuit (one resistor) in which three resistors R1 are connected in series is used. However, the present invention is not limited to this. When using each resistor R1 for each semiconductor device 10-1, 10-2, 10-3 separately, this is possible by connecting pads to the connection points of adjacent resistors R1.

[0054] (Embodiment 7) Fig. 9 is a circuit diagram showing a configuration example of a semiconductor device 100A according to embodiment 7. In Fig. 9, the semiconductor device 100A according to embodiment 7 differs from the semiconductor device 100 in Fig. 8 in the following points. (1) Between the resistor R1 of the semiconductor device 10-1 and the resistor R1 of the semiconductor device 10-2, a linking resistor R2 having a resistance value sufficiently larger than that of the resistor R1 is inserted. (2) Between the resistor R1 of the semiconductor device 10-2 and the resistor R1 of the semiconductor device 10-3, a linking resistor R2 having a resistance value sufficiently larger than that of the resistor R1 is inserted. The differences will be explained below.

[0055] The semiconductor device 100A of FIG. 9 has a resistance R2 between the three semiconductor devices 10 in a minimum configuration that is sufficiently larger than the resistance of the resistor R1 (e.g., sufficiently larger than 100 times the resistance of the resistor R1). Therefore, even if the MOS transistors Q1 and Q2 of the semiconductor devices 10-1, 10-2, and 10-3 are simultaneously set to the H level, almost no current flows between the semiconductor devices 10, and a current sufficient to adjust the resistance of the resistor R1 of each semiconductor device 10 can flow. This shortens the processing time for resistance adjustment. Setting all of the switch control signals Sc1, SC2, and Sc3 to the L level turns off the MOS transistors Q1 and Q2 of the semiconductor devices 10-1, 10-2, and 10-3, thereby achieving a resistance adjustment amount for each resistor R1 between nodes P1 and P2 equivalent to that when each resistor R1 is alone. Here, because three resistors R1 are connected in series, this resistance adjustment amount can be increased.

[0056] According to the semiconductor device 100A configured as described above, three resistors 10 according to the first embodiment are arranged, and one resistor is configured by a series circuit of three resistors R1 and two connecting resistors R2, so that a semiconductor device including resistors can be provided that can obtain an equivalent resistance adjustment amount with a lower voltage than in the prior art (the equivalent resistance adjustment amount is obtained for each resistor R1 by isolating each resistor R1 with a resistor R2) in a single process. This means that, as described above, if it is possible to apply a voltage equivalent to that in the prior art to each resistor R1, it is possible to obtain a larger resistance adjustment amount for the entire resistor circuit.

[0057] In the seventh embodiment, a normal mode is described in which a series circuit (one resistor) is used in which three resistors R1 and two connecting resistors R2 are connected in series. However, the present invention is not limited to this, and when each resistor R1 of each semiconductor device 10-1, 10-2, 10-3 is used separately, this is possible by connecting pads to the connection points of adjacent resistors R1.

[0058] (Embodiment 8) Fig. 10 is a circuit diagram showing a configuration example of a semiconductor device 100B according to embodiment 8. In Fig. 10, the semiconductor device 100B of embodiment 8 differs from the semiconductor device 100A of Fig. 9 in the following points. (1) The semiconductor device 100B in FIG. 9 is defined as a semiconductor device group G1. (2) The semiconductor device groups G2 and G3 and a series circuit of two linking resistors R2 are connected to the rear stage of the semiconductor device group G1 via a linking resistor R2. Here, the semiconductor device group G2 is configured to include two semiconductor devices 10-4 and 10-5 and a series circuit of linking resistor R2, and the semiconductor device group G3 is configured to include one semiconductor device 10-6 and a series circuit of linking resistor R2. Note that linking resistors R2 are inserted between adjacent semiconductor devices 10-1 and 10-2, between adjacent semiconductor devices 10-2 and 10-3, between adjacent semiconductor devices 10-3 and 10-4, between adjacent semiconductor devices 10-4 and 10-5, and between adjacent semiconductor devices 10-5 and 10-6. (3) The input terminal of the inverter INV1 and the gate of the MOS transistor Q2 of each of the semiconductor devices 10-1, 10-2, and 10-3 in the semiconductor device group G1 are connected to a pad P11 to which a switch control signal Sc1 is input. (4) The input terminal of the inverter INV1 and the gate of the MOS transistor Q2 of each of the semiconductor devices 10-4 and 10-5 in the semiconductor device group G2 are connected to the pad P12 to which the switch control signal Sc2 is input. (5) The input terminal of the inverter INV1 and the gate of the MOS transistor Q2 of the semiconductor device 10-6 in the semiconductor device group G3 are connected to a pad P13 to which a switch control signal Sc3 is input. (6) That is, a series circuit of six resistors R1 and five connecting resistors R2 is inserted between nodes P1 and P2. The differences will be explained below.

[0059] 10 has a configuration including six semiconductor devices 10, with a linking resistor R2 inserted between each of the adjacent semiconductor devices 10. Here, the resistance value of each linking resistor R2 is sufficiently larger than the resistance value of each resistor R1, and a large current does not flow between nodes P1 and P2 compared to a semiconductor device having a series circuit of only six resistors R1.

[0060] Furthermore, instead of selecting a single resistor R1 for each semiconductor device 10 as in the seventh embodiment shown in FIG. 9, the resistor R1 is selected by using switch control signals Sc1, Sc2, and Sc3. (1) Select a resistor R1 of a semiconductor device group G1 having three resistors R1; (2) Selecting a resistor R1 of a semiconductor device group G2 having two resistors R1; (3) The resistor R1 of the semiconductor device group G3 having one resistor R1 can be selected. By making it possible to select multiple resistors R1 with a single switch control signal, it is possible to increase the number of selectable resistors R1 without increasing the number of pads for the control signal.

[0061] Furthermore, a sufficiently large resistance R2 exists between the minimum configurations of the six semiconductor devices 10. Therefore, even if the MOS transistors Q1 and Q2 of each of the semiconductor devices 10-1 to 10-6 are simultaneously set to the H level, almost no current flows between the semiconductor devices 10-1 to 10-6, and a current sufficient to adjust the resistance can flow through the resistor R1 of each of the semiconductor devices 10-1 to 10-6. This shortens the processing time. Furthermore, by setting all of the switch control signals Sc1, SC2, and Sc3 to the L level, the MOS transistors Q1 and Q2 of each of the semiconductor devices 10-1 to 10-6 are turned off, and the resistance adjustment amount for each resistor R1 between the nodes P1 and P2 can be obtained equivalent to that when each resistor R1 is alone. Here, since six resistors R1 are connected in series, the resistance adjustment amount can be significantly increased.

[0062] The semiconductor device 100B configured as described above can provide a semiconductor device including resistors that can achieve the same resistance adjustment amount with a single process at a lower voltage compared to conventional techniques. This means that if the same voltage as conventional techniques can be applied to the resistor R1, a series circuit of multiple resistors R1 can achieve a greater resistance adjustment amount for the entire resistor circuit. Furthermore, because the semiconductor devices 10 are grouped, the number of switch control signals and their associated pads can be reduced.

[0063] In embodiment 8, a normal mode is described in which a series circuit (one resistor) is used in which six resistors R1 and five connecting resistors R2 are connected in series. However, the present invention is not limited to this, and when each resistor R1 for each semiconductor device 10-1 to 10-6 is used separately, this can be achieved by connecting pads to the connection points of adjacent resistors R1.

[0064] Although the semiconductor device 100B according to the eighth embodiment includes the linking resistor R2, the present invention is not limited to this, and the linking resistor R2 may be omitted.

[0065] Fig. 11 is a plan view showing a layout example of a part of the semiconductor device 100B of Fig. 10. Fig. 11 shows a layout example of a part relating to the semiconductor devices 10-1 and 10-2 of the semiconductor device 100B of Fig. 10 and the linking resistor R2 inserted therebetween.

[0066] By changing the impurity concentration in the polysilicon portion, it is possible to form high resistance polysilicon that has a high resistance and serves as a resistor, and low resistance polysilicon that has a lower resistance than the former high resistance resistor and serves as wiring. Here, the former high resistance polysilicon is, for example, (1) The impurity concentration of phosphorus is 1.0 × 10 15 ~2.0×10 15 ions / cm 2 or (2) The boron impurity concentration is 5.0 × 10 14 ~2.0×10 15 ions / cm 2 The latter low resistance polysilicon can be formed with a dose of impurity concentration of, for example, 1.0× 20 ions / cm 2 The resistors R1 and the connecting resistor R2 are formed of high-resistance polysilicon 80, and the wiring conductors 60 to 64 are formed of low-resistance polysilicon 70 to 74. Reference numerals 50 to 54 denote via conductors filled in vias that penetrate the semiconductor substrate in the thickness direction.

[0067] 11, node P1 is connected to one end of resistor R1 via wiring conductor 60, via conductor 50, and low-resistance polysilicon 70. Pad P21 is connected to the source of MOS transistor Q1 of semiconductor device 10-1 via wiring conductor 61, via conductor 51, and low-resistance polysilicon 71, and is also connected to the source of MOS transistor Q1 of semiconductor device 10-2 via wiring conductor 62, via conductor 52, and low-resistance polysilicon 72. Pad P22 is connected to the source of MOS transistor Q2 of semiconductor device 10-2 via wiring conductor 63, via conductor 53, and low-resistance polysilicon 73, and is also connected to the source of MOS transistor Q2 of semiconductor device 10-2 via wiring conductor 64, via conductor 54, and low-resistance polysilicon 74.

[0068] (Embodiment 9) Fig. 12 is a circuit diagram showing a configuration example of a semiconductor device 100C according to embodiment 9. In Fig. 12, the semiconductor device 100C of embodiment 9 differs from the semiconductor device 100A of Fig. 9 in the following points. (1) The semiconductor devices 10-1 and 10-2 and the resistor R1B, which is a resistance-adjusting element inserted between the resistors R1 of the semiconductor devices 10-1 and 10-2, are grouped into a semiconductor device group G11. (2) A series circuit of semiconductor device groups G12 and G13 is connected to the rear stage of the semiconductor device group G11 via a resistor R1C, which is a resistance value adjusting element. (3) Semiconductor device group G12 includes one semiconductor device 10-3, a resistor R1C serving as a resistance adjustment element, and an NMOS transistor Q2A, the drain of which is connected to the connection point between resistors R1 and R1C of semiconductor device 10-2, and the source of which is connected to pad P22. (4) The semiconductor device group G13 is configured to include one semiconductor device 10-4. (5) Note that linking resistors R1B and R1C are inserted between the semiconductor devices 10-1 and 10-2 adjacent to each other, and between the semiconductor devices 10-2 and 10-3 adjacent to each other, respectively. (6) The input terminal of the inverter INV1 and the gate of the MOS transistor Q2 of each of the semiconductor devices 10-1 and 10-2 in the semiconductor device group G11 are connected to a pad P11 to which a switch control signal Sc1 is input. (7) The input terminal of the inverter INV1 and the gate of the MOS transistor Q2A of each semiconductor device 10-3 in the semiconductor device group G12 are connected to a pad P12 to which a switch control signal Sc2 is input. (8) The input terminal of the inverter INV1 and the gate of the MOS transistor Q2 of the semiconductor device 10-4 in the semiconductor device group G13 are connected to a pad P13 to which a switch control signal Sc3 is input. (9) That is, a series circuit of six resistors R1, R1B, R1, R1C, R1, and R1 is inserted between nodes P1 and P2. The differences will be explained below.

[0069] The semiconductor device 100C of FIG. 12 has a configuration including four semiconductor devices 10, and has a configuration in which coupling resistors R1B and R1C are inserted between adjacent semiconductor devices 10 (limited to between 10-1 and 10-2, and between 10-2 and 10-3).

[0070] Also, using switch control signals Sc1, Sc2, and Sc3, (1) Selecting resistors R1, R1B, and R1 of a semiconductor device group G11 having three resistors R1, R1B, and R1; (2) Selecting resistors R1C and R1 of a semiconductor device group G12 having two resistors R1C and R1; (3) The resistor R1 of the semiconductor device group G13 having one resistor R1 can be selected. (A) Group G11 has four MOS transistors and three resistance adjustment elements can be selected. (B) Group G12 has three MOS transistors and two resistance adjustment elements can be selected. A similar amount of resistance adjustment can be obtained with a smaller number of MOS transistors compared to the semiconductor device 100B.

[0071] The semiconductor device 100C configured as described above provides a semiconductor device including resistors that can achieve the same resistance adjustment amount with a single process at a lower voltage compared to the prior art. This means that if the same voltage as the prior art can be applied to each resistor R1, a larger resistance adjustment amount can be achieved for the entire resistor circuit. Furthermore, because the semiconductor devices 10 are grouped, the number of switch control signals and their associated pads can be reduced. Furthermore, the chip area of ​​the semiconductor device 100C can be reduced compared to the semiconductor devices 100A and 100B.

[0072] In the ninth embodiment, the normal mode is described as using a series circuit (one resistor) in which six resistors are connected in series, but the present invention is not limited to this. When using each resistor separately for each of the semiconductor devices 10-1 to 10-6, this is possible by connecting a pad to the connection point of adjacent resistors R1.

[0073] (Embodiment 10) Fig. 13 is a circuit diagram showing a configuration example of a semiconductor device 100D according to embodiment 10. In Fig. 13, the semiconductor device 100D of embodiment 10 differs from the semiconductor device 100A of Fig. 9 in the following points. (1) The semiconductor devices 10-1, 10-2, and 10-3 and the two resistors R1 made of polycrystalline silicon are grouped into a semiconductor device group G21. (2) A series circuit of semiconductor device groups G22 and G23 is connected to the rear stage of semiconductor device group G21 via resistor R1. Here, semiconductor device group G22 is configured to include two semiconductor devices 10-4 and 10-5 and resistor R1, and semiconductor device group G23 is configured to include one semiconductor device 10-6. Resistor R1 is inserted between adjacent semiconductor devices 10-1 and 10-2, between adjacent semiconductor devices 10-2 and 10-3, between adjacent semiconductor devices 10-3 and 10-4, between adjacent semiconductor devices 10-4 and 10-5, and between adjacent semiconductor devices 10-5 and 10-6. (3) The input terminal of the inverter INV1 and the gate of the MOS transistor Q2 of each of the semiconductor devices 10-1, 10-2, and 10-3 in the semiconductor device group G21 are connected to a pad P11 to which a switch control signal Sc1 is input. (4) The input terminal of the inverter INV1 and the gate of the MOS transistor Q2 of each of the semiconductor devices 10-4 and 10-5 in the semiconductor device group G22 are connected to a pad P12 to which a switch control signal Sc2 is input. (5) The input terminal of the inverter INV1 and the gate of the MOS transistor Q2 of the semiconductor device 10-6 in the semiconductor device group G23 are connected to the pad P13 to which the switch control signal Sc3 is input. (6) That is, a series circuit of eleven resistors R1 is inserted between nodes P1 and P2. The differences will be explained below.

[0074] 13 has a configuration including six semiconductor devices 10, with a resistor R1 inserted between each of the adjacent semiconductor devices 10. In this embodiment, a series circuit of 11 resistors R1 is inserted between nodes P1 and P2.

[0075] Also, using switch control signals Sc1, Sc2, and Sc3, (1) Selecting a resistor R1 of a semiconductor device group G21 having five resistors R1; (2) Selecting a resistor R1 of a semiconductor device group G22 having three resistors R1; (3) The resistor R1 of the semiconductor device group G23 having one resistor R1 can be selected. (4) By simultaneously setting the switch control signals Sc1 and Sc2 to H level, nine resistors R1 including the resistors R1 between groups G21 and G22 are selected. (5) By simultaneously setting the switch control signals Sc2 and Sc3 to H level, five resistors R1 including the resistors R1 between groups G22 and G23 can be selected.

[0076] That is, the semiconductor device 100D can incorporate more resistance-adjusting elements than the semiconductor device 100B, and can obtain a larger resistance adjustment amount with the same number of MOS transistors.

[0077] The semiconductor device 100D configured as described above can provide a semiconductor device including resistors that can achieve the same resistance adjustment amount with a lower voltage than conventional resistors R1. This means that if the same voltage as conventional resistors R1 can be applied to each resistor R1, a greater resistance adjustment amount can be achieved for the entire resistor circuit. Furthermore, because the semiconductor devices 10 are grouped, the number of switch control signals and their associated pads can be reduced.

[0078] In the semiconductor device 100D of FIG. 13, by aggregating the switch control signals for the resistors R1 and sharing the pads, the number of pads can be reduced, and the chip area can be significantly reduced.

[0079] In the semiconductor device 100D of Figure 13, the resistance adjustment amount (relative value when the application of H-level switch control signal Sc3 is set to 1) for each resistor R1 according to various application procedures of switch control signals Sc1 to Sc3 is shown in Table 1 below.

[0080] [Table 1]

[0081] In the tenth embodiment, the normal mode is described in which a series circuit (one resistor) in which eleven resistors R1 are connected in series is used, but the present invention is not limited to this. When using each resistor R1 for each semiconductor device 10-1 to 10-3 or 10-4, 10-5 separately, this is possible by connecting pads to the connection points of adjacent resistors R1.

[0082] FIG. 14A is a plan view showing a first partial layout example of the semiconductor device 100D of FIG.

[0083] 14A, each resistor R1 is formed of high-resistance polysilicon 81, 83, and 82, and 71 to 76 are formed of low-resistance polysilicon that acts as wiring conductors. Note that 50 to 53A are via conductors filled in vias that penetrate the semiconductor substrate in the thickness direction.

[0084] 14A, node P1 is connected to one end of resistor R1 of high-resistance polysilicon 81 via wiring conductor 60, via conductor 50, and low-resistance polysilicon 71. The other end of resistor R1 is connected to the drain of MOS transistor Q2 of semiconductor device 10-1 via low-resistance polysilicon 73 and via conductor 51A, and is also connected to one end of resistor R1 of high-resistance polysilicon 82 via via conductor 51A, wiring conductor 65, via conductor 51B, and low-resistance polysilicon 74. The other end of resistor R1 of high-resistance polysilicon 82 is connected to the drain of MOS transistor Q1 of semiconductor device 10-2 via low-resistance polysilicon 72 and via conductor 52A. Via conductor 52A is connected to one end of resistor R1 of high-resistance polysilicon 83 via wiring conductor 66, via conductor 52B, and low-resistance polysilicon 75. The other end of the resistor R1 of the high resistance polysilicon 83 is connected to the drain of the MOS transistor Q2 of the semiconductor device 10-2 through the low resistance polysilicon 76 and the via conductor 53A, and the via conductor 53A is connected to the wiring conductor 67. The same applies below.

[0085] Layout example 1 configured as above is an example in which three adjacent resistors R1 are connected by wiring conductors 65 and 66.

[0086] FIG. 14B is a plan view showing a second partial layout example of the semiconductor device 100D of FIG.

[0087] 14B, each resistor R1 is formed of high-resistance polysilicon 81, 83, and 82, and 71 to 74 are formed of low-resistance polysilicon that acts as a wiring conductor. Note that 50 to 53 are via conductors filled in vias that penetrate the semiconductor substrate in the thickness direction.

[0088] 14B, node P1 is connected to one end of resistor R1 of high-resistance polysilicon 81 via wiring conductor 60, via conductor 50, and low-resistance polysilicon 71. The other end of resistor R1 is connected to the drain of MOS transistor Q2 of semiconductor device 10-1 via low-resistance polysilicon 73 and via conductor 51, and via conductor 51 is connected to pad P22 via wiring conductor 63. Low-resistance polysilicon 73 is connected to one end of resistor R1 of high-resistance polysilicon 82, and the other end is connected to the drain of MOS transistor Q2 of semiconductor device 10-2 via low-resistance polysilicon 72 and via conductor 52, and via conductor 52 is connected to pad P21 via wiring conductor 62. Low-resistance polysilicon 72 is connected to one end of resistor R1 of high-resistance polysilicon 83, and the other end is connected to the drain of MOS transistor Q2 of semiconductor device 10-2 via low-resistance polysilicon 74 and via conductor 53. Via conductor 53 is connected to pad P22 via wiring conductor 64. The same applies below.

[0089] Layout example 2 configured as above is an example in which three mutually adjacent resistors R1 are connected by low-resistance polysilicon 73, 72.

[0090] While the above-described embodiments 4 to 10 (FIGS. 7A to 14B) are methods in which a circuit for controlling the voltage or current applied to resistor R1 is provided inside the semiconductor device product, there is also a method in which the control terminal is directly drawn to the outside of the IC chip. Below, we will explain embodiment 11, in which the terminal is directly drawn to the outside of the IC chip.

[0091] (Embodiment 11) Fig. 15 is a circuit diagram showing a configuration example of a semiconductor device 100E according to embodiment 11. The semiconductor device 100E in Fig. 15 shows an example in which a power supply device 110 is connected to the semiconductor device 100 in Fig. 8, and pads P11 to P22 of the semiconductor device 100 are directly drawn out to the outside of the IC chip.

[0092] In Fig. 15, since the terminals need to be drawn out to the outside of the IC chip via pads, dedicated pads P11 to P22 are provided in Fig. 15. The pads P11 to P22 drawn out to the outside of the IC chip of the semiconductor device 100 are connected to a power supply device 110 of an IC tester device or a voltage / current generator. (1) Pad P11 is connected to the positive electrode of DC voltage source 41, the negative electrode of which is connected to pad P22. (2) Pad P12 is connected to the positive electrode of DC voltage source 42, the negative electrode of which is connected to pad P22. (3) Pad P21 is connected to the positive electrode of DC voltage source 40, the negative electrode of which is connected to pad P22. (4) Pad P13 is connected to the positive electrode of DC voltage source 43, the negative electrode of which is connected to pad P22.

[0093] As in embodiment 11 of FIG. 15, an embodiment may be one in which a dedicated pad is provided for the purpose of applying the switch control signal Sc, or an embodiment may be one in which a path is formed to serve as a pad, as needed, for a pad having another purpose.

[0094] (Summary of the first embodiment group (embodiments 1 to 11)) In the prior art example 2 disclosed in Non-Patent Document 1, numerous methods are discussed regarding the mechanism for adjusting the resistance value of a polycrystalline silicon resistor. One of these is a known technique in which a current is passed through the polycrystalline silicon to control the state of the crystal interface of the polycrystalline silicon, thereby changing the resistance value. This principle is applied to the semiconductor device according to the embodiment to control the electrical characteristics of the semiconductor device product. Specifically, in the semiconductor device according to the embodiment, the resistor R1 disposed between two switch elements (e.g., composed of MOS transistors Q1 and Q2) is a "resistance-adjustable element" whose resistance value can be adjusted by applying an electrical signal. Here, the resistance value of the resistor R1 is adjusted by applying an electrical signal from an external circuit to both ends of the resistor R1 via terminal pads.

[0095] 15, by applying switch control signals Sc1, SC2, and Sc3 from power supply device 110 of an external device such as an IC tester device via pads P11 to P13, for example, MOS transistors Q1 and Q2 of semiconductor devices 10-1 to 10-3 are turned on, and a predetermined voltage is applied across resistor R1, which is a resistance-adjusting element, via pad P21, thereby adjusting the resistance. Here, resistor R1 in each embodiment can also be used as an adjustable resistor as part of the resistance within the semiconductor device.

[0096] Incidentally, a semiconductor device product contains many resistors R1. The resistors R1 for which precise control of the resistance value is desired are limited to a small number of these. Therefore, selecting the resistor to which this embodiment is applied is important from the perspective of control time and labor. For this purpose, the resistor R1 through which current flows is selected by MOS transistors Q1 and Q2, which are switching elements, i.e., it is characterized in that it can be controlled from an external circuit via a pad.

[0097] For example, in the case of the semiconductor device 100B according to the eighth embodiment shown in FIG. (1) When applying electrical signals for adjusting the resistance value to the three resistors R1, the switch control signal Sc1 is set to H level, and the switch control signals Sc2 and SC3 are set to L level. (2) When applying the electrical signal for adjusting the resistance value to the two resistors R1, the switch control signal Sc2 is set to H level, and the switch control signals Sc1 and SC3 are set to L level. (3) When applying a resistance value adjusting electrical signal to one resistor R1, the switch control signal Sc3 is set to H level, and the switch control signals Sc1 and SC2 are set to L level. (4) When applying electrical signals for adjusting the resistance value to the four resistors R1, the switch control signals Sc1 and Sc3 are set to H level, and the switch control signal Sc2 is set to L level. (5) When applying electrical signals for adjusting the resistance value to the five resistors R1, the switch control signals Sc1 and Sc2 are set to H level, and the switch control signal Sc3 is set to L level. (6) When applying electrical signals for adjusting the resistance value to the six resistors R1, the switch control signals Sc1, Sc2, and Sc3 are set to H level.

[0098] (Regarding the electrical signal for adjusting the resistance value) The resistance of resistor R1, which is a resistance-adjusting element, can be adjusted by applying a resistance-adjusting electrical signal. The electrical signal is applied from an external device via a pad, which serves as a terminal. The electrical signal may be continuous for one second or more, or may be a short square wave signal with a duration on the order of microseconds, or a series of intermittent square wave signals. Specific embodiments of these signals are described below.

[0099] Here, we will explain an example in which a current pulse or a voltage pulse is input from a tester device to a dedicated terminal or a shared terminal of a completed semiconductor device product. In one embodiment, the resistance value of resistor R1 is adjusted by applying a voltage pulse to resistor R1. First, we will explain the relationship between the resistance value adjustment amount and the applied voltage pulse.

[0100] As mentioned above, to adjust (lower or raise) the resistance value of resistor R1, a local temperature rise is caused, which is achieved by applying electrical energy from an external source. In other words, power W = current I × voltage V, and applying a predetermined voltage to resistor R1 is equivalent to applying a current pulse. The adjustment amount of resistor R1's resistance is essentially zero until the applied power reaches a predetermined threshold. However, once the threshold power is exceeded, the resistance can be adjusted up to a maximum adjustment amount, due to a correlation with the amount of power. This maximum adjustment amount is correlated with the applied power.

[0101] Next, a method for controlling the resistance adjustment amount of the resistor R1 will be described. The methods for controlling the resistance adjustment amount can be broadly classified into the following two types. (A) The first method is to control the applied voltage (= power value) and control the maximum adjustment amount. In this case, the application time of the input voltage pulse should be long enough to reach the maximum adjustment amount. (B) The second method is to control the resistance adjustment value by controlling the time (= amount of power) of the applied voltage pulse. In this case, it is possible to either control the voltage pulse time, or to keep the voltage pulse time constant and control it by the number of input voltage pulses. In addition, the voltage value of the input voltage pulse should be a voltage value that sufficiently covers the expected resistance adjustment range.

[0102] (Voltage pulse time control method) There are two methods for controlling the voltage pulse time: (A) Figure 16 is a timing chart of signals and voltage VR1 applied to resistor R1, illustrating a first control method for adjusting the resistance value of resistor R1 in semiconductor device 10 of Figure 1. In Figure 16, switch control signals Sc (Sc1, Sc2, Sc3) are set to H level to turn on MOS transistors Q1 and Q2, thereby controlling the application time of a voltage pulse applied directly from pad P21. (B) Fig. 17 is a timing chart of signals and a voltage VR1 applied to the resistor R1, illustrating a second control method for adjusting the resistance value of the resistor R1 in the semiconductor device 10 of Fig. 1. In Fig. 17, a predetermined voltage is applied to the resistor R1 from the pad P22, and the switch control signals Sc (Sc1, Sc2, Sc3) are turned on or off to control the time that the MOS transistors Q1 and Q2 are turned on.

[0103] (Functions and Effects of the First Embodiment Group) The semiconductor device according to the first embodiment group is incorporated as part of a semiconductor device, and the resistance value of resistor R1, which operates as part of the function of the semiconductor device, can be adjusted to any value, and the effect of improving the electrical characteristics of the semiconductor device product can also be expected.

[0104] 1 according to the first embodiment, nodes P1 and P2 are connected to the semiconductor device connected to resistor R1, and a predetermined electrical signal is applied between pads P21 and P22, and a switch control signal Sc is input to pad P10 to turn on or off MOS transistors Q1 and Q2, which are switch elements, to adjust the resistance of resistor R1, which is a resistance-adjusting element. This adjusts the resistance between nodes P1 and P2, thereby improving the electrical characteristics of the semiconductor device product.

[0105] Semiconductor elements have a rated voltage, and applying a voltage exceeding this will destroy the element. One solution is to separate the resistor R1, which serves as a resistance-adjusting element, from the semiconductor functional section and provide a dedicated terminal pad. Another solution is to apply a voltage pulse below the rated voltage. This approach reduces the amount of resistance adjustment. The latter issue can be resolved by combining multiple resistors R1, as described above. For example, comparing the semiconductor device 100 according to the sixth embodiment shown in FIG. 8 with the semiconductor device 100D according to the tenth embodiment shown in FIG. 13, the semiconductor device 100D can adjust the resistance three times more than the semiconductor device 100 using three switch control signals Sc1 to Sc3. Furthermore, by setting the amount of resistance adjustment to a fixed value and combining two patterns of resistors R1—adjusted and unadjusted—the resistance adjustment can be more easily controlled. Furthermore, by grouping semiconductor devices 10, as in the semiconductor device 100 according to the eighth embodiment shown in FIG. 10 and the semiconductor device 100D according to the tenth embodiment shown in FIG. 13, a larger amount of resistance adjustment can be achieved for the entire resistor circuit.

[0106] (Second embodiment group) The object of the invention according to each embodiment of the second embodiment group is to adjust the resistance value of resistor R1, prevent the appearance of a current path that flows other than resistor R1 when adjusting the resistance value, and achieve the above without increasing the number of pads. Note that, below, an embodiment including a comparator or an operational amplifier will be described as an embodiment incorporated as part of the function of a semiconductor device, but the present invention is not limited to this, and is not limited to semiconductor devices that include a comparator or an operational amplifier.

[0107] (Embodiment 12) Fig. 18 is a circuit diagram showing a configuration example of a voltage detection circuit 120 according to embodiment 12. In Fig. 18, the voltage detection circuit 120 has pads P31 and P32, and is configured to include a test mode control circuit 20, a semiconductor device circuit 30 including the semiconductor device 10 according to embodiment 1 of Fig. 1, a comparator 31, and a reference voltage source 45. In addition, the peripheral circuit of the voltage detection circuit 120 includes a tester device 90 including a controller 91 and a pulse signal generator 21.

[0108] 18, a semiconductor device circuit 30 includes the semiconductor device 10 of FIG. 1, a power supply voltage VDD, voltage-dividing resistors R11 and R13 that are reference resistors with known resistance ratios, an adjustment variable resistor R12, a resistor R1 that is a resistance-adjusting element, a PMOS transistor Q4 that is a switching element, and an inverter INV2. Here, the adjustment variable resistor R12 is an adjustment resistor that is manufactured by laser trimming according to conventional technology.

[0109] The test mode control circuit 20 can be set to the test mode by inputting the test mode signal Stm. That is, in the tester device 90, the controller 91 outputs the test mode signal Stm to the test mode control circuit 20 via the pad P40, thereby inverting the switch control signal Sc from the test mode control circuit 20 and entering the test mode. The voltage detection signal Sd of the comparator 31 is input to the controller 91 of the tester device 90 via the pad P33.

[0110] The power supply voltage VDD is grounded via the adjustable resistor R12 for adjustment, the voltage-dividing resistors R11 and R13, the resistor body R1, and the drain and source of the MOS transistor Q4. A pulse signal generator 21 that generates a pulse of voltage V21 is connected between pads P31 and P32. Based on an instruction signal from the controller 91, the pulse signal generator 21 applies the pulse voltage V21 between pads P31 and P32, so that it is applied across both ends of the resistor body R1 when the MOS transistors Q1 and Q2 are on.

[0111] Furthermore, the voltage Vdiv (a voltage corresponding proportionally to the voltage between VDD and VSS) obtained by dividing the voltage between VDD and VSS with the voltage-dividing resistors R11, R13, etc. is applied to the non-inverting input terminal of the comparator 31, and the reference voltage Vref of the reference voltage source 45 is applied to its inverting input terminal. Here, the reference voltage Vref is an example of a reference voltage. When Vdiv ≥ Vref, the comparator 31 outputs a high-level voltage detection signal Sd to the pad P33, while when Vdiv < Vref, it outputs a low-level voltage detection signal Sd to the pad P33.

[0112] The voltage detection circuit 120 configured as described above constitutes a resistance value adjustment device.

[0113] FIG. 21 is a timing chart of each signal and the voltage V21 showing the control methods of the voltage detection circuits 120 and 120A in FIGS. 18 to 19 and the error amplifier circuit 120B in FIG. 20. Note that the error amplifier circuit 120B in FIG. 20 is an example of an error amplifier circuit used in a linear regulator such as an LDO (Low Dropout).

[0114] As shown in FIG. 21, the test mode control circuit 20 in FIG. 18 outputs a low-level switch control signal Sc in the normal mode to turn off the MOS transistors Q1 and Q2, turn on the MOS transistor Q4, and prevent the voltage V21 from the pulse signal generator 21 from being applied to the resistor body R1. At this time, the resistor body R1, which is an adjustable resistor, functions as a voltage-dividing resistor between VDD and VSS that generates an input voltage to the comparator 31.

[0115] Meanwhile, in the resistance adjustment mode (test mode), the test mode control circuit 20 outputs a high-level switch control signal Sc to turn on the MOS transistors Q1 and Q2 and turn off the MOS transistor Q4. The pulse signal generator 21 applies a voltage V21 to the resistor R1 only during a predetermined resistance adjustment period during the resistance adjustment mode. In this state, the pulse signal generator 21, which serves as a resistance adjustment power supply, applies a predetermined voltage between the pads P31 and P32 to adjust the resistance of the resistor R1. This mechanism prevents current for resistance adjustment from leaking to any location other than the resistor R1. Even if the pads P31 and P32 are shared with pads for other voltages, such as the power supply voltage VDD and the ground voltage VSS, current can flow only through the resistor R1. After the test mode control circuit 20 has finished adjusting the resistance of the resistor R1, the test mode control circuit 20 outputs a low-level switch control signal Sc to turn off the MOS transistors Q1 and Q2 and the MOS transistor Q4, returning to the normal mode.

[0116] In the voltage detection circuit 120 of FIG. 18 configured as described above, when the voltage between VDD and VSS is equal to or greater than a predetermined threshold voltage, an H-level voltage detection signal Sd is output, and when the voltage between VDD and VSS is less than the predetermined threshold voltage, an L-level voltage detection signal Sd is output.

[0117] 18, protection elements such as ESD protection resistors are omitted. Nodes P21 and P22 are connected to pads P31 and P32, respectively, allowing current to flow from a pulse signal generator 21, which is a power supply device for adjusting resistance values, to resistor R1, which is the adjustment resistor, via MOS transistors Q1 and Q2. Pads P31 and P32 may be shared with other pads, such as those for power supply voltage VDD or ground voltage VSS.

[0118] Although the voltage detection circuit 120 according to the twelfth embodiment includes the semiconductor device 10, the present invention is not limited to this and may be configured with other semiconductor devices 10A to 10E, or semiconductor devices 100, 100A to 100G. In this modification, the MOS transistors Q1 and Q2 and the MOS transistor Q4 are configured to operate mutually exclusively.

[0119] In the voltage detection circuit 120 according to the twelfth embodiment, the power supply voltage VDD is an example of a first power supply voltage, and the ground voltage VSS is an example of a second power supply voltage that is lower than the first power supply voltage.

[0120] (Embodiment 13) Fig. 19 is a circuit diagram showing an example of the configuration of a voltage detection circuit 120A according to embodiment 13. In Fig. 19, the voltage detection circuit 120A differs from the voltage detection circuit 120 in Fig. 18 in the following points. (1) The semiconductor device circuit 30 is replaced with a semiconductor device circuit 30A. (2) Instead of the power supply voltage VDD and the reference voltage source 45, a reference voltage source 22 that generates the reference voltage VREF and DC voltage sources of predetermined voltages V1 and V2 are used. The differences will be explained below.

[0121] 19, a semiconductor device circuit 30A includes the semiconductor device 10 of FIG. 1, voltage dividing resistors R11 and R13 which are reference resistors with known resistance ratios, an adjustment variable resistor R12, a resistor R1 which is also an adjustment variable resistor, a PMOS transistor Q4 which is a switch element, and an inverter INV2.

[0122] The voltage detection circuit 120A configured as described above is used to detect differences between voltages whose absolute values ​​are smaller than those of the voltage detection circuit 120 of FIG. 18. In the voltage detection circuit 120A, the comparator 31 outputs a high-level voltage detection signal Sd when the voltage VR131 (a voltage based on voltage V2), obtained by dividing the voltage between V1 and V2 using voltage-dividing resistors R11, R13, etc., is equal to or greater than a predetermined reference voltage V1, and outputs a low-level voltage detection signal Sd when the voltage between V1 and V2 is less than the reference voltage V1. That is, the comparator 31 outputs a high-level voltage detection signal Sd when the voltage between V1 and V2 is equal to or greater than a predetermined threshold voltage, and outputs a low-level voltage detection signal Sd when the voltage between V1 and V2 is less than the predetermined threshold voltage. The voltage detection circuit 120A operates in a similar manner to that of FIG. 21, and its effects are similar to those of the voltage detection circuit 120 of FIG. 18.

[0123] In the voltage detection circuit 120A according to the thirteenth embodiment, the reference voltage of the reference voltage source 22 is an example of a first power supply voltage, the voltage V2 is an example of a second power supply voltage lower than the first power supply voltage, and the voltage V1 is an example of a fluctuating input voltage.

[0124] (Embodiment 14) Fig. 20 is a circuit diagram showing a configuration example of an error amplifier circuit 120B according to embodiment 14. In Fig. 20, the error amplifier circuit 120B differs from the voltage detection circuit 120 in Fig. 18 in the following points. (1) An operational amplifier (op-amp) 32 is provided instead of the comparator 31. Here, the operational amplifier 32 outputs an output voltage Vd (=Vref×(R12+R11+R13+R1) / (R13+R1), where the reference voltage Vref=Vdiv) to a pad P33 and one end of an adjustment variable resistor R12. (2) Instead of the semiconductor device circuit 30, a semiconductor device circuit 30B is provided, and instead of the power supply voltage VDD and the reference voltage source 45, one end of the adjustment variable resistor R12 to which the power supply voltage VDD is connected is connected to the output terminal of an operational amplifier 32, which is an operational amplifier.

[0125] 20, the semiconductor device circuit 30B includes the semiconductor device 10 of FIG. 1, voltage dividing resistors R11 and R13 which are reference resistors with known resistance ratios, an adjustment variable resistor R12, a resistor R1 which is also an adjustment variable resistor, a PMOS transistor Q4 which is a switch element, and an inverter INV2. In particular, compared to the semiconductor device circuit 30A, the terminal of the voltage V2 of FIG. 19 is grounded to the ground voltage VSS.

[0126] In the error amplifier circuit 120B configured as described above, the resistance value adjustment circuit of the semiconductor device circuit 30B can be used as a voltage dividing resistor used in a negative feedback circuit of a general operational amplifier 32. The error amplifier circuit 120B is an example of an error amplifier circuit incorporated in a linear regulator, such as an LDO (Low Dropout).

[0127] 18 and 19, and the error amplifier circuit 120B of FIG. 20, the variable resistor R12 may have a configuration similar to that of the semiconductor device 10 of FIG. 1. Also, while the variable resistor R12 is arranged on the power supply voltage side and the resistor R1 is arranged on the ground voltage side, the present invention is not limited to this, and they may be arranged on the opposite voltage sides, or both may be arranged on the power supply voltage side or the ground voltage side. That is, while FIG. 20 shows a predetermined series circuit configured in the order of the adjustment variable resistor R12, resistor R11, resistor R13, and resistor R1 from the power supply voltage side, the present invention is not limited to this, and the order of the constituent resistors of the series circuit may be random.

[0128] (Semiconductor Device Manufacturing Processing) FIG. 22 is a flowchart showing a semiconductor device manufacturing process including resistor generation and resistance value adjustment processes for the resistor semiconductor devices according to the first to eleventh embodiments and the voltage detection circuits according to the twelfth to fourteenth embodiments.

[0129] In FIG. 22, the semiconductor device manufacturing process including the resistor generation and resistance value adjustment process includes the following steps. (1) Step S1: Wafer manufacturing process; (2) Step S2: First test process; (3) Step S3: Laser trimming process; (4) Step S4: Packaging process; and (5) Step S5: Second test process (including resistance value adjustment process).

[0130] 22, first, a wafer manufacturing process is performed in step S1, and then, in a first test process in step S2, a test is performed in a state where MOS transistor Q4 is turned on and MOS transistors Q1 and Q2 are turned off by outputting an L-level switch control signal Sc from test mode control circuit 20. Based on the trimming value of variable resistor R12 calculated in the first test process, laser trimming of variable resistor R12 is performed in a laser trimming process in step S3, thereby setting variable resistor R12 to a predetermined resistance value. Next, a packaging process is performed in step S4, and then, a second test process is performed in step S5, in which a resistance value adjustment process of resistor R1 is performed.

[0131] (Third embodiment group) The problem to be solved by the invention according to the third embodiment group is as follows. In the laser trimming process (S3), the resistance value of the variable resistor R12 differs for each device, so the resistor voltage division ratio is not known information for determining the target adjustment value of the resistor R1. Therefore, measurements must be taken in the second test process (S5) to determine the individual resistor voltage division ratios. Furthermore, it is preferable to achieve the above without increasing the number of pads.

[0132] Specifically, if the information on the resistance R12a after trimming of the variable resistor R12 cannot be carried over from the first test process (S2) or the laser trimming process (S3) to the second test process (S5), measurements are required in the second test process (S5) to determine the individual resistor division ratios (R13+R1) / (R12a+R11+R13+R1).

[0133] An object of the invention according to the third embodiment group is to provide a semiconductor device and method for measuring the resistance value of resistor R1, and embodiments 15 to 21 according to the third embodiment group will be described below.

[0134] (Embodiment 15) Fig. 23 is a circuit diagram showing a configuration example of a voltage detection circuit 120C according to embodiment 15. In Fig. 23, the voltage detection circuit 120C differs from the voltage detection circuit 120 in Fig. 18 in the following respects. Note that the following differences also include the peripheral configurations and operations. (1) Instead of the test mode control circuit 20, a test mode control circuit 20A is provided. (2) For example, the test mode control circuit 20A can be set to test mode by inputting a test mode signal Stm. The device further includes a circuit that outputs a divided voltage Vdiv obtained by dividing the power supply voltage VDD1 between VDD and VSS using voltage-dividing resistors R11, R13, etc. (The divided voltage Vdiv is measured by the tester device 90). Specifically, the device further includes a switch SW1 and a pad P34. The divided voltage Vdiv is output to a voltage sensor 92 of the external tester device 90 via the switch SW1 and the pad P34. The voltage sensor 92 of the tester device 90 measures the voltage between the pad P34 and VSS, making it possible to know the divided voltage Vdiv, which differs for each individual semiconductor device. (3) The tester device 90 includes a controller 91, a voltage sensor 92, and a pulse signal generator 21. The controller 91 outputs a test mode signal Stm to the test mode control circuit 20A via the pad P40, thereby inverting the switch control signals Sc and Scs from the test mode control circuit 20A and entering the test mode. The voltage detection signal Sd from the comparator 31 is input to the controller 91 of the tester device 90. (4) The test mode control circuit 20A generates the switch control signal Sc and also controls the on / off of the switch SW1. Therefore, the voltage detection circuit 120C constitutes a resistance value adjustment device. The differences will be explained below.

[0135] 23 configured as above, when the test mode control circuit 20A outputs an H-level switch control signal Scs to the switch SW1, the switch SW1 is turned on and the divided voltage Vdiv is output to the pad P34 via the switch SW1. On the other hand, when the test mode control circuit 20A outputs an L-level switch control signal Scs to the switch SW1, the switch SW1 is turned off and the divided voltage Vdiv is not output to the pad P34 via the switch SW1.

[0136] Next, a method for calculating the resistance change amount Rx (referring to the adjustment resistance change amount by which the resistor R1 should be changed when the resistor R1 has the desired resistance value R1) of the resistor R1 of the voltage detection circuit 120C in FIG. 23 by the test mode control circuit 20A will be described below.

[0137] In the voltage detection circuit 120C of FIG. 23, when the power supply voltage VDD1 is applied between VDD and VSS, if the divided voltage based on the ground voltage VSS output from the pad P34 is Vdiv, the individual resistor voltage division ratios can be calculated by the following equation.

[0138] (R13+R1) / (R12a+R11+R13+R1)=Vdiv / VDD1 (1)

[0139] Before adjusting the resistance value of resistor R1, the power supply voltage VDD1 is changed to a ground voltage VSS reference, and the power supply voltage VDD1 at which the VDD-VSS voltage detection signal Sd, which is the output voltage of comparator 31, inverts from L level to H level is measured as detection voltage VdetA. Furthermore, if the target value of the detection voltage of the VDD-VSS power supply voltage VDD1 when resistor R1 is changed by the resistance change amount Rx is set to detection voltage VdetB, the following equation holds:

[0140] VdetA(R13+R1) / (R12a+R11+R13+R1) =VdetB(R13+R1+Rx) / (R12a+R11+R13+R1+Rx) (2)

[0141] Here, the amount of change in resistance value Rx of the resistor R1 can be calculated from the above formulas (1) and (2) using the following formula:

[0142]

number

[0143] As described above, according to the voltage detection circuit 120C of the fifteenth embodiment, even if the variable resistor R12 is changed to a different value for each device, the resistance change amount Rx of the resistor R1 can be calculated, and based on this, the resistance value of the resistor R1 can be set to a desired resistance value. Therefore, the voltage detection circuit 120C constitutes a resistance value adjusting device.

[0144] In the above-described fifteenth embodiment, the present invention is not limited to this, and the semiconductor device 10 may be any of the semiconductor devices 10A to 10E, or a configuration in which a plurality of these semiconductor devices are connected in series.

[0145] (Embodiment 16) Fig. 24 is a circuit diagram showing a configuration example of a voltage detection circuit 120D according to embodiment 16. In Fig. 23, pad P34 is provided as a dedicated pad for outputting divided voltage Vdiv. In contrast, Fig. 24 shows a configuration example in which pad P34 connected to a predetermined internal circuit 25 can be used in common as a pad for outputting divided voltage Vdiv.

[0146] 24, the voltage detection circuit 120D differs from the voltage detection circuit 120C in FIG. 23 in the following respects: (1) The connection point between the switch SW1 and the pad P34 is connected to the internal circuit 25 via the switch SW2. Here, the internal circuit 25 is a circuit formed on the same silicon as the resistor R1, for example. (2) The switch control signal Scs from the test mode control circuit 20A is further input to the control terminal of the switch SW2 via the inverter INV3. That is, the switch SW2 is controlled to be turned on and off in an inverse relationship to the switch SW1.

[0147] In the voltage detection circuit 120D configured as described above, the test mode control circuit 20A inverts the switch control signal Scs from L level to H level to turn on the switch SW1, and in sync with this, turns off the switch SW2, thereby electrically isolating the divided voltage Vdiv, which is the divided detection voltage, from the internal circuit 25, and the divided voltage Vdiv can be output to the external tester device 90 via the pad P34.

[0148] Fig. 25 is a flowchart showing the process of adjusting the resistance value of the resistor of the voltage detection circuit 120D of Fig. 24, which is executed by the controller 91 of the tester device 90. The process of adjusting the resistance value of the resistor of Fig. 25 can also be applied to the voltage detection circuit 120C of Fig. 23.

[0149] 25, first, in the initialization process for the normal mode in step S11, the switch control signal Sc is set to H level and the switch control signal Scs is set to L level, thereby turning on the MOS transistor Q4 and the switch SW2 and turning off the MOS transistors Q1, Q2 and the switch SW1. Next, in step S12, in this state, the power supply voltage VDD1 is changed in an upward direction, thereby changing the divided voltage Vdiv based on the VDD-VSS power supply voltage VDD1, and when the voltage detection signal Sd is inverted from L level to H level (YES in step S12), in step S13 the power supply voltage VDD1 at that time is measured as the detection voltage VdetA.

[0150] Next, in step S14, the switch control signal Scs is set to H level to turn on switch SW1 and turn off switch SW2. In this state, in step S15, the divided voltage Vdiv output from pad P34 is measured by the voltage sensor 92 of the tester device 90. Furthermore, in step S16, the controller 91 of the tester device 90 calculates the resistance change amount Rx using equation (3) from the detection voltage VdetA obtained above, the divided voltage Vdiv, the known resistance values ​​R13 and R1, and the target detection voltage VdetB. Next, in step S17, the test mode control circuit 20A sets the switch control signal Sc to L level to turn on MOS transistors Q1 and Q2 and turn off MOS transistor Q4. Furthermore, in step S18, based on the calculated resistance change amount Rx, the resistance adjustment pulse signal generator 21 applies a current to the resistor R1 using a predetermined voltage for a predetermined time using the known method described above, thereby changing the resistance of the resistor R1 by the resistance change amount Rx.

[0151] As described above, according to the voltage detection circuit 120D of the sixteenth embodiment, even when the variable resistor R12 is changed, the resistance change amount Rx of the resistor R1 can be calculated, and based on this, the resistance value of the resistor R1 can be set to a desired resistance value. Therefore, the voltage detection circuit 120D constitutes a resistance value adjusting device.

[0152] In the sixteenth embodiment described above, the present invention is not limited to this, and the semiconductor device 10 may be any of the semiconductor devices 10A to 10E, or a configuration in which a plurality of these semiconductor devices are connected in series.

[0153] (Embodiment 17) Fig. 26 is a circuit diagram showing an example of the configuration of a voltage detection circuit 120E according to embodiment 17. Here, the voltage detection circuit 120E is another example of a circuit for determining individual resistor voltage division ratios in the second test process. In Fig. 26, the voltage detection circuit 120D differs from the voltage detection circuit 120C in Fig. 24 in the following respects. (1) Instead of the comparator 31 and the reference voltage source 45, a voltage follower circuit including an operational amplifier 32 and a reference voltage source 45 is provided. When the switch SW3 is off and the switch SW4 is on, the operational amplifier 32 operates as a comparator and outputs a signal voltage (voltage detection signal Vd) similar to the voltage detection signal Sd to the tester device 90. On the other hand, when the switch SW3 is on and the switch SW4 is off, the operational amplifier 32 operates as a voltage follower circuit and outputs Vref as Vd. (2) Peripheral circuits of the voltage follower amplifier circuit include switches SW3, SW4, SW5, an inverter INV4, and a delay circuit 26. The delay circuit 26 has a delay time based on, for example, the voltage detection signal Vd. The differences will be explained below.

[0154] 26, a divided voltage Vdiv obtained by dividing resistors R11, R13, etc. is input to the inverting input terminal of an operational amplifier 32 via a switch SW4, and the output terminal of the operational amplifier 32 is connected to the inverting input terminal of the operational amplifier 32 via a switch SW3. A voltage detection signal Vd, which is the output voltage of the operational amplifier 32, is output to a pad P36 via a switch SW5 and a delay circuit 26. A switch control signal Sca from a test mode control circuit 20B is input to the control terminal of the switch SW3 and also input to the control terminals of the switches SW4 and SW5 via an inverter INV4. In response to the switch control signal Sca at an H level, the switch SW3 is turned on, and the switches SW4 and SW5 are turned off. On the other hand, in response to the switch control signal Sca at an L level, the switch SW3 is turned off, and the switches SW4 and SW5 are turned on.

[0155] In the voltage detection circuit 120E configured as described above, in test mode, the test mode control circuit 20B inverts the switch control signal Sca from L level to H level to turn on the switch SW3 and change the operation of the operational amplifier 32 from a comparator to a voltage follower circuit. By turning off the switches SW4 and SW5 in synchronization with the turning on of the switch SW3, the voltage follower circuit can be electrically disconnected from the circuit of the voltage-dividing resistors R11 and R13 and the delay circuit 26.

[0156] A reference voltage Vref is output from the pad P34, and the individual resistor voltage division ratios can be calculated using the following equation.

[0157] (R13+R1) / (R12a+R11+R13+R1)=Vref / VdetA (4)

[0158] Here, for simplicity, the reference voltage Vref is assumed to be a voltage to which the offset voltage of the operational amplifier 32 is added. Before adjusting the resistance value of resistor R1, when the power supply voltage VDD=VDD1 is changed in an upward direction, the divided voltage Vdiv corresponding to the VDD-VSS power supply voltage VDD1, which is the output voltage of the operational amplifier 32 and which causes the voltage detection signal Vd to invert from H level to L level when operating as a comparator, is measured as the detection voltage VdetA. Equation (2) is valid as in the circuit of Figure 24 and is expressed as the following equation, so the amount of change in resistance value Rx can be calculated using equations (2) and (3).

[0159]

number

[0160] FIG. 27 is a flowchart showing the process of adjusting the resistance value of the resistor of the voltage detection circuit 120E of FIG. 26, which is executed by the controller 91 of the tester device 90.

[0161] 27, first, in the initialization process for the normal mode in step S21, the switch control signal Sc is set to H level and the switch control signals Scs and Sca are set to L level, thereby turning on the MOS transistor Q4 and the switches SW2, SW4, and SW5 and turning off the MOS transistors Q1, Q2 and the switches SW1 and SW3. Next, in step S22, in this state, the power supply voltage VDD1 is changed in an upward direction to change the divided voltage Vdiv based on the VDD-VSS power supply voltage VDD1, and when the voltage detection signal Vd is inverted from H level to L level (YES in step S22), in step S23, the divided voltage Vdiv corresponding to the power supply voltage VDD1 at that time is measured as the detection voltage VdetA.

[0162] Next, in step S24, the switch control signals Scs and Sca are set to H level to turn on switches SW1 and SW3 and turn off switches SW2, SW4, and SW5. In this state, in step S25, the voltage sensor 92 of the tester device 90 measures the reference voltage Vref output from pad P34. In step S26, the controller 91 of the tester device 90 calculates the resistance change amount Rx using equation (5) from the detection voltage VdetA obtained above, the reference voltage Vref, the known resistance values ​​R13 and R1, and the target detection voltage VdetB. Next, in step S27, the test mode control circuit 20B sets the switch control signal Sc to L level to turn on MOS transistors Q1 and Q2 and turn off MOS transistor Q4. Furthermore, in step S28, based on the calculated resistance change amount Rx, while maintaining that state, the resistance adjustment pulse signal generator 21 passes a current through the resistor R1 using a predetermined voltage for a predetermined time, thereby changing the resistance of the resistor R1 by the resistance change amount Rx.

[0163] As described above, according to the voltage detection circuit 120E of the seventeenth embodiment, even when the variable resistor R12 is changed, the resistance change amount Rx of the resistor R1 can be calculated, and based on this, the resistance value of the resistor R1 can be set to a desired resistance value. Therefore, the voltage detection circuit 120E constitutes a resistance value adjusting device.

[0164] In the seventeenth embodiment described above, the present invention is not limited to this, and the semiconductor device 10 may be any of the semiconductor devices 10A to 10E, or a configuration in which a plurality of these semiconductor devices are connected in series.

[0165] Furthermore, the switch control signals Sca and Scs are different control signals, but the present invention is not limited to this, and the switch control signals may be the same or may be inverted in synchronization with each other.

[0166] (Embodiment 18) Fig. 28 is a circuit diagram showing a configuration example of a voltage detection circuit 120F according to embodiment 18. In Fig. 28, the voltage detection circuit 120F differs from the voltage detection circuit 120C in Fig. 23 in the following points. (1) The semiconductor device circuit 30 is replaced with a semiconductor device circuit 30C. (2) A test mode control circuit 20C is provided in place of the test mode control circuit 20A. The differences will be explained below.

[0167] 28, a semiconductor device circuit 30C includes the semiconductor device 100 of FIG. 8, voltage-dividing resistors R11 and R13 that are reference resistors with known resistance ratios, an adjustment variable resistor R12, a resistor R1 that is also an adjustment variable resistor, a PMOS transistor Q4 that is a switch element, and a NOR gate NOR1. Here, in the semiconductor device 100, the resistors R1 of the semiconductor devices 10-1, 10-2, and 10-3 are referred to as resistors R1-1, R1-2, and R1-3 in order to distinguish them from one another.

[0168] The test mode control circuit 20C generates three switch control signals Sc1, Sc2, and Sc3 and outputs them to the nodes P11, P12, and P13 of the semiconductor devices 10-1, 10-2, and 10-3, respectively, and also to the gate of the MOS transistor Q4 via the NOR gate NOR1.

[0169] FIG. 29 is a flowchart showing the process of adjusting the resistance value of the resistor of the voltage detection circuit 120F of FIG. 28, which is executed by the controller 91 of the tester device 90.

[0170] 29, first, in the initialization process for normal mode in step S31, switch control signals Sc1, Sc2, and Sc3 are set to L level to turn on MOS transistor Q4 and turn off MOS transistors Q1 and Q2 of semiconductor devices 10-1, 10-2, and 10-3. Next, in step S32, in this state, power supply voltage VDD1 is changed in an upward direction to change divided voltage Vdiv based on the VDD-VSS voltage. When voltage detection signal Sd is inverted from L level to H level (YES in step S32), power supply voltage VDD1 at that time is measured as detection voltage VdetA in step S33. Here, the following equation holds for detection voltage VdetA:

[0171] Vref =VdetA(R13+(R1-1)+(R2-1)+R42) / (R12a+R11+R13+(R1-1)+(R1-2)+(R1-3)) (6)

[0172] Next, in step S34, the switch control signal Sc1 is set to H level, turning on the MOS transistors Q1 and Q2 of the semiconductor device 10-1 and turning off the MOS transistor Q4. In this state, in step S35, the resistor R1-1 is changed by a predetermined amount ΔR, which is called "trial trimming." Next, in step S36, the switch control signal Sc1 is set to L level, turning off the MOS transistors Q1 and Q2 of the semiconductor device 10-1 and turning on the MOS transistor Q4. Next, in step S37, in this state, the power supply voltage VDD1 is changed in an upward direction, thereby changing the divided voltage Vdiv based on the VDD-VSS voltage. When the voltage detection signal Sd switches from L level to H level (YES in step S37), in step S38, the power supply voltage VDD=VDD1 at that time is measured as the detection voltage VdetC. Here, the following equation holds for the detection voltage VdetC:

[0173] Vref =VdetC(R13+(R1-1)+(R1-2)+(R1-3)+ΔR) / (R12a+R1+R3+(R1-1)+(R1-2)+(R1-3)+ΔR) (7)

[0174] Here, the following equation is established from equations (6) and (7).

[0175] VdetA(R13+(R1-1)+(R1-2)+(R1-3)) / (R12a+R11+R13+(R1-1)+(R1-2)+(R1-3)) =VdetC(R13+(R1-1)+(R1-2)+(R1-3)+ΔR) / (R12a+R11+R13+(R1-1)+(R1-2)+(R1-3)+ΔR) (8)

[0176] Resistance R12a can be calculated by substituting the detection voltages VdetA and VdetC obtained by the above measurement and known resistances R11, R13, R1-1, R1-2, R1-3, and ΔR into equation (8).

[0177] where: Ry = R3 + (R1-1) + (R1-2) + (R1-3) Then, the resistance R12a can be calculated using the following equation:

[0178]

number

[0179] Furthermore, if the amount of change in resistance value to be additionally adjusted in the resistor R1 is Rx and the target value of the VDD-VSS detection voltage is VdetB, the following equation is established.

[0180] VdetC(R13+(R1-1)+(R1-2)+(R1-3)+ΔR) / (R12a+R11+R13+(R1-1)+(R1-2)+(R1-3)+ΔR) =VdetB(R13+(R1-1)+(R1-2)+(R1-3)+ΔR+Rx) / (R12a+R11+R13+(R1-1)+(R1-2)+(R1-3)+ΔR+Rx) (10)

[0181] By substituting the resistance value R12a calculated using equation (8), the detection voltage VdetC obtained by the measurement, and the known detection voltage VdetB, resistances R11, R13, R1-1, R1-2, R1-3, and ΔR into equation (9), the resistance change amount Rx can be calculated using the following equation.

[0182]

number

[0183] Here, when the right side of equation (11) is substituted for the resistor R12a in equation (11), the following equation is obtained.

[0184]

number

[0185] In step S39 of FIG. 29, the controller 91 of the tester device 90 calculates the resistance change amount Rx using Equation (10). Next, in step S40, based on the calculated resistance change amount Rx, the switch control signals Sc2 and Sc3 are set to the H level or the L level. Specifically, it is as follows.

[0186] (1) When 0.5ΔR < Rx ≤ 1.5ΔR, by setting the switch control signal Sc2 to the H level, the MOS transistors Q1 and Q2 of the semiconductor device 10-2 are turned on, and the MOS transistor Q4 is turned off. (2) When 1.5ΔR < Rx ≤ 2.5ΔR, by setting the switch control signals Sc2 and Sc3 to the H level, the MOS transistors Q1 and Q2 of the semiconductor devices 10-2 and 10-3 are turned on, and the MOS transistor Q4 is turned off.

[0187] Next, in step S41, based on the calculated resistance change amount Rx, the resistance adjusting pulse signal generator 21 individually applies currents to the resistors R1-2 and R1-3 using a predetermined voltage for a predetermined time by a known method as described above, thereby adjusting the resistance values of the resistors R1-2 and R1-3.

[0188] As described above, according to the voltage detection circuit 120F according to the eighteenth embodiment, even when the variable resistor R12 is changed, the resistance change amount Rx of the resistors R1-2 and R1-3 for setting the detection voltage VdetB can be calculated without mounting the pads P34 and the switches SW1 to SW5 in FIGS. 23, 24, and 26. Based on this, the resistance values of the resistors R1-1, R1-2, and R1-3 can be set to desired resistance values. Therefore, the voltage detection circuit 120F constitutes a resistance value adjusting device.

[0189] In the above eighteenth embodiment, the semiconductor device 100 is not limited to this, and may be 100A to 100G. Further, the resistors R1-1, R1-2, and R1-3 of the semiconductor device 100 may have a bit configuration in which the number of resistors R1 of the sum of powers of 2 is arranged as shown in FIG. 32 described later.

[0190] (Embodiment 19) Fig. 30 is a circuit diagram showing a configuration example of a semiconductor device 10E according to embodiment 19. In Fig. 30, the semiconductor device 10E differs from the semiconductor device 10 of Fig. 1 in the following points. (1) A polycrystalline silicon resistor R1A was connected in parallel to resistor R1. The differences will be explained below.

[0191] In the semiconductor device 10E of Fig. 30, connecting the resistors R1 and R1A in parallel reduces the amount of resistance change and enables adjustment with higher resolution. Here, if the resistors R1 and R1A use resistance-adjusting elements with the same parameters, and the resistance value is R1 and the resistance adjustment value is ΔR, the resolution of the resistance adjustment value is ΔR in the configuration of Fig. 1.

[0192] In the case of the circuit configuration of FIG. 30, the following equation holds:

[0193] 1 / (R1+ΔR)+1 / (R1+ΔR) =1 / (1 / 2R1+1 / 2×ΔR)

[0194] Therefore, the resolution of the resistance adjustment value is ΔR / 2, which is higher than the resolution in Figure 1. In other words, by incorporating multiple resistors R1 connected in parallel into a circuit in which resistors R1 are connected in series, there is a unique effect of making the resolution finer.

[0195] In addition, connecting another resistor R1A in parallel to the resistor R1 according to embodiment 19 of Figure 30 can be applied to all resistors R1 according to all embodiments in this specification, or to some of the resistors R1.

[0196] (Embodiment 20) Fig. 31 is a circuit diagram showing a configuration example of a semiconductor device 100F according to embodiment 20. In Fig. 31, the semiconductor device 100F includes the semiconductor device 100 of Fig. 8 and the semiconductor device 10E of Fig. 30, and is characterized in that the semiconductor device 10E of Fig. 30 is arranged in the subsequent stage of the semiconductor device 100 of Fig. 8. Below, differences from the semiconductor device 100 of Fig. 8 will be described.

[0197] 31, a switch control signal Sc4 of the semiconductor device 10E is applied to a pad P14. A series circuit of three resistors R1 of the semiconductor device 100 and a parallel circuit of resistors R1 and R1A of the semiconductor device 10E is inserted between nodes P1 and P2.

[0198] In the semiconductor device 100 of FIG. 8, the adjustment effect per resistor R1 is ΔR, and increasing the number of resistors R1 results in an adjustment effect of ΔR, 2ΔR, and 3ΔR, allowing the resistance value to be adjusted with a resolution of ΔR. In contrast, in the semiconductor device 100F of FIG. 30, the MOS transistors Q1 and Q2 of the semiconductor device 10E can be turned on to adjust the resistors R1 and R1A. In this case, the adjustment effect of the resistance value can be adjusted to 1 / 2ΔR, ΔR, 3 / 2ΔR, and so on, with a resolution as fine as 1 / 2ΔR. Furthermore, by increasing the number of resistors R1 connected in parallel to three or four, the resolution can be further improved to 1 / 3ΔR or 1 / 4ΔR.

[0199] (Embodiment 21) Fig. 32 is a circuit diagram showing a configuration example of a semiconductor device 100G according to embodiment 21. The semiconductor device 100G in Fig. 32 is a configuration example when used in a digital circuit, and differs from the semiconductor device 100B in Fig. 10 in the following points. (1) The number of semiconductor device groups is the same at three, but the number of semiconductor devices in the first semiconductor device group is four. (2) The semiconductor device 100G includes semiconductor device groups G31, G32, and G33. (3) The semiconductor device group G31 includes four semiconductor devices 10-1 to 10-4, the semiconductor device group G32 includes two semiconductor devices 10-5 to 10-6, and the semiconductor device group G33 includes one semiconductor device 10-7. (4) A connecting resistor R2 is provided between the resistors R1 of the semiconductor devices 10 adjacent to each other.

[0200] According to the semiconductor device 100G configured as described above, the resistance adjustment effect can be expressed in octal numbers, which can be used in a wider range of applications as a circuit for expressing binary numbers in digital circuits.

[0201] In Figure 32, (1) By setting only the switch control signal Sc1 input to the pad P11 to the H level, the resistance values ​​of the four resistors R1 of the semiconductor devices 10-1 to 10-4 can be adjusted. (2) By setting only the switch control signal Sc2 input to the pad P12 to the H level, the resistance values ​​of the two resistors R1 of the semiconductor devices 10-5 and 10-6 can be adjusted. (3) By setting only the switch control signal Sc3 input to the pad P13 to the H level, the resistance value of one resistor R1 of the semiconductor device 10-7 can be adjusted.

[0202] As described above, according to the twenty-first embodiment, by standardizing a plurality of switch control signals, pads can be standardized, and the chip area of ​​the semiconductor device 100G can be reduced compared to a semiconductor device that does not share pads. In addition, any resistor R1 can be selected by the switch control signal.

[0203] Here, when the resistance adjustment amount of one resistor R1 is ΔR, the resistance adjustment effect can be expressed in eight ways as shown in the table below.

[0204] [Table 2]

[0205] (Effects of the embodiment and modifications) Therefore, the semiconductor device and voltage detection circuit according to the embodiment and the modified example have the following unique effects. (1) One or more resistors and two or more switches that can be turned on and off simultaneously are arranged between two terminals, allowing the flow of current or the application of voltage to the resistors to be selected. (2) The pad is pulled out to the outside, allowing current to flow directly into the resistor or voltage to be applied directly to the resistor. (3) By containing impurities in the resistor, the resistance value can be controlled by the concentration of impurities, and the resistance value can be adjusted by applying a pulse of current or voltage. (4) The resistance value can be changed by applying a current or voltage pulse, which contributes to improving the accuracy of packaged semiconductor devices. (5) The resistor through which current flows can be selected with a switch, and a resistor that changes when current flows in or when a voltage is applied can be selected, and conversely, a resistor that does not change can be selected. (6) The voltage applied between the two pads can be continuous or intermittent, and the resistance value to be adjusted can be controlled.

[0206] Furthermore, the aspects of the invention relating to each embodiment group will be explained below. The aspects of the invention relating to the first embodiment group are as set forth in the claims. The clauses of the aspects of the invention corresponding to the claims are called "aspect clauses," and are assigned consecutive numbers for each embodiment group. In addition, the representative drawing numbers corresponding to the aspect clauses are assigned.

[0207] (Aspects of the invention related to the first embodiment group) The aspects of the "semiconductor device" according to the invention in the first embodiment group are as follows.

[0208] [Aspect 1] (Figure 1) At least one first resistor connected between two terminals, the resistance value of which can be changed by applying a voltage from a power supply or by passing a current therethrough; a pair of switch elements respectively connected between both ends of each of the first resistors and the power supply, the pair of switch elements being simultaneously turned on and off based on a predetermined switch control signal; A semiconductor device comprising:

[0209] [Aspect 2] (Figure 1) Each of the first resistors is formed of polycrystalline silicon containing one or more types of impurities. Item 1. The semiconductor device according to item 1.

[0210] [Aspect 3] (Figure 1) the pair of switch elements are provided to select the first resistor based on the switch control signal when a resistance value is changed by applying a voltage or flowing a current from the power supply; Item 1. The semiconductor device according to item 1.

[0211] [Aspect 4] (Figure 30) a second resistor connected in parallel to the first resistor, The resistance value of the second resistor can be changed by applying a voltage from the power supply or by passing a current therethrough. Item 1. The semiconductor device according to item 1.

[0212] [Embodiment 5] (Figure 30) the pair of switch elements are provided to select the first resistor and the second resistor based on the switch control signal when a resistance value is changed by applying a voltage or flowing a current from the power supply; 5. The semiconductor device according to claim 4.

[0213] [Aspect 6] (Figure 1) The two terminals are two pads for leading out to the outside of the chip of the semiconductor device. The semiconductor device according to any one of the first to fifth aspects.

[0214] [Embodiment 7] (Fig. 16, Fig. 17) The power supply applies or supplies a predetermined current or a predetermined voltage to the first resistor continuously or intermittently. The semiconductor device according to any one of the first to fifth aspects.

[0215] [Embodiment 8] (Figure 9) A semiconductor device including a plurality of first resistors connected in series with each other, The plurality of first resistors further includes a link resistor having a resistance value greater than a resistance value of each of the first resistors, the link resistor being connected between a pair of first resistors adjacent to each other. The semiconductor device according to any one of the first to fifth aspects.

[0216] [Aspect 9] (Fig. 10) A semiconductor device including a plurality of first resistors connected in series with each other, The plurality of first resistors are divided into groups each including a different number of first resistors; the first resistors of each group are connected in series; the switch control signals for the pair of switch elements in each group are identical to each other; The semiconductor device according to any one of the first to fifth aspects.

[0217] [Embodiment 10] (Fig. 10) The plurality of first resistors further includes a link resistor having a resistance value greater than a resistance value of each of the first resistors, the link resistor being connected between a pair of first resistors adjacent to each other. 10. The semiconductor device according to claim 9.

[0218] [Embodiment 11] (Fig. 10, Fig. 12) The plurality of first resistors further includes a third resistor connected between a pair of adjacent first resistors, The resistance value of the third resistor can be changed by applying a voltage from the power supply or by passing a current therethrough. 10. The semiconductor device according to claim 9.

[0219] [Embodiment 12] (Figure 32) The number of first resistors in each group is a power of two, and the number of first resistors in each group is different from each other. 10. The semiconductor device according to claim 9.

[0220] [Embodiment 13] (Figure 28) A plurality of semiconductor devices according to any one of aspects 1 to 5 are provided, The plurality of semiconductor devices are connected in series. Semiconductor device.

[0221] (Aspects of the invention related to the second embodiment group) The "voltage detection circuit" according to the aspect of the invention in the second embodiment group is as follows.

[0222] [Embodiment 1] (Figs. 18 and 19) At least one first resistor connected between two terminals, the resistance value of which can be changed by applying a voltage from a power supply or by passing a current therethrough; a pair of first switch elements respectively connected between both ends of each of the first resistors and the power supply, the pair of first switch elements being simultaneously turned on and off based on a predetermined first switch control signal, The voltage detection circuit a series circuit connected between a first power supply voltage and a second power supply voltage lower than the first power supply voltage, the series circuit including a variable resistor, a pair of voltage dividing resistors, the at least one first resistor, and a second switch element connected in series; a comparator that compares a divided voltage obtained by dividing the voltage by the pair of voltage dividing resistors with a predetermined threshold reference voltage and outputs a voltage detection signal when the divided voltage is equal to or greater than the threshold reference voltage; the second switch element is turned on and off simultaneously with the first switch element based on the first switch control signal; Voltage detection circuit.

[0223] [Aspect 2] (Figure 20) an operational amplifier is provided instead of the comparator; the first power supply voltage is the voltage of the output terminal of the operational amplifier; 2. The voltage detection circuit according to claim 1.

[0224] [Embodiment 3] (Figs. 18 and 19) the second power supply voltage is a ground voltage; 2. The voltage detection circuit according to claim 1.

[0225] [Embodiment 4] (Figs. 18 and 19) Each of the first resistors is formed of polycrystalline silicon containing a predetermined impurity. 2. The voltage detection circuit according to claim 1.

[0226] [Embodiment 5] (Figs. 18 and 19) the pair of first switch elements are provided to select the first resistor based on the first switch control signal when a resistance value is changed by applying a voltage or flowing a current from the power supply; 2. The voltage detection circuit according to claim 1.

[0227] [Aspect 6] (Figure 1) The two terminals are two pads for drawing out the voltage detection circuit chip. The voltage detection circuit according to any one of aspects 1 to 5.

[0228] [Embodiment 7] (Fig. 16, Fig. 17) The power supply applies or supplies a predetermined current or a predetermined voltage to the first resistor continuously or intermittently. The voltage detection circuit according to any one of aspects 1 to 5.

[0229] [Embodiment 8] (Figure 9) A voltage detection circuit including a plurality of first resistors connected in series with each other, The plurality of first resistors further includes a link resistor having a resistance value greater than a resistance value of each of the first resistors, the link resistor being connected between a pair of first resistors adjacent to each other. The voltage detection circuit according to any one of aspects 1 to 5.

[0230] [Aspect 9] (Fig. 10) A voltage detection circuit including a plurality of first resistors connected in series with each other, The plurality of first resistors are divided into groups each including a different number of first resistors; the first resistors of each group are connected in series; the switch control signals for the pair of switch elements in each group are identical to each other; The voltage detection circuit according to any one of aspects 1 to 5.

[0231] [Embodiment 10] (Fig. 10) The plurality of first resistors further includes a link resistor having a resistance value greater than a resistance value of each of the first resistors, the link resistor being connected between a pair of first resistors adjacent to each other. 10. The voltage detection circuit according to aspect 9.

[0232] [Embodiment 11] (Fig. 10, Fig. 12) The plurality of first resistors further includes a third resistor connected between a pair of adjacent first resistors, The resistance value of the third resistor can be changed by applying a voltage from the power supply or by passing a current therethrough. 10. The voltage detection circuit according to aspect 9.

[0233] [Embodiment 12] (Figure 32) The number of first resistors in each group is a power of two, and the number of first resistors in each group is different from each other. 10. The voltage detection circuit according to aspect 9.

[0234] (Aspects of the invention related to the third embodiment group) The "resistance value adjusting device" according to the third embodiment group of the invention has the following features.

[0235] [Embodiment 1] (Figs. 23, 24, and 28) At least one first resistor connected between two terminals, the resistance value of which can be changed by applying a voltage from a power supply or by passing a current therethrough; a resistance value adjusting device including a semiconductor device including a pair of first switch elements respectively connected between both ends of each of the first resistors and the power supply, the pair of first switch elements being simultaneously turned on and off based on a predetermined first switch control signal, the resistance value adjusting device adjusting a resistance value of the at least one first resistor, The resistance value adjusting device is a series circuit connected between a first power supply voltage and a second power supply voltage lower than the first power supply voltage, the series circuit including a variable resistor, a pair of voltage dividing resistors, the at least one first resistor, and a second switch element connected in series; a comparator that compares a divided voltage obtained by dividing the voltage by the pair of voltage dividing resistors with a predetermined threshold reference voltage, and outputs a voltage detection signal when the divided voltage is equal to or greater than the threshold reference voltage; a control circuit that, when the voltage detection signal is output when the first power supply voltage is changed, measures the voltage of the power supply and the divided voltage, calculates an amount of change in resistance of the at least one first resistor based on the measured power supply voltage and the divided voltage when the resistance of the at least one first resistor is set to a desired value, and controls the resistance of the at least one first resistor to be adjusted to the desired value based on the calculated amount of change in resistance; the second switch element is turned on and off simultaneously with the first switch element based on the first switch control signal; Resistance adjustment device.

[0236] [Aspect 2] (Figure 26) an operational amplifier is provided instead of the comparator; The output terminal of the operational amplifier is connected to the input terminal of the operational amplifier to form a voltage follower amplifier circuit, and the operational amplifier outputs a predetermined reference voltage. Item 1. The resistance adjusting device according to item 1.

[0237] [Embodiment 3] (Figs. 23 to 26) the second power supply voltage is a ground voltage; Item 1. The resistance adjusting device according to item 1.

[0238] [Embodiment 4] (Figs. 18 and 19) Each of the first resistors is formed of polycrystalline silicon containing a predetermined impurity. Item 1. The resistance adjusting device according to item 1.

[0239] [Embodiment 5] (Figs. 18 and 19) the pair of first switch elements are provided to select the first resistor based on the first switch control signal when a resistance value is changed by applying a voltage or flowing a current from the power supply; Item 1. The resistance adjusting device according to item 1.

[0240] [Aspect 6] (Figure 1) The two terminals are two pads for leading out to the outside of the chip of the resistance value adjusting device. The resistance adjusting device according to any one of aspects 1 to 5.

[0241] [Embodiment 7] (Fig. 16, Fig. 17) The power supply applies or supplies a predetermined current or a predetermined voltage to the first resistor continuously or intermittently. The resistance adjusting device according to any one of aspects 1 to 5.

[0242] [Embodiment 8] (Figure 9) A resistance value adjusting device including a plurality of first resistors connected in series with each other, The plurality of first resistors further includes a link resistor having a resistance value greater than a resistance value of each of the first resistors, the link resistor being connected between a pair of first resistors adjacent to each other. The resistance adjusting device according to any one of aspects 1 to 5.

[0243] [Aspect 9] (Fig. 10) A resistance value adjusting device including a plurality of first resistors connected in series with each other, The plurality of first resistors are divided into groups each including a different number of first resistors; the first resistors of each group are connected in series; the switch control signals for the pair of switch elements in each group are identical to each other; The resistance adjusting device according to any one of aspects 1 to 5.

[0244] [Embodiment 10] (Fig. 10) The plurality of first resistors further includes a link resistor having a resistance value greater than a resistance value of each of the first resistors, the link resistor being connected between a pair of first resistors adjacent to each other. 10. The resistance adjusting device according to aspect 9.

[0245] [Embodiment 11] (Fig. 10, Fig. 12) The plurality of first resistors further includes a third resistor connected between a pair of adjacent first resistors, The resistance value of the third resistor can be changed by applying a voltage from the power supply or by passing a current therethrough. 10. The resistance adjusting device according to aspect 9.

[0246] [Embodiment 12] (Figure 32) The number of first resistors in each group is a power of two, and the number of first resistors in each group is different from each other. 10. The resistance adjusting device according to aspect 9. [Explanation of symbols]

[0247] 1. Semiconductor wafer 2. Semiconductor chips 3 Pad 10, 10A to 10F, 10-1 to 10-6 Resistor semiconductor device (semiconductor device) 20, 20A~20C Test mode control circuit 21 Pulse signal generator (PSG) 25 Internal circuit 26 Delay Circuit 30, 30A~30C Semiconductor device circuit 31 Comparator 32 operational amplifiers 40~43 DC voltage source 45 Reference voltage source 50~54, 51A, 51B, 52A, 52B, 53A Via conductor 60~64 Wiring conductor 70~76 Low resistance polysilicon 80~83 High resistance polysilicon 90 Tester Equipment 91 Controller 92 Voltage Sensor 100,100A~100G Resistor semiconductor device (semiconductor device) 110 Power supply 120, 120A to 120F voltage detection circuit INV1~INV4 inverters G1~G33 Semiconductor Equipment Group P1,P2 nodes P10~P32, P33, P34, P40 Pads Q1 to Q4, Q2A MOS transistors R1, R1-1 to R1-3, R1A, R1B, R1C Polycrystalline silicon resistors (resistors) R2 connection resistance R11, R13 Voltage dividing resistors (reference resistors) R12 Adjustment variable resistor (variable resistor) SW1 to SW5 switch elements

Claims

1. At least one first resistor connected between two terminals, the resistance value of which can be changed by applying a voltage from a power source or by passing a current therethrough; a pair of switch elements respectively connected between both ends of each of the first resistors and the power source, the pair of switch elements being simultaneously turned on and off based on a predetermined switch control signal; A semiconductor device comprising:

2. Each of the first resistors is formed of polycrystalline silicon containing one or more types of impurities. The semiconductor device according to claim 1 .

3. A semiconductor device according to claim 1 or 2, The plurality of semiconductor devices are connected in series. Semiconductor device.

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