Information processing device and information processing method

Abstract

To provide an information processing device configured to synchronize the progress of data transferring means with the timing of the processing by calculation processing means.SOLUTION: An information processing device comprises: external bus connecting means for connecting data transferring means, local memory means, and command list processing means, to external memory means; the data transferring means for transferring data, which are conditions for calculation stored in the external memory means, to the local memory means; the local memory means for storing data and a list of commands; the command list processing means for generating the commands that cause the calculation processing means to execute calculations, by reading the list of commands from the local memory means while data is being transferred from the external memory means to the local memory means; and the calculation processing means for executing calculations and processing the data.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to an information processing device and an information processing method. [Background technology]

[0002] Patent Document 1 describes an image processing device that improves the speed of image data processing. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-97066 Summary of the Invention [Problem to be solved by the invention]

[0004] However, although the image processing device described in Patent Document 1 transfers data from a main memory to a local memory, it does not describe a method for synchronizing the progress of the transfer with the timing of processing by the arithmetic processing device. Therefore, an object of the present disclosure is to provide an information processing device that synchronizes the progress of a data transfer means with the timing of processing by the arithmetic processing means.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, the information processing device is an information processing device that reads a list of commands from a local memory means and generates commands that cause a processing means to execute a calculation while data is being transferred from an external memory means to the local memory means. [Effects of the Invention]

[0007] According to the embodiment, the progress of the data transfer means and the timing of the processing by the arithmetic processing means can be synchronized, thereby improving processing performance. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing a configuration of a related information processing device. [Figure 2] 10A and 10B are diagrams illustrating an example of performance improvement and an increase in startup waiting time due to an increase in transfer size. [Figure 3] 1 is a block diagram showing a configuration of an information processing device according to a first embodiment; [Figure 4] FIG. 2 is a diagram illustrating an example of performance improvement achieved by the information processing device according to the first embodiment. [Figure 5] FIG. 2 is a diagram illustrating a configuration of functional blocks of the information processing device according to the first embodiment. [Figure 6] FIG. 2 is a detailed diagram of functional blocks of a command list processing means according to the first embodiment. [Figure 7] FIG. 2 is a detailed diagram of functional blocks of a data transfer means according to the first embodiment. [Figure 8] FIG. 10 is a block diagram showing a configuration of an information processing device according to a second embodiment. [Figure 9] FIG. 10 is a block diagram showing a configuration of an information processing device according to a third embodiment. [Figure 10] FIG. 10 is a block diagram showing a configuration of an information processing device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. Furthermore, each element shown in the drawings as a functional block performing various processes can be configured, for example, in hardware terms by a CPU (Central Processing Unit), memory, or other circuits, and in software terms by a program loaded into memory. Therefore, these functional blocks can be realized by hardware, software running on hardware, or a combination thereof. In addition, the same elements are designated by the same reference numerals in each drawing, and redundant explanations are omitted as necessary.

[0010] The above-described program can be stored and supplied to a computer using various types of non-transitory computer-readable media. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic storage media (e.g., flexible disks, magnetic tapes, hard disk drives), magneto-optical storage media (e.g., magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / Ws, and semiconductor memories (e.g., mask ROMs, PROMs (Programmable ROMs), EPROMs (Erasable PROMs), flash ROMs, and RAMs (Random Access Memory)). The program can also be supplied to a computer by various types of transitory computer-readable media. Examples of transitory computer-readable media include electrical signals, optical signals, and electromagnetic waves. The transitory computer-readable media can supply the program to a computer via a wired communication path such as an electric wire or optical fiber, or via a wireless communication path.

[0011] (Description of related information processing devices) Fig. 1 is a block diagram showing the configuration of a related information processing device. Fig. 2 is a diagram showing an example of performance improvement and increased startup wait time due to an increase in transfer size. The related information processing device will be described with reference to Figs. 1 and 2.

[0012] In order to efficiently execute processes such as object detection and area division (segmentation), which are necessary for autonomous driving, on an in-vehicle SoC (System On Chip), it is common practice to equip the SoC with an accelerator for AI processing.

[0013] As the scale of SoCs increases, the speed difference between external memory such as DDRx-SDRAM (Double Data Rate-Synchronous Dynamic Random Access Memory) and the SoC's internal memory becomes larger. Therefore, in order to improve the performance of information processing devices, it is necessary to improve the efficiency of data transfer with external memory.

[0014] When reading from external memory is necessary, transferring as much data as possible at once from DDRx-SDRAM improves memory bandwidth utilization and performance. However, because the AI ​​accelerator must wait for data transfer to internal memory to complete before starting processing, the waiting time until processing starts increases. The same problem occurs with data transfers between the AI ​​accelerator's L2 memory and L1 memory.

[0015] As shown in FIG. 1, the related information processing device 100 includes a memory control device 104, a local memory 103, a main memory 102, a task control device 101, and processing units 105a to 105d.

[0016] The memory control device 104 transfers the required amount of data from the main memory 102 to the high-speed local memory 103. The arithmetic processing devices 105a to 105d access the local memory 103 and perform the required image processing. If there is overlap in the data referenced by the arithmetic processing devices 105a to 105d, the memory control device 104 reuses the overlapping portion. As a result, the memory control device 104 reduces the amount of data transferred from the main memory.

[0017] The memory control device 104 transfers data from the main memory 102 to the local memory 103, but does not synchronize the progress of the transfer with the timing of the processing of the arithmetic processing devices 105a to 105d. Therefore, the arithmetic processing devices 105a to 105d start processing only after all the data used in the tasks assigned to those arithmetic processing devices 105a to 105d by the task control device 101 has been transferred to the local memory 103.

[0018] As shown in Figure 2, when the transfer size is doubled when reading input tensors and weights of a neural network from external memory in processes such as image recognition, the latency time for one transfer is eliminated, resulting in an overall improvement in performance. However, the related information processing device must wait for the data transfer to the internal memory to be completed before starting processing, which increases the data transfer time and startup wait time.

[0019] (Description of Information Processing Device According to First Embodiment) FIG. 3 is a block diagram showing the configuration of an information processing device according to the first embodiment. FIG. 4 is a diagram showing an example of performance improvement achieved by the information processing device according to the first embodiment. FIG. 5 is a diagram showing the configuration of functional blocks of the information processing device according to the first embodiment. FIG. 6 is a detailed diagram of functional blocks of a command list processing means according to the first embodiment. FIG. 7 is a detailed diagram of functional blocks of a data transfer means according to the first embodiment. The information processing device according to the first embodiment will be described with reference to FIGS. 3 to 7.

[0020] 3, the information processing device 300 according to the first embodiment is, for example, an AI (Artificial Intelligence) accelerator. The AI ​​accelerator includes an Acc core 305, which is a calculation means, a local memory 303, a DMAC (Direct Memory Access Controller) 302, a transfer size monitor 306, a command list processor 304, and a bus bridge 301.

[0021] The information processing device 300 adds a transfer size monitor 306 to the DMAC 302, and notifies the command list processor 304 of an event each time a transfer of a set size is completed. The command list processor 304 starts the Acc core 305 if the Acc core 305 is free, and if not, waits until it becomes free before starting the Acc core 305.

[0022] As shown in the upper diagram of Figure 4, in the related information processing device, it took time from the request to starting up the arithmetic unit. Therefore, as shown in the lower diagram of Figure 4, the command list processor 304 receives an event and starts up the arithmetic unit every time a transfer of a set size is completed, making it possible to start up the arithmetic unit during data transfer. Therefore, compared to the upper diagram of Figure 4, the lower diagram of Figure 4 reduces the overall processing time and improves performance.

[0023] As shown in FIG. 5, the information processing device 300 according to the first embodiment includes an arithmetic processing unit 505 , a local memory unit 503 , a data transfer unit 502 , a command list processing unit 504 , and an external bus connection unit 501 .

[0024] The arithmetic processing means 505 executes calculations and processes data. The arithmetic processing means 505 is, for example, the Acc core 305. The arithmetic processing means 505 performs calculations required for AI processing and the like. The calculations to be performed are specified by commands sent from the command list processing means 504. The arithmetic processing means 505 reads data used in calculations and writes the results to the local memory means 503. Furthermore, when processing is completed, the arithmetic processing means 505 notifies an event to the command list processing means 504.

[0025] The local memory means 503 stores data and a list of commands. The local memory means 503 is, for example, the local memory 303. The local memory means 503 is a memory that can be accessed at high speed from the arithmetic processing means 505. The local memory means 503 can also be accessed from the data transfer means 502, the external bus connection means 501, and the command list processing means 504.

[0026] The data transfer means 502 transfers data, which are the conditions for the calculations, stored in the external memory means to the local memory means 503. The data transfer means 502 is, for example, the DMAC 302. In response to a command from the command list processing means 504, the data transfer means 502 reads data to be used by the calculation processing means 505 from the external memory means, such as a DDRx-SDRAM, connected to the SoC via the external bus connection means 501. The data transfer means 502 also writes the processing results of the calculation processing means 505 to the external memory means connected to the SoC.

[0027] The data transfer means 502 includes a transfer size monitoring means, for example, the transfer size monitor 306. The transfer size monitoring means is part of the data transfer means 502. The transfer size monitoring means notifies the command list processing means 504 of an event every time the data transfer means 502 completes a transfer of a specified size.

[0028] The external bus connection means 501 connects the data transfer means 502, the local memory means 503, and the command list processing means 504 to the external memory means. The external bus connection means 501 is, for example, the bus bridge 301. The external bus connection means 501 accesses the local memory means 503, the data transfer means 502, and the command list processing means 504 in response to an access request from the SoC system bus. The external bus connection means 501 also accesses the SoC system bus in response to access requests from the data transfer means 502 and the command list processing means 504.

[0029] The command list processing means 504 reads a list of commands from the local memory means 503, and generates commands that cause the arithmetic processing means 505 to execute operations while data is being transferred from the external memory means to the local memory means 503. The command list processing means 504 is, for example, the command list processor 304. The command list processing means 504 reads and executes the list of commands stored in the local memory means 503. The command list processing means 504 sends commands that determine the operations of the arithmetic processing means 505 and the data transfer means 502. The command list processing means 504 also receives events from the arithmetic processing means 505 and the data transfer means 502, and uses these events to determine the conditions for generating commands.

[0030] Fig. 6 is a block diagram showing detailed functions of the command list processing means 504 of Fig. 5. As shown in Fig. 6, the command list processing means 504 includes a command executable condition determination means 601, a command list reading means 602, a command list execution control command generation means 603, an arithmetic processing command generation means 604, a data transfer command generation means 605, an arithmetic processing command output means 606, and a data transfer command output means 607.

[0031] The command executable condition determination means 601 determines the necessary conditions for each command to be determined, and instructs the arithmetic operation command output means 606 and the data transfer command output means 607 to output the target command. For example, when an event indicating the completion of transfer of a certain amount of data is notified from the data transfer means 502, the command executable condition determination means 601 instructs the arithmetic operation command output means 606 to issue a command to execute arithmetic processing. When an event indicating the completion of processing is notified from the arithmetic processing means 505, the command executable condition determination means 601 instructs the data transfer command output means 607 to issue a command to transfer data.

[0032] Furthermore, in the case of a command list execution control command, the command executable condition determination means 601 instructs the command list reading means 602 to change the command list reading operation. The change in operation is, for example, a change in the command list reading address.

[0033] Fig. 7 is a block diagram showing detailed functions of the data transfer means 502 in Fig. 5. As shown in Fig. 7, the data transfer means 502 includes an event notification data size determination means 701, an external bus side read transfer execution means 702, a data transfer command input means 703, an external bus side write transfer execution means 704, a read transfer data size counting means 705, a transfer data temporary storage means 706, a write transfer data size counting means 707, a local memory side read transfer execution means 708, a local memory side write transfer execution means 709, and an event notification means 710.

[0034] The read transfer data size counting means 705 measures the amount of data from the external bus connection means 501. The event notification data size determination means 701 acquires the amount of data from the read transfer data size counting means 705, and when it determines that the amount of data has reached a certain amount, the event notification means 710 notifies the command list processing means 504 of the event.

[0035] In this way, the event notification data size determination means 701 monitors the data transfer completion size on the read or write side according to the specified conditions. If the current transfer completion size meets the event notification conditions input in advance as part of the data transfer command, it notifies the command list processing means 504 using the event notification means 710.

[0036] In the first embodiment, a transfer size monitor 306 is built into the DMAC 302, which transfers data from an external memory to the local memory 303 via the SoC system bus and bus bridge 301. The transfer size monitor 306 detects that the data required by the Acc core 305 for one unit of processing has been transferred to the local memory 303, without waiting for the completion of a series of transfers by the DMAC 302, and notifies the command list processor 304. The command list processor 304 can instruct the Acc core 305 to start processing.

[0037] In this way, the technology of the first embodiment allows the Acc core 305 to start processing earlier than related technologies. For example, when the Acc core 305 processes two units of data, the DMAC 302 can advance the start of the Acc core 305's processing by the time it takes from the completion of the transfer of the first unit to the completion of the transfer of the remaining unit. This advancement shortens the overall processing time by the amount equivalent to the shorter of the processing time for one unit of data by the Acc core 305 and the time it takes to complete the transfer of the remaining unit to the local memory 303 after the transfer of one unit is completed, thereby making it possible to improve processing performance.

[0038] The above configuration provides an information processing device and an information processing method that synchronize the progress of the data transfer means with the timing of the processing of the arithmetic processing means.

[0039] (Description of Information Processing Device According to Second Embodiment) 8 is a block diagram showing a configuration of an information processing device according to the second embodiment. The information processing device according to the second embodiment will be described with reference to FIG.

[0040] The information processing device 800 according to the second embodiment differs from the information processing device 300 according to the first embodiment in that the information processing device 800 has a plurality of Acc cores 305. As shown in Fig. 8, the information processing device 800 according to the second embodiment has a plurality of Acc cores 305. That is, the arithmetic processing means 505 of the information processing device 800 is configured with multiple cores.

[0041] The command list processor 304 issues commands to and receives events from each Acc core 305 individually. Therefore, the information processing device 800 can execute one part of a process on one core while executing another part of the process on another core. This allows processing that makes efficient use of multiple cores.

[0042] (Description of Information Processing Device According to Third Embodiment) 9 is a block diagram showing a configuration of an information processing device according to the third embodiment. The information processing device according to the third embodiment will be described with reference to FIG.

[0043] The information processing device 900 of the third embodiment differs from the information processing device 300 of the first embodiment in that it has a local memory 901 in the Acc core 305 and further has a DMAC 902 which has a transfer size monitor 903 for data transfer between the local memory 303 and the local memory 901.

[0044] Local memory 901 is assumed to be L1 memory, and local memory 303 is assumed to be L2 memory. Information processing device 900 is equipped with DMAC 902, which performs transfers between L1 memory and L2 memory, and transfer size monitor 903, and performs control similar to that of embodiment 1. That is, arithmetic processing means 505 is equipped with second local memory means. Also, second data transfer means, which is DMAC 902 equipped with second transfer size monitoring means, which is transfer size monitor 903, detects that one unit of data that arithmetic processing means 505 can operate on has been transferred from local memory means 503 to second local memory means. At that time, command list processing means 504 generates a command to cause arithmetic processing means 505 to perform an operation.

[0045] In this way, by hierarchizing the local memory, the processing time can be reduced for each layer in the same way as in the first embodiment, and a significant time reduction effect can be obtained for the entire layer.

[0046] (Description of Information Processing Device According to Fourth Embodiment) 10 is a block diagram showing a configuration of an information processing device according to the fourth embodiment. The information processing device according to the fourth embodiment will be described with reference to FIG.

[0047] The information processing device 1000 according to the fourth embodiment differs from the information processing device 300 according to the first embodiment in that it includes a plurality of DMACs 302 each including a transfer size monitor 306 .

[0048] That is, it is provided with a plurality of data transfer means 502. Furthermore, each of the plurality of data transfer means 502 is provided with transfer size monitoring means. The transfer size monitoring means detects that one unit of data that can be calculated by the arithmetic processing means 505 has been transferred from the external memory means to the local memory means 503. At that time, the command list processing means 504 generates a command to cause the arithmetic processing means 505 to execute the calculation.

[0049] The command list processor 304 issues commands individually to each of the multiple DMACs 302 and receives events individually. This allows the processing time to be reduced even when the processing in the Acc core 305 is an operation that uses multiple inputs by starting the Acc core 305 after confirming the completion of data transfer for the unit required for one processing for each input.

[0050] (Other embodiments) In addition to using the transfer size monitor 306 of the first embodiment, a command list processor 304 can be used. For transfers between the external memory and the local memory 303, a command list is used that includes a command sequence divided into a plurality of consecutive transfer commands that transfer a size equal to or larger than the unit amount required for processing by the Acc core 305. Furthermore, the bus bridge 301 is equipped with a function that concatenates a plurality of internal transfer requests with the same attribute (reader / writer, privilege level, optimization mode, etc.) for consecutive addresses, converts them into a transfer request of a larger size, and then outputs the concatenated request to the external bus.

[0051] That is, the command list processing means 504 rearranges and concatenates a plurality of transfer commands, each of which transfers a size equal to or larger than one unit of data that the arithmetic processing means 505 can calculate, into a plurality of transfer commands of the same attribute for consecutive addresses within the local memory means 503. The command list processing means 504 issues a transfer command to request the external bus connection means 501 to transfer data. The command list processing means 504 generates a command for causing the arithmetic processing means 505 to execute calculations when the transfer of the required amount of data to the local memory means 503 is complete. In this way, the Acc core 305 can be started when the transfer of the required amount of data is complete, without waiting for the completion of the entire transfer, as in the case where the transfer size monitor 306 is used. In this case, the notification of the completion of each divided transfer command corresponds to the timing of the notification by the transfer size monitor 306 in the first embodiment.

[0052] In addition to using the transfer size monitor 306 of the first embodiment, a mechanism for determining the access range may be provided in the local memory 303 to monitor the progress of the transfer. The local memory 303 notifies the command list processor 304 of an event when a portion of the data transfer is completed. That is, the local memory means 503 is provided with a mechanism for determining the access range. Then, when the mechanism for determining the access range detects that one unit of data that the arithmetic processing means 505 can operate on has been transferred from the external memory means to the local memory means 503, the command list processing means 504 generates a command to cause the arithmetic processing means 505 to execute the operation. In this way, the same effect as when the transfer size monitor 306 is provided in the DMAC 302 can be obtained.

[0053] The information processing device 300 according to the first embodiment may generate an event at the progress of a predetermined process other than when the process of the Acc core 305 ends. In this way, the DMAC 302 can start transferring processed data before the process of the Acc core 305 ends. That is, the command list processing means 504 generates a command to start transferring the data being processed from the local memory means 503 to the external memory means while the arithmetic processing means 505 is performing an operation. This reduces the processing time required for the DMAC to transfer data from the local memory 303 to the external memory after the processing result of the Acc core 305 has been written to the local memory 303.

[0054] In the fourth embodiment, instead of installing multiple DMACs 302, two or more pairs of source and destination data may be specified within a single DMAC 302, and each pair may be transferred in a separately specified order. Furthermore, for each pair, the amount of data to be transferred each time its turn comes around is independently specified. That is, the data transfer means 502 specifies two or more pairs of source and destination data, divides the data transfer for each pair, and transfers the data in order, independently specifying the amount of data to be divided for each pair. This prevents uneven progress of the overall transfer, which would otherwise reduce the processing time, even when there are differences in the amount of data among multiple inputs, as in the third embodiment. For example, if image data A is 500 MB and image data B is 250 MB, uneven progress of the transfer can be prevented by transferring A 50 MB at a time and B 25 MB at a time.

[0055] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible within the scope of the gist of the invention. [Explanation of symbols]

[0056] 100 Information processing device, 300 Information processing device, 301 Bus bridge, 302 DMAC, 303 Local memory, 304 Command list processor, 305 Acc core, 306 Transfer size monitor, 501 External bus connection means, 502 Data transfer means, 503 Local memory means, 504 Command list processing means, 505 Arithmetic processing means, 601 Command executable condition determination means, 602 Command list reading means, 603 Command list execution control command generation means, 604 Arithmetic processing command generation means, 605 Data transfer command generation means, 606 Arithmetic processing command output means, 607 Data transfer command output means, 701 Event notification data size determination means, 702 External bus side read transfer execution means, 703 Data transfer command input means, 704 External bus side write transfer execution means, 705 Read transfer data size counting means, 706 Transfer data temporary storage means, 707 Write transfer data size counting means, 708 Local memory side read transfer execution means, 709 local memory side write transfer execution means, 710 event notification means, 800 information processing device, 900 information processing device, 901 local memory, 902 DMAC, 903 transfer size monitor, 1000 information processing device

Claims

1. an external bus connection means for connecting the data transfer means, the local memory means, and the command list processing means to the external memory means; said data transfer means for transferring data, which are conditions for calculations, stored in said external memory means to said local memory means; said local memory means for storing said list of data and commands; said command list processing means for reading said list of commands from said local memory means and generating said commands for causing said processing means to execute operations while said data is being transferred from said external memory means to said local memory means; and the arithmetic processing means for executing an operation and processing the data.

2. the data transfer means includes a transfer size monitoring means; 2. The information processing device according to claim 1, wherein said command list processing means generates a command for causing said arithmetic processing means to execute an operation when said transfer size monitoring means detects that one unit of said data that can be operated on by said arithmetic processing means has been transferred from said external memory means to said local memory means.

3. 2. The information processing device according to claim 1, wherein said command list processing means rearranges and concatenates a plurality of transfer commands for transferring a size equal to or larger than one unit of data that can be operated on by said arithmetic processing means into a plurality of transfer commands of the same attribute for consecutive addresses within said local memory means, issues said transfer commands to request said external bus connection means to transfer said data, and generates a command for causing said arithmetic processing means to execute an operation when transfer of a required amount of said data to said local memory means has been completed.

4. 2. The information processing apparatus according to claim 1, wherein said command list processing means generates a command for starting transfer of said data being processed from said local memory means to said external memory means during an operation by said arithmetic processing means.

5. the arithmetic processing means is configured with a multi-core; The information processing device according to claim 1 , wherein while one core is executing a part of a process, another core is executing a part of the process.

6. the processing means includes a second local memory means; 2. The information processing device according to claim 1, wherein said command list processing means generates a command for causing said arithmetic processing means to execute an operation when second data transfer means including second transfer size monitoring means detects that one unit of data that can be operated on by said arithmetic processing means has been transferred from said local memory means to said second local memory means.

7. the local memory means includes a mechanism for determining an access range; 2. The information processing apparatus according to claim 1, wherein said command list processing means generates a command for causing said arithmetic processing means to execute an operation when said mechanism for determining access range detects that one unit of data on which said arithmetic processing means can perform an operation has been transferred from said external memory means to said local memory means.

8. a plurality of the data transfer means; each of the plurality of data transfer means includes a transfer size monitoring means; 2. The information processing device according to claim 1, wherein said command list processing means generates a command for causing said arithmetic processing means to execute an operation when said transfer size monitoring means detects that one unit of data that can be operated on by said arithmetic processing means has been transferred from said external memory means to said local memory means.

9. 2. The information processing apparatus according to claim 1, wherein said data transfer means designates two or more sets of data transfer sources and destinations, divides the data transfer of each set and transfers it in order, and independently designates the amount of data to be divided for each set.

10. The information processing device according to claim 9 , wherein the source data and the destination data are image data.

11. an external bus connection means for connecting the local memory means, the data transfer means, and the command list processing means to the external memory means; the data transfer means transfers data that are conditions for the calculation stored in the external memory means to the local memory means; said local memory means storing said list of data and commands; the command list processing means reads out the list of commands from the local memory means and generates the commands that cause the arithmetic processing means to execute an operation while data is being transferred from the external memory means to the local memory means; The information processing method, wherein the arithmetic processing means executes an operation to process the data.

12. the data transfer means includes a transfer size monitoring means; 12. The information processing method according to claim 11, wherein said command list processing means generates a command for causing said arithmetic processing means to execute an operation when said transfer size monitoring means detects that one unit of said data that can be operated on by said arithmetic processing means has been transferred from said external memory means to said local memory means.

13. 12. The information processing method according to claim 11, wherein said command list processing means rearranges and concatenates a plurality of transfer commands for transferring a size equal to or larger than one unit of data that can be operated on by said arithmetic processing means into a plurality of transfer commands of the same attribute for consecutive addresses within said local memory means, issues said transfer commands to request said external bus connection means to transfer said data, and generates a command for causing said arithmetic processing means to execute an operation when transfer of a required amount of said data to said local memory means has been completed.

14. 12. The information processing method according to claim 11, wherein the data transfer means specifies two or more sets of data sources and destinations, divides the data for each set and transfers it in order, and independently specifies the amount of data to be divided for each set.

15. The information processing method according to claim 14 , wherein the source data and the destination data are image data.

Images