Transmitting device and transmitting method

Abstract

To ensure good communication quality in data transmission using LDPC codes. [Solution] In group-wise interleaving, an LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups, with the (i+1)th bit group from the beginning of the LDPC code being bit group i, and the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code being interleaved in a predetermined order. In group-wise deinterleaving, the arrangement of the LDPC code after group-wise interleaving is restored to its original order. This technology can be applied, for example, to data transmission using LDPC codes.

Description

[Technical Field]

[0001] The present technology relates to a transmission device and a transmission method, and more particularly to a transmission device and a transmission method that can ensure good communication quality in data transmission using, for example, LDPC codes. [Background technology]

[0002] LDPC (Low Density Parity Check) codes have high error correction capabilities, and in recent years have been widely adopted in transmission systems for digital broadcasting, such as DVB (Digital Video Broadcasting)-S.2, DVB-T.2, and DVB-C.2 in Europe, and ATSC (Advanced Television Systems Committee) 3.0 in the United States (see, for example, Non-Patent Document 1).

[0003] Recent research has shown that LDPC codes, like turbo codes, can achieve performance approaching the Shannon limit as the code length is increased. LDPC codes also have the property that the minimum distance is proportional to the code length, which gives them good block error probability characteristics. Another advantage is that they rarely suffer from the so-called error floor phenomenon observed in the decoding characteristics of turbo codes and the like. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] ATSC Standard:Physical Layer Protocol(A / 322), 7 September 2016 Summary of the Invention [Problem to be solved by the invention]

[0005] In data transmission using LDPC codes, for example, the LDPC codes are converted (symbolized) into symbols for quadrature modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying), and the symbols are mapped to signal points of the quadrature modulation and transmitted.

[0006] Data transmission using LDPC codes as described above is becoming more widespread worldwide, and there is a demand for ensuring good communication (transmission) quality.

[0007] The present technology has been made in view of such circumstances, and makes it possible to ensure good communication quality in data transmission using LDPC codes. [Means for solving the problem]

[0008] The transmission device / method of the present technology includes a coding unit / step that performs LDPC coding based on a check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 4 / 16, a group-wise interleaving unit / step that performs group-wise interleaving of the LDPC code in units of 360-bit bit groups, and a mapping unit / step that maps the LDPC code to one of 16 signal points of a 16QAM 2D-NUC (Non-Uniform Constellation) in units of 4 bits, wherein the group-wise interleaving defines an (i+1)-th bit group from the beginning of the LDPC code as bit group i, and maps a sequence of bit groups 0 to 191 of the 69120-bit LDPC code to bit group i. 154, 83, 159, 153, 136, 6, 19, 73, 122, 40, 97, 144, 101, 106, 130, 174, 48, 176, 14, 27, 52, 152, 173, 63, 39, 92, 114, 98, 190, 149, 103, 160, 118, 13, 29, 51, 66, 168, 180, 23, 170, 24, 5, 157, 28, 45, 53, 68, 25, 191, 148, 139, 15, 67, 77, 100, 58, 91, 50, 131, 65, 17, 11, 123, 86, 135, 115, 120, 59, 162, 9, 189, 21, 12, 179, 178, 110, 35, 137, 3, 84, 177, 124, 186, 143, 26, 96, 80, 31, 169, 119, 33, 87, 140, 88, 171, 133, 150, 151, 72, 85, 89, 112, 126, 167, 56, 49, 187, 138, 145, 18, 32, 90, 158, 54, 104, 62, 165, 79, 1, 81, 102, 44, 61, 10, 166, 2, 116, 161, 60, 108, 142, 30, 78, 127, 111, 46, 43, 184, 163, 64, 22, 41, 156, 70, 20, 42, 182, 55, 95, 105, 132, 38, 69, 134, 74, 155, 141, 172, 57, 7, 175, 128, 75, 107, 109, 99, 147, 146, 117, 125, 185, 0, 76, 82, 129, 36, 34, 93, 188, 113, 71, 183, 121, 47, 16, 164, 4, 181, 94, 37, 8 the parity check matrix includes an A matrix at the top left of the parity check matrix, which has M1 rows and K columns and is represented by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N-K-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N-K-M1 rows and N-K-M1 columns, the predetermined value M1 is 1800, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 in the A matrix and the C matrix every 360 columns, 561 825 1718 4745 7515 13041 13466 18039 19065 21821 32596 32708 35323 36399 36450 41124 43036 43218 43363 44875 49948 56 102 1779 2427 5381 8768 15336 26473 35717 38748 39066 45002 50720 694 1150 1533 2177 5801 6610 7601 16657 18949 33472 47746 49581 50668 90 1122 1472 2085 2593 4986 8200 9175 15502 44084 46057 48546 50487 521 619 708 6915 8978 14211 17426 23058 23463 27440 29822 33443 42871 449 912 1471 8058 9344 11928 20533 20600 20737 26557 26970 27616 33791 355 700 1528 6478 9588 10790 20992 33122 34283 41295 43439 46249 47763 997 1543 1679 5874 7973 7975 11113 28275 28812 29864 35070 36864 50676 85 326 1392 4186 10855 11005 12913 19263 22984 31733 33787 37567 48173 986 1144 1508 19864 28918 29117 33609 36452 47975 48432 48842 49274 51533 437 1190 1413 3814 6695 17541 22060 25845 28431 37453 38912 44170 49231 327 1171 1204 6952 11880 16469 25058 28956 31523 36770 40189 43422 46481 123 605 619 8118 8455 19550 20529 21762 21950 28485 30946 34755 34765 113 896 971 6400 27059 33383 34537 35827 38796 40582 42594 43098 48525 162 854 1015 2938 10659 12085 13040 32772 33023 35878 49674 51060 51333 100 452 1703 1932 4208 5127 12086 14549 16084 17890 20870 41364 48498 1569 1633 1666 12957 18611 22499 38418 38719 42135 46815 48274 50947 51387 119 691 1190 2457 3865 7468 12512 30782 31811 33508 36586 41789 47426 867 1117 1666 4376 13263 13466 33524 37440 38136 39800 41454 41620 42510 378 900 1754 16303 25369 27103 28360 30958 35316 44165 46682 47016 50004 1321 1549 1570 16276 17284 19431 23482 23920 27386 27517 46253 48617 50118 37 383 1418 15792 22551 28843 36532 36718 38805 39226 45671 47712 51769 150 787 1441 17828 19396 21576 21805 24048 31868 32891 42486 43020 45492 1095 1214 1744 2445 5773 10209 11526 29604 30121 36526 45786 47376 49366 412 448 1281 11164 14501 15538 15773 23305 31960 32721 40744 45731 50269 183 626 837 4491 12237 13705 15177 15973 21266 25374 41232 44147 50529 618 1550 1594 5474 9260 16552 18122 26061 30420 30922 32661 34390 43236 135 496 757 9327 15659 20738 24327 26688 29063 38993 46155 49532 50001 64 126 1714 5561 8921 11300 12688 14454 16857 19585 20528 24107 27252 528 687 1730 9735 11737 16396 19200 33712 34271 38241 42027 44471 45581 69 646 1447 8603 19706 22153 22398 23840 24638 27254 29107 30368 41419 673 845 1285 9100 11064 14804 15425 17357 27248 31223 32410 35444 48018 124 1531 1677 3672 3673 3786 8886 9557 10003 11053 13053 22458 25413 102 1154 1758 5721 6034 14567 17772 28670 33380 34284 35356 47480 48123 48 351 760 2078 9797 22956 26120 34119 39658 41039 45237 47861 49022 254 445 841 6835 18340 19021 20053 22874 32639 36679 42004 45696 49530 16 802 903 6218 16206 22068 23049 28201 30377 33947 44358 44739 49303 153 1542 1629 7992 29900 34931 36927 38651 39981 41085 41327 50185 51484 525 1291 1765 9425 20271 31229 37444 38996 39145 41711 43188 45203 51255 2 244 1648 12321 14991 17426 18456 20126 29915 32581 38880 39516 49013 23 452 705 9414 11862 13764 18179 35458 37892 40471 46041 46494 48746 509 1201 1328 8921 9867 10947 19476 22693 32636 34301 38356 39238 51797 246 249 1390 12438 13266 24060 33628 37130 42923 43298 43709 43721 45413 117 257 748 9419 9461 11350 12790 16724 33147 34168 34683 37884 42699 619 646 740 7468 7604 8152 16296 19120 27614 27748 40170 40289 49366 914 1360 1716 10817 17672 18919 26146 29631 40903 46716 49502 51576 51657 68 702 1552 10431 10925 12856 24516 26440 30834 31179 32277 35019 44108 588 880 1524 6641 9453 9653 13679 14488 20714 25865 42217 42637 48312 6380 12240 12558 12816 21460 24206 26129 28555 41616 51767 8889 16221 21629 23476 33954 40572 43494 44666 44885 49813 16938 17727 17913 18898 21754 32515 35686 36920 39898 43560 9170 11747 14681 22874 24537 24685 26989 28947 33592 34621 2427 10241 29649 30522 37700 37789 41656 44020 49801 51268 The transmitting device / method is as follows.

[0009] The receiving device / method of the present technology includes: a coding step of performing LDPC coding based on a check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 4 / 16; a group-wise interleaving step of performing group-wise interleaving of the LDPC code in units of 360-bit bit groups; and a mapping step of mapping the LDPC code to one of 16 signal points of a 16QAM 2D-NUC (Non-Uniform Constellation) in units of 4 bits, wherein in the group-wise interleaving, the i+1-th bit group from the beginning of the LDPC code is defined as bit group i, and a sequence of bit groups 0 to 191 of the 69120-bit LDPC code is defined as bit group i. 154, 83, 159, 153, 136, 6, 19, 73, 122, 40, 97, 144, 101, 106, 130, 174, 48, 176, 14, 27, 52, 152, 173, 63, 39, 92, 114, 98, 190, 149, 103, 160, 118, 13, 29, 51, 66, 168, 180, 23, 170, 24, 5, 157, 28, 45, 53, 68, 25, 191, 148, 139, 15, 67, 77, 100, 58, 91, 50, 131, 65, 17, 11, 123, 86, 135, 115, 120, 59, 162, 9, 189, 21, 12, 179, 178, 110, 35, 137, 3, 84, 177, 124, 186, 143, 26, 96, 80, 31, 169, 119, 33, 87, 140, 88, 171, 133, 150, 151, 72, 85, 89, 112, 126, 167, 56, 49, 187, 138, 145, 18, 32, 90, 158, 54, 104, 62, 165, 79, 1, 81, 102, 44, 61, 10, 166, 2, 116, 161, 60, 108, 142, 30, 78, 127, 111, 46, 43, 184, 163, 64, 22, 41, 156, 70, 20, 42, 182, 55, 95, 105, 132, 38, 69, 134, 74, 155, 141, 172, 57, 7, 175, 128, 75, 107, 109, 99, 147, 146, 117, 125, 185, 0, 76, 82, 129, 36, 34, 93, 188, 113, 71, 183, 121, 47, 16, 164, 4, 181, 94, 37, 8 the parity check matrix includes an A matrix at the top left of the parity check matrix, which has M1 rows and K columns and is represented by a predetermined value M1 and an information length K=N×r of the LDPC code, a B matrix of a staircase structure adjacent to the right of the A matrix, which has M1 rows and M1 columns, a Z matrix which is a zero matrix adjacent to the right of the B matrix, which has M1 rows and N-K-M1 columns, a C matrix adjacent below the A matrix and the B matrix, which has N-K-M1 rows and K+M1 columns, and a D matrix which is an identity matrix adjacent to the right of the C matrix, which has N-K-M1 rows and N-K-M1 columns, the predetermined value M1 is 1800, the A matrix and the C matrix are represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table which represents positions of elements of 1 in the A matrix and the C matrix every 360 columns, 561 825 1718 4745 7515 13041 13466 18039 19065 21821 32596 32708 35323 36399 36450 41124 43036 43218 43363 44875 49948 56 102 1779 2427 5381 8768 15336 26473 35717 38748 39066 45002 50720 694 1150 1533 2177 5801 6610 7601 16657 18949 33472 47746 49581 50668 90 1122 1472 2085 2593 4986 8200 9175 15502 44084 46057 48546 50487 521 619 708 6915 8978 14211 17426 23058 23463 27440 29822 33443 42871 449 912 1471 8058 9344 11928 20533 20600 20737 26557 26970 27616 33791 355 700 1528 6478 9588 10790 20992 33122 34283 41295 43439 46249 47763 997 1543 1679 5874 7973 7975 11113 28275 28812 29864 35070 36864 50676 85 326 1392 4186 10855 11005 12913 19263 22984 31733 33787 37567 48173 986 1144 1508 19864 28918 29117 33609 36452 47975 48432 48842 49274 51533 437 1190 1413 3814 6695 17541 22060 25845 28431 37453 38912 44170 49231 327 1171 1204 6952 11880 16469 25058 28956 31523 36770 40189 43422 46481 123 605 619 8118 8455 19550 20529 21762 21950 28485 30946 34755 34765 113 896 971 6400 27059 33383 34537 35827 38796 40582 42594 43098 48525 162 854 1015 2938 10659 12085 13040 32772 33023 35878 49674 51060 51333 100 452 1703 1932 4208 5127 12086 14549 16084 17890 20870 41364 48498 1569 1633 1666 12957 18611 22499 38418 38719 42135 46815 48274 50947 51387 119 691 1190 2457 3865 7468 12512 30782 31811 33508 36586 41789 47426 867 1117 1666 4376 13263 13466 33524 37440 38136 39800 41454 41620 42510 378 900 1754 16303 25369 27103 28360 30958 35316 44165 46682 47016 50004 1321 1549 1570 16276 17284 19431 23482 23920 27386 27517 46253 48617 50118 37 383 1418 15792 22551 28843 36532 36718 38805 39226 45671 47712 51769 150 787 1441 17828 19396 21576 21805 24048 31868 32891 42486 43020 45492 1095 1214 1744 2445 5773 10209 11526 29604 30121 36526 45786 47376 49366 412 448 1281 11164 14501 15538 15773 23305 31960 32721 40744 45731 50269 183 626 837 4491 12237 13705 15177 15973 21266 25374 41232 44147 50529 618 1550 1594 5474 9260 16552 18122 26061 30420 30922 32661 34390 43236 135 496 757 9327 15659 20738 24327 26688 29063 38993 46155 49532 50001 64 126 1714 5561 8921 11300 12688 14454 16857 19585 20528 24107 27252 528 687 1730 9735 11737 16396 19200 33712 34271 38241 42027 44471 45581 69 646 1447 8603 19706 22153 22398 23840 24638 27254 29107 30368 41419 673 845 1285 9100 11064 14804 15425 17357 27248 31223 32410 35444 48018 124 1531 1677 3672 3673 3786 8886 9557 10003 11053 13053 22458 25413 102 1154 1758 5721 6034 14567 17772 28670 33380 34284 35356 47480 48123 48 351 760 2078 9797 22956 26120 34119 39658 41039 45237 47861 49022 254 445 841 6835 18340 19021 20053 22874 32639 36679 42004 45696 49530 16 802 903 6218 16206 22068 23049 28201 30377 33947 44358 44739 49303 153 1542 1629 7992 29900 34931 36927 38651 39981 41085 41327 50185 51484 525 1291 1765 9425 20271 31229 37444 38996 39145 41711 43188 45203 51255 2 244 1648 12321 14991 17426 18456 20126 29915 32581 38880 39516 49013 23 452 705 9414 11862 13764 18179 35458 37892 40471 46041 46494 48746 509 1201 1328 8921 9867 10947 19476 22693 32636 34301 38356 39238 51797 246 249 1390 12438 13266 24060 33628 37130 42923 43298 43709 43721 45413 117 257 748 9419 9461 11350 12790 16724 33147 34168 34683 37884 42699 619 646 740 7468 7604 8152 16296 19120 27614 27748 40170 40289 49366 914 1360 1716 10817 17672 18919 26146 29631 40903 46716 49502 51576 51657 68 702 1552 10431 10925 12856 24516 26440 30834 31179 32277 35019 44108 588 880 1524 6641 9453 9653 13679 14488 20714 25865 42217 42637 48312 6380 12240 12558 12816 21460 24206 26129 28555 41616 51767 8889 16221 21629 23476 33954 40572 43494 44666 44885 49813 16938 17727 17913 18898 21754 32515 35686 36920 39898 43560 9170 11747 14681 22874 24537 24685 26989 28947 33592 34621 2427 10241 29649 30522 37700 37789 41656 44020 49801 51268 The receiving device / method includes a group-wise deinterleaving unit / step for restoring the arrangement of the LDPC codes after group-wise interleaving, obtained from data transmitted by the transmission method described above, to the original arrangement.

[0010] In the transmission device / method of the present technology, LDPC coding is performed based on a check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 4 / 16, and group-wise interleaving is performed to interleave the LDPC code in 360-bit bit group units. Then, the LDPC code is mapped in 4-bit units to one of 16 signal points of 2D-NUC (Non-Uniform Constellation) of 16QAM. In the group-wise interleaving, the (i+1)-th bit group from the beginning of the LDPC code is defined as bit group i, and the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is defined as bit group i. 154, 83, 159, 153, 136, 6, 19, 73, 122, 40, 97, 144, 101, 106, 130, 174, 48, 176, 14, 27, 52, 152, 173, 63, 39, 92, 114, 98, 190, 149, 103, 160, 118, 13, 29, 51, 66, 168, 180, 23, 170, 24, 5, 157, 28, 45, 53, 68, 25, 191, 148, 139, 15, 67, 77, 100, 58, 91, 50, 131, 65, 17, 11, 123, 86, 135, 115, 120, 59, 162, 9, 189, 21, 12, 179, 178, 110, 35, 137, 3, 84, 177, 124, 186, 143, 26, 96, 80, 31, 169, 119, 33, 87, 140, 88, 171, 133, 150, 151, 72, 85, 89, 112, 126, 167, 56, 49, 187, 138, 145, 18, 32, 90, 158, 54, 104, 62, 165, 79, 1, 81, 102, 44, 61, 10, 166, 2, 116, 161, 60, 108, 142, 30, 78, 127, 111, 46, 43, 184, 163, 64, 22, 41, 156, 70, 20, 42, 182, 55, 95, 105, 132, 38, 69, 134, 74, 155, 141, 172, 57, 7, 175, 128, 75, 107, 109, 99, 147, 146, 117, 125, 185, 0, 76, 82, 129, 36, 34, 93, 188, 113, 71, 183, 121, 47, 16, 164, 4, 181, 94, 37, 8 The check matrix initial value table that defines the check matrix is ​​as described above.

[0011] In the receiving device / method of the present technology, the arrangement of the LDPC codes after group-wise interleaving, which is obtained from data transmitted by the transmission method of the present technology, is restored to the original arrangement.

[0012] The receiving device and the transmitting device may each be an independent device, or may be an internal block constituting a single device. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 2 is a diagram illustrating a check matrix H of an LDPC code. [Figure 2] 10 is a flowchart illustrating a decoding procedure for an LDPC code. [Figure 3] FIG. 1 is a diagram illustrating an example of a check matrix of an LDPC code. [Figure 4] FIG. 10 is a diagram illustrating an example of a Tanner graph of a parity check matrix. [Figure 5] FIG. 10 is a diagram illustrating an example of a variable node. [Figure 6] FIG. 2 is a diagram illustrating an example of a check node. [Figure 7] 1 is a diagram illustrating a configuration example of an embodiment of a transmission system to which the present technology is applied. [Figure 8] FIG. 2 is a block diagram showing an example of the configuration of a transmission device 11. [Figure 9] FIG. 10 is a block diagram showing an example of the configuration of a bit interleaver 116. [Figure 10] FIG. 10 is a diagram illustrating an example of a check matrix. [Figure 11] FIG. 10 is a diagram illustrating an example of a parity matrix. [Figure 12] FIG. 1 is a diagram illustrating a check matrix of an LDPC code defined in the DVB-T.2 standard. [Figure 13] FIG. 1 is a diagram illustrating a check matrix of an LDPC code defined in the DVB-T.2 standard. [Figure 14] FIG. 1 is a diagram illustrating an example of a Tanner graph for decoding an LDPC code. [Figure 15]FIG. 1 is a diagram illustrating an example of a parity matrix H T having a staircase structure and a Tanner graph corresponding to the parity matrix H T. [Figure 16] FIG. 10 is a diagram illustrating an example of a parity matrix H T of a check matrix H corresponding to an LDPC code after parity interleaving. [Figure 17] 10 is a flowchart illustrating an example of processing performed by the bit interleaver 116 and the mapper 117. [Figure 18] FIG. 2 is a block diagram showing an example of the configuration of an LDPC encoder 115. [Figure 19] 10 is a flowchart illustrating an example of processing performed by the LDPC encoder 115. [Figure 20] FIG. 10 is a diagram illustrating an example of a check matrix initial value table for a coding rate of 1 / 4 and a code length of 16200. [Figure 21] 10 is a diagram illustrating a method for obtaining a check matrix H from a check matrix initial value table. FIG. [Figure 22] FIG. 10 is a diagram illustrating the structure of a parity check matrix. [Figure 23] FIG. 10 is a diagram illustrating an example of a check matrix initial value table. [Figure 24] FIG. 10 is a diagram illustrating matrix A generated from the check matrix initial value table. [Figure 25] FIG. 10 is a diagram illustrating parity interleaving of a B matrix. [Figure 26] FIG. 10 is a diagram illustrating a C matrix generated from a check matrix initial value table. [Figure 27] FIG. 10 is a diagram illustrating parity interleaving of a D matrix. [Figure 28] FIG. 10 is a diagram showing a parity check matrix obtained by performing column permutation on the parity check matrix as parity deinterleaving to restore parity interleaving to its original state. [Figure 29] FIG. 10 is a diagram showing a transformed check matrix obtained by performing row permutation on a check matrix. [Figure 30] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type A code where N=69120 bits and r=2 / 16. [Figure 31] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type A code where N=69120 bits and r=3 / 16. [Figure 32] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type A code where N=69120 bits and r=3 / 16. [Figure 33] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type A code where N=69120 bits and r=4 / 16. [Figure 34] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type A code where N=69120 bits and r=5 / 16. [Figure 35] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type A code where N=69120 bits and r=5 / 16. [Figure 36] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type A code where N=69120 bits and r=6 / 16. [Figure 37] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type A code where N=69120 bits and r=6 / 16. [Figure 38] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type A code where N=69120 bits and r=7 / 16. [Figure 39] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type A code where N=69120 bits and r=7 / 16. [Figure 40] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type A code where N=69120 bits and r=8 / 16. [Figure 41] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type A code where N=69120 bits and r=8 / 16. [Figure 42] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=7 / 16. [Figure 43] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=7 / 16. [Figure 44]FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=7 / 16. [Figure 45] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=7 / 16. [Figure 46] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=8 / 16. [Figure 47] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=8 / 16. [Figure 48] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=8 / 16. [Figure 49] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=8 / 16. [Figure 50] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=9 / 16. [Figure 51] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=9 / 16. [Figure 52] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=9 / 16. [Figure 53] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=9 / 16. [Figure 54] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=9 / 16. [Figure 55] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=9 / 16. [Figure 56] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=10 / 16. [Figure 57]FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=10 / 16. [Figure 58] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=10 / 16. [Figure 59] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=10 / 16. [Figure 60] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=10 / 16. [Figure 61] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=10 / 16. [Figure 62] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code with N=69120 bits and r=11 / 16. [Figure 63] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code with N=69120 bits and r=11 / 16. [Figure 64] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code with N=69120 bits and r=11 / 16. [Figure 65] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=11 / 16. [Figure 66] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=11 / 16. [Figure 67] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=11 / 16. [Figure 68] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=12 / 16. [Figure 69] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=12 / 16. [Figure 70]FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=12 / 16. [Figure 71] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=12 / 16. [Figure 72] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=12 / 16. [Figure 73] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=12 / 16. [Figure 74] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code with N=69120 bits and r=13 / 16. [Figure 75] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code with N=69120 bits and r=13 / 16. [Figure 76] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code with N=69120 bits and r=13 / 16. [Figure 77] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=13 / 16. [Figure 78] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=13 / 16. [Figure 79] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=13 / 16. [Figure 80] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=14 / 16. [Figure 81] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=14 / 16. [Figure 82] FIG. 10 is a diagram showing an example of a check matrix initial value table for a Type B code where N=69120 bits and r=14 / 16. [Figure 83]FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=14 / 16. [Figure 84] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=14 / 16. [Figure 85] FIG. 10 is a diagram showing another example of a parity check matrix initial value table for a Type B code with N=69120 bits and r=14 / 16. [Figure 86] FIG. 10 is a diagram illustrating an example of a Tanner graph of an ensemble of degree sequences with column weight 3 and row weight 6. [Figure 87] FIG. 10 is a diagram illustrating an example of a Tanner graph of a multi-edge type ensemble. [Figure 88] FIG. 10 is a diagram illustrating a parity check matrix of the Type A method. [Figure 89] FIG. 10 is a diagram illustrating a parity check matrix of the Type A method. [Figure 90] FIG. 10 is a diagram illustrating a parity check matrix of the Type B method. [Figure 91] FIG. 10 is a diagram illustrating a parity check matrix of the Type B method. [Figure 92] FIG. 10 is a diagram illustrating an example of coordinates of UC signal points when the modulation method is QPSK. [Figure 93] FIG. 10 is a diagram illustrating an example of the coordinates of signal points of 2D-NUC when the modulation method is 16QAM. [Figure 94] FIG. 10 is a diagram illustrating an example of the coordinates of signal points of 1D-NUC when the modulation method is 1024QAM. [Figure 95] FIG. 10 is a diagram showing the relationship between a 1024QAM symbol y and a position vector u. [Figure 96] FIG. 10 is a diagram illustrating an example of coordinates zq of a signal point of QPSK-UC. [Figure 97] FIG. 10 is a diagram illustrating an example of coordinates zq of a signal point of QPSK-UC. [Figure 98] FIG. 10 is a diagram illustrating an example of coordinates zq of a 16QAM-UC signal point. [Figure 99] FIG. 10 is a diagram illustrating an example of coordinates zq of a 16QAM-UC signal point. [Figure 100] FIG. 10 is a diagram illustrating an example of coordinates zq of a 64QAM-UC signal point. [Figure 101] FIG. 10 is a diagram illustrating an example of coordinates zq of a 64QAM-UC signal point. [Figure 102] FIG. 10 is a diagram illustrating an example of coordinates zq of a signal point of 256QAM-UC. [Figure 103] FIG. 10 is a diagram illustrating an example of coordinates zq of a signal point of 256QAM-UC. [Figure 104] FIG. 10 is a diagram illustrating an example of coordinates zq of a 1024QAM-UC signal point. [Figure 105] FIG. 10 is a diagram illustrating an example of coordinates zq of a 1024QAM-UC signal point. [Figure 106] FIG. 10 is a diagram illustrating an example of coordinates zq of a 4096QAM-UC signal point. [Figure 107] FIG. 10 is a diagram illustrating an example of coordinates zq of a 4096QAM-UC signal point. [Figure 108] FIG. 10 is a diagram illustrating an example of coordinates zs of a signal point of 16QAM-2D-NUC. [Figure 109] FIG. 10 is a diagram illustrating an example of coordinates zs of a signal point of 64QAM-2D-NUC. [Figure 110] FIG. 10 is a diagram illustrating an example of the coordinates zs of a signal point of 256QAM-2D-NUC. [Figure 111] FIG. 10 is a diagram illustrating an example of the coordinates zs of a signal point of 256QAM-2D-NUC. [Figure 112] FIG. 10 is a diagram illustrating an example of the coordinates zs of a signal point of 1024QAM-1D-NUC. [Figure 113] FIG. 10 is a diagram showing the relationship between a 1024QAM symbol y and a position vector u. [Figure 114] FIG. 10 is a diagram illustrating an example of coordinates zs of a signal point of 4096QAM-1D-NUC. [Figure 115] FIG. 10 is a diagram showing the relationship between a 4096QAM symbol y and a position vector u. [Figure 116] FIG. 10 is a diagram showing the relationship between a 4096QAM symbol y and a position vector u. [Figure 117]FIG. 2 is a diagram illustrating block interleaving performed by the block interleaver 25. [Figure 118] FIG. 2 is a diagram illustrating block interleaving performed by the block interleaver 25. [Figure 119] FIG. 2 is a diagram illustrating group-wise interleaving performed by group-wise interleaver 24. [Figure 120] FIG. 10 is a diagram illustrating a first example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 121] FIG. 10 is a diagram illustrating a second example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 122] FIG. 10 is a diagram illustrating a third example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 123] FIG. 10 is a diagram illustrating a fourth example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 124] FIG. 10 is a diagram illustrating a fifth example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 125] FIG. 10 is a diagram illustrating a sixth example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 126] FIG. 10 is a diagram illustrating a seventh example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 127] FIG. 10 is a diagram illustrating an eighth example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 128] FIG. 13 is a diagram illustrating a ninth example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 129] FIG. 16 is a diagram illustrating a tenth example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 130] FIG. 11 is a diagram illustrating an eleventh example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 131]FIG. 12 is a diagram illustrating a twelfth example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 132] FIG. 13 is a diagram illustrating a thirteenth example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 133] FIG. 14 is a diagram illustrating a fourteenth example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 134] FIG. 15 is a diagram illustrating a fifteenth example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 135] FIG. 16 is a diagram illustrating a sixteenth example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 136] FIG. 17 is a diagram illustrating a 17th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 137] FIG. 18 is a diagram illustrating an 18th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 138] FIG. 19 is a diagram illustrating a 19th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 139] FIG. 13 is a diagram illustrating a twentieth example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 140] FIG. 21 is a diagram illustrating a 21st example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 141] FIG. 22 is a diagram illustrating a 22nd example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 142] FIG. 23 is a diagram illustrating a 23rd example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 143] FIG. 24 is a diagram illustrating a 24th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 144] FIG. 25 is a diagram illustrating a 25th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 145]FIG. 26 is a diagram illustrating a 26th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 146] FIG. 27 is a diagram illustrating a 27th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 147] FIG. 28 is a diagram illustrating a 28th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 148] FIG. 13 is a diagram illustrating a 29th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 149] FIG. 10 is a diagram illustrating a 30th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 150] FIG. 10 is a diagram illustrating a 31st example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 151] FIG. 10 is a diagram illustrating a 32nd example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 152] FIG. 10 is a diagram illustrating a 33rd example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 153] FIG. 10 is a diagram illustrating a 34th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Fig. 154] FIG. 10 is a diagram illustrating a 35th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 155] FIG. 10 is a diagram illustrating a 36th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 156] FIG. 10 is a diagram illustrating a 37th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 157] FIG. 10 is a diagram illustrating a 38th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 158] FIG. 10 is a diagram illustrating a 39th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 159]FIG. 10 is a diagram illustrating a 40th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 160] FIG. 41 is a diagram showing a 41st example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 161] FIG. 42 is a diagram illustrating a 42nd example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 162] FIG. 10 is a diagram illustrating a 43rd example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 163] FIG. 10 is a diagram illustrating a 44th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Fig. 164] FIG. 10 is a diagram illustrating a 45th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 165] FIG. 10 is a diagram illustrating a 46th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 166] FIG. 10 is a diagram illustrating a 47th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 167] FIG. 10 is a diagram illustrating a 48th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 168] FIG. 10 is a diagram illustrating a 49th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 169] FIG. 10 is a diagram illustrating a 50th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 170] FIG. 10 is a diagram illustrating a 51st example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 171] FIG. 10 is a diagram illustrating a 52nd example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Fig. 172] FIG. 10 is a diagram illustrating a 53rd example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 173]FIG. 10 is a diagram illustrating a 54th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Fig. 174] FIG. 10 is a diagram illustrating a 55th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 175] FIG. 10 is a diagram illustrating a 56th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 176] FIG. 10 is a diagram illustrating a 57th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 177] FIG. 10 is a diagram illustrating a 58th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 178] FIG. 10 is a diagram illustrating a 59th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 179] FIG. 10 is a diagram illustrating a 60th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 180] FIG. 10 is a diagram illustrating a 61st example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 181] FIG. 10 is a diagram illustrating a 62nd example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 182] FIG. 10 is a diagram illustrating a 63rd example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 183] FIG. 10 is a diagram illustrating a 64th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 184] FIG. 10 is a diagram illustrating a 65th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 185] FIG. 10 is a diagram illustrating a 66th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 186] FIG. 10 is a diagram illustrating a 67th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 187]FIG. 10 is a diagram illustrating a 68th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 188] FIG. 10 is a diagram illustrating a 69th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 189] FIG. 10 is a diagram showing a 70th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 190] FIG. 10 is a diagram showing a 71st example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 191] FIG. 10 is a diagram illustrating a 72nd example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 192] FIG. 10 is a diagram illustrating a 73rd example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 193] FIG. 10 is a diagram illustrating a 74th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 194] FIG. 10 is a diagram illustrating a 75th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 195] FIG. 10 is a diagram illustrating a 76th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 196] FIG. 10 is a diagram illustrating a 77th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 197] FIG. 10 is a diagram illustrating a 78th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 198] FIG. 10 is a diagram showing an example of coordinates of other 16QAM-2D-NUC signal points that can be used for the new LDPC code. [Figure 199] FIG. 10 is a diagram showing simulation results of the BER of a Type A code with a code length N of 69120 bits and r=4 / 16. [Figure 200] FIG. 10 is a diagram showing a simulation result of a required carrier-to-noise ratio (CNR) of a Type A code with a code length N of 69120 bits and r=4 / 16. [Figure 201] FIG. 10 is a diagram illustrating a 79th example of a GW pattern for an LDPC code having a code length N of 69120 bits. [Figure 202] FIG. 10 is a diagram showing simulation results of BER for a combination of Type A code with r=4 / 16 and code length N of 69120 bits, 16QAM, new 16QAM-2D-NUC, and new GW pattern. [Figure 203] FIG. 10 is a diagram showing simulation results of required CNR for a combination of Type A code with r=4 / 16 and code length N of 69120 bits, 16QAM, new 16QAM-2D-NUC, and new GW pattern. [Figure 204] FIG. 2 is a block diagram showing an example of the configuration of a receiving device 12. [Figure 205] FIG. 10 is a block diagram showing an example of the configuration of a bit deinterleaver 165. [Figure 206] 10 is a flowchart illustrating an example of processing performed by a demapper 164, a bit deinterleaver 165, and an LDPC decoder 166. [Figure 207] FIG. 1 is a diagram illustrating an example of a check matrix of an LDPC code. [Figure 208] FIG. 10 is a diagram showing an example of a matrix (transformed parity check matrix) obtained by performing row permutation and column permutation on a parity check matrix. [Figure 209] FIG. 10 is a diagram showing an example of a transformed check matrix divided into 5×5 units. [Figure 210] FIG. 10 is a block diagram showing an example of the configuration of a decoding device that performs P node operations at once. [Figure 211] FIG. 2 is a block diagram showing an example of the configuration of an LDPC decoder 166. [Figure 212] FIG. 10 is a diagram illustrating block deinterleaving performed by the block deinterleaver 54. [Figure 213] FIG. 10 is a block diagram showing another example configuration of the bit deinterleaver 165. [Figure 214] 1 is a block diagram showing a first example of the configuration of a receiving system to which a receiving device 12 can be applied. [Figure 215]It is a block diagram showing a second configuration example of a reception system to which the reception device 12 can be applied. [Figure 216] It is a block diagram showing a third configuration example of a reception system to which the reception device 12 can be applied. [Figure 217] It is a block diagram showing a configuration example of an embodiment of a computer to which this technology is applied.

Embodiments for Carrying Out the Invention

[0014] Hereinafter, embodiments of the present technology will be described. Prior to that, the LDPC code will be described.

[0015] <LDPC Code>

[0016] Note that the LDPC code is a linear code and does not necessarily have to be binary, but here it will be described as being binary.

[0017] The LDPC code is characterized in that the parity check matrix defining the LDPC code is sparse. Here, a sparse matrix is a matrix in which the number of "1"s in the elements of the matrix is very small (a matrix in which most elements are 0).

[0018] FIG. 1 is a diagram showing an example of the parity check matrix H of the LDPC code.

[0019] In the parity check matrix H of FIG. 1, the weight of each column (column weight) (the number of "1"s) (weight) is "3", and the weight of each row (row weight) is "6".

[0020] In encoding by the LDPC code (LDPC encoding), for example, a generator matrix G is generated based on the parity check matrix H, and this generator matrix G is multiplied by binary information bits to generate a codeword (LDPC code).

[0021] Specifically, an encoding device that performs LDPC encoding first calculates the transposed matrix H of the parity check matrix H T and between them, the equation GHT = 0. Here, if generator matrix G is a K × N matrix, the encoding device multiplies generator matrix G by a bit string (vector u) of K information bits to generate a codeword c (= uG) consisting of N bits. The codeword (LDPC code) generated by this encoding device is received at the receiving side via a predetermined communication channel.

[0022] Decoding of LDPC codes is an algorithm proposed by Gallager called Probabilistic Decoding, and can be performed by a message-passing algorithm using belief propagation on a Tanner graph consisting of variable nodes (also called message nodes) and check nodes. Hereinafter, variable nodes and check nodes will be referred to simply as nodes where appropriate.

[0023] FIG. 2 is a flowchart showing the procedure for decoding an LDPC code.

[0024] In the following, the real value (received LLR) that expresses the likelihood of the value being "0" of the i-th code bit of the LDPC code (one code word) received on the receiving side as a log likelihood ratio is referred to as the received value u 0i Also, the message output from the check node is called u j The message output from the variable node is v i Let's say.

[0025] First, in decoding an LDPC code, as shown in FIG. 2, in step S11, an LDPC code is received and a message (check node message) u jis initialized to "0", and a variable k that takes an integer and serves as a counter for repeated processing is initialized to "0", and the process proceeds to step S12. In step S12, the received value u obtained by receiving the LDPC code is 0i Based on this, the message (variable node message) v is generated by performing the calculation (variable node calculation) shown in Equation (1). i is required, and furthermore, this message v i Based on this, the message u is generated by performing the operation (check node operation) shown in equation (2). j is required.

[0026]

number

[0027]

number

[0028] Here, d in Equation (1) and Equation (2) v and d c are arbitrarily selectable parameters that indicate the number of "1"s in the vertical direction (columns) and horizontal direction (rows) of the check matrix H. For example, in the case of an LDPC code ((3,6) LDPC code) for a check matrix H with a column weight of 3 and a row weight of 6 as shown in FIG. 1, d v =3,d c =6.

[0029] In the variable node operation of formula (1) and the check node operation of formula (2), messages input from edges (lines connecting variable nodes and check nodes) that are about to output messages are not included in the operation, so the range of operation is from 1 to d. v -1 or 1 to d cThe check node operation of equation (2) is actually performed by creating a table of the function R(v1, v2) shown in equation (3), which is defined as one output for two inputs v1 and v2, in advance, and then using this table continuously (recursively) as shown in equation (4).

[0030]

number

[0031]

number

[0032] In step S12, the variable k is further incremented by "1", and the process proceeds to step S13. In step S13, it is determined whether the variable k is greater than a predetermined number of decoding iterations C. If it is determined in step S13 that the variable k is not greater than C, the process returns to step S12, and the same processes are repeated thereafter.

[0033] If it is determined in step S13 that the variable k is greater than C, the process proceeds to step S14, where the message v i is calculated and output, and the LDPC code decoding process is completed.

[0034]

number

[0035] Here, the operation of formula (5) differs from the variable node operation of formula (1) in that it receives messages u from all edges connected to the variable node. j This is done using

[0036] FIG. 3 is a diagram showing an example of a parity check matrix H of a (3,6) LDPC code (coding rate 1 / 2, code length 12).

[0037] In the parity check matrix H in FIG. 3, the column weight is 3 and the row weight is 6, similar to FIG.

[0038] FIG. 4 is a diagram showing a Tanner graph of the parity check matrix H of FIG.

[0039] Here, in Figure 4, check nodes are represented by plus signs "+" and variable nodes are represented by equal signs "=". Check nodes and variable nodes correspond to the rows and columns of the parity check matrix H, respectively. The connection between a check node and a variable node is an edge, which corresponds to the element "1" of the parity check matrix.

[0040] That is, when the element in the j-th row and i-th column of the parity check matrix is ​​1, in FIG. 4, the i-th variable node from the top (node ​​marked "=") and the j-th check node from the top (node ​​marked "+") are connected by a branch. The branch indicates that the code bit corresponding to the variable node has a constraint corresponding to the check node.

[0041] In a sum product algorithm, which is a decoding method for LDPC codes, variable node calculations and check node calculations are repeatedly performed.

[0042] FIG. 5 is a diagram showing variable node operations performed at the variable node.

[0043] At the variable node, the message v corresponding to the branch to be calculated is i is the message u1 and u2 from the remaining branches connected to the variable node, and the received value u 0i The messages corresponding to the other branches can be calculated in the same way.

[0044] FIG. 6 is a diagram illustrating check node operations performed at a check node.

[0045] Here, the check node operation of equation (2) can be rewritten as equation (6) using the relationship of the equation a×b=exp{ln(|a|)+ln(|b|)}×sign(a)×sign(b), where sign(x) is 1 when x≧0 and −1 when x<0.

[0046]

number

[0047] If we define the function φ(x) as φ(x)=ln(tanh(x / 2)) for x≧0, then the function φ -1 (x)=2tanh -1 (e -x ) holds, so equation (6) can be transformed into equation (7).

[0048]

number

[0049] At the check nodes, the check node operation of equation (2) is performed according to equation (7).

[0050] That is, at the check node, as shown in Figure 6, the message u corresponding to the branch to be calculated is j is calculated by the check node calculation of equation (7) using messages v1, v2, v3, v4, and v5 from the remaining edges connected to the check node. Messages corresponding to other edges can be calculated in the same way.

[0051] The function φ(x) in equation (7) is expressed as φ(x)=ln((e x +1) / (e x -1), and for x>0, φ(x)=φ -1 (x). The functions φ(x) and φ -1 When (x) is implemented in hardware, it may be implemented using an LUT (Look Up Table), but both will be the same LUT.

[0052] <Configuration example of a transmission system applying this technology>

[0053] FIG. 7 is a diagram showing an example of the configuration of one embodiment of a transmission system to which the present technology is applied (a system refers to a logical collection of multiple devices, and it does not matter whether the devices are located in the same housing or not).

[0054] In FIG. 7, the transmission system is made up of a transmitting device 11 and a receiving device 12.

[0055] The transmitting device 11 transmits (broadcasts) (transmits), for example, television broadcast programs, etc. That is, the transmitting device 11 encodes target data to be transmitted, such as image data or audio data as a program, into an LDPC code, and transmits the encoded data via a communication path 13, such as a satellite line, terrestrial wave, or cable (wired line).

[0056] The receiving device 12 receives the LDPC code transmitted from the transmitting device 11 via the communication path 13, decodes it into target data, and outputs it.

[0057] Here, the LDPC code used in the transmission system of FIG. 7 is known to exhibit extremely high performance in an AWGN (Additive White Gaussian Noise) communication channel.

[0058] On the other hand, burst errors and erasures may occur in the communication path 13. For example, in an OFDM (Orthogonal Frequency Division Multiplexing) system, particularly when the communication path 13 is a terrestrial wave, in a multipath environment where the D / U (Desired to Undesired Ratio) is 0 dB (Undesired = echo power is equal to Desired = main path power), the power of a specific symbol may become 0 (erasure) depending on the delay of the echo (path other than the main path).

[0059] Furthermore, even in a flutter channel (a channel with zero delay and an echo with a Doppler frequency added), if the D / U is 0 dB, the Doppler frequency can cause the power of the entire OFDM symbol at a specific time to become 0 (erasure).

[0060] Furthermore, burst errors may occur due to the condition of the wiring from the receiving unit (not shown) such as an antenna that receives signals from the transmitting device 11 to the receiving device 12, or due to instability in the power supply of the receiving device 12.

[0061] On the other hand, in decoding the LDPC code, the columns of the check matrix H, and in turn, the variable nodes corresponding to the code bits of the LDPC code, are used to decode the received values ​​u 0i Since the variable node operation of equation (1) involves the addition of (a) and (b), if an error occurs in the sign bit used in the variable node operation, the accuracy of the message obtained will decrease.

[0062] In decoding an LDPC code, the check node calculation of equation (7) is performed at a check node using a message obtained at a variable node connected to that check node. Therefore, if there are a large number of check nodes where multiple connected variable nodes (corresponding code bits of the LDPC code) simultaneously have errors (including erasures), the decoding performance will deteriorate.

[0063] That is, for example, when two or more variable nodes connected to the check node are simultaneously erased, a check node returns to all variable nodes a message with an equal probability that the value is 0 and that the value is 1. In this case, the check node that returns a message with equal probability does not contribute to one decoding process (one set of variable node calculation and check node calculation), and as a result, the decoding process needs to be repeated many times, degrading the decoding performance and further increasing the power consumption of the receiving device 12 that decodes the LDPC code.

[0064] Therefore, the transmission system of FIG. 7 can improve the tolerance to burst errors and erasures while maintaining the performance in an AWGN communication path (AWGN channel).

[0065] <Configuration example of transmitter 11>

[0066] FIG. 8 is a block diagram showing an example of the configuration of the transmitting device 11 of FIG.

[0067] In the transmitting device 11, one or more input streams as target data are supplied to a mode adaptation / multiplexer 111.

[0068] The mode adaptation / multiplexer 111 performs processing such as mode selection and multiplexing of one or more input streams supplied thereto as necessary, and supplies the resulting data to a padder 112 .

[0069] The padder 112 performs necessary zero padding (insertion of nulls) on the data from the mode adaptation / multiplexer 111 and supplies the resulting data to a BB scrambler 113 .

[0070] The BB scrambler 113 performs BB scrambling (Base-Band Scrambling) on ​​the data from the padder 112 and supplies the resulting data to a BCH encoder 114 .

[0071] The BCH encoder 114 performs BCH encoding on the data from the BB scrambler 113, and supplies the resulting data to an LDPC encoder 115 as LDPC target data that is to be LDPC encoded.

[0072] The LDPC encoder 115 performs LDPC encoding on the LDPC target data from the BCH encoder 114, for example, according to a check matrix in which the parity matrix, which is the part corresponding to the parity bits of the LDPC code, has a staircase (dual diagonal) structure, and outputs an LDPC code in which the LDPC target data is information bits.

[0073] That is, the LDPC encoder 115 performs LDPC encoding on the LDPC target data to encode the LDPC target data into an LDPC code (corresponding to a check matrix) specified in a predetermined standard such as DVB-S.2, DVB-T.2, DVB-C.2, or ATSC3.0, or another LDPC code, and outputs the resulting LDPC code.

[0074] Here, the LDPC codes specified in the DVB-S.2 and ATSC3.0 standards and the LDPC codes to be adopted in ATSC3.0 are IRA (Irregular Repeat Accumulate) codes, and the parity matrix (part or all) in the check matrix of the LDPC code has a staircase structure. The parity matrix and the staircase structure will be described later. The IRA code is described, for example, in "Irregular Repeat-Accumulate Codes," by H. Jin, A. Khandekar, and RJ McEliece, in Proceedings of the 2nd International Symposium on Turbo Codes and Related Topics, pp. 1-8, September 2000.

[0075] The LDPC code output by the LDPC encoder 115 is supplied to a bit interleaver 116 .

[0076] The bit interleaver 116 performs bit interleaving, which will be described later, on the LDPC code from the LDPC encoder 115 and supplies the bit-interleaved LDPC code to a mapper 117 .

[0077] The mapper 117 performs quadrature modulation (multi-level modulation) by mapping the LDPC code from the bit interleaver 116 to a signal point representing one symbol of quadrature modulation in units of one or more code bits (symbol units) of the LDPC code.

[0078] That is, the mapper 117 performs orthogonal modulation by mapping the LDPC code from the bit interleaver 116 to a signal point determined by a modulation method for orthogonally modulating the LDPC code on a constellation, which is an IQ plane defined by an I axis representing an I component that is in-phase with the carrier wave and a Q axis representing a Q component that is orthogonal to the carrier wave.

[0079] The number of signal points of the constellation used in the modulation method of the quadrature modulation performed by the mapper 117 is 2 m In this case, the m-bit code bits of the LDPC code are treated as a symbol (1 symbol), and the mapper 117 divides the LDPC code from the bit interleaver 116 into 2 symbols. m are mapped to signal points representing symbols among the signal points.

[0080] Here, the modulation method of the quadrature modulation performed by the mapper 117 includes, for example, modulation methods defined in the DVB-S.2 and ATSC3.0 standards, and other modulation methods, that is, for example, BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), 8PSK (Phase-Shift Keying), 16APSK (Amplitude Phase-Shift Keying), 32APSK, 16QAM (Quadrature Amplitude Modulation), 16QAM, 64QAM, 256QAM, 1024QAM, 4096QAM, 4PAM (Pulse Amplitude Modulation), etc. Which modulation method is used for quadrature modulation in the mapper 117 is set in advance, for example, according to an operation by an operator of the transmission device 11.

[0081] The data obtained by the processing in the mapper 117 (the mapping result of mapping symbols to signal points) is supplied to a time interleaver 118 .

[0082] The time interleaver 118 performs time interleaving (interleaving in the time direction) on a symbol-by-symbol basis on the data from the mapper 117, and supplies the resulting data to a SISO / MISO (Single Input Single Output / Multiple Input Single Output) encoder 119.

[0083] The SISO / MISO encoder 119 performs space-time coding on the data from the time interleaver 118 and supplies the data to a frequency interleaver 120 .

[0084] The frequency interleaver 120 performs frequency interleaving (interleaving in the frequency direction) on the data from the SISO / MISO encoder 119 in units of symbols, and supplies the data to a frame builder & resource allocation unit (Frame Builder & Resource Allocation) 131 .

[0085] On the other hand, the BCH encoder 121 is supplied with control data (signalling) for transmission control, such as BB signaling (Base Band Signaling) (BB Header).

[0086] The BCH encoder 121 BCH-encodes the control data supplied thereto in the same manner as the BCH encoder 114 , and supplies the resulting data to the LDPC encoder 122 .

[0087] The LDPC encoder 122 LDPC-encodes the data from the BCH encoder 121 as LDPC target data in the same manner as the LDPC encoder 115 , and supplies the resulting LDPC code to the mapper 123 .

[0088] Similar to the mapper 117, the mapper 123 performs orthogonal modulation by mapping the LDPC code from the LDPC encoder 122 to a signal point representing one symbol of orthogonal modulation in units of one or more code bits (symbol units) of the LDPC code, and supplies the resulting data to the frequency interleaver 124.

[0089] Similar to the frequency interleaver 120 , the frequency interleaver 124 performs frequency interleaving on the data from the mapper 123 in units of symbols, and supplies the data to a frame builder / resource allocation unit 131 .

[0090] The frame builder / resource allocation unit 131 inserts pilot symbols into required positions in the data (symbols) from the frequency interleavers 120 and 124, and constructs a frame (e.g., a PL (Physical Layer) frame, a T2 frame, a C2 frame, etc.) consisting of a predetermined number of symbols from the resulting data (symbols), and supplies it to an OFDM generation unit (OFDM generation) 132.

[0091] The OFDM generating unit 132 generates an OFDM signal corresponding to the frame from the frame supplied from the frame builder / resource allocating unit 131, and transmits the signal via the communication path 13 (FIG. 7).

[0092] The transmitting device 11 can be configured without some of the blocks shown in FIG. 8, such as the time interleaver 118, the SISO / MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124.

[0093] <Configuration example of bit interleaver 116>

[0094] FIG. 9 is a block diagram showing an example of the configuration of the bit interleaver 116 in FIG.

[0095] The bit interleaver 116 has a function of interleaving data, and is made up of a parity interleaver 23 , a group-wise interleaver 24 , and a block interleaver 25 .

[0096] The parity interleaver 23 performs parity interleaving to interleave the parity bits of the LDPC code from the LDPC encoder 115 at the positions of other parity bits, and supplies the LDPC code after the parity interleaving to the group-wise interleaver 24.

[0097] The group - wise interleaver 24 performs group - wise interleaving on the LDPC code from the parity interleaver 23, and supplies the LDPC code after the group - wise interleaving to the block interleaver 25.

[0098] Here, in the group - wise interleaving, the LDPC code for one code is divided from its head into units of 360 bits equal to the unit size P described later. The 360 - bit one - division is interleaved in units of bit groups for the LDPC code from the parity interleaver 23.

[0099] When performing group - wise interleaving, the error rate can be improved compared to the case where group - wise interleaving is not performed. As a result, good communication quality can be ensured in data transmission.

[0100] The block interleaver 25 performs block interleaving for demultiplexing the LDPC code from the group - wise interleaver 24. For example, the LDPC code for one code is symbolized into m - bit symbols which are the units of mapping, and supplied to the mapper 117 (FIG. 8).

[0101] Here, in the block interleaving, for example, columns as storage areas for storing a predetermined number of bits in the column (vertical) direction are arranged in the row (horizontal) direction in a storage area with a number equal to the number of bits m of the symbol. The LDPC code from the group - wise interleaver 24 is written in the column direction and read in the row direction, so that the LDPC code is symbolized into m - bit symbols.

[0102] <Check matrix of LDPC code>

[0103] FIG. 10 is a diagram showing an example of the check matrix H used for LDPC encoding in the LDPC encoder 115 of FIG. 8.

[0104] The check matrix H has an LDGM (Low-Density Generation Matrix) structure, and the information matrix H of the part of the code bits of the LDPC code corresponding to the information bits is A and the parity matrix H corresponding to the parity bits T Therefore, the formula H=[H A |H T ](information matrix H A The elements of are the left elements, and the parity matrix H T The right-hand element of the matrix is ​​the element of

[0105] Here, the number of information bits and the number of parity bits among the code bits of one LDPC code (one code word) are called the information length K and the parity length M, respectively, and the number of code bits of one LDPC code (one code word) is called the code length N (= K + M).

[0106] The information length K and parity length M for an LDPC code with a certain code length N are determined by the coding rate. The check matrix H is an M×N matrix (a matrix with M rows and N columns). A is an M×K matrix, and the parity matrix H T is an M×M matrix.

[0107] FIG. 11 shows the parity matrix H of the check matrix H used for LDPC encoding in the LDPC encoder 115 of FIG. T FIG.

[0108] The parity matrix H of the check matrix H used for LDPC encoding in the LDPC encoder 115 T For example, a parity matrix H similar to the check matrix H of the LDPC code specified in standards such as DVB-T.2 is used. T can be adopted.

[0109] Parity matrix H of the check matrix H of the LDPC code specified in standards such as DVB-T.2 TAs shown in Figure 11, the parity matrix H is a lower bidiagonal matrix in which the elements of 1 are arranged in a staircase pattern. T The row weight is 1 for the first row and 2 for all remaining rows. The column weight is 1 for the last column and 2 for all remaining columns.

[0110] As mentioned above, the parity matrix H T An LDPC code for a check matrix H having a staircase structure can be easily generated using the check matrix H.

[0111] That is, the LDPC code (one code word) is represented by a row vector c, and the column vector obtained by transposing the row vector is c T In addition, the information bit portion of row vector c, which is an LDPC code, is represented by row vector A, and the parity bit portion is represented by row vector T.

[0112] In this case, row vector c can be expressed as c = [A|T] (a row vector with elements of row vector A as the left elements and elements of row vector T as the right elements) using row vector A as the information bits and row vector T as the parity bits.

[0113] The check matrix H and the row vector c=[A|T] as the LDPC code are expressed by the formula Hc T = 0, and the formula Hc T = 0, the row vector T as the parity bit that constitutes the row vector c=[A|T] is the check matrix H=[H A |H T ]'s parity matrix H T When the step structure shown in Figure 11 is formed, the formula Hc T =0 column vector Hc T It can be calculated sequentially (in order) by setting the elements of each row to 0, starting from the first row.

[0114] FIG. 12 is a diagram illustrating a check matrix H of an LDPC code defined in standards such as DVB-T.2.

[0115] The first KX columns of the check matrix H of an LDPC code specified in standards such as DVB-T.2 have a column weight of X, the next K3 columns have a column weight of 3, the next M-1 columns have a column weight of 2, and the last column has a column weight of 1.

[0116] Here, KX+K3+M-1+1 is equal to the code length N.

[0117] FIG. 13 is a diagram showing the numbers of columns KX, K3, and M, and the column weight X for each coding rate r of the LDPC code defined in standards such as DVB-T.2.

[0118] Standards such as DVB-T.2 prescribe LDPC codes with code lengths N of 64,800 bits and 16,200 bits.

[0119] For an LDPC code with a code length N of 64,800 bits, eleven coding rates (nominal rates) 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, 8 / 9, and 9 / 10 are specified, and for an LDPC code with a code length N of 16,200 bits, ten coding rates 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, and 8 / 9 are specified.

[0120] Hereinafter, a code length N of 64,800 bits will also be referred to as 64 kbits, and a code length N of 16,200 bits will also be referred to as 16 kbits.

[0121] In an LDPC code, the code bits corresponding to columns with larger column weights in the parity check matrix H tend to have lower error rates.

[0122] In the check matrix H specified in standards such as DVB-T.2 shown in Figures 12 and 13, the column weight tends to be larger as it approaches the beginning (left side). Therefore, for the LDPC code corresponding to the check matrix H, the code bits at the beginning tend to be more resistant to errors (more resistant to errors), and the code bits at the end tend to be more susceptible to errors.

[0123] <Parity interleave>

[0124] Parity interleaving by the parity interleaver 23 of FIG. 9 will be described with reference to FIGS.

[0125] FIG. 14 is a diagram showing an example of (a part of) a Tanner graph of a parity check matrix of an LDPC code.

[0126] As shown in Fig. 14, when two or more of the variable nodes (corresponding code bits) connected to the check node simultaneously become erasure or other errors, the check node returns a message to all variable nodes connected to the check node, with the probability that the value is 0 and the probability that the value is 1 being equal. For this reason, when multiple variable nodes connected to the same check node simultaneously become erasure or other errors, decoding performance deteriorates.

[0127] Incidentally, the LDPC code output by the LDPC encoder 115 in FIG. 8 is an IRA code, similar to the LDPC code defined in the standards such as DVB-T.2, and the parity matrix H of the check matrix H is T As shown in Figure 11, the structure is a staircase.

[0128] Figure 15 shows the parity matrix H T and its parity matrix H T FIG. 1 is a diagram illustrating an example of a Tanner graph corresponding to

[0129] A in Figure 15 shows the parity matrix H T15A shows an example of the parity matrix H T The Tanner graph corresponding to

[0130] The parity matrix H has a staircase structure T In each row, elements with a value of 1 are adjacent (except the first row). Therefore, the parity matrix H T In the Tanner graph of T Two adjacent variable nodes corresponding to a column of two adjacent elements where the value of is 1 are connected to the same check node.

[0131] Therefore, when parity bits corresponding to the two adjacent variable nodes described above become erroneous at the same time due to a burst error, erasure, or the like, the check nodes connected to the two variable nodes corresponding to the two erroneous parity bits (variable nodes that use the parity bits to find a message) return messages with equal probabilities of being 0 and 1 to the variable nodes connected to those check nodes, degrading decoding performance.As the burst length (the number of consecutive erroneous parity bits) increases, the number of check nodes that return messages with equal probabilities increases, further degrading decoding performance.

[0132] Therefore, in order to prevent the above-mentioned degradation of decoding performance, the parity interleaver 23 (FIG. 9) performs parity interleaving, which interleaves the parity bits of the LDPC code from the LDPC encoder 115 at the positions of other parity bits.

[0133] FIG. 16 shows the parity matrix H of the check matrix H corresponding to the LDPC code after parity interleaving performed by the parity interleaver 23 in FIG. T FIG.

[0134] Here, the information matrix H of the check matrix H corresponding to the LDPC code output by the LDPC encoder 115 is Ahas a cyclic structure, similar to the information matrix of the check matrix H corresponding to the LDPC code defined in standards such as DVB-T.2.

[0135] A cyclic structure refers to a structure in which a column matches another column cyclically shifted, and includes, for example, a structure in which the position of 1 in each row of each P column is cyclically shifted in the column direction by a predetermined value, such as a value proportional to the value q obtained by dividing the first column of the P columns by the parity length M. Hereinafter, the P columns in the cyclic structure will be referred to as the unit size as appropriate.

[0136] As described in FIGS. 12 and 13, there are two types of LDPC codes specified in standards such as DVB-T.2, with code lengths N of 64,800 bits and 16,200 bits, and for both of these two types of LDPC codes, the unit size P is specified to be 360, which is one of the divisors of the parity length M excluding 1 and M.

[0137] Furthermore, the parity length M is a value other than a prime number expressed by the equation M = q × P = q × 360, with the value q varying depending on the coding rate. Therefore, like the unit size P, the value q is one of the divisors of the parity length M other than 1 and M, and is obtained by dividing the parity length M by the unit size P (the product of P and q, which are divisors of the parity length M, is the parity length M).

[0138] As described above, the parity interleaver 23 interleaves the K+qx+y+1-th code bit of the code bits of the N-bit LDPC code to the K+Py+x+1-th code bit position, where K is the information length, x is an integer greater than or equal to 0 and less than P, and y is an integer greater than or equal to 0 and less than q, as parity interleaving.

[0139] The K+qx+y+1th code bit and the K+Py+x+1th code bit are both parity bits since they are code bits after the K+1th bit. Therefore, according to parity interleaving, the position of the parity bit of the LDPC code is moved.

[0140] With this type of parity interleaving, variable nodes (and corresponding parity bits) connected to the same check node are spaced apart by the unit size P, i.e., 360 bits in this case. Therefore, if the burst length is less than 360 bits, it is possible to avoid a situation in which multiple variable nodes connected to the same check node experience an error at the same time, thereby improving resistance to burst errors.

[0141] The LDPC code after parity interleaving, in which the K+qx+y+1-th code bit is interleaved at the K+Py+x+1-th code bit position, matches the LDPC code of the check matrix (hereinafter also referred to as the transformed check matrix) obtained by performing column permutation, in which the K+qx+y+1-th column of the original check matrix H is replaced with the K+Py+x+1-th column.

[0142] Furthermore, as shown in FIG. 16, a quasi-cyclic structure appears in the parity matrix of the converted parity check matrix, with P columns (360 columns in FIG. 16) as a unit.

[0143] Here, the pseudo-cyclic structure means a structure in which all but a part are cyclic structures.

[0144] The transformed check matrix obtained by performing column permutation equivalent to parity interleaving on the check matrix of an LDPC code specified in standards such as DVB-T.2 has a 360 row x 360 column part in the upper right corner of the transformed check matrix (the shift matrix described below) that is missing one element of 1 (it becomes an element of 0), and in that respect it is not a (complete) cyclic structure, but rather a quasi-cyclic structure.

[0145] The conversion check matrix for the check matrix of the LDPC code output by the LDPC encoder 115 has a quasi-cyclic structure, similar to the conversion check matrix for the check matrix of the LDPC code defined in standards such as DVB-T.2.

[0146] The transformed check matrix in Figure 16 is a matrix in which, in addition to column permutation equivalent to parity interleaving, row permutation (row permutation) has also been performed on the original check matrix H so that the transformed check matrix is ​​composed of the constituent matrices described below.

[0147] FIG. 17 is a flowchart illustrating the processing performed by the LDPC encoder 115, the bit interleaver 116, and the mapper 117 in FIG.

[0148] The LDPC encoder 115 waits for the LDPC target data to be supplied from the BCH encoder 114, and in step S101 encodes the LDPC target data into an LDPC code and supplies the LDPC code to the bit interleaver 116, after which the process proceeds to step S102.

[0149] In step S102, the bit interleaver 116 performs bit interleaving on the LDPC code from the LDPC encoder 115, and supplies the symbols obtained by the bit interleaving to the mapper 117, after which the process proceeds to step S103.

[0150] That is, in step S102, in the bit interleaver 116 (FIG. 9), the parity interleaver 23 performs parity interleaving on the LDPC code from the LDPC encoder 115, and supplies the parity-interleaved LDPC code to the group-wise interleaver 24.

[0151] The group-wise interleaver 24 performs group-wise interleaving on the LDPC code from the parity interleaver 23 and supplies the result to the block interleaver 25 .

[0152] The block interleaver 25 performs block interleaving on the LDPC code after group-wise interleaving by the group-wise interleaver 24 , and supplies the resulting m-bit symbols to the mapper 117 .

[0153] In step S103, the mapper 117 converts the symbols from the block interleaver 25 into two symbols determined by the modulation method of the quadrature modulation performed by the mapper 117. m signal points and orthogonally modulated, and the resulting data is supplied to a time interleaver 118.

[0154] As described above, by performing parity interleaving or group-wise interleaving, it is possible to improve the error rate when multiple code bits of an LDPC code are transmitted as one symbol.

[0155] Here, in Figure 9, for the sake of convenience of explanation, the parity interleaver 23, which is a block that performs parity interleaving, and the group-wise interleaver 24, which is a block that performs group-wise interleaving, are configured separately, but the parity interleaver 23 and the group-wise interleaver 24 can be configured as an integrated unit.

[0156] In other words, both parity interleaving and group-wise interleaving can be performed by writing and reading code bits to memory, and can be represented by a matrix that converts the address at which the code bits are written (write address) into the address at which the code bits are read (read address).

[0157] Therefore, if a matrix obtained by multiplying a matrix representing a parity interleaving and a matrix representing a group-wise interleaving is obtained, by using those matrices, by converting the code bits, parity interleaving can be performed, and furthermore, as a result of group-wise interleaving the LDPC code after the parity interleaving can be obtained.

[0158] In addition to the parity interleaver 23 and the group-wise interleaver 24, the block interleaver 25 can also be integrally configured.

[0159] That is, the block interleaving performed by the block interleaver 25 can also be represented by a matrix that converts the write address of the memory storing the LDPC code into the read address.

[0160] Therefore, if a matrix obtained by multiplying a matrix representing a parity interleaving, a matrix representing a group-wise interleaving, and a matrix representing a block interleaving is obtained, by using those matrices, parity interleaving, group-wise interleaving, and block interleaving can be performed collectively.

[0161] Note that one or both of the parity interleaving and the group-wise interleaving can be not performed.

[0162] <Configuration example of LDPC encoder 115>

[0163] FIG. 18 is a block diagram showing a configuration example of the LDPC encoder 115 of FIG. 8.

[0164] Note that the LDPC encoder 122 of FIG. 8 is also configured in the same manner.

[0165] As described in FIGS. 12 and 13, in standards such as DVB-T.2, LDPC codes with two code lengths N of 64800 bits and 16200 bits are defined.

[0166] For an LDPC code with a code length N of 64,800 bits, eleven coding rates are specified: 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, 8 / 9, and 9 / 10, and for an LDPC code with a code length N of 16,200 bits, ten coding rates are specified: 1 / 4, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 2 / 3, 3 / 4, 4 / 5, 5 / 6, and 8 / 9 (Figures 12 and 13).

[0167] The LDPC encoder 115 can perform, for example, encoding (error correction encoding) using an LDPC code with a code length N of 64,800 bits or 16,200 bits and each coding rate, in accordance with a check matrix H prepared for each code length N and each coding rate.

[0168] Additionally, the LDPC encoder 115 can perform LDPC encoding in accordance with a check matrix H of an LDPC code with an arbitrary code length N and an arbitrary coding rate r.

[0169] The LDPC encoder 115 is made up of an encoding processing unit 601 and a storage unit 602 .

[0170] The encoding processing unit 601 is composed of a coding rate setting unit 611, an initial value table reading unit 612, a check matrix generation unit 613, an information bit reading unit 614, an encoding parity calculation unit 615, and a control unit 616, and performs LDPC encoding of the LDPC target data supplied to the LDPC encoder 115, and supplies the resulting LDPC code to the bit interleaver 116 (FIG. 8).

[0171] That is, the coding rate setting unit 611 sets the code length N and coding rate r of the LDPC code, and other specific information that identifies the LDPC code, in response to, for example, an operation by an operator.

[0172] The initial value table reading unit 612 reads from the storage unit 602 a check matrix initial value table, which will be described later, that indicates the check matrix of the LDPC code specified by the specification information set by the coding rate setting unit 611 .

[0173] The check matrix generation unit 613 generates a check matrix H based on the check matrix initial value table read by the initial value table reading unit 612, and stores the generated check matrix H in the storage unit 602. For example, the check matrix generation unit 613 generates an information matrix H corresponding to an information length K (=code length N-parity length M) according to the code length N and coding rate r set by the coding rate setting unit 611. A The elements of 1 are arranged in the column direction at a period of 360 columns (unit size P) to generate a check matrix H, which is stored in the storage unit 602.

[0174] The information bit reading unit 614 reads (extracts) information bits of an information length K from the LDPC target data supplied to the LDPC encoder 115.

[0175] The encoding parity calculation unit 615 reads out the check matrix H generated by the check matrix generation unit 613 from the memory unit 602, and uses the check matrix H to calculate parity bits for the information bits read out by the information bit reading unit 614 based on a predetermined formula, thereby generating a codeword (LDPC code).

[0176] The control unit 616 controls each block that constitutes the encoding processing unit 601 .

[0177] The storage unit 602 stores a plurality of check matrix initial value tables and the like corresponding to a plurality of coding rates and the like shown in Fig. 12 and Fig. 13 for each code length N of, for example, 64800 bits, 16200 bits, etc. The storage unit 602 also temporarily stores data necessary for processing by the encoding processing unit 601.

[0178] FIG. 19 is a flowchart illustrating an example of processing by the LDPC encoder 115 of FIG.

[0179] In step S201, the coding rate setting unit 611 sets the code length N and coding rate r for LDPC coding, as well as other specific information for specifying the LDPC code.

[0180] In step S202, the initial value table reading unit 612 reads from the storage unit 602 a predetermined check matrix initial value table that is specified by the code length N, the coding rate r, and the like, as the specific information set by the coding rate setting unit 611.

[0181] In step S203, the check matrix generation unit 613 uses the check matrix initial value table read out from the storage unit 602 by the initial value table reading unit 612 to determine (generate) the check matrix H of the LDPC code having the code length N and coding rate r set by the coding rate setting unit 611, and supplies it to the storage unit 602 for storage.

[0182] In step S204, the information bit reading unit 614 reads out information bits of an information length K (=N×r) corresponding to the code length N and coding rate r set by the coding rate setting unit 611 from the LDPC target data supplied to the LDPC encoder 115, and also reads out the check matrix H calculated by the check matrix generation unit 613 from the storage unit 602 and supplies it to the encoding parity calculation unit 615.

[0183] In step S205, the coded parity calculation unit 615 uses the information bits from the information bit reading unit 614 and the check matrix H to sequentially calculate parity bits of the codeword c that satisfy equation (8).

[0184] Hc T =0 ···(8)

[0185] In equation (8), c represents a row vector as a codeword (LDPC code), and c T represents the transpose of the row vector c.

[0186] Here, as described above, in the row vector c as an LDPC code (one code word), when the information bit portion is represented by row vector A and the parity bit portion is represented by row vector T, the row vector c can be expressed by the formula c = [A|T] using the row vector A as the information bit and the row vector T as the parity bit.

[0187] The check matrix H and the row vector c=[A|T] as the LDPC code are expressed by the formula Hc T = 0, and the formula Hc T = 0, the row vector T as the parity bit that constitutes the row vector c=[A|T] is the check matrix H=[H A |H T ]'s parity matrix H T When the step structure shown in Figure 11 is formed, the formula Hc T =0 column vector Hc T It can be calculated sequentially by setting the elements of each row to 0, starting from the elements of the first row.

[0188] The encoding parity calculation unit 615 calculates a parity bit T for the information bit A from the information bit reading unit 614, and outputs the code word c = [A|T] represented by the information bit A and the parity bit T as the LDPC encoding result of the information bit A.

[0189] Thereafter, in step S206, the control unit 616 determines whether or not to end the LDPC encoding. If it is determined in step S206 that the LDPC encoding should not be ended, that is, for example, if there is still LDPC target data to be LDPC encoded, the process returns to step S201 (or step S204), and the processes of steps S201 (or step S204) to S206 are repeated.

[0190] Also, if it is determined in step S206 that the LDPC encoding is to be ended, that is, for example, if there is no LDPC target data to be LDPC encoded, the LDPC encoder 115 ends the process.

[0191] A check matrix initial value table (representing a check matrix) for LDPC codes with various code lengths N and coding rates r can be prepared in advance for the LDPC encoder 115. The LDPC encoder 115 can perform LDPC encoding into LDPC codes with various code lengths N and coding rates r by using a check matrix H generated from the check matrix initial value table prepared in advance.

[0192] <Example of a check matrix initial value table>

[0193] The check matrix initial value table is, for example, an information matrix H corresponding to an information length K according to the code length N and coding rate r of the LDPC code (LDPC code defined by the check matrix H) of the check matrix H. A 10 for each 360 columns (unit size P), and is created in advance for each check matrix H for each code length N and each coding rate r.

[0194] That is, the check matrix initial value table includes at least the information matrix H A The position of the element 1 is represented every 360 columns (unit size P).

[0195] In addition, the check matrix H contains a parity matrix H T All of the check matrices have a staircase structure, and the parity matrix H T There is a check matrix in which a part of it has a staircase structure and the remaining part is a diagonal matrix (identity matrix).

[0196] Below, the parity matrix H T The representation method of the parity check matrix initial value table, which represents a parity check matrix in which a part of the matrix has a staircase structure and the remaining part is a diagonal matrix, is also called the Type A method. TThe representation method of the check matrix initial value table representing the check matrix in which all of the check matrices have a staircase structure is also called Type B method.

[0197] An LDPC code for a parity check matrix indicated by a parity check matrix initial value table of the Type A system is also called a Type A code, and an LDPC code for a parity check matrix indicated by a parity check matrix initial value table of the Type B system is also called a Type B code.

[0198] The designations "Type A" and "Type B" are based on the ATSC 3.0 standard. For example, ATSC 3.0 uses both Type A and Type B codes.

[0199] In addition, DVB-T.2 and the like use Type B coding.

[0200] FIG. 20 is a diagram showing an example of a parity check matrix initial value table of the Type B method.

[0201] That is, Figure 20 shows a check matrix initial value table (representing the check matrix H) for a Type B code (defined in the DVB-T.2 standard) with a code length N of 16,200 bits and a coding rate (the notational coding rate in DVB-T.2) r of 1 / 4.

[0202] The check matrix generation unit 613 (FIG. 18) uses the check matrix initial value table of the Type B method to obtain the check matrix H as follows.

[0203] FIG. 21 is a diagram for explaining a method for obtaining a check matrix H from a check matrix initial value table of the Type B method.

[0204] That is, FIG. 21 shows a check matrix initial value table for a Type B code with a code length N of 16200 bits and a coding rate r of 2 / 3, as defined in the DVB-T.2 standard.

[0205] The check matrix initial value table of the Type B method is an information matrix H corresponding to the information length K according to the code length N and the coding rate r of the LDPC code. AIn the i-th row, the row numbers of the elements of 1 in the 1+360×(i-1)-th column of the check matrix H (the row numbers of the first row of the check matrix H are 0) are listed as the number of column weights of the 1+360×(i-1)-th column.

[0206] Here, the parity matrix H corresponding to the parity length M of the check matrix H of the Type B system is T Since (Fig. 10) is determined to have a staircase structure as shown in Fig. 15, the information matrix H corresponding to the information length K is calculated using the check matrix initial value table. A If (FIG. 10) can be obtained, the check matrix H can be obtained.

[0207] The number of rows k+1 of the check matrix initial value table of the Type B method varies depending on the information length K.

[0208] The relationship of equation (9) holds between the information length K and the number of rows k+1 of the parity check matrix initial value table.

[0209] K = (k + 1) × 360 ···(9)

[0210] Here, 360 in equation (9) is the unit size P explained in FIG.

[0211] In the parity check matrix initial value table of FIG. 21, 13 numerical values ​​are arranged in the first to third rows, and 3 numerical values ​​are arranged in the fourth to k+1th rows (the 30th row in FIG. 21).

[0212] Therefore, the column weight of the check matrix H obtained from the check matrix initial value table of Figure 21 is 13 from the 1st column to the 1+360×(3-1)-1th column, and 3 from the 1+360×(3-1)th column to the Kth column.

[0213] The first row of the parity check matrix initial value table in Figure 21 is 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622, which indicates that in the first column of parity check matrix H, the elements in the rows with row numbers 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622 are 1 (and the other elements are 0).

[0214] In addition, the second row of the parity check matrix initial value table in Figure 21 is 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358,3108, which indicates that in the 361st (=1+360×(2-1))th column of the parity check matrix H, the elements of the rows with row numbers 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358,3108 are 1.

[0215] As described above, the check matrix initial value table is the information matrix H A Represents the position of the 1 element in every 360 columns.

[0216] Columns other than the 1+360×(i-1)th column of the check matrix H, i.e., each column from the 2+360×(i-1)th column to the 360×ith column, are arranged by periodically cyclically shifting the element of 1 in the 1+360×(i-1)th column, which is determined by the check matrix initial value table, downward (downward in the column) according to the parity length M.

[0217] That is, for example, the 2+360×(i-1)th column is the 1+360×(i-1)th column cyclically shifted downward by M / 360(=q), and the next 3+360×(i-1)th column is the 1+360×(i-1)th column cyclically shifted downward by 2×M / 360(=2×q) (the 2+360×(i-1)th column cyclically shifted downward by M / 360(=q)).

[0218] Now, let the value in the ith row (ith from the top) and jth column (jth from the left) of the check matrix initial value table be h i,j and the row number of the j-th element of 1 in the w-th column of the check matrix H is expressed as H w-j Then, the row number H of the element of 1 in the w-th column, which is a column other than the 1+360×(i-1)-th column of the check matrix H, is w-j can be calculated using equation (10).

[0219] H w-j =mod{h i,j +mod((w-1),P)×q,M) ···(10)

[0220] Here, mod(x,y) means the remainder when x is divided by y.

[0221] Furthermore, P is the unit size described above, which in this embodiment is 360, similar to the standards such as DVB-T.2 and ATSC3.0. Furthermore, q is a value M / 360 obtained by dividing the parity length M by the unit size P (=360).

[0222] The check matrix generation unit 613 (FIG. 18) identifies the row number of the element of 1 in the 1+360×(i−1)th column of the check matrix H using the check matrix initial value table.

[0223] Furthermore, the check matrix generation unit 613 (FIG. 18) generates a row number H of an element of 1 in the w-th column, which is a column other than the 1+360×(i−1)-th column of the check matrix H. w-j is calculated according to equation (10), and a check matrix H is generated in which the elements of the row numbers obtained above are set to 1.

[0224] FIG. 22 is a diagram showing the structure of the parity check matrix H of the Type A method.

[0225] The check matrix of the Type A method is made up of an A matrix, a B matrix, a C matrix, a D matrix, and a Z matrix.

[0226] Matrix A is an upper left matrix of parity check matrix H, with M1 rows and K columns, expressed by a predetermined value M1 and information length K of the LDPC code = code length N × coding rate r.

[0227] The B matrix is ​​a step structure matrix adjacent to the A matrix on the right, with M1 rows and M1 columns.

[0228] The C matrix is ​​a matrix adjacent below the A and B matrices, with N−M1 rows and K+M1 columns.

[0229] The D matrix is ​​an identity matrix adjacent to the right of the C matrix, with N-K-M1 rows and N-K-M1 columns.

[0230] The Z matrix is ​​a zero matrix (0 matrix) adjacent to the right of the B matrix, with M1 rows and NK-M1 columns.

[0231] In the type A check matrix H composed of the above-mentioned A matrix to D matrix and Z matrix, part of A matrix and C matrix constitutes the information matrix, and the remaining parts of B matrix, C matrix, D matrix and Z matrix constitute the parity matrix.

[0232] Since the B matrix is ​​a matrix with a staircase structure and the D matrix is ​​a unit matrix, part of the parity matrix of the check matrix H of the Type A method (the B matrix part) has a staircase structure, and the remaining part (the D matrix part) is a diagonal matrix (unit matrix).

[0233] Like the information matrix of the check matrix H of the Type B method, the A matrix and the C matrix have a cyclic structure with a unit size of P (for example, 360 columns) for each column, and the check matrix initial value table of the Type A method represents the positions of elements of 1 in the A matrix and the C matrix for each 360 columns.

[0234] Here, as mentioned above, the A matrix and a part of the C matrix constitute an information matrix, so it can be said that the Type A method check matrix initial value table, which represents the positions of elements of 1 in the A matrix and the C matrix every 360 columns, at least represents the positions of elements of 1 in the information matrix every 360 columns.

[0235] In addition, since the Type A method check matrix initial value table represents the positions of elements of 1 in the A matrix and C matrix every 360 columns, it can also be said that it represents the positions of elements of 1 in a part of the check matrix (the remaining part of the C matrix) every 360 columns.

[0236] FIG. 23 is a diagram showing an example of a parity check matrix initial value table of the Type A method.

[0237] That is, FIG. 23 shows an example of a parity check matrix initial value table that represents a parity check matrix H with a code length N of 35 bits and a coding rate r of 2 / 7.

[0238] The Type A method check matrix initial value table is a table that represents the positions of elements of 1 in the A matrix and the C matrix for each unit size P, and in its i-th row, the row numbers of elements of 1 in the 1+P×(i-1)th column of the check matrix H (row numbers where the row number of the first row of the check matrix H is 0) are arranged as many times as the column weight of the 1+P×(i-1)th column.

[0239] For ease of explanation, it is assumed here that the unit size P is, for example, 5.

[0240] The check matrix H of the Type A system has parameters M1, M2, Q1, and Q2.

[0241] M1 (FIG. 22) is a parameter that determines the size of the B matrix, and takes a value that is a multiple of the unit size P. By adjusting M1, the performance of the LDPC code changes, and when determining the check matrix H, it is adjusted to a predetermined value. Here, it is assumed that 15, which is three times the unit size P=5, is adopted as M1.

[0242] M2 (FIG. 22) is the value M-M1 obtained by subtracting M1 from the parity length M.

[0243] Here, the information length K is N×r=35×2 / 7=10, and the parity length M is NK=35−10=25, so M2 is M−M1=25−15=10.

[0244] Q1 is calculated according to the formula Q1=M1 / P, and represents the number of cyclic shifts (number of rows) in the A matrix.

[0245] That is, the columns other than the 1+P×(i-1)th column of the A matrix of the check matrix H of the Type A method, i.e., each column from the 2+P×(i-1)th column to the P×ith column, are arranged by periodically cyclically shifting the element of 1 in the 1+P×(i-1)th column determined by the check matrix initial value table downward (downward in the column), and Q1 represents the number of cyclic shifts in the A matrix.

[0246] Q2 is calculated according to the formula Q2=M2 / P, and represents the number of cyclic shifts (number of rows) in the C matrix.

[0247] That is, the columns other than the 1+P×(i-1)th column of the C matrix of the check matrix H of the Type A method, i.e., each column from the 2+P×(i-1)th column to the P×ith column, are arranged by periodically cyclically shifting the element of 1 in the 1+P×(i-1)th column determined by the check matrix initial value table downward (downward in the column), and Q2 represents the number of cyclic shifts in the C matrix.

[0248] Here, Q1 is M1 / P=15 / 5=3, and Q2 is M2 / P=10 / 5=2.

[0249] In the parity check matrix initial value table of Figure 23, three numerical values ​​are arranged in the first and second rows, and one numerical value is arranged in the third to fifth rows. According to this arrangement of numerical values, the column weight of the A matrix and C matrix portion of the parity check matrix H obtained from the parity check matrix initial value table of Figure 23 is 3 from the 1=1+5×(1-1)th column to the 10=5×2nd column, and is 1 from the 11=1+5×(3-1)th column to the 25=5×5th column.

[0250] That is, the first row of the check matrix initial value table in Figure 23 is 2, 6, 18, which indicates that in the first column of the check matrix H, the elements in the rows with row numbers 2, 6, 18 are 1 (and the other elements are 0).

[0251] In this case, the A matrix (Figure 22) is a matrix with 15 rows and 10 columns (M1 rows and K columns), and the C matrix (Figure 22) is a matrix with 10 rows and 25 columns (NK-M1 rows and K+M1 columns), so the rows with row numbers 0 to 14 of the check matrix H are rows of the A matrix, and the rows with row numbers 15 to 24 of the check matrix H are rows of the C matrix.

[0252] Therefore, of the rows with row numbers 2, 6, and 18 (hereinafter referred to as rows #2, #6, and #18), rows #2 and #6 are rows of the A matrix, and row #18 is a row of the C matrix.

[0253] The second row of the parity check matrix initial value table in Figure 23 is 2, 10, 19, which indicates that the elements of rows #2, #10, and #19 in the 6th (=1+5×(2-1)) column of parity check matrix H are 1.

[0254] Here, in the 6th (=1+5×(2−1)) column of parity check matrix H, of rows #2, #10, and #19, rows #2 and #10 are rows of the A matrix, and row #19 is a row of the C matrix.

[0255] The third row of the parity check matrix initial value table in FIG. 23 is 22, which indicates that the element of row #22 in the 11th (=1+5×(3−1)) column of parity check matrix H is 1.

[0256] Here, in the 11th (=1+5×(3−1)) column of the parity check matrix H, row #22 is a row of the C matrix.

[0257] Similarly, the 19 in the fourth row of the parity check matrix initial value table of Figure 23 indicates that the element of row #19 in the 16th (=1+5×(4-1)) column of the parity check matrix H is 1, and the 15 in the fifth row of the parity check matrix initial value table of Figure 23 indicates that the element of row #15 in the 21st (=1+5×(5-1)) column of the parity check matrix H is 1.

[0258] As described above, the parity check matrix initial value table indicates the positions of elements of 1 in the A matrix and C matrix of the parity check matrix H for each unit size P=5 columns.

[0259] Columns other than the 1+5×(i-1)th column of the A matrix and C matrix of the check matrix H, i.e., each column from the 2+5×(i-1)th column to the 5×ith column, are arranged by periodically cyclically shifting the element of 1 in the 1+5×(i-1)th column determined by the check matrix initial value table downward (downward in the column direction) according to parameters Q1 and Q2.

[0260] That is, for example, the 2+5×(i-1)th column of matrix A is the 1+5×(i-1)th column cyclically shifted downward by Q1 (=3), and the next 3+5×(i-1)th column is the 1+5×(i-1)th column cyclically shifted downward by 2×Q1 (=2×3) (the 2+5×(i-1)th column cyclically shifted downward by Q1).

[0261] For example, the 2+5×(i-1)th column of matrix C is the 1+5×(i-1)th column cyclically shifted downward by Q2 (=2), and the next 3+5×(i-1)th column is the 1+5×(i-1)th column cyclically shifted downward by 2×Q2 (=2×2) (the 2+5×(i-1)th column cyclically shifted downward by Q2).

[0262] FIG. 24 is a diagram showing matrix A generated from the check matrix initial value table of FIG.

[0263] In matrix A in FIG. 24, elements of rows #2 and #6 in the 1st (=1+5×(1−1))th column are 1, in accordance with the first row of the parity check matrix initial value table in FIG.

[0264] Each of the columns from the 2nd (=2+5×(1-1)) to the 5th (=5+5×(1-1)) is a cyclic shift of the previous column downward by Q1=3.

[0265] Furthermore, in matrix A in FIG. 24, elements of rows #2 and #10 in the 6th (=1+5×(2−1)) column are 1, in accordance with the second row of the parity check matrix initial value table in FIG.

[0266] Each column from the 7th (=2+5×(2-1)) column to the 10th (=5+5×(2-1)) column is cyclically shifted downward by Q1=3 from the previous column.

[0267] FIG. 25 is a diagram showing parity interleaving of a B matrix.

[0268] The check matrix generation unit 613 (FIG. 18) uses a check matrix initial value table to generate matrix A, and places matrix B of a staircase structure to the immediate right of matrix A. Then, the check matrix generation unit 613 regards matrix B as a parity matrix, and performs parity interleaving so that adjacent elements of 1 in matrix B of the staircase structure are spaced apart by unit size P=5 in the row direction.

[0269] FIG. 25 shows the A and B matrices after parity interleaving of the B matrix of FIG.

[0270] FIG. 26 is a diagram showing a C matrix generated from the parity check matrix initial value table of FIG.

[0271] In matrix C in FIG. 26, the element in row #18 of the 1st (=1+5×(1−1))th column of parity check matrix H is 1, in accordance with the first row of the parity check matrix initial value table in FIG.

[0272] Each column from the 2nd (=2+5×(1-1)) to the 5th (=5+5×(1-1)) column of the C matrix is ​​a cyclic shift of the previous column downward by Q2=2.

[0273] Furthermore, in matrix C of Figure 26, in accordance with rows 2 to 5 of the parity check matrix initial value table of Figure 23, the elements of row #19 in the 6th (=1+5×(2-1)) column, row #22 in the 11th (=1+5×(3-1)) column, row #19 in the 16th (=1+5×(4-1)) column, and row #15 in the 21st (=1+5×(5-1)) column of parity check matrix H are 1.

[0274] Each of the columns from the 7th (=2+5×(2-1)) to the 10th (=5+5×(2-1)) columns, the 12th (=2+5×(3-1)) to the 15th (=5+5×(3-1)) columns, the 17th (=2+5×(4-1)) to the 20th (=5+5×(4-1)) columns, and the 22nd (=2+5×(5-1)) to the 25th (=5+5×(5-1)) columns are cyclically shifted downward by Q2=2 from the previous column.

[0275] The check matrix generation section 613 (FIG. 18) generates the C matrix using the check matrix initial value table, and places the C matrix below the A matrix and the B matrix (after parity interleaving).

[0276] Furthermore, parity check matrix generation section 613 places matrix Z to the right of matrix B, and matrix D to the right of matrix C, thereby generating parity check matrix H shown in FIG.

[0277] FIG. 27 is a diagram illustrating parity interleaving of a D matrix.

[0278] After generating the check matrix H of FIG. 26, the check matrix generation unit 613 regards the D matrix as a parity matrix and performs parity interleaving (of only the D matrix) so that elements of 1 in the odd-numbered rows and the next even-numbered rows of the unit matrix D matrix are spaced apart by unit size P=5 in the row direction.

[0279] FIG. 27 shows the parity check matrix H after D matrix parity interleaving is performed on the parity check matrix H of FIG.

[0280] The LDPC encoder 115 (the encoding parity calculation unit 615 (FIG. 18)) performs LDPC encoding (generation of LDPC code) using, for example, the check matrix H in FIG.

[0281] Here, the LDPC code generated using the parity check matrix H of Fig. 27 is an LDPC code that has been parity interleaved, and therefore, for the LDPC code generated using the parity check matrix H of Fig. 27, there is no need to perform parity interleaving in the parity interleaver 23 (Fig. 9). In other words, the LDPC code generated using the parity check matrix H after parity interleaving of the D matrix is ​​an LDPC code that has been parity interleaved, and therefore, for such an LDPC code, parity interleaving in the parity interleaver 23 is skipped.

[0282] FIG. 28 is a diagram showing a check matrix H in which column permutation is performed on the B matrix, part of the C matrix (the part of the C matrix that is arranged below the B matrix), and the D matrix of the check matrix H in FIG. 27 as parity deinterleaving that restores the parity interleaving to its original state.

[0283] The LDPC encoder 115 can perform LDPC encoding (generation of LDPC codes) using the parity check matrix H in FIG.

[0284] When LDPC coding is performed using the check matrix H in Fig. 28, an LDPC code that is not parity interleaved is obtained by the LDPC coding. Therefore, when LDPC coding is performed using the check matrix H in Fig. 28, parity interleaving is performed in the parity interleaver 23 (Fig. 9).

[0285] FIG. 29 is a diagram showing a transformed parity check matrix H obtained by performing row permutation on the parity check matrix H of FIG.

[0286] As will be described later, the conversion check matrix is ​​a matrix expressed by a combination of a P×P unit matrix, a quasi-unit matrix in which one or more of the 1's in the unit matrix are changed to 0, a shift matrix obtained by cyclically shifting a unit matrix or quasi-unit matrix, a sum matrix which is the sum of two or more of a unit matrix, a quasi-unit matrix, or a shift matrix, and a P×P 0 matrix.

[0287] By using the conversion check matrix for decoding an LDPC code, an architecture can be adopted in which P check node operations and variable node operations are performed simultaneously, as will be described later, in decoding the LDPC code.

[0288] <New LDPC code>

[0289] In data transmission using LDPC codes, one method for ensuring good communication quality is to use high-performance LDPC codes.

[0290] A new LDPC code with good performance (hereinafter also referred to as a new LDPC code) will be described below.

[0291] As the new LDPC code, for example, a type A code or type B code can be adopted in which the unit size P is 360, which is the same as that of DVB-T.2, ATSC3.0, etc., and which corresponds to a check matrix H with a cyclic structure.

[0292] The LDPC encoder 115 (FIGS. 8 and 18) can perform LDPC encoding into a new LDPC code using a check matrix initial value table (a check matrix H obtained from) of a new LDPC code in which the code length N is longer than 64 k bits, for example, 69120 bits, and the coding rate r is, for example, any of 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, or 14 / 16, as shown below.

[0293] In this case, a check matrix initial value table for the new LDPC code is stored in the storage unit 602 of the LDPC encoder 115 (FIG. 8).

[0294] FIG. 30 is a diagram showing an example of a check matrix initial value table (for the Type A method) that represents the check matrix H of a Type A code (hereinafter also referred to as a Type A code with r=2 / 16) that is a new LDPC code having a code length N of 69120 bits and a coding rate r of 2 / 16.

[0295] 31 and 32 are diagrams showing examples of check matrix initial value tables representing a check matrix H of a Type A code (hereinafter also referred to as a Type A code with r=3 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 3 / 16.

[0296] FIG. 32 is a continuation of FIG.

[0297] FIG. 33 is a diagram showing an example of a check matrix initial value table representing a check matrix H of a Type A code (hereinafter also referred to as a Type A code with r=4 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 4 / 16.

[0298] 34 and 35 are diagrams showing examples of check matrix initial value tables representing a check matrix H of a Type A code (hereinafter also referred to as a Type A code with r=5 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 5 / 16.

[0299] FIG. 35 is a continuation of FIG.

[0300] 36 and 37 are diagrams showing examples of check matrix initial value tables representing a check matrix H of a Type A code (hereinafter also referred to as a Type A code with r=6 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 6 / 16.

[0301] FIG. 37 is a continuation of FIG.

[0302] 38 and 39 are diagrams showing examples of check matrix initial value tables representing check matrix H of a Type A code (hereinafter also referred to as Type A code with r=7 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 7 / 16.

[0303] FIG. 39 is a continuation of FIG.

[0304] 40 and 41 are diagrams showing examples of check matrix initial value tables representing a check matrix H of a Type A code (hereinafter also referred to as a Type A code with r=8 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 8 / 16.

[0305] FIG. 41 is a continuation of FIG.

[0306] 42 and 43 are diagrams showing examples of check matrix initial value tables (for the Type B method) that represent the check matrix H of a Type B code (hereinafter also referred to as a Type B code where r=7 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 7 / 16.

[0307] FIG. 43 is a continuation of FIG.

[0308] 44 and 45 are diagrams showing other examples of the check matrix initial value table representing the check matrix H of the Type B code where r=7 / 16.

[0309] 45 is a diagram following FIG. 44. The type B code with r=7 / 16 obtained from (the check matrix H represented by) the check matrix initial value table in FIG. 44 and FIG. 45 is also referred to as another type B code with r=7 / 16 hereinafter.

[0310] 46 and 47 are diagrams showing examples of check matrix initial value tables representing check matrix H of a Type B code (hereinafter also referred to as Type B code with r=8 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 8 / 16.

[0311] FIG. 47 is a continuation of FIG.

[0312] 48 and 49 are diagrams showing other examples of the check matrix initial value table representing the check matrix H of the Type B code where r=8 / 16.

[0313] Note that Fig. 49 is a diagram following Fig. 48. The Type B code with r=8 / 16 obtained from the parity check matrix initial value tables in Fig. 48 and Fig. 49 will hereinafter also be referred to as another Type B code with r=8 / 16.

[0314] 50, 51, and 52 are diagrams showing examples of check matrix initial value tables representing check matrix H of a Type B code (hereinafter also referred to as Type B code with r=9 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 9 / 16.

[0315] 51 is a continuation of FIG. 50, and FIG. 52 is a continuation of FIG.

[0316] 53, 54, and 55 are diagrams showing other examples of the check matrix initial value table representing the check matrix H of the Type B code where r=9 / 16.

[0317] Note that Figure 54 is a continuation of Figure 53, and Figure 55 is a continuation of Figure 54. The Type B code with r=9 / 16 obtained from the check matrix initial value tables of Figures 53 to 55 will hereinafter also be referred to as other Type B code with r=9 / 16.

[0318] 56, 57, and 58 are diagrams showing examples of check matrix initial value tables representing check matrix H of a Type B code (hereinafter also referred to as Type B code with r=10 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 10 / 16.

[0319] 57 is a continuation of FIG. 56, and FIG. 58 is a continuation of FIG. 57.

[0320] 59, 60, and 61 are diagrams showing other examples of the check matrix initial value table representing the check matrix H of the Type B code where r=10 / 16.

[0321] Note that Fig. 60 is a diagram continuing from Fig. 59, and Fig. 61 is a diagram continuing from Fig. 60. The Type B code with r=10 / 16 obtained from the check matrix initial value tables of Figs. 59 to 61 will hereinafter also be referred to as other Type B code with r=10 / 16.

[0322] 62, 63, and 64 are diagrams showing examples of check matrix initial value tables representing check matrix H of a Type B code (hereinafter also referred to as Type B code with r=11 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 11 / 16.

[0323] 63 is a continuation of FIG. 62, and FIG. 64 is a continuation of FIG. 63.

[0324] 65, 66, and 67 are diagrams showing other examples of the check matrix initial value table representing the check matrix H of the Type B code where r=11 / 16.

[0325] Note that Figure 66 is a diagram continuing from Figure 65, and Figure 67 is a diagram continuing from Figure 66. The Type B code with r=11 / 16 obtained from the check matrix initial value tables of Figures 65 to 67 will hereinafter also be referred to as other Type B code with r=11 / 16.

[0326] 68, 69, and 70 are diagrams showing examples of check matrix initial value tables representing check matrix H of a Type B code (hereinafter also referred to as Type B code with r=12 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 12 / 16.

[0327] 69 is a continuation of FIG. 68, and FIG. 70 is a continuation of FIG. 69.

[0328] 71, 72, and 73 are diagrams showing other examples of the check matrix initial value table representing the check matrix H of the Type B code where r=12 / 16.

[0329] Note that Figure 72 is a diagram continuing from Figure 71, and Figure 73 is a diagram continuing from Figure 72. The Type B code of r=12 / 16 obtained from the check matrix initial value tables of Figures 71 to 73 is also referred to as other Type B code of r=12 / 16 hereinafter.

[0330] 74, 75, and 76 are diagrams showing examples of check matrix initial value tables representing check matrix H of a Type B code (hereinafter also referred to as Type B code with r=13 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 13 / 16.

[0331] 75 is a continuation of FIG. 74, and FIG. 76 is a continuation of FIG.

[0332] 77, 78, and 79 are diagrams showing other examples of the check matrix initial value table representing the check matrix H of the Type B code where r=13 / 16.

[0333] Note that Figure 78 is a continuation of Figure 77, and Figure 79 is a continuation of Figure 78. The Type B code of r=13 / 16 obtained from the check matrix initial value tables of Figures 77 to 79 is also referred to as other Type B code of r=13 / 16 hereinafter.

[0334] 80, 81, and 82 are diagrams showing examples of check matrix initial value tables representing check matrix H of a Type B code (hereinafter also referred to as Type B code with r=14 / 16) as a new LDPC code having a code length N of 69120 bits and a coding rate r of 14 / 16.

[0335] It should be noted that FIG. 81 is a continuation of FIG. 80, and FIG. 82 is a continuation of FIG.

[0336] 83, 84, and 85 are diagrams showing other examples of the check matrix initial value table representing the check matrix H of the Type B code where r=14 / 16.

[0337] Note that Figure 84 is a continuation of Figure 83, and Figure 85 is a continuation of Figure 84. The Type B code of r=14 / 16 obtained from the check matrix initial value tables of Figures 83 to 85 will hereinafter also be referred to as other Type B code of r=14 / 16.

[0338] The new LDPC code is an LDPC code with good performance.

[0339] Here, an LDPC code with good performance is an LDPC code obtained from an appropriate check matrix H.

[0340] An appropriate check matrix H is, for example, a check matrix H that can be used to obtain an LDPC code with low E s / N0 or E b / N o It is a check matrix that satisfies certain conditions and reduces the BER (bit error rate) (and FER (frame error rate)) when transmitted at a signal power to noise power ratio per bit.

[0341] An appropriate check matrix H is, for example, a method for converting LDPC codes obtained from various check matrices that satisfy predetermined conditions into low E s / N o This can be obtained by performing a simulation to measure the BER when transmitting at

[0342] The predetermined conditions that an appropriate check matrix H should satisfy include, for example, that the analysis results obtained by a code performance analysis method called Density Evolution are good, that there is no loop of elements of 1, called cycle 4, and so on.

[0343] Here, the information matrix H A It is known that if elements of 1 are concentrated, as in cycle 4, the decoding performance of the LDPC code deteriorates. For this reason, it is desirable that cycle 4 does not exist in the parity check matrix H.

[0344] In the parity check matrix H, the minimum length of a loop formed by elements of 1 (loop length) is called a girth. The absence of a cycle of 4 means that the girth is greater than 4.

[0345] The predetermined conditions that an appropriate check matrix H should satisfy can be determined appropriately from the viewpoint of improving the decoding performance of the LDPC code, facilitating (simplifying) the decoding process of the LDPC code, and so on.

[0346] 86 and 87 are diagrams for explaining density evolution that obtains analysis results as predetermined conditions that an appropriate parity check matrix H should satisfy.

[0347] Density evolution is a code analysis method that calculates the expected value of the error probability for the entire LDPC code (ensemble) with a code length N of ∞, characterized by a degree sequence (described later).

[0348] For example, in an AWGN channel, if the noise variance is increased from 0, the expected error probability of a certain ensemble is initially 0, but once the noise variance exceeds a certain threshold, it no longer becomes 0.

[0349] According to density evolution, the performance of the ensemble (the appropriateness of the check matrix) can be determined by comparing the threshold of the noise variance (hereinafter referred to as the performance threshold) at which the expected value of the error probability is no longer zero.

[0350] For a specific LDPC code, if the ensemble to which the LDPC code belongs is determined and density evolution is performed on the ensemble, the rough performance of the LDPC code can be predicted.

[0351] Therefore, if an ensemble with good performance is found, an LDPC code with good performance can be found from among the LDPC codes that belong to that ensemble.

[0352] Here, the above-mentioned degree sequence indicates the proportion of variable nodes and check nodes having each weight value with respect to the code length N of the LDPC code.

[0353] For example, a regular (3,6) LDPC code with a coding rate of 1 / 2 belongs to an ensemble characterized by a degree sequence in which all variable nodes have a weight (column weight) of 3 and all check nodes have a weight (row weight) of 6.

[0354] Figure 86 shows the Tanner graph of such an ensemble.

[0355] In the Tanner Bluff of Figure 86, there are N variable nodes, indicated by circles (○) in the figure, which is equal to the code length N, and there are N / 2 check nodes, indicated by squares (□) in the figure, which is equal to the product of the code length N and the coding rate 1 / 2.

[0356] Each variable node is connected to three edges equal to the column weight, so there are a total of 3N edges connecting to the N variable nodes.

[0357] Each check node is connected to six edges, the number of which is equal to the row weight. Therefore, there are a total of 3N edges connected to the N / 2 check nodes.

[0358] Furthermore, in the Tanner graph of Figure 86, there is one interleaver.

[0359] The interleaver randomly rearranges the 3N branches connected to the N variable nodes, and then connects each rearranged branch to one of the 3N branches connected to the N / 2 check nodes.

[0360] There are (3N)! (=(3N) × (3N-1) × × 1) possible permutations of the 3N branches connected to N variable nodes in an interleaver. Therefore, an ensemble characterized by a degree sequence in which all variable nodes have a weight of 3 and all check nodes have a weight of 6 is a set of (3N)! LDPC codes.

[0361] In the simulation to find a high-performance LDPC code (appropriate check matrix), a multi-edge type ensemble was used in density evolution.

[0362] In the multi-edge type, the interleaver through which the branches connected to the variable nodes and the branches connected to the check nodes pass is divided into multiple (multi-edge) sections, which allows for more precise characterization of the ensemble.

[0363] Figure 87 shows an example of a Tanner graph of a multi-edge type ensemble.

[0364] In the Tanner graph of FIG. 87, there are two interleavers: a first interleaver and a second interleaver.

[0365] In addition, in the Tanner graph of Figure 87, there are only v1 variable nodes with one branch connected to the first interleaver and zero branches connected to the second interleaver, only v2 variable nodes with one branch connected to the first interleaver and two branches connected to the second interleaver, and only v3 variable nodes with zero branches connected to the first interleaver and two branches connected to the second interleaver.

[0366] Furthermore, in the Tanner graph of Figure 87, there are only c1 check nodes with two branches connected to the first interleaver and no branches connected to the second interleaver, only c2 check nodes with two branches connected to the first interleaver and two branches connected to the second interleaver, and only c3 check nodes with no branches connected to the first interleaver and three branches connected to the second interleaver.

[0367] Here, density evolution and its implementation are described, for example, in "On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit," by S.Y. Chung, G.D. Forney, T.J. Richardson, and R. Urbane, IEEE Communications Leggers, Vol. 5, No. 2, February 2001.

[0368] In the simulation to find the new LDPC code (check matrix), the BER starts to drop (become smaller) due to the multi-edge type density evolution. b We found an ensemble where the performance threshold, / N0 (signal power to noise power ratio per bit), is below a specified value, and from among the LDPC codes belonging to that ensemble, we selected the LDPC code that reduces the BER when using orthogonal modulation of 1 or more, such as QPSK, as the LDPC code with good performance.

[0369] The new LDPC code (the check matrix initial value table representing the check matrix of the new LDPC code) was obtained by the above simulation.

[0370] Therefore, the new LDPC code can ensure good communication quality in data transmission.

[0371] FIG. 88 is a diagram for explaining column weights of a check matrix H of a type A code as a new LDPC code.

[0372] For the check matrix H of the type A code, as shown in Figure 88, the column weight of the first K1 columns of the A matrix is ​​represented as Y1, the column weight of the subsequent K2 columns of the A matrix is ​​represented as Y2, the column weight of the first K1 columns of the C matrix is ​​represented as X1, the column weight of the subsequent K2 columns of the C matrix is ​​represented as X2, and the column weight of the further subsequent M1 columns of the C matrix is ​​represented as X3.

[0373] Note that K1+K2 is equal to the information length K, and M1+M2 is equal to the parity length M. Therefore, K1+K2+M1+M2 is equal to the code length N=69120 bits.

[0374] In addition, for the check matrix H of the type A code, the column weight of the first to M1-1 columns of the B matrix is ​​2, and the column weight of the M1-th column (the last column) of the B matrix is ​​1. Furthermore, the column weight of the D matrix is ​​1, and the column weight of the Z matrix is ​​0.

[0375] FIG. 89 is a diagram showing parameters of the check matrix H of the type A code (represented by the check matrix initial value tables) of FIGS.

[0376] X1, Y1, K1, X2, Y2, K2, X3, M1, M2 as parameters of check matrix H of type A code for r=2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, and performance thresholds are as shown in Figure 89.

[0377] The parameters X1, Y1, K1 (or K2), X2, Y2, X3, and M1 (or M2) are set so as to further improve the performance (for example, error rate) of the LDPC code.

[0378] FIG. 90 is a diagram for explaining column weights of a check matrix H of a Type B code as a new LDPC code.

[0379] For the check matrix H of the Type B code, as shown in FIG. 90, the column weight of the first to KX1 columns is represented as X1, the column weight of the subsequent KX2 columns is represented as X2, the column weight of the subsequent KY1 columns is represented as Y1, and the column weight of the subsequent KY2 columns is represented as Y2.

[0380] It should be noted that KX1+KX2+KY1+KY2 is equal to the information length K, and KX1+KX2+KY1+KY2+M is equal to the code length N=69120 bits.

[0381] Furthermore, in the parity check matrix H of the type B code, of the last M columns, the column weight of M−1 columns excluding the last column is 2, and the column weight of the last column is 1.

[0382] FIG. 91 is a diagram showing parameters of the check matrix H of the type B code (represented by the check matrix initial value tables) of FIGS.

[0383] The parameters X1, KX1, X2, KX2, Y1, KY1, Y2, KY2, M of the check matrix H for Type B codes of r=7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, 14 / 16 and other Type B codes, and the performance thresholds are as shown in Figure 91.

[0384] The parameters X1, KX1, X2, KX2, Y1, KY1, Y2, and KY2 are set to further improve the performance of the LDPC code.

[0385] The new LDPC code not only achieves a good BER / FER but also achieves a capacity (communication channel capacity) close to the Shannon limit.

[0386] <Constellation>

[0387] 92 to 116 are diagrams showing examples of constellations that can be used in the transmission system of FIG.

[0388] In the transmission system of FIG. 7, for example, a constellation to be used in a MODCOD, which is a combination of a modulation method (MODulation) and an LDPC code (CODe), can be set.

[0389] For a MODCOD of 1, more than one constellation can be set.

[0390] Constellations include UC (Uniform Constellation), in which the signal points are arranged uniformly, and NUC (Non Uniform Constellation), in which the signal points are not arranged uniformly.

[0391] In addition, there are various types of NUCs, such as 1D-NUC (1-dimensional (M 2 There are constellations called 2D-NUC (2-dimensional (QQAM) non-uniform constellation) and 2D-NUC (2-dimensional (QQAM) non-uniform constellation).

[0392] In general, 1D-NUC provides a better BER than UC, and 2D-NUC provides a better BER than 1D-NUC.

[0393] The constellation for a QPSK modulation scheme is UC. For example, UC or 2D-NUC can be used as a constellation for modulation schemes such as 16QAM, 64QAM, and 256QAM, and for example, UC or 1D-NUC can be used as a constellation for modulation schemes such as 1024QAM and 4096QAM.

[0394] In the transmission system of FIG. 7, various constellations that improve the error rate, such as constellations defined in ATSC3.0, DVB-C.2, etc., can be used.

[0395] That is, when the modulation method is QPSK, for example, the same UC can be used for each coding rate r of the LDPC code.

[0396] In addition, when the modulation method is 16QAM, 64QAM, or 256QAM, for example, the same UC can be used for each coding rate r of the LDPC code.Furthermore, when the modulation method is 16QAM, 64QAM, or 256QAM, for example, different 2D-NUCs can be used for each coding rate r of the LDPC code.

[0397] In addition, when the modulation method is 1024QAM or 4096QAM, for example, the same UC can be used for each coding rate r of the LDPC code.Furthermore, when the modulation method is 1024QAM or 4096QAM, for example, different 1D-NUCs can be used for each coding rate r of the LDPC code.

[0398] Here, UC of QPSK is also written as QPSK-UC, and m QAM UC, 2 m Also referred to as QAM-UC. m QAM 1D-NUC and 2D-NUC are respectively m QAM-1D-NUC and 2 m Also written as QAM-2D-NUC.

[0399] Below, we will explain some of the constellations specified in ATSC3.0.

[0400] FIG. 92 is a diagram showing the coordinates of QPSK-UC signal points used for all coding rates of LDPC codes specified in ATSC3.0 when the modulation scheme is QPSK.

[0401] In Figure 92, "Input Data cell y" represents a 2-bit symbol to be mapped to QPSK-UC, and "Constellation point z" represents a 2-bit symbol to be mapped to QPSK-UC. s " is the signal point z s The coordinates of the signal point z s The index s of the signal point z q The index q of the symbol sigma is also used), which represents the discrete time of the symbol (the time interval between one symbol and the next symbol).

[0402] In Figure 92, signal point z s The coordinates of are expressed in the form of complex numbers, and j represents the imaginary unit (√(-1)).

[0403] Figure 93 is a diagram showing the coordinates of 16QAM-2D-NUC signal points used for coding rates r(CR) = 2 / 15, 3 / 15, 4 / 15, 5 / 15, 6 / 15, 7 / 15, 8 / 15, 9 / 15, 10 / 15, 11 / 15, 12 / 15, 13 / 15 of the LDPC code specified in ATSC3.0 when the modulation method is 16QAM.

[0404] In Figure 93, as in Figure 92, signal point z s The coordinates of are expressed in the form of complex numbers, and j represents the imaginary unit.

[0405] In Figure 93, w#k represents the coordinates of the signal point in the first quadrant of the constellation.

[0406] In 2D-NUC, the signal points in the second quadrant of the constellation are arranged at positions obtained by moving the signal points in the first quadrant symmetrically about the Q axis, the signal points in the third quadrant of the constellation are arranged at positions obtained by moving the signal points in the first quadrant symmetrically about the origin, and the signal points in the fourth quadrant of the constellation are arranged at positions obtained by moving the signal points in the first quadrant symmetrically about the I axis.

[0407] Here, the modulation method is 2 m In the case of QAM, m bits are treated as one symbol, and each symbol is mapped to a signal point corresponding to that symbol.

[0408] An m-bit symbol can be, for example, 0 to 2 m It can be expressed as an integer value of -1, but now, b=2 m / 4, 0 to 2 m Symbols y(0), y(1), . . . , y(2 m -1) can be classified into four symbols: y(0) to y(b-1), y(b) to y(2b-1), y(2b) to y(3b-1), and y(3b) to y(4b-1).

[0409] In Figure 93, the suffix k of w#k takes an integer value ranging from 0 to b-1, and w#k represents the coordinates of the signal point corresponding to symbol y(k) ranging from symbol y(0) to y(b-1).

[0410] The coordinates of the constellation point corresponding to symbol y(k+b) in the range of symbols y(b) to y(2b-1) are represented by -conj(w#k), the coordinates of the constellation point corresponding to symbol y(k+2b) in the range of symbols y(2b) to y(3b-1) are represented by conj(w#k), and the coordinates of the constellation point corresponding to symbol y(k+3b) in the range of symbols y(3b) to y(4b-1) are represented by -w#k.

[0411] Here, conj(w#k) represents the complex conjugate of w#k.

[0412] For example, when the modulation method is 16QAM, the m=4-bit symbols y(0), y(1), . . . , y(15) are 4 / 4=4, the symbols are classified into four: y(0) to y(3), y(4) to y(7), y(8) to y(11), and y(12) to y(15).

[0413] Of the symbols y(0) to y(15), for example, symbol y(12) is a symbol y(k+3b)=y(0+3×4) in the range of symbols y(3b) to y(4b−1), where k=0, and therefore the coordinates of the signal point corresponding to symbol y(12) are -w#k=-w0.

[0414] Now, if the coding rate r(CR) of the LDPC code is, for example, 9 / 15, then according to FIG. 93, when the modulation method is 16QAM and the coding rate r is 9 / 15, w0 is 0.2386+j0.5296, and therefore the coordinate −w0 of the signal point corresponding to the symbol y(12) is −(0.2386+j0.5296).

[0415] Figure 94 is a diagram showing an example of the coordinates of 1024QAM-1D-NUC signal points used for coding rates r(CR) = 2 / 15, 3 / 15, 4 / 15, 5 / 15, 6 / 15, 7 / 15, 8 / 15, 9 / 15, 10 / 15, 11 / 15, 12 / 15, 13 / 15 of the LDPC code specified in ATSC3.0 when the modulation method is 1024QAM.

[0416] In FIG. 94, u#k is the signal point z of 1D-NUC. s The real part of the complex number Re(z s ) and imaginary part Im(z s ) and are the components of a vector u=(u0, u1,..., u#V-1) called the position vector. The number V of components u#k of the position vector u is given by the formula V=√(2 m ) / 2.

[0417] FIG. 95 is a diagram showing the relationship between the 1024QAM symbol y and the position vector u (component u#k of the position vector u).

[0418] Now, let's consider the 10-bit symbol y of 1024QAM, starting from its leading bit (most significant bit), as y 0,s ,y 1,s ,y 2,s ,y 3,s ,y 4,s ,y 5,s ,y 6,s ,y 7,s ,y 8,s ,y 9,s This will be expressed as follows.

[0419] A in Figure 95 shows the even-numbered 5 bits of symbol y. 1,s ,y 3,s ,y 5,s ,y 7,s ,y 9,s and the signal point z corresponding to that symbol y s The real part of the coordinates Re(z s ) represents the correspondence with u#k.

[0420] B in Figure 95 shows the odd-numbered 5 bits y of the symbol y. 0,s ,y 2,s ,y 4,s ,y 6,s ,y 8,s and the signal point z corresponding to that symbol y s Imaginary Part Im(z s ) represents the correspondence with u#k.

[0421] 1024QAM 10-bit symbol y=(y 0,s ,y 1,s ,y 2,s ,y 3,s ,y 4,s ,y 5,s ,y 6,s ,y 7,s ,y 8,s ,y 9,s ) is, for example, (0,0,1,0,0,1,1,1,0,0), the odd-numbered 5 bits (y 0,s ,y 2,s,y 4,s ,y 6,s ,y 8,s ) is (0,1,0,1,0), and the even-numbered 5 bits (y 1,s ,y 3,s ,y 5,s ,y 7,s ,y 9,s ) is (0,0,1,1,0).

[0422] In Figure 95A, the even-numbered 5 bits (0,0,1,1,0) are associated with u11, and therefore the signal point z corresponding to the symbol y = (0,0,1,0,0,1,1,1,0,0) s The real part of Re(z s ) becomes u11.

[0423] In Figure 95B, the odd-numbered 5 bits (0,1,0,1,0) are associated with u3, and therefore the signal point z corresponding to the symbol y = (0,0,1,0,0,1,1,1,0,0) s Imaginary Part Im(z s ) becomes u3.

[0424] On the other hand, if the coding rate r of the LDPC code is, for example, 6 / 15, according to the above-mentioned Figure 94, for the 1D-NUC used when the modulation method is 1024QAM and the coding rate of the LDPC code r(CR) = 6 / 15, u3 is 0.1295 and u11 is 0.7196.

[0425] Therefore, the signal point z corresponding to the symbol y=(0,0,1,0,0,1,1,1,0,0) s The real part of Re(z s ) becomes u11=0.7196, and the imaginary part Im(z s ) results in u3=0.1295. As a result, the signal point z corresponding to the symbol y=(0,0,1,0,0,1,1,1,0,0) s The coordinates of are expressed as 0.7196+j0.1295.

[0426] In addition, the signal points of 1D-NUC are arranged in a grid pattern on a line parallel to the I axis or a line parallel to the Q axis in the constellation. However, the intervals between signal points are not constant. In addition, when transmitting the signal points (data mapped to them), the average power of the signal points on the constellation can be normalized. Normalization is performed by taking the root mean square of the absolute values ​​of all the signal points (coordinates of the signal points) on the constellation as P ave Then, the mean square value P ave Square root of √P ave The reciprocal of 1 / (√P ave ) for each signal point z on the constellation s This can be done by multiplying

[0427] The transmission system of FIG. 7 can use the constellations defined in ATSC 3.0 as described above.

[0428] 96 to 107 are diagrams showing the coordinates of UC signal points defined in DVB-C.2.

[0429] That is, Figure 96 shows the coordinates z of the signal point of QPSK-UC (UC of QPSK) specified in DVB-C.2. q The real part of Re(z q ) is a diagram showing the coordinates z of the signal point of QPSK-UC defined in DVB-C.2. q Imaginary Part Im(z q ) is a diagram showing the same.

[0430] Figure 98 shows the coordinates z of the signal point of 16QAM-UC (UC of 16QAM) specified in DVB-C.2. q The real part of Re(z q ) is a diagram showing the coordinates z of the 16QAM-UC signal point specified in DVB-C.2. q Imaginary Part Im(z q ) is a diagram showing the same.

[0431] Figure 100 shows the coordinates z of the signal point of 64QAM-UC (UC of 64QAM) specified in DVB-C.2. q The real part of Re(z q ) is a diagram showing the coordinates z of the 64QAM-UC signal point specified in DVB-C.2. q Imaginary Part Im(z q ) is a diagram showing the same.

[0432] Figure 102 shows the coordinates z of the signal point of 256QAM-UC (UC of 256QAM) specified in DVB-C.2. q The real part of Re(z q ) is a diagram showing the coordinates z of the 256QAM-UC signal point specified in DVB-C.2. q Imaginary Part Im(z q ) is a diagram showing the same.

[0433] Figure 104 shows the coordinates z of the signal point of 1024QAM-UC (UC of 1024QAM) specified in DVB-C.2. q The real part of Re(z q ) is a diagram showing the coordinates z of the 1024QAM-UC signal point specified in DVB-C.2. q Imaginary Part Im(z q ) is a diagram showing the same.

[0434] Figure 106 shows the coordinates z of the signal point of 4096QAM-UC (UC of 4096QAM) specified in DVB-C.2. q The real part of Re(z q ) is a diagram showing the coordinates z of the 4096QAM-UC signal point specified in DVB-C.2. q Imaginary Part Im(z q ) is a diagram showing the same.

[0435] In addition, in Figures 96 to 107, y i,q is 2 mIt represents the (i+1)th bit from the beginning of the m-bit QAM symbol (for example, 2 bits in QPSK). In addition, when transmitting (data mapped to) a UC signal point, the average power of the signal point on the constellation can be normalized. Normalization is performed by taking the root mean square of the absolute value of all of the signal points (coordinates of the signal points) on the constellation as P ave Then, the mean square value P ave Square root of √P ave The reciprocal of 1 / (√P ave ) for each signal point z on the constellation q This can be done by multiplying

[0436] In the transmission system of FIG. 7, the UC defined in DVB-C.2 as described above can be used.

[0437] That is, for the new LDPC codes (corresponding to the check matrix initial value tables) in Figures 30 to 85 where the code length N is 69120 bits and the coding rate r is 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, and 14 / 16, the UCs shown in Figures 96 to 107 can be used.

[0438] Figures 108 to 116 are diagrams showing examples of coordinates of other NUC signal points that can be used for the new LDPC codes in Figures 30 to 85, where the code length N is 69120 bits and the coding rate r is 2 / 16, 3 / 16, 4 / 16, 5 / 16, 6 / 16, 7 / 16, 8 / 16, 9 / 16, 10 / 16, 11 / 16, 12 / 16, 13 / 16, and 14 / 16.

[0439] That is, FIG. 108 is a diagram showing examples of coordinates of signal points of 16QAM-2D-NUC that can be used for each of the new LDPC codes with a code length N of 69120 bits and a coding rate r(CR) of 2 / 16, 4 / 16, 6 / 16, 8 / 16, 10 / 16, 12 / 16, and 14 / 16, among the new LDPC codes of FIGS. 30 to 85.

[0440] FIG. 109 is a diagram showing examples of coordinates of 64QAM-2D-NUC signal points that can be used for the new LDPC codes of FIGS. 30 to 85, each having a code length N of 69120 bits and a coding rate r of 3 / 16, 5 / 16, 7 / 16, 9 / 16, 11 / 16, and 13 / 16.

[0441] 110 and 111 are diagrams showing examples of coordinates of signal points of 256QAM-2D-NUC that can be used for the new LDPC codes of FIGS. 30 to 85, each having a code length N of 69120 bits and a coding rate r of 2 / 16, 4 / 16, 6 / 16, 8 / 16, 10 / 16, 12 / 16, and 14 / 16.

[0442] Note that FIG. 111 is a continuation of FIG.

[0443] In Figures 108 to 111, similarly to Figure 93, signal point z s The coordinates of are expressed in the form of complex numbers, and j represents the imaginary unit.

[0444] 108 to 111, w#k represents the coordinates of the signal point in the first quadrant of the constellation, as in FIG. 93.

[0445] Here, as explained in FIG. 93, the m-bit symbol is divided into 0 to 2 m It is expressed as an integer value of -1, and b=2 m / 4, 0 to 2 m Symbols y(0), y(1), . . . , y(2 m -1) can be classified into four symbols: y(0) to y(b-1), y(b) to y(2b-1), y(2b) to y(3b-1), and y(3b) to y(4b-1).

[0446] In Figures 108 to 111, as in Figure 93, the suffix k of w#k takes an integer value ranging from 0 to b-1, and w#k represents the coordinates of the signal point corresponding to symbol y(k) ranging from symbol y(0) to y(b-1).

[0447] Furthermore, in Figures 108 to 111, as in Figure 93, the coordinates of the signal point corresponding to symbol y(k+3b) in the range of symbols y(3b) to y(4b-1) are expressed as -w#k.

[0448] However, in Figure 93, the coordinates of the signal point corresponding to symbol y(k+b) in the range of symbols y(b) to y(2b-1) are represented by -conj(w#k), and the coordinates of the signal point corresponding to symbol y(k+2b) in the range of symbols y(2b) to y(3b-1) are represented by conj(w#k), but in Figures 108 to 111, the sign of conj is reversed.

[0449] That is, in Figures 108 to 111, the coordinates of the signal point corresponding to symbol y(k+b) in the range of symbols y(b) to y(2b-1) are represented by conj(w#k), and the coordinates of the signal point corresponding to symbol y(k+2b) in the range of symbols y(2b) to y(3b-1) are represented by -conj(w#k).

[0450] FIG. 112 is a diagram showing examples of coordinates of 1024QAM-1D-NUC signal points that can be used for the new LDPC codes of FIGS. 30 to 85, each having a code length N of 69120 bits and a coding rate r of 3 / 16, 5 / 16, 7 / 16, 9 / 16, 11 / 16, and 13 / 16.

[0451] That is, FIG. 112 shows the signal point z of 1024QAM-1D-NUC. s The real part of the complex number Re(z s ) and imaginary part Im(z s ) and the position vector u (its component u#k).

[0452] FIG. 113 is a diagram showing the relationship between the 1024QAM symbol y and the position vector u (component u#k) of FIG.

[0453] That is, let us now consider a 10-bit symbol y of 1024QAM, starting from its leading bit (most significant bit), as y 0,s ,y 1,s ,y 2,s ,y 3,s ,y 4,s ,y 5,s ,y 6,s ,y 7,s ,y 8,s ,y 9,s This will be expressed as follows.

[0454] A in Figure 113 shows the odd-numbered 5 bits y of the 10-bit symbol y. 0,s ,y 2,s ,y 4,s ,y 6,s ,y 8,s and the signal point z corresponding to that symbol y s (coordinates) real part Re(z s ) and the position vector u#k.

[0455] B in Figure 113 shows the even-numbered 5 bits y of the 10-bit symbol y. 1,s ,y 3,s ,y 5,s ,y 7,s ,y 9,s and the signal point z corresponding to that symbol y s Imaginary Part Im(z s ) and the position vector u#k.

[0456] The 10-bit symbol y of 1024QAM corresponds to the signal point z of 1024QAM-1D-NUC defined in Figures 112 and 113. s When the signal point z is mapped to s The method for determining the coordinates is the same as that explained in FIGS. 94 and 95, so the explanation will be omitted.

[0457] FIG. 114 is a diagram showing examples of coordinates of 4096QAM-1D-NUC signal points that can be used for the new LDPC codes of FIGS. 30 to 85, each having a code length N of 69120 bits and a coding rate r of 2 / 16, 4 / 16, 6 / 16, 8 / 16, 10 / 16, 12 / 16, and 14 / 16.

[0458] That is, FIG. 114 shows the signal point z of 4096QAM-1D-NUC. s The real part of the complex number Re(z s ) and imaginary part Im(z s ) and the position vector u(u#k).

[0459] 115 and 116 are diagrams showing the relationship between the 4096QAM symbol y and the position vector u (component u#k) of FIG. 114.

[0460] That is, let us now consider a 12-bit symbol y of 4096QAM, starting from its leading bit (most significant bit), as y 0,s ,y 1,s ,y 2,s ,y 3,s ,y 4,s ,y 5,s ,y 6,s ,y 7,s ,y 8,s ,y 9,s ,y 10,s ,y 11,s This will be expressed as follows.

[0461] Figure 115 shows the odd-numbered 6 bits y of the 12-bit symbol y. 0,s ,y 2,s ,y 4,s ,y 6,s ,y 8,s ,y 10,s and the signal point z corresponding to that symbol y s The real part of Re(z s ) and the position vector u#k.

[0462] Figure 116 shows the even-numbered 6 bits y of the 12-bit symbol y.1,s ,y 3,s ,y 5,s ,y 7,s ,y 9,s ,y 11,s and the signal point z corresponding to that symbol y s Imaginary Part Im(z s ) and the position vector u#k.

[0463] The 12-bit symbol y of 4096QAM corresponds to the signal point z of 4096QAM-1D-NUC defined in Figures 114 to 116. s When the signal point z is mapped to s The method for determining the coordinates is the same as that explained in FIGS. 94 and 95, so the explanation will be omitted.

[0464] When transmitting the NUC signal points (data mapped to them) in Figures 108 to 116, the average power of the signal points on the constellation can be normalized. Normalization is performed by taking the root mean square of the absolute values ​​of all the signal points (coordinates) on the constellation as P ave Then, the mean square value P ave Square root of √P ave The reciprocal of 1 / (√P ave ) for each signal point z on the constellation s In addition, in FIG. 95, odd-numbered bits of symbol y are multiplied by signal point z. s Imaginary Part Im(z s ) and the even-numbered bits of the symbol y correspond to the signal point z s The real part of Re(z s ), but in Figures 113, 115 and 116, the odd-numbered bits of the symbol y correspond to the signal point z s The real part of Re(z s ) and the even-numbered bits of the symbol y correspond to the signal point z s Imaginary Part Im(z s) is associated with a position vector u#k representing the

[0465] <Block Interleaver 25>

[0466] FIG. 117 is a diagram for explaining the block interleaving performed by the block interleaver 25 in FIG.

[0467] Block interleaving is performed by dividing an LDPC code of one codeword into a part called part 1 and a part called part 2, starting from the beginning.

[0468] If the length (number of bits) of part 1 is represented as Npart1 and the length of part 2 is represented as Npart2, then Npart1+Npart2 is equal to the code length N.

[0469] Conceptually, in block interleaving, columns as storage areas for storing Npart1 / m bits are arranged in one direction (vertical) as a column direction, and m columns, which is equal to the number of bits m of a symbol, are arranged in a row direction perpendicular to the column direction, and each column is divided from the top into small units of 360 bits, which is the unit size P. These small units of columns are also called column units.

[0470] In block interleaving, as shown in Figure 117, part 1 of the LDPC code of one codeword is written from top to bottom (column direction) in the first column unit of the column, moving from left to right towards the column.

[0471] Then, when writing to the first column unit of the rightmost column is completed, as shown in Figure 117, it returns to the leftmost column and writing from top to bottom of the second column unit of the column is performed from left to right column, and so on, and so on, writing part 1 of one codeword LDPC code is performed.

[0472] When writing of part 1 of the LDPC code of one codeword is completed, part 1 of the LDPC code is read out in m-bit units in the row direction from the first row of all m columns, as shown in FIG.

[0473] The m-bit units of part 1 are supplied as m-bit symbols from block interleaver 25 to mapper 117 (FIG. 8).

[0474] Part 1 is read out in m-bit units sequentially moving down the m columns, and when reading of part 1 is completed, part 2 is divided into m-bit units from the beginning and supplied as m-bit symbols from block interleaver 25 to mapper 117.

[0475] Therefore, part 1 is symbolized while being interleaved, and part 2 is symbolized sequentially, separated into m bits, without being interleaved.

[0476] The length of the column, Npart1 / m, is a multiple of 360, which is the unit size P, and an LDPC code of one code word is divided into part 1 and part 2 so that Npart1 / m is a multiple of 360.

[0477] FIG. 118 is a diagram showing examples of part 1 and part 2 of an LDPC code with a code length N of 69120 bits when the modulation scheme is QPSK, 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM.

[0478] In Figure 118, when the modulation method is 1024QAM, part 1 is 68,400 bits and part 2 is 720 bits, and when the modulation method is QPSK, 16QAM, 64QAM, 256QAM, or 4096QAM, in all cases part 1 is 69,120 bits and part 2 is 0 bits.

[0479] <Group-wise interleaving>

[0480] FIG. 119 is a diagram for explaining group-wise interleaving performed by the group-wise interleaver 24 in FIG.

[0481] In group-wise interleaving, as shown in FIG. 119, the LDPC code of one codeword is divided into 360-bit units, which is equal to the unit size P, from the beginning, and the 360 ​​bits of each unit are treated as a bit group, and the LDPC code of one codeword is interleaved in bit group units according to a predetermined pattern (hereinafter also referred to as a GW pattern).

[0482] Here, when an LDPC code of one codeword is divided into bit groups, the (i+1)th bit group from the beginning will hereinafter also be referred to as bit group i.

[0483] When the unit size P is 360, for example, an LDPC code with a code length N of 1800 bits is divided into 5 (=1800 / 360) bit groups: bit groups 0, 1, 2, 3, and 4. Furthermore, for example, an LDPC code with a code length N of 69120 bits is divided into 192 (=69120 / 360) bit groups: bit groups 0, 1, . . . , 191.

[0484] In the following, the GW pattern will be represented by a sequence of numbers representing the bit group. For example, for an LDPC code with a code length N of 1800 bits, a GW pattern of 4,2,0,3,1 indicates that the sequence of bit groups 0,1,2,3,4 is interleaved (rearranged) into the sequence of bit groups 4,2,0,3,1.

[0485] For example, let us consider the i+1th code bit from the beginning of an LDPC code whose code length N is 1800 bits as x i Let us express it as:

[0486] In this case, according to the group-wise interleaving of GW pattern 4,2,0,3,1, the 1800-bit LDPC code {x0,x1,...,x1799}, which is {x 1440 , x 1441 ,..., x 1799}, {x 720 , x 721 ,..., x 1079}, {x0, x1,..., x 359}, {x 1080 , x 1081 ,..., x 1439}, {x 360 , x 361 ,..., x 719} are interleaved in the order.

[0487] The GW pattern can be set for each code length N of the LDPC code, for each coding rate r, for each modulation method, for each constellation, and further for each combination of two or more of the code length N, coding rate r, modulation method, and constellation.

[0488] <Example of GW Pattern for LDPC Code>

[0489] Figure 120 is a diagram showing a first example of the GW pattern for an LDPC code with a code length N of 69120 bits.

[0490] According to the GW pattern in Figure 120, the order of bit groups 0 to 191 of the 69120-bit LDPC code is the bit group 12, 8, 132, 26, 3, 18, 19, 98, 37, 190, 123, 81, 95, 167, 76, 66, 27, 46, 105, 28, 29, 170, 20, 96, 35, 177, 24, 86, 114, 63, 52, 80, 119, 153, 121, 107, 97, 129, 57, 38, 15, 91, 122, 14, 104, 175, 150, 1, 124, 72, 90, 32, 161, 78, 44, 73, 134, 162, 5, 11, 179, 93, 6, 152, 180, 68, 36, 103, 160, 100, 138, 146, 9, 82, 187, 147, 7, 87, 17, 102, 69, 110, 130, 42, 16, 71, 2, 169, 58, 33, 136, 106, 140, 84, 79, 143, 156, 139, 55, 116, 4, 21, 144, 64, 70, 158, 48, 118, 184, 50, 181, 120, 174, 133, 115, 53, 127, 74, 25, 49, 88, 22, 89, 34, 126, 61, 94, 172, 131, 39, 99, 183, 163, 111, 155, 51, 191, 31, 128, 149, 56, 85, 109, 10, 151, 188, 40, 83, 41, 47, 178, 186, 43, 54, 164, 13, 142, 117, 92, 113, 182, 168, 165, 101, 171, 159, 60, 166, 77, 30, 67, 23, 0, 65, 141, 185, 112, 145, 135, 108, 176, 45, 148, 137, 125, 62, 75, 189, 59, 173, 154, 157 are interleaved in the sequence.

[0491] FIG. 121 is a diagram showing a second example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0492] According to the GW pattern in FIG. 121, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 14, 119, 182, 5, 127, 21, 152, 11, 39, 164, 25, 69, 59, 140, 73, 9, 104, 148, 77, 44, 138, 89, 184, 35, 112, 150, 178, 26, 123, 133, 91, 76, 70, 0, 176, 118, 22, 147, 96, 108, 109, 139, 18, 157, 181, 126, 174, 179, 116, 38, 45, 158, 106, 168, 10, 97, 114, 129, 180, 52, 7, 67, 43, 50, 120, 122, 3, 13, 72, 185, 34, 83, 124, 105, 162, 87, 131, 155, 135, 42, 64, 165, 41, 71, 189, 159, 143, 102, 153, 17, 24, 30, 66, 137, 62, 55, 48, 98, 110, 40, 121, 187, 74, 92, 60, 101, 57, 33, 130, 173, 32, 166, 128, 54, 99, 111, 100, 16, 84, 132, 161, 4, 190, 49, 95, 141, 28, 85, 61, 53, 183, 6, 68, 2, 163, 37, 103, 186, 154, 171, 170, 78, 117, 93, 8, 145, 51, 56, 191, 90, 82, 151, 115, 175, 1, 125, 79, 20, 80, 36, 169, 46, 167, 63, 177, 149, 81, 12, 156, 142, 31, 47, 88, 65, 134, 94, 86, 160, 172, 19, 23, 136, 58, 146, 15, 75, 107, 188, 29, 113, 144, 27 are interleaved in the sequence.

[0493] FIG. 122 is a diagram illustrating a third example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0494] According to the GW pattern in FIG. 122, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 121, 28, 49, 4, 21, 191, 90, 101, 188, 126, 8, 131, 81, 150, 141, 152, 17, 82, 61, 119, 125, 145, 153, 45, 108, 22, 94, 48, 29, 12, 59, 140, 75, 169, 183, 157, 142, 158, 113, 79, 89, 186, 112, 80, 56, 120, 166, 15, 43, 2, 62, 115, 38, 123, 73, 179, 155, 171, 185, 5, 168, 172, 190, 106, 174, 96, 116, 91, 30, 147, 19, 149, 37, 175, 124, 156, 14, 144, 86, 110, 40, 68, 162, 66, 130, 74, 165, 180, 13, 177, 122, 23, 109, 95, 42, 117, 65, 3, 111, 18, 32, 52, 97, 184, 54, 46, 167, 136, 1, 134, 189, 187, 16, 36, 84, 132, 170, 34, 57, 24, 137, 100, 39, 127, 6, 102, 10, 25, 114, 146, 53, 99, 85, 35, 78, 148, 9, 143, 139, 92, 173, 27, 11, 26, 104, 176, 98, 129, 51, 103, 160, 71, 154, 118, 67, 33, 181, 87, 77, 47, 159, 178, 83, 70, 164, 44, 69, 88, 63, 161, 182, 133, 20, 41, 64, 76, 31, 50, 128, 105, 0, 135, 55, 72, 93, 151, 107, 163, 60, 138, 7, 58 are interleaved in the sequence.

[0495] FIG. 123 is a diagram showing a fourth example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0496] According to the GW pattern in FIG. 123, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 99, 59, 95, 50, 122, 15, 144, 6, 129, 36, 175, 159, 165, 35, 182, 181, 189, 29, 2, 115, 91, 41, 60, 160, 51, 106, 168, 173, 20, 138, 183, 70, 24, 127, 47, 5, 119, 171, 102, 135, 116, 156, 120, 105, 117, 136, 149, 128, 85, 46, 186, 113, 73, 103, 52, 82, 89, 184, 22, 185, 155, 125, 133, 37, 27, 10, 137, 76, 12, 98, 148, 109, 42, 16, 190, 84, 94, 97, 25, 11, 88, 166, 131, 48, 161, 65, 9, 8, 58, 56, 124, 68, 54, 3, 169, 146, 87, 108, 110, 121, 163, 57, 90, 100, 66, 49, 61, 178, 18, 7, 28, 67, 13, 32, 34, 86, 153, 112, 63, 43, 164, 132, 118, 93, 38, 39, 17, 154, 170, 81, 141, 191, 152, 111, 188, 147, 180, 75, 72, 26, 177, 126, 179, 55, 1, 143, 45, 21, 40, 123, 23, 162, 77, 62, 134, 158, 176, 31, 69, 114, 142, 19, 96, 101, 71, 30, 140, 187, 92, 80, 79, 0, 104, 53, 145, 139, 14, 33, 74, 157, 150, 44, 172, 151, 64, 78, 130, 83, 167, 4, 107, 174 are interleaved in the sequence.

[0497] FIG. 124 is a diagram illustrating a fifth example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0498] According to the GW pattern in FIG. 124, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 170, 45, 67, 94, 110, 153, 19, 38, 112, 176, 49, 138, 35, 114, 184, 159, 17, 41, 47, 189, 65, 125, 154, 57, 83, 6, 97, 167, 51, 59, 23, 81, 54, 46, 168, 178, 148, 5, 122, 129, 155, 179, 95, 102, 8, 119, 29, 113, 14, 60, 43, 66, 55, 103, 111, 88, 56, 7, 118, 63, 134, 108, 61, 187, 124, 31, 133, 22, 79, 52, 36, 144, 89, 177, 40, 116, 121, 135, 163, 92, 117, 162, 149, 106, 173, 181, 11, 164, 185, 99, 18, 158, 16, 12, 48, 9, 123, 147, 145, 169, 130, 183, 28, 151, 71, 126, 69, 165, 21, 13, 15, 62, 80, 182, 76, 90, 180, 50, 127, 131, 109, 3, 115, 120, 161, 82, 34, 78, 128, 142, 136, 75, 86, 137, 26, 25, 44, 91, 42, 73, 140, 146, 152, 27, 101, 93, 20, 166, 171, 100, 70, 84, 53, 186, 24, 98, 4, 37, 141, 190, 68, 150, 1, 72, 39, 87, 188, 191, 156, 33, 30, 160, 143, 64, 132, 77, 0, 58, 174, 157, 105, 175, 10, 172, 104, 2, 96, 139, 32, 85, 107, 74 are interleaved in the sequence.

[0499] FIG. 125 is a diagram illustrating a sixth example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0500] According to the GW pattern in FIG. 125, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 111, 156, 189, 11, 132, 114, 100, 154, 77, 79, 95, 161, 47, 142, 36, 98, 3, 125, 159, 120, 40, 160, 29, 153, 16, 39, 101, 58, 191, 46, 76, 4, 183, 176, 62, 60, 74, 7, 37, 127, 19, 186, 71, 50, 139, 27, 188, 113, 38, 130, 124, 26, 146, 131, 102, 110, 105, 147, 86, 150, 94, 162, 175, 88, 104, 55, 89, 181, 34, 69, 22, 92, 133, 1, 25, 0, 158, 10, 24, 116, 164, 165, 112, 72, 106, 129, 81, 66, 54, 49, 136, 118, 83, 41, 2, 56, 145, 28, 177, 168, 117, 9, 157, 173, 115, 149, 42, 103, 14, 84, 155, 187, 99, 6, 43, 70, 140, 73, 32, 78, 75, 167, 148, 48, 134, 178, 59, 15, 63, 91, 82, 33, 135, 166, 190, 152, 96, 137, 12, 182, 61, 107, 128, 119, 179, 45, 184, 65, 172, 138, 31, 57, 174, 17, 180, 5, 30, 170, 23, 85, 185, 35, 44, 123, 90, 20, 122, 8, 64, 141, 169, 121, 97, 108, 80, 171, 18, 13, 87, 163, 109, 52, 51, 21, 93, 67, 126, 68, 53, 143, 144, 151 are interleaved in the sequence.

[0501] FIG. 126 is a diagram illustrating a seventh example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0502] According to the GW pattern in FIG. 126, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191 are interleaved in the sequence.

[0503] FIG. 127 is a diagram illustrating an eighth example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0504] According to the GW pattern in FIG. 127, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191 are interleaved in the sequence.

[0505] FIG. 128 is a diagram illustrating a ninth example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0506] According to the GW pattern in FIG. 128, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191 are interleaved in the sequence.

[0507] FIG. 129 is a diagram illustrating a tenth example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0508] According to the GW pattern in FIG. 129, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191 are interleaved in the sequence.

[0509] FIG. 130 is a diagram showing an eleventh example of a GW pattern for an LDPC code with a code length N of 69120 bits.

[0510] According to the GW pattern in FIG. 130, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191 are interleaved in the sequence.

[0511] FIG. 131 is a diagram illustrating a twelfth example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0512] According to the GW pattern in Figure 131, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191 are interleaved in the sequence.

[0513] FIG. 132 is a diagram illustrating a thirteenth example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0514] According to the GW pattern in Figure 132, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191 are interleaved in the sequence.

[0515] FIG. 133 is a diagram illustrating a fourteenth example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0516] According to the GW pattern in Figure 133, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 154, 106, 99, 177, 191, 55, 189, 181, 22, 62, 80, 114, 110, 141, 83, 103, 169, 156, 130, 186, 92, 45, 68, 126, 112, 185, 160, 158, 17, 145, 162, 127, 152, 174, 134, 18, 157, 120, 3, 29, 13, 135, 173, 86, 73, 150, 46, 153, 33, 61, 142, 102, 171, 168, 78, 77, 139, 85, 176, 163, 128, 101, 42, 2, 14, 38, 10, 125, 90, 30, 63, 172, 47, 108, 89, 0, 32, 94, 23, 34, 59, 35, 129, 12, 146, 8, 60, 27, 147, 180, 100, 87, 184, 167, 36, 79, 138, 4, 95, 148, 72, 54, 91, 182, 28, 133, 164, 175, 123, 107, 137, 88, 44, 116, 69, 7, 31, 124, 144, 105, 170, 6, 165, 15, 161, 24, 58, 70, 11, 56, 143, 111, 104, 74, 67, 109, 82, 21, 52, 9, 71, 48, 26, 117, 50, 149, 140, 20, 57, 136, 113, 64, 151, 190, 131, 19, 51, 96, 76, 1, 97, 40, 53, 84, 166, 75, 159, 98, 81, 49, 66, 188, 118, 39, 132, 187, 25, 119, 41, 122, 16, 5, 93, 115, 178, 65, 121, 37, 155, 183, 43, 179 are interleaved in the sequence.

[0517] FIG. 134 is a diagram illustrating a fifteenth example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0518] According to the GW pattern in Figure 134, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 1, 182, 125, 0, 121, 47, 63, 154, 76, 99, 82, 163, 102, 166, 28, 189, 56, 67, 54, 39, 40, 185, 184, 65, 179, 4, 91, 87, 137, 170, 98, 71, 169, 49, 73, 37, 11, 143, 150, 123, 93, 62, 3, 50, 26, 140, 178, 95, 183, 33, 21, 53, 112, 128, 118, 120, 106, 139, 32, 130, 173, 132, 156, 119, 83, 176, 159, 13, 145, 36, 30, 113, 2, 41, 147, 174, 94, 88, 92, 60, 165, 59, 25, 161, 100, 85, 81, 61, 138, 48, 177, 77, 6, 22, 16, 43, 115, 23, 12, 66, 70, 9, 164, 122, 58, 105, 69, 42, 38, 19, 24, 180, 175, 74, 160, 34, 101, 72, 114, 142, 20, 8, 15, 190, 144, 104, 79, 172, 148, 31, 168, 10, 107, 14, 35, 52, 134, 126, 167, 149, 116, 186, 17, 162, 151, 5, 136, 55, 44, 110, 158, 46, 191, 29, 153, 155, 117, 188, 131, 97, 146, 103, 78, 109, 129, 57, 111, 45, 68, 157, 84, 141, 89, 64, 7, 108, 152, 75, 18, 96, 133, 171, 86, 181, 127, 27, 124, 187, 135, 80, 51, 90 are interleaved in the sequence.

[0519] FIG. 135 is a diagram illustrating a 16th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0520] According to the GW pattern in Figure 135, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 35, 75, 166, 145, 143, 184, 62, 96, 54, 63, 157, 103, 32, 43, 126, 187, 144, 91, 78, 44, 39, 109, 185, 102, 10, 68, 29, 42, 149, 83, 133, 94, 130, 27, 171, 19, 51, 165, 148, 28, 36, 33, 173, 136, 87, 82, 100, 49, 120, 152, 161, 162, 147, 71, 137, 57, 8, 53, 132, 151, 163, 123, 47, 92, 90, 60, 99, 79, 59, 108, 115, 72, 0, 12, 140, 160, 61, 180, 74, 37, 86, 117, 191, 101, 52, 15, 80, 156, 127, 81, 131, 141, 142, 31, 95, 4, 73, 64, 16, 18, 146, 70, 181, 7, 89, 124, 77, 67, 116, 21, 34, 41, 105, 113, 97, 2, 6, 55, 17, 65, 38, 48, 158, 159, 179, 5, 30, 183, 170, 135, 125, 20, 106, 186, 182, 188, 114, 1, 14, 3, 134, 178, 189, 167, 40, 119, 22, 190, 58, 23, 155, 138, 98, 84, 11, 110, 88, 46, 177, 175, 25, 150, 118, 121, 129, 168, 13, 128, 104, 69, 112, 169, 9, 45, 174, 93, 26, 56, 76, 50, 154, 139, 66, 85, 153, 107, 111, 172, 176, 164, 24, 122 are interleaved in the sequence.

[0521] FIG. 136 is a diagram illustrating a 17th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0522] According to the GW pattern in Figure 136, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 155, 188, 123, 132, 15, 79, 59, 119, 66, 68, 41, 175, 184, 78, 142, 32, 54, 111, 139, 134, 95, 34, 161, 150, 58, 141, 74, 112, 121, 99, 178, 179, 57, 90, 80, 21, 11, 29, 67, 104, 52, 87, 38, 81, 181, 160, 176, 16, 71, 13, 186, 171, 9, 170, 2, 177, 0, 88, 149, 190, 69, 33, 183, 146, 61, 117, 113, 6, 96, 120, 162, 23, 53, 140, 91, 128, 46, 93, 174, 126, 159, 133, 8, 152, 103, 102, 151, 143, 100, 4, 180, 166, 55, 164, 18, 49, 62, 20, 83, 7, 187, 153, 64, 37, 144, 185, 19, 114, 25, 116, 12, 173, 122, 127, 89, 115, 75, 101, 189, 124, 157, 108, 28, 165, 163, 65, 168, 77, 82, 27, 137, 86, 22, 110, 63, 148, 158, 97, 31, 105, 135, 98, 44, 70, 182, 191, 17, 156, 129, 39, 136, 169, 3, 145, 154, 109, 76, 5, 10, 106, 35, 94, 172, 45, 51, 60, 42, 50, 72, 85, 40, 118, 36, 14, 130, 131, 138, 43, 48, 125, 84, 24, 26, 1, 56, 107, 92, 147, 47, 30, 73, 167 are interleaved in the sequence.

[0523] FIG. 137 is a diagram illustrating an 18th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0524] According to the GW pattern in Figure 137, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 152, 87, 170, 33, 48, 95, 2, 184, 145, 51, 94, 164, 38, 90, 158, 70, 124, 128, 66, 111, 79, 42, 45, 141, 83, 73, 57, 119, 20, 67, 31, 179, 123, 183, 26, 188, 15, 163, 1, 133, 105, 72, 81, 153, 69, 182, 101, 180, 185, 190, 77, 6, 127, 138, 75, 59, 24, 175, 30, 186, 139, 56, 100, 176, 147, 189, 116, 131, 25, 5, 16, 117, 74, 50, 171, 114, 76, 44, 107, 135, 71, 181, 13, 43, 122, 78, 4, 58, 35, 63, 187, 98, 37, 169, 148, 7, 10, 49, 80, 161, 167, 28, 142, 46, 97, 92, 121, 112, 88, 102, 106, 173, 19, 27, 41, 172, 91, 191, 34, 118, 108, 136, 166, 155, 96, 3, 165, 103, 84, 109, 104, 53, 23, 0, 178, 17, 86, 9, 168, 134, 110, 18, 32, 146, 129, 159, 55, 154, 126, 40, 151, 174, 60, 52, 22, 149, 156, 113, 143, 11, 93, 62, 177, 64, 61, 160, 150, 65, 130, 82, 29, 115, 137, 36, 8, 157, 54, 89, 99, 120, 68, 21, 140, 14, 39, 132, 125, 12, 85, 162, 47, 144 are interleaved in the sequence.

[0525] FIG. 138 is a diagram illustrating a 19th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0526] According to the GW pattern in Figure 138, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 140, 8, 176, 13, 41, 165, 27, 109, 121, 153, 58, 181, 143, 164, 103, 115, 91, 66, 60, 189, 101, 4, 14, 102, 45, 124, 104, 159, 130, 133, 135, 77, 25, 59, 180, 141, 144, 62, 114, 182, 134, 148, 11, 20, 125, 83, 162, 75, 126, 67, 9, 178, 171, 152, 166, 69, 174, 15, 80, 168, 131, 95, 56, 48, 63, 82, 147, 51, 108, 52, 30, 139, 22, 37, 173, 112, 191, 98, 116, 149, 167, 142, 29, 154, 92, 94, 71, 117, 79, 122, 129, 24, 81, 105, 97, 137, 128, 1, 113, 170, 119, 7, 158, 76, 19, 183, 68, 31, 50, 118, 33, 72, 55, 65, 146, 185, 111, 145, 28, 21, 177, 160, 32, 61, 70, 106, 156, 78, 132, 88, 184, 35, 5, 53, 138, 47, 100, 10, 42, 36, 175, 93, 120, 190, 16, 123, 87, 54, 186, 18, 57, 84, 99, 12, 163, 157, 188, 64, 38, 26, 2, 136, 40, 169, 90, 107, 46, 172, 49, 6, 39, 44, 150, 85, 0, 17, 127, 155, 110, 34, 96, 74, 86, 187, 89, 151, 43, 179, 161, 73, 23, 3 are interleaved in the sequence.

[0527] FIG. 139 is a diagram showing a twentieth example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0528] According to the GW pattern in Figure 139, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 10, 61, 30, 88, 33, 60, 1, 102, 45, 103, 119, 181, 82, 112, 12, 67, 69, 171, 108, 26, 145, 156, 81, 152, 8, 16, 68, 13, 99, 183, 146, 27, 158, 147, 132, 118, 180, 120, 173, 59, 186, 49, 7, 17, 35, 104, 129, 75, 54, 72, 18, 48, 15, 177, 191, 51, 24, 93, 106, 22, 71, 29, 141, 32, 143, 128, 175, 86, 190, 74, 36, 43, 144, 46, 63, 65, 133, 31, 87, 44, 20, 117, 76, 187, 80, 101, 151, 47, 130, 116, 162, 127, 153, 100, 94, 2, 41, 138, 125, 131, 11, 50, 40, 21, 184, 167, 172, 85, 160, 105, 73, 38, 157, 53, 39, 97, 107, 165, 168, 89, 148, 126, 3, 4, 114, 161, 155, 182, 136, 149, 111, 98, 113, 139, 92, 109, 174, 185, 95, 56, 135, 37, 163, 154, 0, 96, 78, 122, 5, 179, 140, 83, 123, 77, 9, 19, 66, 42, 137, 14, 23, 159, 189, 110, 142, 84, 169, 166, 52, 91, 164, 28, 124, 121, 70, 115, 90, 170, 58, 6, 178, 176, 64, 188, 57, 34, 79, 62, 25, 134, 150, 55 are interleaved in the sequence.

[0529] FIG. 140 is a diagram showing a 21st example of a GW pattern for an LDPC code with a code length N of 69120 bits.

[0530] According to the GW pattern in FIG. 140, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 8, 165, 180, 182, 189, 61, 7, 140, 105, 78, 86, 75, 15, 28, 82, 1, 136, 130, 35, 24, 70, 152, 121, 11, 36, 66, 83, 57, 164, 111, 137, 128, 175, 156, 151, 48, 44, 147, 18, 64, 184, 42, 159, 3, 6, 162, 170, 98, 101, 29, 102, 21, 188, 79, 138, 45, 124, 118, 155, 125, 34, 27, 5, 97, 109, 145, 54, 56, 126, 187, 16, 149, 160, 178, 23, 141, 30, 117, 25, 69, 116, 131, 94, 65, 191, 99, 181, 185, 115, 67, 93, 106, 38, 71, 76, 113, 132, 172, 103, 95, 92, 107, 4, 163, 139, 72, 157, 0, 12, 52, 68, 88, 161, 183, 39, 14, 32, 49, 19, 77, 174, 47, 154, 17, 134, 133, 51, 120, 74, 177, 41, 108, 142, 143, 13, 26, 59, 100, 123, 55, 158, 62, 104, 148, 135, 9, 179, 53, 176, 33, 169, 129, 186, 43, 167, 87, 119, 84, 90, 150, 20, 10, 122, 114, 80, 50, 146, 144, 96, 171, 40, 73, 81, 168, 112, 190, 37, 173, 46, 110, 60, 85, 153, 2, 63, 91, 127, 89, 31, 58, 22, 166 are interleaved in the sequence.

[0531] FIG. 141 is a diagram illustrating a 22nd example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0532] According to the GW pattern in Figure 141, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 17, 84, 125, 70, 134, 63, 68, 162, 61, 31, 74, 137, 7, 138, 5, 60, 76, 105, 160, 12, 114, 81, 155, 112, 153, 191, 82, 148, 118, 108, 58, 159, 43, 161, 149, 96, 71, 30, 145, 174, 67, 77, 47, 94, 48, 156, 151, 141, 131, 176, 183, 41, 35, 83, 164, 55, 169, 98, 187, 124, 100, 54, 104, 40, 2, 72, 8, 85, 182, 103, 6, 37, 107, 39, 42, 123, 57, 106, 13, 150, 129, 46, 109, 188, 45, 113, 44, 90, 20, 165, 142, 110, 22, 28, 173, 38, 52, 16, 34, 0, 3, 144, 27, 49, 139, 177, 132, 184, 25, 87, 152, 119, 158, 78, 186, 167, 97, 24, 99, 69, 120, 122, 133, 163, 21, 51, 101, 185, 111, 26, 18, 10, 33, 170, 95, 65, 14, 130, 157, 59, 115, 127, 92, 56, 1, 80, 66, 126, 178, 147, 75, 179, 171, 53, 146, 88, 4, 128, 121, 86, 117, 19, 23, 168, 181, 11, 102, 93, 73, 140, 89, 136, 9, 180, 62, 36, 79, 91, 190, 143, 29, 154, 32, 64, 166, 116, 15, 189, 175, 50, 135, 172 are interleaved in the sequence.

[0533] FIG. 142 is a diagram illustrating a 23rd example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0534] According to the GW pattern in Figure 142, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 157, 20, 116, 115, 49, 178, 148, 152, 174, 130, 171, 81, 60, 146, 182, 72, 46, 22, 93, 101, 9, 55, 40, 163, 118, 30, 52, 181, 151, 31, 87, 117, 120, 82, 95, 190, 23, 36, 67, 62, 14, 167, 80, 27, 24, 43, 94, 0, 63, 5, 74, 78, 158, 88, 84, 109, 147, 112, 124, 110, 21, 47, 45, 68, 184, 70, 1, 66, 149, 105, 140, 170, 56, 98, 135, 61, 79, 123, 166, 185, 41, 108, 122, 92, 16, 26, 37, 177, 173, 113, 136, 89, 162, 85, 54, 39, 73, 58, 131, 134, 188, 127, 3, 164, 13, 132, 129, 179, 25, 18, 57, 32, 119, 111, 53, 155, 28, 107, 133, 144, 19, 160, 71, 186, 153, 103, 2, 12, 91, 106, 64, 175, 75, 189, 128, 142, 187, 76, 180, 34, 59, 169, 90, 11, 172, 97, 141, 38, 191, 17, 114, 126, 145, 83, 143, 125, 121, 10, 44, 137, 86, 29, 104, 154, 168, 65, 159, 15, 99, 35, 50, 48, 138, 96, 100, 102, 7, 42, 156, 8, 4, 69, 183, 51, 165, 6, 150, 77, 161, 33, 176, 139 are interleaved in the sequence.

[0535] FIG. 143 is a diagram illustrating a 24th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0536] According to the GW pattern in Figure 143, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 42, 168, 36, 37, 152, 118, 14, 83, 105, 131, 26, 120, 92, 130, 158, 132, 49, 72, 137, 100, 88, 24, 53, 142, 110, 102, 74, 188, 113, 121, 12, 173, 5, 126, 127, 3, 93, 46, 164, 109, 151, 2, 98, 153, 116, 89, 101, 136, 35, 80, 0, 133, 183, 162, 185, 56, 17, 87, 117, 184, 54, 70, 176, 91, 134, 51, 38, 73, 165, 99, 169, 43, 167, 86, 11, 144, 78, 58, 64, 13, 119, 33, 166, 6, 75, 31, 15, 28, 125, 148, 27, 114, 82, 45, 55, 191, 160, 115, 1, 69, 187, 122, 177, 32, 172, 52, 112, 171, 124, 180, 85, 150, 7, 57, 60, 94, 181, 29, 97, 128, 19, 149, 175, 50, 140, 10, 174, 68, 59, 39, 106, 44, 62, 71, 18, 107, 156, 159, 146, 48, 81, 111, 96, 103, 34, 161, 141, 154, 76, 61, 135, 20, 84, 77, 108, 23, 145, 182, 170, 139, 157, 47, 9, 63, 123, 138, 155, 79, 4, 30, 143, 25, 90, 66, 147, 186, 179, 129, 21, 65, 41, 95, 67, 22, 163, 190, 16, 8, 104, 189, 40, 178 are interleaved in the sequence.

[0537] FIG. 144 is a diagram illustrating a 25th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0538] According to the GW pattern in Figure 144, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 92, 132, 39, 44, 190, 21, 70, 146, 48, 13, 17, 187, 119, 43, 94, 157, 150, 98, 96, 47, 86, 63, 152, 158, 84, 170, 81, 7, 62, 191, 174, 99, 116, 10, 85, 113, 135, 28, 53, 122, 83, 141, 77, 23, 131, 4, 40, 168, 129, 109, 51, 130, 188, 147, 29, 50, 26, 78, 148, 164, 167, 103, 36, 134, 2, 177, 20, 123, 27, 90, 176, 5, 33, 133, 189, 138, 76, 41, 89, 35, 72, 139, 32, 73, 68, 67, 101, 166, 93, 54, 52, 42, 110, 59, 8, 179, 34, 171, 143, 137, 9, 126, 155, 108, 142, 120, 163, 12, 3, 75, 159, 107, 65, 128, 87, 6, 22, 57, 100, 24, 64, 106, 117, 19, 58, 95, 74, 180, 125, 136, 186, 154, 121, 161, 88, 37, 114, 102, 105, 160, 80, 185, 82, 124, 184, 15, 16, 18, 118, 173, 151, 11, 91, 79, 46, 140, 127, 1, 169, 0, 61, 66, 45, 162, 149, 115, 144, 30, 25, 175, 153, 183, 60, 38, 31, 111, 182, 49, 55, 145, 56, 181, 104, 14, 71, 178, 112, 172, 165, 69, 97, 156 are interleaved in the sequence.

[0539] FIG. 145 is a diagram illustrating a 26th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0540] According to the GW pattern in Figure 145, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 133, 96, 46, 148, 78, 109, 149, 161, 55, 39, 183, 54, 186, 73, 150, 180, 189, 190, 22, 135, 12, 80, 42, 130, 164, 70, 126, 107, 57, 67, 15, 157, 52, 88, 5, 23, 123, 66, 53, 147, 177, 60, 131, 108, 171, 191, 44, 140, 98, 154, 37, 118, 176, 92, 124, 138, 132, 167, 173, 13, 79, 32, 145, 14, 113, 30, 2, 0, 165, 182, 153, 24, 144, 87, 82, 75, 141, 89, 137, 33, 100, 106, 128, 168, 29, 36, 172, 11, 111, 68, 16, 10, 34, 188, 35, 160, 77, 83, 178, 58, 59, 7, 56, 110, 104, 61, 76, 85, 121, 93, 19, 134, 179, 155, 163, 115, 185, 125, 112, 71, 8, 119, 18, 47, 151, 26, 103, 122, 9, 170, 146, 99, 49, 72, 102, 31, 40, 43, 158, 142, 4, 69, 139, 28, 174, 101, 84, 129, 156, 74, 62, 91, 159, 41, 38, 45, 136, 169, 21, 51, 181, 97, 166, 175, 90, 27, 86, 65, 105, 143, 127, 17, 6, 116, 94, 117, 48, 50, 25, 64, 95, 63, 184, 152, 120, 1, 187, 162, 114, 3, 81, 20 are interleaved in the sequence.

[0541] FIG. 146 is a diagram illustrating a 27th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0542] According to the GW pattern in Figure 146, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 59, 34, 129, 18, 137, 6, 83, 139, 47, 148, 147, 110, 11, 98, 62, 149, 158, 14, 42, 180, 23, 128, 99, 181, 54, 176, 35, 130, 53, 179, 39, 152, 32, 52, 69, 82, 84, 113, 79, 21, 95, 7, 126, 191, 86, 169, 111, 12, 55, 27, 182, 120, 123, 88, 107, 50, 144, 49, 38, 165, 0, 159, 10, 43, 114, 187, 150, 19, 65, 48, 124, 8, 141, 171, 173, 17, 167, 92, 74, 170, 184, 67, 33, 172, 16, 119, 66, 57, 89, 106, 26, 78, 178, 109, 70, 2, 157, 15, 105, 22, 174, 127, 100, 71, 97, 163, 9, 77, 87, 41, 183, 117, 46, 40, 131, 85, 136, 72, 122, 1, 45, 13, 44, 56, 61, 146, 25, 132, 177, 76, 121, 160, 112, 5, 134, 73, 91, 135, 68, 3, 80, 90, 190, 60, 75, 145, 115, 81, 161, 156, 116, 166, 96, 28, 138, 94, 162, 140, 102, 4, 133, 30, 155, 189, 143, 64, 185, 164, 104, 142, 154, 118, 24, 31, 153, 103, 51, 108, 29, 37, 58, 186, 175, 36, 151, 63, 93, 188, 125, 101, 20, 168 are interleaved in the sequence.

[0543] FIG. 147 is a diagram illustrating a 28th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0544] According to the GW pattern in Figure 147, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 61, 110, 123, 127, 148, 162, 131, 71, 176, 22, 157, 0, 151, 155, 112, 189, 36, 181, 10, 46, 133, 75, 80, 88, 6, 165, 97, 54, 31, 174, 49, 139, 98, 4, 170, 26, 50, 16, 141, 187, 13, 109, 106, 120, 72, 32, 63, 59, 79, 172, 83, 100, 92, 24, 56, 130, 167, 81, 103, 111, 158, 159, 153, 175, 8, 41, 136, 70, 33, 45, 84, 150, 39, 166, 164, 99, 126, 190, 134, 40, 87, 64, 154, 140, 116, 184, 115, 183, 30, 35, 7, 42, 146, 86, 58, 12, 14, 149, 89, 179, 128, 160, 95, 171, 74, 25, 29, 119, 143, 178, 28, 21, 23, 90, 188, 96, 173, 93, 147, 191, 18, 62, 2, 132, 20, 11, 17, 135, 152, 67, 73, 108, 76, 91, 156, 104, 48, 121, 94, 125, 38, 65, 177, 68, 37, 124, 78, 118, 186, 34, 185, 113, 169, 9, 69, 82, 163, 114, 145, 168, 44, 52, 105, 51, 137, 1, 161, 3, 55, 182, 101, 57, 43, 77, 5, 47, 144, 180, 66, 53, 19, 117, 60, 138, 142, 107, 122, 85, 27, 129, 15, 102 are interleaved in the sequence.

[0545] FIG. 148 is a diagram illustrating a 29th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0546] According to the GW pattern in Figure 148, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 8, 174, 121, 46, 70, 106, 183, 9, 96, 109, 72, 130, 47, 168, 1, 190, 18, 90, 103, 135, 105, 112, 23, 33, 185, 31, 171, 111, 0, 115, 4, 159, 25, 65, 134, 146, 26, 37, 16, 169, 167, 74, 67, 155, 154, 83, 117, 53, 19, 161, 76, 12, 7, 131, 59, 51, 189, 42, 114, 142, 126, 66, 164, 191, 55, 132, 35, 153, 137, 87, 5, 100, 122, 150, 2, 49, 32, 172, 149, 177, 15, 82, 98, 34, 140, 170, 56, 78, 188, 57, 118, 186, 181, 52, 71, 24, 81, 22, 11, 156, 86, 148, 97, 38, 48, 64, 40, 165, 180, 125, 127, 143, 88, 43, 61, 158, 28, 162, 187, 110, 84, 157, 27, 41, 39, 124, 85, 58, 20, 44, 102, 36, 77, 147, 120, 179, 21, 60, 92, 138, 119, 173, 160, 144, 91, 99, 107, 101, 145, 184, 108, 95, 69, 63, 3, 89, 128, 136, 94, 129, 50, 79, 68, 151, 104, 163, 123, 182, 93, 29, 133, 152, 178, 80, 62, 54, 14, 141, 166, 176, 45, 30, 10, 6, 75, 73, 116, 175, 17, 113, 139, 13 are interleaved in the sequence.

[0547] FIG. 149 is a diagram showing a 30th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0548] According to the GW pattern in Figure 149, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 179, 91, 101, 128, 169, 69, 185, 35, 156, 168, 132, 163, 46, 28, 5, 41, 162, 112, 108, 130, 153, 79, 118, 102, 125, 176, 71, 20, 115, 98, 124, 75, 103, 21, 164, 173, 9, 36, 56, 134, 24, 16, 159, 34, 15, 42, 104, 54, 120, 76, 60, 33, 127, 88, 133, 137, 61, 19, 3, 170, 87, 190, 13, 141, 188, 106, 113, 67, 145, 146, 111, 74, 89, 62, 175, 49, 32, 99, 93, 107, 171, 66, 80, 155, 100, 152, 4, 10, 126, 109, 181, 154, 105, 48, 136, 161, 183, 97, 31, 12, 8, 184, 47, 142, 18, 14, 117, 73, 84, 70, 68, 0, 23, 96, 165, 29, 122, 81, 17, 131, 44, 157, 26, 25, 189, 83, 178, 37, 123, 82, 191, 39, 7, 72, 160, 64, 143, 149, 138, 65, 58, 119, 63, 166, 114, 95, 172, 43, 140, 57, 158, 186, 86, 174, 92, 45, 139, 144, 147, 148, 151, 59, 30, 85, 40, 51, 187, 78, 38, 150, 129, 121, 27, 94, 52, 177, 110, 182, 55, 22, 167, 90, 77, 6, 11, 1, 116, 53, 2, 50, 135, 180 are interleaved in the sequence.

[0549] FIG. 150 is a diagram showing a 31st example of a GW pattern for an LDPC code with a code length N of 69120 bits.

[0550] According to the GW pattern in FIG. 150, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 99, 59, 95, 50, 122, 15, 144, 6, 129, 36, 175, 159, 165, 35, 182, 181, 189, 29, 2, 115, 91, 41, 60, 160, 51, 106, 168, 173, 20, 138, 183, 70, 24, 127, 47, 5, 119, 171, 102, 135, 116, 156, 120, 105, 117, 136, 149, 128, 85, 46, 186, 113, 73, 103, 52, 82, 89, 184, 22, 185, 155, 125, 133, 37, 27, 10, 137, 76, 12, 98, 148, 109, 42, 16, 190, 84, 94, 97, 25, 11, 88, 166, 131, 48, 161, 65, 9, 8, 58, 56, 124, 68, 54, 3, 169, 146, 87, 108, 110, 121, 163, 57, 90, 100, 66, 49, 61, 178, 18, 7, 28, 67, 13, 32, 34, 86, 153, 112, 63, 43, 164, 132, 118, 93, 38, 39, 17, 154, 170, 81, 141, 191, 152, 111, 188, 147, 180, 75, 72, 26, 177, 126, 179, 55, 1, 143, 45, 21, 40, 123, 23, 162, 77, 62, 134, 158, 176, 31, 69, 114, 142, 19, 96, 101, 71, 30, 140, 187, 92, 80, 79, 0, 104, 53, 145, 139, 14, 33, 74, 157, 150, 44, 172, 151, 64, 78, 130, 83, 167, 4, 107, 174 are interleaved in the sequence.

[0551] FIG. 151 is a diagram illustrating a 32nd example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0552] According to the GW pattern in Figure 151, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 16, 133, 14, 114, 145, 191, 53, 80, 166, 68, 21, 184, 73, 165, 147, 89, 180, 55, 135, 94, 189, 78, 103, 115, 72, 24, 105, 188, 84, 148, 85, 32, 1, 131, 34, 134, 41, 167, 81, 54, 142, 141, 75, 155, 122, 140, 13, 17, 8, 23, 61, 49, 51, 74, 181, 162, 143, 42, 71, 123, 161, 177, 110, 149, 126, 0, 63, 178, 35, 175, 186, 52, 43, 139, 112, 10, 40, 150, 182, 164, 64, 83, 174, 38, 47, 30, 2, 116, 25, 128, 160, 144, 99, 5, 187, 176, 82, 60, 18, 185, 104, 169, 39, 183, 137, 22, 109, 96, 151, 46, 33, 29, 65, 132, 95, 31, 136, 159, 170, 168, 67, 79, 93, 111, 90, 97, 113, 92, 76, 58, 127, 26, 27, 156, 3, 6, 28, 77, 125, 173, 98, 138, 172, 86, 45, 118, 171, 62, 179, 100, 19, 163, 50, 57, 56, 36, 102, 121, 117, 154, 119, 66, 20, 91, 130, 69, 44, 70, 153, 152, 158, 88, 108, 12, 59, 4, 11, 120, 87, 101, 37, 129, 146, 9, 106, 48, 7, 15, 124, 190, 107, 157 are interleaved in the sequence.

[0553] FIG. 152 is a diagram illustrating a 33rd example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0554] According to the GW pattern in Figure 152, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 178, 39, 54, 68, 122, 20, 86, 137, 156, 55, 52, 72, 130, 152, 147, 12, 69, 48, 107, 44, 88, 23, 181, 174, 124, 81, 59, 93, 22, 46, 82, 110, 3, 99, 75, 36, 38, 119, 131, 51, 115, 78, 84, 33, 163, 11, 2, 188, 161, 34, 89, 50, 8, 90, 109, 136, 77, 103, 67, 41, 149, 176, 134, 189, 159, 184, 153, 53, 129, 63, 160, 139, 150, 169, 148, 127, 25, 175, 142, 98, 56, 144, 102, 94, 101, 85, 132, 76, 5, 177, 0, 128, 45, 162, 92, 62, 133, 30, 17, 9, 61, 70, 154, 4, 146, 24, 135, 104, 13, 185, 79, 138, 31, 112, 1, 49, 113, 106, 100, 65, 10, 83, 73, 26, 58, 114, 66, 126, 117, 96, 186, 14, 40, 164, 158, 118, 29, 121, 151, 168, 183, 179, 16, 105, 125, 190, 116, 165, 80, 64, 170, 140, 171, 173, 97, 60, 43, 123, 71, 182, 167, 95, 145, 141, 187, 166, 87, 143, 15, 74, 111, 157, 32, 172, 18, 57, 35, 191, 27, 47, 21, 6, 19, 155, 42, 120, 180, 37, 28, 91, 108, 7 are interleaved in the sequence.

[0555] FIG. 153 is a diagram illustrating a 34th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0556] According to the GW pattern in Figure 153, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 139, 112, 159, 99, 87, 70, 175, 161, 51, 56, 174, 143, 12, 36, 77, 60, 155, 167, 160, 73, 127, 82, 123, 145, 8, 76, 164, 178, 144, 86, 7, 124, 27, 187, 130, 162, 191, 182, 16, 106, 141, 38, 72, 179, 111, 29, 59, 183, 66, 52, 43, 121, 20, 11, 190, 92, 55, 166, 94, 138, 1, 122, 171, 119, 109, 58, 23, 31, 163, 53, 13, 188, 100, 158, 156, 136, 34, 118, 185, 10, 25, 126, 104, 30, 83, 47, 146, 63, 134, 39, 21, 44, 151, 28, 22, 79, 110, 71, 90, 2, 103, 42, 35, 5, 57, 4, 0, 107, 37, 54, 18, 128, 148, 129, 26, 75, 120, 19, 116, 117, 147, 114, 48, 96, 61, 46, 88, 67, 135, 65, 180, 9, 74, 176, 6, 149, 49, 50, 125, 64, 169, 168, 157, 153, 24, 108, 89, 98, 33, 132, 93, 40, 154, 62, 142, 41, 69, 105, 189, 115, 152, 45, 133, 3, 95, 17, 186, 184, 85, 165, 32, 173, 113, 172, 78, 181, 150, 170, 102, 97, 140, 81, 91, 15, 137, 101, 80, 68, 14, 177, 131, 84 are interleaved in the sequence.

[0557] FIG. 154 is a diagram illustrating a 35th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0558] According to the GW pattern in Figure 154, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 21, 20, 172, 86, 178, 25, 104, 133, 17, 106, 191, 68, 80, 190, 129, 29, 125, 108, 147, 23, 94, 167, 27, 61, 12, 166, 131, 120, 159, 28, 7, 62, 134, 59, 78, 0, 121, 149, 6, 5, 143, 171, 153, 161, 186, 35, 92, 113, 55, 163, 16, 54, 93, 79, 37, 44, 75, 182, 127, 148, 179, 95, 169, 141, 38, 168, 128, 56, 31, 57, 175, 140, 164, 24, 177, 88, 51, 112, 49, 185, 170, 87, 32, 60, 65, 77, 89, 3, 18, 116, 184, 45, 109, 53, 160, 9, 100, 8, 111, 69, 189, 36, 173, 33, 72, 144, 183, 115, 137, 98, 90, 142, 30, 154, 180, 122, 155, 130, 83, 138, 14, 41, 150, 132, 70, 152, 117, 11, 4, 124, 15, 42, 181, 58, 10, 22, 145, 99, 126, 107, 66, 174, 39, 13, 97, 63, 123, 84, 85, 67, 76, 158, 71, 46, 118, 81, 162, 146, 135, 2, 73, 50, 114, 82, 103, 188, 74, 101, 157, 151, 91, 119, 102, 48, 1, 40, 43, 64, 156, 34, 110, 52, 96, 136, 139, 165, 19, 176, 187, 47, 26, 105 are interleaved in the sequence.

[0559] FIG. 155 is a diagram illustrating a 36th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0560] According to the GW pattern in Figure 155, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 160, 7, 29, 39, 110, 189, 140, 143, 163, 130, 173, 71, 191, 106, 60, 62, 149, 135, 9, 147, 124, 152, 55, 116, 85, 112, 14, 20, 79, 103, 156, 167, 19, 45, 73, 26, 159, 44, 86, 76, 56, 12, 109, 117, 128, 67, 150, 151, 31, 27, 133, 17, 120, 153, 108, 180, 52, 187, 98, 63, 176, 186, 179, 113, 161, 32, 24, 111, 41, 95, 38, 10, 154, 97, 141, 2, 127, 40, 105, 34, 11, 185, 155, 61, 114, 74, 158, 162, 5, 177, 43, 51, 148, 137, 28, 181, 171, 13, 104, 42, 168, 93, 172, 144, 80, 123, 89, 81, 68, 75, 78, 121, 53, 65, 122, 142, 157, 107, 136, 66, 90, 23, 8, 1, 77, 54, 125, 174, 35, 88, 82, 134, 101, 131, 33, 50, 87, 36, 15, 47, 83, 18, 6, 21, 30, 94, 72, 145, 138, 184, 69, 84, 58, 49, 16, 48, 70, 183, 3, 92, 25, 115, 0, 182, 139, 91, 146, 102, 96, 100, 119, 129, 178, 46, 37, 57, 118, 126, 59, 165, 170, 190, 188, 175, 166, 99, 4, 22, 132, 164, 64, 169 are interleaved in the sequence.

[0561] FIG. 156 is a diagram illustrating a 37th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0562] According to the GW pattern in Figure 156, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 167, 97, 86, 166, 11, 57, 187, 169, 104, 102, 108, 63, 12, 181, 1, 71, 134, 152, 45, 144, 124, 22, 0, 51, 100, 150, 179, 54, 66, 79, 25, 172, 59, 48, 23, 55, 64, 185, 164, 123, 56, 80, 153, 9, 177, 176, 81, 17, 14, 43, 76, 27, 175, 60, 133, 91, 61, 41, 111, 163, 72, 95, 84, 67, 129, 52, 88, 121, 7, 49, 168, 154, 74, 138, 142, 158, 132, 127, 40, 139, 20, 44, 6, 128, 75, 114, 119, 2, 8, 157, 98, 118, 89, 46, 160, 190, 5, 165, 28, 68, 189, 161, 112, 173, 148, 183, 33, 131, 105, 186, 156, 70, 117, 170, 174, 36, 19, 135, 125, 122, 50, 113, 141, 37, 38, 31, 94, 149, 78, 32, 178, 34, 107, 13, 182, 146, 93, 10, 106, 109, 4, 77, 87, 3, 184, 83, 30, 180, 96, 15, 155, 110, 145, 191, 151, 101, 65, 99, 115, 140, 26, 147, 42, 136, 137, 18, 53, 116, 171, 16, 21, 92, 162, 130, 85, 69, 47, 35, 82, 120, 24, 73, 39, 58, 62, 126, 29, 90, 143, 159, 188, 103 are interleaved in the sequence.

[0563] FIG. 157 is a diagram illustrating a 38th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0564] According to the GW pattern in Figure 157, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 74, 151, 79, 49, 174, 180, 133, 106, 116, 16, 163, 62, 164, 45, 187, 128, 176, 2, 126, 136, 63, 28, 118, 173, 19, 46, 93, 121, 162, 88, 0, 147, 131, 54, 117, 138, 69, 182, 68, 143, 78, 15, 7, 59, 109, 32, 10, 179, 165, 90, 73, 71, 171, 135, 123, 125, 31, 22, 70, 185, 155, 60, 120, 113, 41, 154, 177, 85, 64, 55, 26, 129, 84, 38, 166, 44, 30, 183, 189, 191, 124, 77, 80, 98, 190, 167, 140, 52, 153, 43, 25, 188, 103, 152, 137, 76, 149, 34, 172, 122, 40, 168, 141, 96, 142, 58, 110, 65, 9, 36, 42, 50, 184, 105, 156, 127, 8, 61, 146, 169, 181, 5, 87, 150, 91, 17, 18, 24, 112, 81, 170, 95, 29, 100, 130, 48, 159, 72, 75, 160, 27, 108, 148, 66, 144, 97, 57, 115, 114, 1, 132, 4, 21, 92, 11, 107, 175, 67, 145, 14, 186, 20, 51, 39, 3, 86, 89, 47, 53, 102, 82, 139, 23, 104, 157, 99, 158, 12, 161, 35, 178, 37, 134, 83, 94, 101, 111, 119, 6, 33, 13, 56 are interleaved in the sequence.

[0565] FIG. 158 is a diagram illustrating a 39th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0566] According to the GW pattern in Figure 158, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 20, 118, 185, 106, 82, 53, 41, 40, 121, 180, 45, 10, 145, 175, 191, 160, 177, 172, 13, 29, 133, 42, 89, 51, 141, 99, 7, 134, 52, 48, 169, 162, 124, 25, 165, 128, 95, 148, 98, 171, 14, 75, 59, 26, 76, 47, 34, 122, 69, 131, 105, 60, 132, 63, 81, 109, 43, 189, 19, 186, 79, 62, 85, 54, 16, 46, 27, 44, 139, 113, 11, 102, 130, 184, 119, 1, 152, 146, 37, 178, 61, 150, 32, 163, 92, 166, 142, 67, 140, 157, 188, 18, 87, 149, 65, 183, 161, 5, 31, 71, 173, 73, 15, 138, 156, 28, 66, 170, 179, 135, 86, 39, 104, 17, 154, 174, 56, 153, 0, 97, 9, 72, 23, 167, 190, 80, 3, 38, 120, 4, 24, 159, 12, 103, 22, 125, 83, 50, 6, 77, 168, 74, 93, 49, 57, 147, 2, 155, 181, 96, 114, 107, 110, 30, 117, 127, 101, 94, 129, 35, 58, 70, 126, 182, 151, 111, 91, 64, 88, 144, 137, 143, 176, 84, 136, 8, 112, 123, 164, 115, 78, 36, 90, 100, 55, 108, 21, 158, 68, 33, 116, 187 are interleaved in the sequence.

[0567] FIG. 159 is a diagram showing a 40th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0568] According to the GW pattern in Figure 159, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 42, 43, 190, 119, 183, 103, 51, 28, 171, 20, 18, 25, 85, 22, 157, 99, 174, 5, 53, 62, 150, 128, 38, 153, 37, 148, 39, 24, 118, 102, 184, 49, 111, 48, 87, 76, 81, 40, 55, 82, 70, 105, 66, 115, 14, 86, 88, 135, 168, 139, 56, 80, 93, 95, 165, 13, 4, 100, 29, 104, 11, 72, 116, 83, 112, 67, 186, 169, 8, 57, 44, 17, 164, 31, 96, 84, 2, 125, 59, 3, 6, 173, 149, 78, 27, 160, 156, 187, 34, 129, 154, 79, 52, 117, 110, 0, 7, 113, 137, 26, 47, 12, 178, 46, 136, 97, 15, 188, 101, 58, 35, 71, 32, 16, 109, 163, 134, 75, 68, 98, 132, 90, 124, 189, 121, 123, 170, 158, 159, 77, 108, 63, 180, 36, 74, 127, 21, 146, 147, 54, 155, 10, 144, 130, 60, 1, 141, 23, 177, 133, 50, 126, 167, 151, 161, 191, 91, 114, 162, 30, 181, 182, 9, 94, 69, 176, 65, 142, 152, 175, 73, 140, 41, 179, 172, 145, 64, 19, 138, 131, 166, 33, 107, 185, 106, 122, 120, 92, 45, 143, 61, 89 are interleaved in the sequence.

[0569] FIG. 160 is a diagram showing a 41st example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0570] According to the GW pattern in FIG. 160, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 111, 33, 21, 133, 18, 30, 73, 139, 125, 35, 77, 105, 122, 91, 41, 86, 11, 8, 55, 71, 151, 107, 45, 12, 168, 51, 50, 59, 7, 132, 144, 16, 190, 31, 108, 89, 124, 110, 94, 67, 159, 46, 140, 87, 54, 142, 185, 85, 84, 120, 178, 101, 180, 20, 174, 47, 28, 145, 70, 24, 131, 4, 83, 56, 79, 37, 27, 109, 92, 52, 96, 177, 141, 188, 155, 38, 156, 169, 136, 81, 137, 112, 95, 93, 106, 149, 138, 15, 39, 170, 146, 103, 184, 43, 5, 9, 189, 34, 19, 63, 90, 36, 23, 78, 100, 75, 162, 42, 161, 119, 64, 65, 152, 62, 173, 104, 88, 118, 48, 44, 40, 60, 102, 61, 74, 99, 53, 10, 6, 172, 186, 163, 134, 14, 148, 3, 26, 1, 157, 150, 25, 123, 115, 116, 57, 175, 127, 82, 117, 114, 160, 164, 153, 176, 76, 13, 181, 68, 128, 0, 183, 49, 22, 166, 17, 191, 135, 165, 72, 158, 130, 154, 167, 66, 2, 147, 69, 58, 98, 97, 143, 32, 29, 179, 113, 80, 182, 129, 126, 171, 121, 187 are interleaved in the sequence.

[0571] FIG. 161 is a diagram showing a 42nd example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0572] According to the GW pattern in Figure 161, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 148, 32, 94, 31, 146, 15, 41, 7, 79, 58, 52, 167, 154, 4, 161, 38, 64, 127, 131, 78, 34, 125, 171, 173, 133, 122, 50, 95, 129, 57, 71, 37, 137, 69, 82, 107, 26, 10, 140, 156, 47, 178, 163, 117, 139, 174, 143, 138, 111, 11, 166, 43, 141, 114, 45, 39, 177, 103, 96, 123, 63, 23, 18, 20, 187, 27, 66, 130, 65, 142, 5, 135, 113, 90, 121, 54, 190, 134, 153, 147, 92, 157, 3, 97, 102, 106, 172, 91, 46, 89, 56, 184, 115, 99, 62, 93, 100, 88, 152, 109, 124, 182, 70, 74, 159, 165, 60, 183, 185, 164, 175, 108, 176, 2, 118, 72, 151, 0, 51, 33, 28, 80, 14, 128, 179, 84, 77, 42, 55, 160, 119, 110, 86, 22, 101, 13, 170, 36, 104, 189, 191, 169, 112, 12, 29, 30, 162, 136, 24, 68, 9, 81, 120, 145, 180, 144, 73, 21, 44, 1, 16, 67, 19, 158, 188, 181, 61, 35, 8, 53, 168, 150, 105, 59, 87, 6, 126, 75, 85, 17, 83, 98, 48, 132, 40, 76, 49, 25, 149, 186, 155, 116 are interleaved in the sequence.

[0573] FIG. 162 is a diagram showing a 43rd example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0574] According to the GW pattern in Figure 162, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 161, 38, 41, 138, 20, 24, 14, 35, 32, 179, 68, 97, 94, 142, 43, 53, 22, 28, 44, 81, 148, 187, 169, 89, 115, 144, 75, 40, 31, 152, 30, 124, 80, 135, 160, 8, 129, 147, 60, 112, 171, 0, 133, 100, 156, 180, 77, 110, 151, 69, 95, 25, 117, 127, 154, 64, 146, 143, 29, 168, 177, 183, 126, 10, 26, 3, 50, 92, 164, 163, 11, 109, 21, 37, 84, 122, 49, 71, 52, 15, 88, 149, 86, 61, 90, 155, 162, 9, 153, 67, 119, 189, 82, 131, 190, 4, 46, 118, 47, 178, 59, 150, 186, 123, 18, 79, 57, 120, 70, 62, 137, 23, 185, 167, 175, 16, 134, 73, 139, 166, 55, 165, 116, 76, 99, 182, 78, 93, 141, 33, 176, 101, 130, 58, 12, 17, 132, 45, 102, 7, 19, 145, 54, 91, 113, 36, 27, 114, 174, 39, 83, 140, 191, 74, 56, 87, 48, 158, 121, 159, 136, 63, 181, 34, 173, 103, 42, 125, 104, 107, 96, 65, 1, 13, 157, 184, 170, 105, 188, 108, 6, 2, 98, 72, 5, 66, 128, 106, 172, 111, 85, 51 are interleaved in the sequence.

[0575] FIG. 163 is a diagram showing a 44th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0576] According to the GW pattern in Figure 163, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 57, 73, 173, 63, 179, 186, 148, 181, 160, 163, 4, 109, 137, 99, 118, 15, 5, 115, 44, 153, 185, 40, 12, 169, 2, 37, 188, 97, 65, 67, 117, 90, 66, 135, 154, 159, 146, 86, 61, 182, 59, 83, 91, 175, 58, 138, 93, 43, 98, 22, 152, 96, 45, 120, 180, 10, 116, 170, 162, 68, 3, 13, 41, 131, 21, 172, 55, 24, 1, 79, 106, 189, 52, 184, 112, 53, 136, 166, 29, 62, 107, 128, 71, 111, 187, 161, 101, 49, 155, 28, 94, 70, 48, 0, 33, 157, 151, 25, 89, 88, 114, 134, 75, 87, 142, 6, 27, 64, 69, 19, 150, 38, 35, 130, 127, 76, 102, 123, 158, 129, 133, 110, 141, 95, 7, 126, 85, 108, 174, 190, 165, 156, 171, 54, 17, 121, 103, 14, 36, 105, 82, 8, 178, 51, 23, 84, 167, 30, 100, 42, 72, 149, 92, 77, 104, 183, 39, 125, 80, 143, 144, 56, 119, 16, 132, 139, 191, 50, 164, 122, 46, 140, 31, 176, 60, 26, 32, 11, 177, 124, 74, 145, 20, 34, 18, 81, 168, 9, 78, 113, 147, 47 are interleaved in the sequence.

[0577] FIG. 164 is a diagram illustrating a 45th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0578] According to the GW pattern in Figure 164, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 89, 123, 13, 47, 178, 159, 1, 190, 53, 12, 57, 109, 115, 19, 36, 143, 82, 96, 163, 66, 154, 173, 49, 65, 131, 2, 78, 15, 155, 90, 38, 130, 63, 188, 138, 184, 166, 102, 139, 28, 50, 186, 17, 20, 112, 41, 11, 8, 59, 79, 45, 162, 146, 40, 43, 129, 119, 18, 157, 37, 126, 124, 110, 191, 85, 165, 60, 142, 135, 74, 187, 179, 141, 164, 34, 69, 26, 33, 113, 120, 95, 169, 30, 0, 175, 70, 91, 104, 140, 25, 132, 23, 105, 158, 171, 6, 121, 56, 22, 127, 54, 68, 107, 133, 84, 81, 150, 99, 73, 185, 67, 29, 151, 87, 10, 167, 148, 72, 147, 5, 31, 125, 145, 4, 52, 44, 134, 83, 46, 75, 152, 62, 7, 86, 172, 180, 111, 61, 9, 58, 14, 116, 92, 170, 93, 77, 88, 42, 21, 106, 97, 144, 182, 108, 55, 94, 122, 114, 153, 64, 24, 80, 117, 3, 177, 149, 76, 128, 136, 39, 181, 160, 103, 174, 156, 27, 183, 16, 137, 101, 161, 176, 35, 118, 98, 168, 48, 100, 71, 189, 32, 51 are interleaved in the sequence.

[0579] FIG. 165 is a diagram showing a 46th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0580] According to the GW pattern in Figure 165, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 116, 157, 105, 191, 110, 149, 0, 186, 88, 165, 141, 179, 160, 121, 35, 170, 97, 7, 181, 31, 130, 123, 184, 34, 101, 167, 68, 135, 18, 91, 159, 81, 53, 36, 164, 139, 61, 162, 79, 4, 176, 127, 42, 148, 147, 150, 55, 109, 132, 124, 9, 66, 14, 128, 134, 27, 29, 59, 153, 22, 120, 13, 187, 112, 69, 163, 11, 70, 58, 15, 25, 102, 188, 182, 156, 20, 17, 10, 32, 76, 5, 28, 46, 166, 140, 143, 65, 63, 107, 119, 87, 145, 62, 108, 189, 114, 71, 78, 122, 93, 37, 12, 137, 118, 56, 67, 98, 113, 173, 169, 39, 51, 177, 1, 84, 40, 158, 2, 144, 73, 43, 82, 92, 16, 133, 129, 99, 86, 57, 47, 183, 171, 131, 33, 26, 168, 155, 178, 175, 64, 52, 100, 142, 90, 8, 106, 45, 19, 24, 80, 146, 136, 125, 95, 172, 104, 154, 138, 6, 85, 94, 74, 151, 44, 174, 115, 185, 89, 23, 190, 111, 72, 180, 54, 77, 75, 117, 126, 49, 103, 48, 60, 83, 3, 21, 50, 161, 30, 96, 152, 41, 38 are interleaved in the sequence.

[0581] FIG. 166 is a diagram showing a 47th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0582] According to the GW pattern in Figure 166, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 115, 167, 98, 128, 174, 73, 109, 79, 40, 6, 190, 113, 158, 56, 183, 61, 134, 13, 32, 133, 173, 1, 76, 151, 147, 70, 155, 77, 51, 150, 146, 12, 186, 33, 74, 171, 53, 11, 17, 68, 136, 9, 181, 91, 125, 161, 42, 124, 72, 96, 101, 81, 84, 107, 63, 55, 65, 5, 163, 157, 135, 18, 130, 120, 87, 85, 47, 187, 3, 46, 49, 112, 159, 188, 169, 127, 78, 25, 83, 45, 143, 182, 59, 36, 19, 110, 39, 43, 35, 15, 90, 180, 82, 145, 48, 34, 144, 178, 177, 86, 27, 103, 94, 62, 170, 57, 154, 166, 54, 164, 20, 185, 29, 2, 16, 60, 37, 75, 10, 162, 116, 92, 71, 106, 105, 175, 44, 108, 50, 26, 7, 176, 38, 99, 4, 122, 52, 66, 0, 140, 184, 24, 80, 97, 23, 114, 30, 126, 148, 64, 119, 165, 137, 123, 95, 111, 160, 8, 153, 149, 172, 121, 129, 28, 104, 156, 100, 189, 14, 138, 88, 118, 139, 93, 191, 31, 131, 179, 152, 89, 22, 41, 168, 117, 21, 69, 132, 102, 58, 67, 142, 141 are interleaved in the sequence.

[0583] FIG. 167 is a diagram showing a 48th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0584] According to the GW pattern in Figure 167, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 31, 178, 143, 125, 159, 168, 34, 127, 158, 157, 21, 124, 153, 162, 59, 156, 165, 40, 108, 43, 98, 119, 33, 13, 175, 166, 117, 25, 63, 111, 74, 1, 38, 169, 131, 100, 164, 0, 171, 101, 151, 113, 20, 185, 17, 86, 146, 11, 12, 19, 145, 85, 3, 80, 133, 93, 10, 72, 152, 172, 140, 45, 115, 79, 161, 39, 99, 5, 37, 110, 155, 170, 123, 70, 52, 81, 65, 160, 132, 103, 9, 88, 15, 130, 71, 129, 177, 128, 121, 150, 36, 35, 163, 83, 142, 105, 48, 64, 82, 46, 148, 138, 147, 149, 27, 56, 47, 50, 42, 54, 182, 23, 97, 89, 167, 141, 75, 32, 118, 44, 96, 66, 73, 190, 181, 191, 92, 53, 87, 176, 102, 144, 28, 134, 77, 184, 189, 67, 187, 174, 49, 94, 68, 18, 186, 26, 120, 62, 136, 24, 4, 16, 61, 179, 106, 95, 135, 41, 173, 154, 78, 2, 22, 139, 76, 58, 90, 137, 114, 126, 51, 84, 14, 91, 183, 180, 112, 122, 30, 29, 69, 107, 116, 55, 8, 104, 6, 60, 57, 7, 109, 188 are interleaved in the sequence.

[0585] FIG. 168 is a diagram showing a 49th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0586] According to the GW pattern in Figure 168, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 36, 20, 126, 165, 181, 59, 90, 186, 191, 120, 182, 170, 171, 137, 62, 84, 146, 106, 64, 129, 56, 136, 57, 108, 190, 74, 70, 10, 68, 139, 35, 104, 63, 16, 19, 66, 1, 15, 61, 97, 172, 72, 26, 141, 80, 151, 138, 156, 46, 82, 95, 142, 77, 76, 17, 102, 92, 60, 148, 99, 140, 2, 78, 145, 29, 174, 32, 103, 3, 133, 163, 23, 150, 155, 44, 185, 65, 134, 184, 11, 38, 119, 117, 167, 79, 5, 130, 94, 33, 157, 154, 109, 30, 31, 160, 96, 49, 178, 110, 128, 166, 7, 162, 48, 34, 55, 22, 143, 149, 121, 89, 114, 176, 107, 67, 73, 51, 53, 132, 83, 158, 69, 153, 180, 188, 101, 37, 179, 111, 71, 147, 189, 124, 43, 86, 98, 91, 45, 135, 168, 183, 42, 27, 81, 152, 164, 58, 100, 25, 4, 13, 144, 112, 122, 159, 187, 52, 85, 50, 9, 87, 127, 169, 173, 14, 93, 116, 175, 177, 24, 40, 0, 28, 12, 161, 105, 41, 75, 123, 39, 125, 18, 54, 6, 131, 118, 115, 88, 8, 113, 21, 47 are interleaved in the sequence.

[0587] FIG. 169 is a diagram showing a 50th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0588] According to the GW pattern in Figure 169, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 12, 183, 40, 66, 35, 155, 137, 58, 108, 93, 47, 78, 56, 122, 51, 114, 10, 164, 148, 190, 53, 76, 75, 11, 46, 2, 174, 146, 119, 170, 98, 22, 116, 28, 67, 63, 59, 154, 94, 105, 187, 9, 97, 166, 19, 125, 189, 185, 178, 115, 123, 150, 60, 77, 86, 69, 26, 145, 143, 134, 124, 111, 162, 141, 80, 34, 138, 130, 45, 33, 127, 37, 91, 84, 102, 13, 16, 172, 61, 182, 57, 55, 101, 142, 117, 87, 131, 188, 191, 113, 39, 54, 74, 72, 29, 48, 161, 139, 151, 180, 1, 160, 103, 173, 15, 52, 186, 133, 71, 132, 31, 135, 70, 81, 24, 112, 6, 175, 96, 3, 79, 156, 109, 8, 153, 90, 177, 49, 99, 128, 21, 7, 158, 89, 92, 126, 32, 121, 100, 88, 163, 136, 20, 83, 17, 42, 95, 129, 118, 43, 157, 50, 5, 179, 140, 147, 62, 38, 176, 149, 159, 44, 106, 152, 65, 14, 168, 184, 0, 107, 167, 36, 73, 110, 165, 120, 104, 23, 25, 82, 27, 41, 181, 169, 85, 144, 4, 18, 171, 30, 68, 64 are interleaved in the sequence.

[0589] FIG. 170 is a diagram showing a 51st example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0590] According to the GW pattern in FIG. 170, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 140, 166, 22, 87, 107, 121, 66, 80, 85, 109, 45, 13, 144, 63, 0, 52, 131, 122, 135, 173, 105, 98, 117, 168, 8, 123, 157, 93, 129, 37, 119, 143, 40, 59, 162, 21, 79, 102, 34, 36, 32, 41, 177, 48, 83, 94, 191, 78, 101, 155, 160, 189, 77, 57, 11, 148, 124, 65, 187, 110, 100, 114, 67, 150, 82, 156, 43, 5, 1, 126, 46, 167, 149, 72, 31, 161, 23, 113, 137, 132, 35, 76, 26, 61, 141, 15, 4, 25, 17, 182, 92, 29, 27, 73, 170, 53, 64, 127, 112, 171, 56, 106, 186, 183, 95, 165, 10, 103, 74, 84, 116, 20, 185, 6, 133, 147, 75, 62, 14, 142, 44, 181, 146, 164, 128, 9, 60, 50, 91, 88, 97, 145, 28, 7, 118, 99, 115, 39, 125, 136, 180, 179, 96, 175, 3, 47, 158, 172, 154, 138, 176, 33, 81, 134, 120, 174, 151, 49, 30, 108, 68, 38, 153, 2, 69, 111, 54, 130, 71, 24, 58, 178, 19, 42, 51, 190, 89, 16, 90, 169, 70, 18, 86, 184, 12, 188, 163, 55, 139, 104, 152, 159 are interleaved in the sequence.

[0591] FIG. 171 is a diagram showing a 52nd example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0592] According to the GW pattern in Figure 171, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 128, 120, 91, 121, 189, 30, 127, 35, 76, 26, 144, 45, 178, 93, 14, 31, 123, 155, 19, 28, 152, 174, 177, 168, 56, 169, 95, 7, 96, 133, 136, 146, 172, 187, 90, 44, 98, 150, 40, 20, 104, 191, 37, 61, 42, 43, 27, 159, 163, 100, 164, 151, 111, 102, 165, 132, 138, 180, 22, 70, 184, 62, 167, 134, 60, 160, 175, 157, 153, 77, 87, 185, 116, 115, 176, 78, 5, 39, 88, 33, 126, 13, 71, 188, 171, 135, 21, 16, 143, 51, 99, 182, 85, 129, 162, 66, 0, 55, 73, 117, 75, 181, 179, 53, 170, 1, 125, 69, 80, 83, 57, 38, 103, 109, 137, 63, 74, 9, 15, 118, 67, 2, 113, 124, 114, 6, 154, 141, 50, 149, 4, 46, 8, 130, 94, 34, 23, 54, 145, 81, 58, 82, 139, 156, 108, 140, 166, 36, 183, 110, 101, 161, 84, 119, 92, 3, 142, 186, 158, 173, 147, 49, 10, 32, 65, 89, 86, 131, 18, 47, 107, 79, 72, 25, 68, 122, 29, 11, 41, 190, 59, 52, 97, 148, 12, 24, 105, 17, 106, 48, 64, 112 are interleaved in the sequence.

[0593] FIG. 172 is a diagram showing a 53rd example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0594] According to the GW pattern in Figure 172, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 36, 180, 61, 100, 163, 168, 14, 24, 105, 104, 131, 56, 40, 73, 165, 157, 126, 47, 160, 181, 166, 161, 1, 81, 58, 182, 189, 177, 85, 17, 13, 46, 171, 149, 91, 79, 109, 133, 164, 125, 52, 77, 118, 186, 107, 150, 135, 33, 130, 87, 167, 158, 23, 83, 152, 114, 68, 12, 132, 178, 106, 184, 176, 72, 31, 53, 21, 110, 76, 146, 4, 18, 113, 65, 34, 179, 111, 185, 84, 144, 27, 39, 151, 50, 69, 30, 169, 175, 9, 42, 54, 43, 90, 22, 139, 129, 170, 115, 45, 140, 67, 25, 155, 82, 102, 29, 188, 108, 15, 80, 128, 48, 0, 64, 141, 93, 191, 190, 174, 32, 35, 119, 159, 41, 55, 162, 49, 59, 88, 156, 123, 136, 28, 60, 26, 16, 89, 147, 92, 98, 38, 20, 173, 71, 44, 94, 5, 7, 99, 75, 122, 120, 66, 121, 112, 62, 8, 137, 142, 103, 116, 117, 37, 63, 70, 86, 10, 74, 95, 11, 134, 154, 51, 101, 127, 183, 57, 97, 78, 148, 6, 172, 3, 138, 145, 153, 143, 19, 2, 96, 187, 124 are interleaved in the sequence.

[0595] FIG. 173 is a diagram showing a 54th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0596] According to the GW pattern in Figure 173, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 92, 83, 138, 67, 27, 88, 13, 26, 73, 16, 187, 18, 76, 28, 79, 130, 91, 58, 140, 38, 6, 43, 17, 168, 141, 96, 70, 147, 112, 164, 97, 161, 139, 65, 78, 95, 146, 3, 32, 158, 24, 0, 94, 120, 176, 128, 59, 81, 21, 102, 190, 8, 114, 113, 29, 45, 103, 56, 54, 173, 177, 12, 174, 108, 169, 148, 123, 129, 150, 77, 157, 184, 61, 127, 121, 156, 104, 111, 68, 160, 107, 117, 124, 84, 35, 10, 90, 106, 144, 66, 64, 15, 46, 125, 44, 37, 20, 135, 53, 71, 152, 183, 162, 50, 167, 11, 142, 149, 131, 191, 166, 31, 185, 134, 19, 178, 52, 188, 2, 75, 110, 145, 41, 159, 136, 100, 9, 62, 60, 34, 116, 23, 42, 105, 40, 118, 186, 4, 5, 182, 170, 87, 1, 22, 55, 126, 63, 14, 25, 153, 98, 49, 33, 69, 179, 171, 93, 36, 133, 57, 151, 82, 72, 163, 86, 47, 119, 48, 99, 30, 189, 115, 165, 101, 80, 175, 132, 89, 39, 181, 85, 51, 154, 137, 7, 180, 155, 74, 109, 122, 172, 143 are interleaved in the sequence.

[0597] FIG. 174 is a diagram showing a 55th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0598] According to the GW pattern in Figure 174, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 52, 117, 42, 131, 45, 120, 44, 63, 91, 0, 33, 176, 95, 36, 134, 170, 148, 32, 130, 20, 124, 51, 152, 96, 92, 90, 184, 103, 53, 14, 110, 80, 107, 145, 181, 137, 61, 149, 114, 126, 136, 161, 58, 162, 88, 8, 171, 178, 174, 94, 118, 19, 35, 1, 191, 115, 23, 10, 150, 67, 46, 56, 172, 129, 109, 98, 89, 68, 101, 121, 78, 182, 12, 173, 128, 77, 168, 156, 186, 165, 39, 187, 5, 158, 104, 2, 49, 154, 59, 82, 65, 30, 127, 17, 113, 164, 179, 34, 69, 189, 123, 147, 183, 21, 163, 143, 57, 100, 28, 185, 25, 140, 13, 66, 141, 62, 47, 54, 169, 106, 38, 86, 116, 151, 41, 4, 75, 108, 85, 153, 72, 125, 22, 135, 50, 70, 74, 11, 76, 138, 132, 55, 167, 40, 144, 31, 142, 37, 29, 99, 83, 26, 119, 64, 27, 9, 15, 97, 73, 133, 79, 190, 111, 43, 48, 102, 7, 139, 84, 24, 112, 177, 16, 180, 175, 81, 3, 60, 18, 188, 93, 105, 157, 87, 166, 159, 155, 122, 146, 6, 160, 71 are interleaved in the sequence.

[0599] FIG. 175 is a diagram showing a 56th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0600] According to the GW pattern in Figure 175, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 60, 117, 182, 104, 53, 26, 11, 121, 71, 32, 179, 34, 38, 145, 166, 65, 137, 7, 124, 58, 90, 29, 144, 116, 91, 88, 98, 161, 83, 177, 85, 154, 146, 178, 123, 76, 75, 3, 64, 151, 99, 118, 57, 106, 16, 61, 162, 19, 12, 94, 39, 93, 92, 73, 82, 138, 108, 139, 130, 163, 152, 159, 168, 189, 102, 134, 101, 66, 4, 171, 170, 188, 107, 23, 180, 35, 175, 18, 89, 181, 17, 97, 62, 56, 52, 128, 40, 25, 191, 74, 95, 143, 5, 8, 1, 132, 133, 135, 184, 33, 37, 45, 127, 122, 136, 190, 158, 72, 77, 114, 46, 55, 105, 78, 183, 103, 22, 20, 24, 155, 86, 63, 79, 164, 13, 174, 2, 14, 47, 126, 84, 165, 59, 142, 87, 153, 112, 43, 156, 50, 6, 0, 81, 51, 21, 9, 148, 111, 147, 48, 31, 36, 129, 167, 150, 70, 42, 15, 110, 119, 109, 125, 80, 27, 131, 49, 140, 187, 96, 120, 100, 141, 160, 186, 185, 68, 69, 28, 176, 169, 44, 173, 149, 54, 115, 113, 67, 10, 157, 41, 30, 172 are interleaved in the sequence.

[0601] FIG. 176 is a diagram showing a 57th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0602] According to the GW pattern in Figure 176, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 7, 156, 171, 76, 165, 68, 5, 72, 86, 57, 42, 98, 162, 130, 88, 31, 63, 170, 92, 100, 145, 146, 117, 62, 123, 55, 22, 138, 75, 99, 177, 83, 135, 190, 79, 84, 182, 140, 136, 0, 108, 77, 8, 154, 73, 37, 147, 14, 10, 128, 111, 168, 38, 159, 125, 32, 120, 132, 148, 27, 69, 96, 127, 103, 34, 110, 161, 41, 18, 35, 142, 116, 28, 121, 91, 112, 51, 178, 139, 95, 155, 20, 78, 33, 133, 29, 9, 54, 24, 176, 122, 3, 102, 56, 181, 175, 174, 81, 166, 30, 26, 43, 113, 137, 150, 89, 179, 70, 11, 2, 118, 183, 13, 50, 46, 12, 49, 40, 172, 17, 47, 65, 16, 74, 141, 129, 101, 48, 87, 187, 167, 134, 158, 15, 44, 53, 93, 152, 23, 126, 52, 97, 189, 36, 115, 169, 64, 25, 58, 82, 1, 45, 39, 191, 144, 173, 6, 60, 85, 149, 163, 21, 90, 4, 80, 105, 164, 180, 61, 114, 188, 151, 185, 94, 124, 104, 106, 119, 107, 160, 67, 71, 19, 131, 186, 153, 157, 66, 143, 184, 109, 59 are interleaved in the sequence.

[0603] FIG. 177 is a diagram showing a 58th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0604] According to the GW pattern in Figure 177, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 134, 124, 102, 133, 161, 34, 18, 17, 119, 172, 43, 25, 130, 84, 46, 167, 23, 100, 31, 121, 30, 15, 99, 127, 62, 20, 143, 103, 139, 171, 13, 42, 1, 26, 76, 159, 27, 82, 48, 146, 22, 156, 188, 69, 86, 177, 129, 160, 33, 67, 176, 148, 168, 158, 169, 0, 155, 118, 154, 110, 96, 191, 4, 36, 39, 56, 112, 14, 145, 182, 3, 88, 126, 91, 105, 174, 128, 157, 125, 74, 116, 61, 52, 187, 117, 98, 73, 95, 92, 181, 111, 65, 63, 152, 163, 147, 66, 178, 87, 179, 64, 93, 144, 83, 140, 8, 78, 2, 131, 115, 123, 47, 94, 186, 28, 68, 21, 135, 37, 151, 11, 104, 77, 81, 35, 71, 162, 97, 41, 58, 190, 101, 153, 85, 166, 7, 173, 44, 29, 10, 49, 54, 150, 32, 50, 51, 45, 183, 107, 113, 137, 80, 79, 175, 142, 141, 138, 40, 122, 75, 120, 53, 59, 60, 184, 5, 38, 6, 164, 189, 24, 16, 72, 19, 109, 106, 114, 108, 185, 165, 149, 9, 57, 170, 12, 90, 180, 89, 132, 136, 55, 70 are interleaved in the sequence.

[0605] FIG. 178 is a diagram showing a 59th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0606] According to the GW pattern in Figure 178, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 18, 161, 152, 30, 91, 138, 83, 88, 127, 54, 33, 46, 125, 120, 122, 169, 51, 150, 100, 52, 95, 186, 149, 81, 11, 53, 164, 130, 19, 176, 93, 107, 29, 86, 124, 65, 75, 71, 74, 68, 44, 82, 59, 104, 118, 103, 131, 101, 8, 96, 97, 119, 166, 77, 50, 34, 158, 21, 184, 24, 165, 171, 142, 36, 181, 45, 90, 175, 99, 13, 37, 10, 140, 3, 69, 16, 133, 172, 173, 27, 132, 79, 76, 111, 123, 7, 94, 70, 116, 174, 15, 156, 187, 110, 84, 185, 14, 72, 159, 143, 78, 135, 17, 12, 139, 67, 58, 151, 177, 73, 154, 145, 179, 25, 108, 148, 137, 85, 147, 61, 20, 89, 155, 183, 134, 128, 191, 26, 121, 126, 0, 141, 112, 62, 114, 48, 182, 146, 115, 64, 113, 189, 31, 1, 39, 168, 2, 43, 163, 188, 35, 129, 153, 66, 23, 40, 6, 5, 98, 56, 9, 63, 180, 157, 167, 162, 60, 42, 49, 28, 22, 80, 87, 92, 160, 55, 136, 170, 106, 117, 178, 32, 38, 105, 102, 41, 57, 109, 144, 47, 190, 4 are interleaved in the sequence.

[0607] FIG. 179 is a diagram showing the 60th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0608] According to the GW pattern in Figure 179, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 172, 48, 104, 60, 184, 162, 86, 185, 11, 132, 155, 50, 146, 178, 5, 28, 133, 169, 106, 90, 174, 95, 42, 10, 78, 177, 21, 112, 54, 153, 136, 12, 115, 108, 92, 152, 180, 151, 13, 62, 25, 51, 191, 84, 167, 139, 96, 111, 130, 150, 7, 143, 144, 117, 124, 27, 38, 72, 6, 128, 36, 39, 26, 156, 32, 127, 181, 122, 52, 131, 68, 140, 173, 182, 154, 190, 137, 61, 2, 138, 43, 110, 29, 116, 176, 30, 57, 189, 14, 4, 65, 80, 33, 75, 135, 20, 103, 98, 56, 179, 129, 105, 113, 71, 160, 85, 55, 0, 166, 59, 183, 142, 19, 22, 63, 125, 165, 88, 87, 93, 168, 77, 45, 69, 175, 100, 145, 31, 91, 141, 114, 157, 119, 16, 1, 34, 15, 147, 46, 188, 70, 74, 109, 126, 18, 64, 89, 134, 9, 161, 158, 44, 3, 47, 148, 187, 81, 164, 121, 35, 23, 24, 159, 82, 40, 94, 67, 163, 170, 58, 97, 8, 83, 53, 118, 149, 73, 107, 123, 79, 41, 99, 186, 101, 49, 120, 66, 76, 17, 171, 102, 37 are interleaved in the sequence.

[0609] FIG. 180 is a diagram showing the 61st example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0610] According to the GW pattern in Figure 180, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 16, 133, 14, 114, 145, 191, 53, 80, 166, 68, 21, 184, 73, 165, 147, 89, 180, 55, 135, 94, 189, 78, 103, 115, 72, 24, 105, 188, 84, 148, 85, 32, 1, 131, 34, 134, 41, 167, 81, 54, 142, 141, 75, 155, 122, 140, 13, 17, 8, 23, 61, 49, 51, 74, 181, 162, 143, 42, 71, 123, 161, 177, 110, 149, 126, 0, 63, 178, 35, 175, 186, 52, 43, 139, 112, 10, 40, 150, 182, 164, 64, 83, 174, 38, 47, 30, 2, 116, 25, 128, 160, 144, 99, 5, 187, 176, 82, 60, 18, 185, 104, 169, 39, 183, 137, 22, 109, 96, 151, 46, 33, 29, 65, 132, 95, 31, 136, 159, 170, 168, 67, 79, 93, 111, 90, 97, 113, 92, 76, 58, 127, 26, 27, 156, 3, 6, 28, 77, 125, 173, 98, 138, 172, 86, 45, 118, 171, 62, 179, 100, 19, 163, 50, 57, 56, 36, 102, 121, 117, 154, 119, 66, 20, 91, 130, 69, 44, 70, 153, 152, 158, 88, 108, 12, 59, 4, 11, 120, 87, 101, 37, 129, 146, 9, 106, 48, 7, 15, 124, 190, 107, 157 are interleaved in the sequence.

[0611] FIG. 181 is a diagram showing a 62nd example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0612] According to the GW pattern in Figure 181, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is 97, 121, 122, 73, 108, 167, 75, 156, 64, 49, 29, 18, 110, 171, 8, 27, 54, 41, 164, 15, 129, 157, 130, 111, 112, 120, 152, 12, 13, 101, 31, 69, 180, 143, 78, 125, 79, 172, 40, 116, 58, 71, 126, 55, 35, 191, 185, 159, 44, 86, 3, 80, 88, 145, 98, 144, 0, 62, 38, 150, 166, 114, 139, 60, 149, 10, 72, 155, 181, 26, 85, 128, 19, 25, 4, 170, 94, 175, 136, 117, 135, 102, 21, 89, 140, 138, 100, 33, 142, 74, 133, 56, 124, 17, 77, 65, 119, 59, 182, 105, 99, 158, 24, 96, 70, 83, 23, 81, 132, 7, 141, 61, 57, 82, 115, 162, 186, 103, 43, 148, 47, 176, 113, 151, 50, 184, 165, 109, 189, 90, 32, 20, 46, 127, 153, 161, 106, 11, 67, 36, 9, 28, 174, 160, 16, 93, 95, 6, 131, 66, 39, 14, 91, 163, 68, 48, 123, 137, 52, 5, 183, 76, 179, 22, 34, 147, 107, 168, 146, 42, 173, 53, 190, 104, 51, 118, 45, 30, 178, 134, 169, 37, 187, 177, 1, 2, 154, 87, 63, 92, 188, 84 are interleaved in the sequence.

[0613] FIG. 182 is a diagram showing a 63rd example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0614] According to the GW pattern in Figure 182, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 47, 85, 118, 136, 166, 98, 72, 163, 63, 116, 162, 169, 114, 124, 144, 110, 46, 152, 104, 88, 99, 106, 181, 109, 3, 10, 172, 107, 33, 100, 191, 75, 157, 79, 52, 128, 6, 12, 139, 30, 68, 111, 83, 5, 119, 1, 97, 56, 38, 117, 78, 80, 155, 141, 185, 20, 161, 123, 28, 180, 77, 50, 29, 64, 41, 121, 53, 36, 48, 127, 44, 22, 35, 165, 59, 147, 187, 153, 89, 154, 18, 55, 90, 69, 19, 148, 129, 188, 24, 8, 102, 151, 11, 74, 105, 81, 92, 70, 101, 7, 132, 120, 112, 145, 57, 96, 42, 45, 91, 71, 149, 164, 51, 130, 95, 140, 178, 9, 135, 34, 175, 21, 32, 25, 67, 17, 61, 58, 134, 43, 122, 2, 16, 183, 54, 86, 4, 39, 60, 184, 171, 94, 179, 13, 115, 49, 143, 158, 168, 159, 87, 73, 156, 15, 93, 125, 126, 131, 40, 66, 138, 76, 173, 65, 27, 170, 186, 182, 103, 108, 82, 37, 174, 167, 142, 26, 160, 84, 62, 190, 176, 31, 150, 189, 113, 137, 14, 23, 0, 146, 177, 133 are interleaved in the sequence.

[0615] FIG. 183 is a diagram showing a 64th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0616] According to the GW pattern in Figure 183, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 97, 39, 99, 33, 10, 6, 189, 179, 130, 172, 76, 185, 131, 40, 176, 159, 8, 17, 167, 116, 16, 160, 5, 174, 27, 115, 43, 41, 136, 175, 153, 144, 106, 29, 105, 84, 67, 35, 152, 191, 72, 56, 83, 168, 12, 184, 65, 146, 104, 80, 98, 79, 51, 26, 64, 137, 181, 165, 52, 129, 186, 48, 128, 154, 58, 141, 77, 187, 94, 109, 81, 119, 82, 38, 18, 188, 143, 170, 147, 2, 162, 95, 21, 11, 74, 151, 19, 59, 1, 138, 145, 7, 177, 30, 42, 44, 28, 20, 91, 14, 4, 70, 110, 31, 37, 61, 55, 85, 15, 183, 171, 96, 103, 101, 112, 161, 54, 178, 78, 87, 126, 57, 180, 88, 92, 113, 73, 90, 117, 93, 89, 122, 62, 25, 158, 148, 118, 45, 123, 60, 107, 173, 114, 166, 120, 13, 23, 139, 86, 135, 164, 47, 124, 149, 150, 46, 157, 100, 142, 0, 71, 50, 49, 36, 9, 127, 156, 75, 34, 163, 125, 190, 182, 155, 66, 69, 140, 32, 169, 132, 53, 68, 102, 63, 133, 111, 22, 134, 108, 3, 24, 121 are interleaved in the sequence.

[0617] FIG. 184 is a diagram showing the 65th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0618] According to the GW pattern in Figure 184, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is 35, 75, 166, 145, 143, 184, 62, 96, 54, 63, 157, 103, 32, 43, 126, 187, 144, 91, 78, 44, 39, 109, 185, 102, 10, 68, 29, 42, 149, 83, 133, 94, 130, 27, 171, 19, 51, 165, 148, 28, 36, 33, 173, 136, 87, 82, 100, 49, 120, 152, 161, 162, 147, 71, 137, 57, 8, 53, 132, 151, 163, 123, 47, 92, 90, 60, 99, 79, 59, 108, 115, 72, 0, 12, 140, 160, 61, 180, 74, 37, 86, 117, 191, 101, 52, 15, 80, 156, 127, 81, 131, 141, 142, 31, 95, 4, 73, 64, 16, 18, 146, 70, 181, 7, 89, 124, 77, 67, 116, 21, 34, 41, 105, 113, 97, 2, 6, 55, 17, 65, 38, 48, 158, 159, 179, 5, 30, 183, 170, 135, 125, 20, 106, 186, 182, 188, 114, 1, 14, 3, 134, 178, 189, 167, 40, 119, 22, 190, 58, 23, 155, 138, 98, 84, 11, 110, 88, 46, 177, 175, 25, 150, 118, 121, 129, 168, 13, 128, 104, 69, 112, 169, 9, 45, 174, 93, 26, 56, 76, 50, 154, 139, 66, 85, 153, 107, 111, 172, 176, 164, 24, 122 are interleaved in the sequence.

[0619] FIG. 185 is a diagram showing the 66th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0620] According to the GW pattern in Figure 185, the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is 138, 38, 106, 76, 172, 27, 150, 95, 44, 187, 64, 18, 28, 98, 180, 101, 149, 146, 126, 26, 93, 178, 186, 70, 104, 131, 19, 45, 102, 122, 152, 66, 63, 173, 9, 55, 25, 1, 154, 85, 5, 51, 43, 82, 86, 151, 148, 48, 190, 179, 62, 60, 94, 174, 142, 39, 169, 170, 47, 125, 33, 128, 162, 2, 129, 57, 79, 118, 114, 69, 78, 167, 11, 136, 99, 155, 90, 21, 119, 10, 52, 91, 115, 185, 6, 110, 88, 96, 181, 143, 0, 160, 124, 130, 183, 71, 121, 182, 68, 191, 3, 32, 40, 189, 41, 156, 35, 159, 58, 89, 29, 67, 17, 109, 30, 111, 12, 46, 65, 177, 53, 77, 74, 56, 184, 15, 141, 135, 54, 163, 14, 145, 139, 134, 59, 147, 87, 107, 7, 61, 36, 113, 103, 188, 24, 165, 137, 22, 42, 49, 83, 73, 50, 161, 20, 166, 127, 157, 108, 171, 37, 72, 176, 112, 123, 144, 34, 175, 168, 117, 80, 81, 8, 31, 133, 92, 164, 132, 97, 158, 84, 100, 140, 16, 105, 23, 75, 13, 153, 116, 4, 120 are interleaved in the sequence.

[0621] FIG. 186 is a diagram showing the 67th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0622] According to the GW pattern in Figure 186, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is 37, 136, 161, 62, 163, 129, 160, 73, 76, 66, 34, 162, 122, 5, 87, 94, 50, 105, 132, 32, 121, 47, 74, 189, 110, 45, 75, 175, 17, 29, 108, 191, 1, 153, 20, 113, 61, 42, 51, 2, 165, 124, 43, 186, 40, 86, 168, 180, 155, 16, 93, 26, 166, 119, 159, 56, 12, 44, 46, 143, 49, 25, 176, 158, 92, 147, 54, 172, 182, 64, 157, 112, 38, 39, 11, 6, 127, 48, 151, 82, 4, 36, 183, 88, 126, 117, 111, 188, 138, 65, 70, 170, 133, 137, 146, 128, 114, 148, 141, 125, 10, 41, 116, 33, 99, 81, 187, 130, 131, 107, 60, 90, 173, 13, 71, 15, 106, 3, 149, 154, 181, 174, 190, 27, 177, 18, 21, 22, 83, 91, 150, 14, 96, 53, 0, 145, 67, 68, 144, 184, 59, 23, 118, 115, 135, 55, 134, 102, 8, 169, 85, 156, 97, 63, 104, 95, 52, 98, 139, 24, 78, 179, 19, 28, 69, 58, 109, 57, 164, 31, 84, 140, 103, 77, 123, 171, 72, 79, 152, 35, 80, 7, 185, 167, 9, 100, 142, 89, 30, 120, 178, 101 are interleaved in the sequence.

[0623] FIG. 187 is a diagram showing the 68th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0624] According to the GW pattern in Figure 187, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is 148, 189, 3, 121, 80, 135, 7, 96, 46, 109, 190, 111, 118, 23, 5, 149, 19, 140, 106, 36, 161, 71, 6, 176, 160, 76, 8, 168, 171, 173, 40, 37, 25, 50, 164, 108, 139, 31, 127, 142, 163, 177, 24, 20, 157, 83, 116, 42, 73, 69, 88, 184, 147, 136, 187, 49, 45, 35, 170, 62, 63, 181, 117, 123, 122, 72, 55, 53, 133, 159, 94, 175, 179, 158, 97, 93, 13, 130, 144, 81, 68, 2, 64, 155, 119, 43, 143, 1, 112, 18, 146, 172, 132, 191, 134, 61, 138, 9, 178, 103, 15, 47, 154, 17, 152, 153, 107, 115, 39, 166, 33, 104, 56, 52, 60, 131, 141, 78, 186, 162, 54, 0, 85, 12, 86, 77, 126, 34, 180, 10, 87, 38, 4, 26, 79, 27, 98, 66, 75, 67, 110, 101, 128, 16, 22, 28, 151, 21, 99, 74, 11, 100, 65, 58, 150, 145, 14, 59, 102, 51, 48, 113, 92, 167, 188, 174, 156, 114, 82, 125, 124, 70, 137, 90, 30, 44, 57, 105, 95, 165, 29, 89, 41, 169, 120, 91, 32, 183, 129, 182, 185, 84 are interleaved in the sequence.

[0625] FIG. 188 is a diagram showing the 69th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0626] According to the GW pattern in Figure 188, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is 67, 20, 9, 75, 143, 94, 144, 122, 56, 88, 180, 72, 102, 100, 113, 157, 170, 59, 128, 162, 26, 38, 61, 156, 115, 117, 190, 77, 22, 74, 119, 12, 8, 179, 182, 85, 188, 191, 154, 41, 58, 142, 186, 107, 73, 189, 15, 130, 127, 160, 55, 19, 45, 137, 124, 133, 146, 43, 60, 183, 153, 177, 123, 181, 95, 49, 140, 4, 51, 3, 21, 164, 83, 187, 148, 11, 168, 149, 92, 65, 30, 90, 23, 116, 57, 161, 125, 175, 129, 126, 97, 14, 96, 66, 37, 178, 64, 173, 184, 80, 101, 34, 81, 131, 76, 147, 47, 135, 111, 121, 44, 68, 98, 48, 120, 40, 87, 176, 104, 106, 28, 163, 52, 1, 152, 79, 42, 139, 16, 2, 71, 7, 109, 114, 112, 54, 62, 169, 35, 150, 171, 110, 50, 108, 105, 69, 118, 84, 39, 132, 63, 31, 18, 134, 103, 185, 6, 145, 24, 70, 36, 29, 5, 93, 99, 33, 82, 89, 167, 174, 27, 165, 91, 138, 155, 32, 159, 141, 136, 151, 25, 158, 86, 17, 13, 172, 53, 10, 46, 166, 0, 78 are interleaved in the sequence.

[0627] FIG. 189 is a diagram showing a 70th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0628] According to the GW pattern in Figure 189, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is 84, 126, 45, 76, 121, 91, 52, 162, 79, 187, 134, 108, 47, 16, 72, 119, 43, 107, 98, 135, 147, 110, 0, 60, 4, 61, 117, 24, 167, 65, 40, 55, 73, 112, 85, 35, 156, 95, 137, 171, 9, 11, 54, 131, 138, 157, 152, 111, 183, 161, 41, 69, 21, 94, 113, 8, 153, 39, 57, 143, 86, 12, 188, 184, 15, 30, 118, 136, 64, 169, 148, 22, 6, 68, 168, 78, 105, 101, 190, 3, 59, 124, 170, 62, 87, 46, 28, 29, 186, 2, 25, 177, 140, 53, 154, 37, 18, 189, 93, 114, 33, 1, 158, 122, 103, 5, 104, 80, 166, 34, 106, 51, 10, 180, 139, 125, 178, 100, 13, 70, 142, 185, 159, 50, 66, 102, 150, 127, 160, 92, 81, 173, 115, 144, 145, 128, 74, 88, 20, 116, 179, 96, 17, 155, 175, 75, 165, 7, 191, 149, 44, 23, 99, 48, 163, 42, 63, 164, 90, 120, 27, 31, 14, 19, 32, 174, 26, 67, 89, 97, 56, 146, 82, 133, 129, 109, 71, 58, 130, 182, 123, 176, 49, 36, 181, 38, 141, 151, 83, 77, 172, 132 are interleaved in the sequence.

[0629] FIG. 190 is a diagram showing a 71st example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0630] According to the GW pattern in FIG. 190, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is 30, 127, 60, 115, 80, 50, 150, 39, 176, 171, 47, 104, 70, 33, 56, 3, 10, 26, 19, 149, 153, 141, 98, 46, 64, 71, 130, 107, 94, 16, 164, 169, 57, 168, 126, 157, 133, 12, 154, 135, 35, 53, 40, 183, 28, 1, 160, 67, 163, 134, 181, 59, 99, 186, 86, 36, 178, 152, 48, 117, 44, 14, 66, 172, 17, 31, 182, 166, 187, 55, 62, 143, 69, 77, 9, 113, 158, 91, 189, 84, 151, 74, 45, 97, 122, 114, 75, 41, 162, 90, 110, 106, 116, 131, 129, 188, 92, 11, 147, 108, 20, 159, 146, 51, 29, 109, 89, 6, 96, 155, 43, 111, 138, 85, 119, 5, 22, 105, 170, 4, 15, 148, 145, 63, 0, 156, 81, 68, 13, 137, 79, 103, 2, 179, 38, 180, 132, 123, 144, 167, 140, 174, 49, 37, 82, 128, 101, 21, 124, 177, 121, 8, 23, 136, 42, 27, 139, 72, 185, 18, 65, 161, 7, 125, 88, 34, 73, 184, 52, 190, 120, 102, 100, 87, 95, 118, 83, 112, 175, 78, 58, 24, 165, 54, 61, 25, 191, 76, 142, 93, 173, 32 are interleaved in the sequence.

[0631] FIG. 191 is a diagram showing a 72nd example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0632] According to the GW pattern in Figure 191, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is 166, 161, 43, 77, 177, 54, 162, 185, 127, 62, 6, 64, 30, 12, 27, 89, 130, 116, 190, 28, 38, 135, 149, 164, 48, 173, 175, 71, 132, 68, 5, 111, 158, 24, 59, 26, 145, 118, 51, 37, 178, 69, 189, 163, 133, 98, 53, 29, 169, 188, 17, 180, 155, 73, 45, 22, 107, 104, 76, 143, 70, 88, 99, 124, 126, 34, 80, 10, 168, 66, 72, 123, 63, 140, 176, 49, 65, 50, 52, 122, 4, 181, 121, 57, 18, 101, 42, 179, 100, 157, 165, 106, 156, 95, 170, 174, 117, 109, 102, 186, 148, 3, 134, 96, 67, 150, 151, 153, 11, 83, 1, 105, 25, 144, 8, 108, 84, 78, 97, 141, 60, 16, 112, 7, 82, 93, 46, 137, 35, 103, 61, 113, 129, 20, 119, 92, 31, 154, 115, 56, 44, 90, 14, 131, 160, 2, 36, 21, 23, 110, 152, 187, 0, 184, 41, 183, 120, 146, 47, 114, 32, 81, 75, 39, 91, 136, 167, 172, 58, 147, 125, 86, 138, 94, 33, 79, 159, 87, 55, 171, 85, 182, 191, 9, 19, 74, 13, 142, 40, 139, 15, 128 are interleaved in the sequence.

[0633] FIG. 192 is a diagram showing a 73rd example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0634] According to the GW pattern in Figure 192, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is 191, 38, 101, 9, 62, 79, 127, 18, 51, 6, 95, 114, 35, 123, 31, 99, 133, 81, 136, 106, 5, 130, 159, 124, 146, 41, 110, 150, 185, 8, 158, 178, 119, 171, 121, 129, 164, 168, 111, 52, 177, 190, 85, 179, 142, 174, 46, 61, 176, 23, 163, 49, 28, 86, 2, 143, 120, 166, 13, 87, 27, 39, 115, 131, 92, 117, 187, 56, 11, 180, 118, 30, 149, 60, 71, 44, 103, 140, 48, 162, 125, 122, 126, 29, 153, 77, 72, 4, 7, 165, 25, 89, 26, 68, 20, 12, 141, 37, 139, 15, 36, 82, 21, 137, 80, 3, 57, 128, 42, 43, 47, 93, 147, 70, 50, 170, 54, 96, 17, 152, 24, 172, 10, 22, 45, 169, 83, 69, 134, 78, 64, 183, 76, 189, 184, 112, 109, 33, 88, 32, 105, 175, 94, 53, 1, 90, 66, 100, 19, 108, 104, 113, 58, 40, 144, 97, 138, 154, 148, 157, 67, 145, 102, 132, 173, 84, 167, 0, 98, 182, 156, 63, 135, 14, 181, 73, 75, 65, 161, 116, 186, 55, 34, 151, 91, 160, 107, 16, 188, 74, 155, 59 are interleaved in the sequence.

[0635] FIG. 193 is a diagram showing a 74th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0636] According to the GW pattern in Figure 193, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is 100, 152, 16, 39, 26, 58, 60, 6, 126, 7, 59, 75, 62, 47, 27, 113, 41, 115, 169, 30, 95, 189, 138, 136, 70, 140, 149, 187, 177, 141, 125, 171, 178, 134, 15, 154, 131, 183, 46, 35, 44, 11, 51, 170, 112, 20, 161, 159, 101, 52, 181, 71, 28, 128, 3, 167, 156, 123, 18, 139, 102, 13, 19, 37, 90, 105, 92, 135, 185, 121, 50, 158, 29, 104, 155, 12, 184, 93, 166, 14, 133, 146, 24, 191, 188, 116, 109, 89, 65, 45, 25, 21, 1, 76, 151, 180, 33, 124, 91, 107, 119, 5, 132, 118, 111, 96, 143, 150, 173, 108, 2, 122, 22, 148, 130, 142, 147, 67, 97, 103, 36, 63, 40, 117, 55, 68, 137, 144, 94, 83, 56, 79, 175, 0, 182, 114, 85, 86, 9, 10, 74, 106, 17, 190, 4, 34, 84, 98, 38, 88, 64, 78, 145, 77, 163, 42, 120, 69, 164, 48, 23, 129, 160, 81, 127, 82, 53, 72, 179, 31, 66, 32, 168, 110, 73, 186, 157, 172, 49, 165, 176, 80, 61, 174, 153, 162, 54, 99, 57, 87, 8, 43 are interleaved in the sequence.

[0637] FIG. 194 is a diagram showing the 75th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0638] According to the GW pattern in Figure 194, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is 21, 5, 2, 24, 12, 28, 52, 118, 129, 3, 122, 149, 105, 16, 136, 99, 133, 171, 84, 79, 59, 62, 155, 78, 134, 20, 1, 51, 22, 161, 173, 46, 172, 162, 55, 148, 70, 57, 121, 86, 131, 114, 31, 72, 104, 120, 164, 127, 83, 179, 187, 7, 108, 40, 73, 144, 48, 68, 60, 190, 135, 61, 116, 106, 19, 35, 143, 180, 102, 76, 182, 117, 93, 191, 165, 23, 80, 146, 153, 42, 53, 139, 124, 64, 167, 96, 138, 132, 158, 90, 110, 82, 39, 175, 170, 66, 145, 94, 119, 130, 98, 63, 87, 32, 160, 34, 151, 77, 95, 109, 56, 113, 147, 50, 38, 15, 156, 11, 169, 185, 183, 92, 186, 107, 10, 101, 33, 4, 150, 41, 81, 89, 166, 0, 30, 54, 168, 26, 140, 74, 100, 9, 111, 126, 43, 112, 25, 88, 44, 189, 37, 178, 141, 49, 13, 29, 8, 69, 154, 45, 97, 47, 36, 75, 137, 6, 115, 188, 85, 174, 17, 142, 18, 91, 163, 157, 177, 103, 125, 71, 14, 181, 65, 184, 176, 159, 128, 152, 58, 27, 123, 67 are interleaved in the sequence.

[0639] FIG. 195 is a diagram showing a 76th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0640] According to the GW pattern in Figure 195, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is 113, 23, 166, 150, 133, 130, 38, 18, 71, 115, 111, 44, 135, 11, 98, 96, 67, 114, 112, 87, 146, 119, 28, 86, 120, 49, 175, 14, 30, 144, 53, 165, 162, 128, 108, 39, 116, 158, 62, 110, 83, 93, 118, 80, 88, 173, 157, 102, 177, 132, 174, 59, 106, 34, 64, 22, 4, 29, 97, 155, 109, 9, 107, 92, 36, 24, 161, 50, 21, 137, 17, 43, 58, 124, 31, 37, 172, 100, 178, 129, 79, 160, 167, 32, 181, 154, 7, 183, 90, 54, 68, 191, 156, 104, 147, 10, 65, 81, 134, 169, 142, 57, 171, 78, 48, 47, 5, 40, 46, 51, 151, 77, 1, 72, 164, 152, 70, 141, 2, 89, 13, 182, 85, 52, 41, 66, 75, 63, 185, 148, 179, 138, 61, 73, 180, 189, 76, 84, 8, 27, 184, 105, 42, 69, 153, 188, 19, 131, 121, 26, 159, 45, 16, 186, 25, 176, 82, 103, 163, 99, 101, 122, 187, 20, 136, 126, 168, 145, 6, 91, 55, 117, 35, 56, 143, 140, 190, 125, 127, 74, 95, 94, 12, 149, 33, 0, 139, 3, 123, 170, 15, 60 are interleaved in the sequence.

[0641] FIG. 196 is a diagram showing a 77th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0642] According to the GW pattern in Figure 196, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is 131, 148, 141, 17, 53, 138, 45, 97, 112, 111, 77, 184, 129, 135, 27, 122, 2, 123, 156, 128, 80, 116, 40, 89, 84, 41, 105, 42, 39, 187, 145, 18, 54, 44, 183, 57, 136, 13, 65, 162, 51, 178, 59, 104, 163, 70, 87, 152, 94, 126, 23, 169, 9, 179, 177, 139, 130, 38, 35, 20, 86, 180, 48, 108, 47, 133, 167, 75, 168, 25, 67, 185, 91, 165, 157, 158, 110, 127, 82, 58, 50, 64, 76, 31, 159, 8, 79, 78, 146, 71, 69, 3, 36, 155, 160, 21, 29, 49, 28, 150, 81, 154, 149, 182, 24, 30, 72, 109, 173, 33, 113, 43, 55, 189, 132, 176, 120, 172, 166, 143, 90, 125, 7, 5, 66, 12, 98, 83, 10, 62, 11, 175, 85, 0, 63, 181, 188, 74, 171, 117, 106, 61, 153, 174, 147, 93, 190, 34, 142, 100, 6, 1, 140, 191, 161, 19, 151, 14, 73, 99, 121, 119, 92, 95, 115, 118, 186, 60, 144, 22, 32, 52, 164, 15, 88, 46, 114, 101, 124, 26, 96, 4, 107, 103, 16, 37, 102, 56, 170, 68, 134, 137 are interleaved in the sequence.

[0643] FIG. 197 is a diagram showing the 78th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0644] According to the GW pattern in Figure 197, the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is 93, 61, 37, 170, 63, 60, 135, 5, 158, 47, 65, 179, 76, 182, 72, 20, 104, 7, 181, 11, 117, 152, 184, 172, 143, 92, 109, 177, 191, 119, 132, 1, 98, 10, 148, 35, 126, 9, 18, 70, 190, 38, 66, 54, 62, 122, 100, 3, 2, 189, 144, 153, 165, 14, 154, 44, 161, 113, 147, 12, 90, 167, 112, 34, 39, 139, 142, 41, 159, 149, 82, 131, 88, 106, 138, 105, 55, 163, 71, 168, 80, 96, 108, 40, 50, 25, 114, 79, 103, 141, 151, 69, 74, 110, 36, 24, 67, 145, 26, 8, 56, 180, 13, 17, 134, 28, 129, 185, 85, 121, 137, 136, 68, 86, 188, 0, 124, 120, 127, 32, 94, 83, 133, 97, 31, 58, 33, 57, 166, 162, 183, 186, 81, 111, 19, 107, 155, 42, 84, 6, 43, 130, 48, 123, 64, 78, 53, 173, 95, 75, 45, 174, 178, 160, 15, 187, 102, 23, 150, 156, 101, 99, 91, 157, 128, 175, 59, 125, 22, 46, 115, 164, 52, 16, 21, 30, 176, 146, 51, 116, 87, 140, 77, 73, 89, 169, 4, 171, 27, 49, 29, 118 are interleaved in the sequence.

[0645] The above-described first to 78th examples of GW patterns for an LDPC code having a code length N of 69120 bits can be applied to any combination of an LDPC code having a code length N of 69120 bits, any coding rate r, any modulation method, and any constellation.

[0646] However, for group-wise interleaving, the error rate can be further improved for each combination by setting the GW pattern to be applied for each combination of the code length N of the LDPC code, the coding rate r of the LDPC code, the modulation method, and the constellation.

[0647] The GW pattern of FIG. 120 can achieve a particularly good error rate by applying it to a combination of, for example, an LDPC code of N=69120, r=2 / 16 (corresponding to the parity check matrix initial value table) of FIG. 30 (an LDPC code with a code length N of 69120 and a coding rate r of 2 / 16), QPSK, and QPSK-UC of FIG. 96 and FIG. 97.

[0648] The GW pattern in FIG. 121 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=3 / 16 in FIGS. 31 and 32, QPSK, and QPSK-UC in FIGS. 96 and 97.

[0649] The GW pattern of FIG. 122 can achieve a particularly good error rate by applying it to, for example, the LDPC code of N=69120, r=4 / 16 of FIG. 33, QPSK, and a combination of QPSK-UC of FIGS. 96 and 97.

[0650] The GW pattern of FIG. 123 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=5 / 16 of FIGS. 34 and 35, QPSK, and QPSK-UC of FIGS. 96 and 97.

[0651] The GW pattern of FIG. 124 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=6 / 16 of FIGS. 36 and 37, QPSK, and QPSK-UC of FIGS. 96 and 97, for example.

[0652] The GW pattern of FIG. 125 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=7 / 16 of FIGS. 38 and 39, QPSK, and QPSK-UC of FIGS. 96 and 97, for example.

[0653] The GW pattern of FIG. 126 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=8 / 16 of FIGS. 46 and 47, QPSK, and QPSK-UC of FIGS. 96 and 97, for example.

[0654] The GW pattern in FIG. 127 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=9 / 16 in FIGS. 50 to 52, QPSK, and QPSK-UC in FIGS. 96 and 97, for example.

[0655] The GW pattern of FIG. 128 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=10 / 16 of FIGS. 56 to 58, QPSK, and QPSK-UC of FIGS. 96 and 97, for example.

[0656] The GW pattern of FIG. 129 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=11 / 16 of FIGS. 62 to 64, QPSK, and QPSK-UC of FIGS. 96 and 97, for example.

[0657] The GW pattern in FIG. 130 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=12 / 16 in FIGS. 68 to 70, QPSK, and QPSK-UC in FIGS. 96 and 97, for example.

[0658] The GW pattern in FIG. 131 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=13 / 16 in FIGS. 74 to 76, QPSK, and QPSK-UC in FIGS. 96 and 97, for example.

[0659] The GW pattern in FIG. 132 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=14 / 16 in FIGS. 80 to 82, QPSK, and QPSK-UC in FIGS. 96 and 97, for example.

[0660] The GW pattern of FIG. 133 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=3 / 16 of FIGS. 31 and 32, 16QAM, and 16QAM-UC of FIGS. 98 and 99.

[0661] The GW pattern of FIG. 134 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=5 / 16 of FIGS. 34 and 35, 16QAM, and 16QAM-UC of FIGS. 98 and 99.

[0662] The GW pattern of FIG. 135 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=7 / 16 of FIGS. 38 and 39, 16QAM, and 16QAM-UC of FIGS. 98 and 99.

[0663] The GW pattern of FIG. 136 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=9 / 16 of FIGS. 50 to 52, 16QAM, and 16QAM-UC of FIGS. 98 and 99, for example.

[0664] The GW pattern in FIG. 137 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=11 / 16 in FIGS. 62 to 64, 16QAM, and 16QAM-UC in FIGS. 98 and 99, for example.

[0665] The GW pattern in FIG. 138 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=13 / 16 in FIGS. 74 to 76, 16QAM, and 16QAM-UC in FIGS. 98 and 99.

[0666] The GW pattern of Figure 139 can achieve a particularly good error rate by applying it to, for example, the combination of the LDPC code of N=69120, r=2 / 16 of Figure 30, 64QAM, and 64QAM-UC of Figures 100 and 101.

[0667] The GW pattern of FIG. 140 can achieve a particularly good error rate by applying it to, for example, the combination of the LDPC code of N=69120, r=4 / 16 of FIG. 33, 64QAM, and 64QAM-UC of FIGS. 100 and 101.

[0668] The GW pattern in FIG. 141 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=6 / 16 in FIGS. 36 and 37, 64QAM, and 64QAM-UC in FIGS. 100 and 101.

[0669] The GW pattern in FIG. 142 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=8 / 16 in FIGS. 46 and 47, 64QAM, and 64QAM-UC in FIGS. 100 and 101.

[0670] The GW pattern in FIG. 143 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=10 / 16 in FIGS. 56 to 58, 64QAM, and 64QAM-UC in FIGS. 100 and 101, for example.

[0671] The GW pattern in FIG. 144 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=12 / 16 in FIGS. 68 to 70, 64QAM, and 64QAM-UC in FIGS. 100 and 101.

[0672] The GW pattern in FIG. 145 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=14 / 16 in FIGS. 80 to 82, 64QAM, and 64QAM-UC in FIGS. 100 and 101, for example.

[0673] The GW pattern in FIG. 146 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=3 / 16 in FIGS. 31 and 32, 256QAM, and 256QAM-UC in FIGS. 102 and 103.

[0674] The GW pattern in FIG. 147 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=5 / 16 in FIGS. 34 and 35, 256QAM, and 256QAM-UC in FIGS. 102 and 103, for example.

[0675] The GW pattern in FIG. 148 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=7 / 16 in FIGS. 38 and 39, 256QAM, and 256QAM-UC in FIGS. 102 and 103.

[0676] The GW pattern in FIG. 149 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=9 / 16 in FIGS. 50 to 52, 256QAM, and 256QAM-UC in FIGS. 102 and 103.

[0677] The GW pattern in FIG. 150 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=11 / 16 in FIGS. 62 to 64, 256QAM, and 256QAM-UC in FIGS. 102 and 103.

[0678] The GW pattern in FIG. 151 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=13 / 16 in FIGS. 74 to 76, 256QAM, and 256QAM-UC in FIGS. 102 and 103.

[0679] The GW pattern in FIG. 152 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=2 / 16 in FIG. 30, 1024QAM, and 1024QAM-UC in FIGS. 104 and 105.

[0680] The GW pattern in FIG. 153 can achieve a particularly good error rate by applying it to, for example, the combination of the LDPC code of N=69120, r=4 / 16 in FIG. 33, 1024QAM, and 1024QAM-UC in FIGS. 104 and 105.

[0681] The GW pattern in Figure 154 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=6 / 16 in Figures 36 and 37, 1024QAM, and 1024QAM-UC in Figures 104 and 105.

[0682] The GW pattern in Figure 155 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=8 / 16 in Figures 46 and 47, 1024QAM, and 1024QAM-UC in Figures 104 and 105.

[0683] The GW pattern in Figure 156 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=10 / 16 in Figures 56 to 58, 1024QAM, and 1024QAM-UC in Figures 104 and 105, for example.

[0684] The GW pattern in FIG. 157 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=12 / 16 in FIGS. 68 to 70, 1024QAM, and 1024QAM-UC in FIGS. 104 and 105, for example.

[0685] The GW pattern in FIG. 158 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=14 / 16 in FIGS. 80 to 82, 1024QAM, and 1024QAM-UC in FIGS. 104 and 105, for example.

[0686] The GW pattern in Figure 159 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=3 / 16 in Figures 31 and 32, 4096QAM, and 4096QAM-UC in Figures 106 and 107.

[0687] The GW pattern in FIG. 160 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=5 / 16 in FIGS. 34 and 35, 4096QAM, and 4096QAM-UC in FIGS. 106 and 107, for example.

[0688] The GW pattern in FIG. 161 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=7 / 16 in FIGS. 38 and 39, 4096QAM, and 4096QAM-UC in FIGS. 106 and 107.

[0689] The GW pattern in FIG. 162 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=9 / 16 in FIGS. 50 to 52, 4096QAM, and 4096QAM-UC in FIGS. 106 and 107.

[0690] The GW pattern in Figure 163 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=11 / 16 in Figures 62 to 64, 4096QAM, and 4096QAM-UC in Figures 106 and 107.

[0691] The GW pattern in FIG. 164 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=13 / 16 in FIGS. 74 to 76, 4096QAM, and 4096QAM-UC in FIGS. 106 and 107, for example.

[0692] The GW pattern of Figure 165 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=2 / 16 of Figure 30, 16QAM, and 16QAM-2D-NUC of Figure 108.

[0693] The GW pattern of Figure 166 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=4 / 16 of Figure 33, 16QAM, and 16QAM-2D-NUC of Figure 108, for example.

[0694] The GW pattern in Figure 167 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=6 / 16 in Figures 36 and 37, 16QAM, and 16QAM-2D-NUC in Figure 108, for example.

[0695] The GW pattern in Figure 168 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=8 / 16 in Figures 46 and 47, 16QAM, and 16QAM-2D-NUC in Figure 108, for example.

[0696] The GW pattern in Figure 169 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=10 / 16 in Figures 56 to 58, 16QAM, and 16QAM-2D-NUC in Figure 108, for example.

[0697] The GW pattern in FIG. 170 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=12 / 16 in FIGS. 68 to 70, 16QAM, and 16QAM-2D-NUC in FIG. 108, for example.

[0698] The GW pattern in FIG. 171 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=14 / 16 in FIGS. 80 to 82, 16QAM, and 16QAM-2D-NUC in FIG. 108, for example.

[0699] The GW pattern in Figure 172 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=3 / 16 in Figures 31 and 32, 64QAM, and 64QAM-2D-NUC in Figure 109, for example.

[0700] The GW pattern in Figure 173 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=5 / 16 in Figures 34 and 35, 64QAM, and 64QAM-2D-NUC in Figure 109.

[0701] The GW pattern in Figure 174 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=7 / 16 in Figures 38 and 39, 64QAM, and 64QAM-2D-NUC in Figure 109.

[0702] The GW pattern in Figure 175 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=9 / 16 in Figures 50 to 52, 64QAM, and 64QAM-2D-NUC in Figure 109, for example.

[0703] The GW pattern in Figure 176 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=11 / 16 in Figures 62 to 64, 64QAM, and 64QAM-2D-NUC in Figure 109, for example.

[0704] The GW pattern in Figure 177 can achieve a particularly good error rate by applying it to a combination of the LDPC code of N=69120, r=13 / 16 in Figures 74 to 76, 64QAM, and 64QAM-2D-NUC in Figure 109, for example.

[0705] The GW pattern of Figure 178 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=2 / 16 of Figure 30, 256QAM, and 256QAM-2D-NUC of Figures 110 and 111.

[0706] The GW pattern of Figure 179 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=4 / 16 of Figure 33, 256QAM, and 256QAM-2D-NUC of Figures 110 and 111.

[0707] The GW pattern of Figure 180 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=6 / 16 of Figures 36 and 37, 256QAM, and 256QAM-2D-NUC of Figures 110 and 111.

[0708] The GW pattern in Figure 181 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=8 / 16 in Figures 46 and 47, 256QAM, and 256QAM-2D-NUC in Figures 110 and 111.

[0709] The GW pattern in Figure 182 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=10 / 16 in Figures 56 to 58, 256QAM, and 256QAM-2D-NUC in Figures 110 and 111.

[0710] The GW pattern in Figure 183 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=12 / 16 in Figures 68 to 70, 256QAM, and 256QAM-2D-NUC in Figures 110 and 111.

[0711] The GW pattern in Figure 184 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=14 / 16 in Figures 80 to 82, 256QAM, and 256QAM-2D-NUC in Figures 110 and 111.

[0712] The GW pattern in Figure 185 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=3 / 16 in Figures 31 and 32, 1024QAM, and 1024QAM-1D-NUC in Figures 112 and 113.

[0713] The GW pattern of Figure 186 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=5 / 16 of Figures 34 and 35, 1024QAM, and 1024QAM-1D-NUC of Figures 112 and 113.

[0714] The GW pattern in Figure 187 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=7 / 16 in Figures 38 and 39, 1024QAM, and 1024QAM-1D-NUC in Figures 112 and 113.

[0715] The GW pattern of Figure 188 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=9 / 16 of Figures 50 to 52, 1024QAM, and 1024QAM-1D-NUC of Figures 112 and 113.

[0716] The GW pattern of Figure 189 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=11 / 16 of Figures 62 to 64, 1024QAM, and 1024QAM-1D-NUC of Figures 112 and 113.

[0717] The GW pattern in Figure 190 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=13 / 16 in Figures 74 to 76, 1024QAM, and 1024QAM-1D-NUC in Figures 112 and 113.

[0718] The GW pattern in Figure 191 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=2 / 16 in Figure 30, 4096QAM, and 4096QAM-1D-NUC in Figures 114 to 116.

[0719] The GW pattern in Figure 192 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=4 / 16 in Figure 33, 4096QAM, and 4096QAM-1D-NUC in Figures 114 to 116.

[0720] The GW pattern in Figure 193 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=6 / 16 in Figures 36 and 37, 4096QAM, and 4096QAM-1D-NUC in Figures 114 to 116.

[0721] The GW pattern in Figure 194 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=8 / 16 in Figures 46 and 47, 4096QAM, and 4096QAM-1D-NUC in Figures 114 to 116.

[0722] The GW pattern in Figure 195 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=10 / 16 in Figures 56 to 58, 4096QAM, and 4096QAM-1D-NUC in Figures 114 to 116.

[0723] The GW pattern in Figure 196 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=12 / 16 in Figures 68 to 70, 4096QAM, and 4096QAM-1D-NUC in Figures 114 to 116.

[0724] The GW pattern in Figure 197 can achieve a particularly good error rate by applying it to a combination of, for example, the LDPC code of N=69120, r=14 / 16 in Figures 80 to 82, 4096QAM, and 4096QAM-1D-NUC in Figures 114 to 116.

[0725] <Other examples of constellations and GW patterns>

[0726] FIG. 198 is a diagram showing an example of the coordinates of other 16QAM-2D-NUC signal points that can be used for the new LDPC code.

[0727] In FIG. 198, the horizontal axis represents the real axis direction, and the vertical axis represents the imaginary axis direction.

[0728] Figure 198 is a diagram showing an example of the coordinates of signal points of another 16QAM-2D-NUC (hereinafter also referred to as new 16QAM-2D-NUC) that can be used for the Type A code of Figure 33, where the code length N is 69120 bits and r=4 / 16.

[0729] The coordinates of the signal points of 16QAM-2D-NUC (hereinafter also referred to as old 16QAM-2D-NUC) shown in Figure 108 and usable for the Type A code of Figure 33 with code length N of 69120 bits and r = 4 / 16 are expressed as w0 = w1 = w2 = w3 = 0.707107 + j0.707107.

[0730] In contrast, the coordinates of the signal points of the new 16QAM-2D-NUC are expressed as w0 = 0.657419 + j0.829501, w1 = 0.524706 + j0.684103, w2 = 0.92367 + j0.686811, and w3 = 0.689478 + j0.579793.

[0731] Figure 199 shows the simulation results of the BER when the old 16QAM-2D-NUC and the new 16QAM-2D-NUC are applied to the Type A code of Figure 33 with a code length N of 69120 bits and r=4 / 16.

[0732] In Figure 199, the horizontal axis is E s / N0 (the signal power to noise power ratio per symbol), and the vertical axis represents the BER.

[0733] As described above, for the combination of Type A code with code length N of 69120 bits and r=4 / 16, 16QAM, and the old 16QAM-2D-NUC in Figure 33, a good error rate can be achieved by applying the GW pattern in Figure 166.

[0734] Therefore, in Figure 199, the GW pattern of Figure 166 is adopted as the GW pattern to be applied to the Type A code of Figure 33 with a code length N of 69120 bits and r=4 / 16, and the simulation results of the BER (shown by a rectangle in the figure) when the old 16QAM-2D-NUC of Figure 108 is applied to the combination of the Type A code of Figure 33 with a code length N of 69120 bits and r=4 / 16, 16QAM, and the GW pattern of Figure 166, and the BER (shown by a cross in the figure) when the new 16QAM-2D-NUC of Figure 198 is applied are shown.

[0735] In the simulation, a Rayleigh fading communication path (channel) was adopted as the communication path 13 .

[0736] Since a Rayleigh fading channel is similar to a multipath environment, improving the BER in a Rayleigh fading channel can improve the gain when the transmission system of FIG. 7 is used in a multipath environment.

[0737] According to Figure 199, a better BER can be obtained when the new 16QAM-2D-NUC is applied than when the old 16QAM-2D-NUC is applied. In other words, at the same E s It can be seen that the BER is lower at / N0.

[0738] FIG. 200 is a diagram showing the simulation results of the required CNR (carrier-to-noise ratio) of the Type A code of FIG. 33, where the code length N is 69120 bits and r=4 / 16.

[0739] The required CNR is the minimum CNR that can achieve a certain BER, and in this case, for example, is the CNR that can achieve BER=1E-7.

[0740] Figure 200 shows the simulation results of the required CNR when the old 16QAM-2D-NUC is applied to the combination of Type A code with r=4 / 16 and code length N of 69120 bits, 16QAM, and the GW pattern of Figure 166, and the required CNR when the new 16QAM-2D-NUC is applied.

[0741] According to FIG. 200, when the new 16QAM-2D-NUC is applied, the required CNR can be improved by 0.229 dB, which is shown as a difference, compared to when the old 16QAM-2D-NUC is applied.

[0742] FIG. 201 is a diagram showing a 79th example of a GW pattern for an LDPC code having a code length N of 69120 bits.

[0743] According to the GW pattern of FIG. 201 (hereinafter also referred to as the new GW pattern), the arrangement of bit groups 0 to 191 of the 69120-bit LDPC code is 154, 83, 159, 153, 136, 6, 19, 73, 122, 40, 97, 144, 101, 106, 130, 174, 48, 176, 14, 27, 52, 152, 173, 63, 39, 92, 114, 98, 190, 149, 103, 160, 118, 13, 29, 51, 66, 168, 180, 23, 170, 24, 5, 157, 28, 45, 53, 68, 25, 191, 148, 139, 15, 67, 77, 100, 58, 91, 50, 131, 65, 17, 11, 123, 86, 135, 115, 120, 59, 162, 9, 189, 21, 12, 179, 178, 110, 35, 137, 3, 84, 177, 124, 186, 143, 26, 96, 80, 31, 169, 119, 33, 87, 140, 88, 171, 133, 150, 151, 72, 85, 89, 112, 126, 167, 56, 49, 187, 138, 145, 18, 32, 90, 158, 54, 104, 62, 165, 79, 1, 81, 102, 44, 61, 10, 166, 2, 116, 161, 60, 108, 142, 30, 78, 127, 111, 46, 43, 184, 163, 64, 22, 41, 156, 70, 20, 42, 182, 55, 95, 105, 132, 38, 69, 134, 74, 155, 141, 172, 57, 7, 175, 128, 75, 107, 109, 99, 147, 146, 117, 125, 185, 0, 76, 82, 129, 36, 34, 93, 188, 113, 71, 183, 121, 47, 16, 164, 4, 181, 94, 37, 8 are interleaved in the sequence.

[0744] The new GW pattern can achieve an even better error rate by applying it to a combination of, for example, Type A code with a code length N of 69120 bits and r=4 / 16, 16QAM, and the new 16QAM-2D-NUC in FIG. 198, as shown in FIG.

[0745] That is, for the combination of Type A code with r=4 / 16 and code length N of 69120 bits and new 16QAM-2D-NUC, by applying the GW pattern of Figure 166 (hereinafter also referred to as the old GW pattern), the BER in the Rayleigh fading channel can be improved as shown in Figure 199, but by applying the new GW pattern, the BER in the Rayleigh fading channel can be further improved.

[0746] FIG. 202 is a diagram showing simulation results of the BER for a combination of the Type A code of r=4 / 16 with a code length N of 69120 bits, 16QAM, new 16QAM-2D-NUC, and new GW pattern in FIG.

[0747] In Figure 202, the horizontal axis is E s / N0, and the vertical axis represents BER.

[0748] In Figure 202, as in Figure 199, the rectangles represent the BER of the combination of Type A code with r=4 / 16 and code length N of 69120 bits, 16QAM, the old GW pattern, and the old 16QAM-2D-NUC, and the crosses represent the BER of the combination of Type A code with r=4 / 16 and code length N of 69120 bits, 16QAM, the old GW pattern, and the new 16QAM-2D-NUC.

[0749] Furthermore, in FIG. 202, the circles represent the BER of the combination of Type A code with r=4 / 16 and code length N of 69120 bits, 16QAM, new GW pattern, and new 16QAM-2D-NUC.

[0750] According to Figure 202, it can be confirmed that a better BER can be obtained when the new GW pattern is applied to the combination of Type A code with r=4 / 16 and code length N of 69120 bits, 16QAM, and new 16QAM-2D-NUC than when the old GW pattern is applied.

[0751] FIG. 203 is a diagram showing simulation results of required CNR for a combination of Type A code with r=4 / 16 and code length N of 69120 bits, 16QAM, new 16QAM-2D-NUC, and new GW pattern in FIG.

[0752] In Figure 203, the required CNR of the combination of Type A code with r=4 / 16 and code length N of 69120 bits, 16QAM, new 16QAM-2D-NUC, and new GW pattern (hereinafter also referred to as the required CNR of new 16QAM-2D-NUC + new GW pattern) is shown together with the required CNR of Type A code with r=4 / 16 and code length N of 69120 bits, 16QAM, old 16QAM-2D-NUC, Also shown are the required CNR for the combination of the old GW pattern (hereinafter also referred to as the required CNR of the old 16QAM-2D-NUC + old GW pattern), and the required CNR for the combination of a Type A code with a code length N of 69120 bits and r=4 / 16, 16QAM, new 16QAM-2D-NUC, and the old GW pattern (hereinafter also referred to as the required CNR of the new 16QAM-2D-NUC + old GW pattern).

[0753] In Figure 203, Difference 1 represents the difference shown in Figure 200, i.e., the difference between the required CNR of the new 16QAM-2D-NUC + old GW pattern and the required CNR of the old 16QAM-2D-NUC + old GW pattern. Difference 2 represents the difference between the required CNR of the new 16QAM-2D-NUC + new GW pattern and the required CNR of the old 16QAM-2D-NUC + old GW pattern.

[0754] The improvement in the required CNR of the new 16QAM-2D-NUC + old GW pattern compared to the required CNR of the old 16QAM-2D-NUC + old GW pattern is 0.229 dB, as shown in difference 1, while the improvement in the required CNR of the new 16QAM-2D-NUC + new GW pattern is 0.326 dB, as shown in difference 2.

[0755] Therefore, by applying both the new 16QAM-2D-NUC and the new GW pattern, the required CNR can be further improved.

[0756] <Configuration example of receiving device 12>

[0757] FIG. 204 is a block diagram showing an example of the configuration of the receiving device 12 of FIG.

[0758] The OFDM operation unit 151 receives an OFDM signal from the transmitting device 11 (FIG. 7) and performs signal processing on the OFDM signal. Data obtained by the signal processing by the OFDM operation unit 151 is supplied to a frame management unit (Frame Management) 152.

[0759] The frame management unit 152 processes (frame interpretation) the frames composed of data supplied from the OFDM processing unit 151, and supplies the resulting target data signal and control data signal to frequency deinterleavers 161 and 153, respectively.

[0760] The frequency deinterleaver 153 performs frequency deinterleaving on the data from the frame management unit 152 in units of symbols, and supplies the result to a demapper 154 .

[0761] The demapper 154 performs orthogonal demodulation by demapping (signal point arrangement decoding) the data (data on a constellation) from the frequency deinterleaver 153 based on the signal point arrangement (constellation) determined by the orthogonal modulation performed on the transmitting device 11 side, and supplies the resulting data (LDPC code (likelihood)) to an LDPC decoder 155.

[0762] The LDPC decoder 155 performs LDPC decoding on the LDPC code from the demapper 154 and supplies the resulting LDPC target data (here, BCH code) to a BCH decoder 156.

[0763] The BCH decoder 156 performs BCH decoding on the LDPC target data from the LDPC decoder 155, and outputs the resulting control data (signaling).

[0764] On the other hand, the frequency deinterleaver 161 performs frequency deinterleaving on the data from the frame management unit 152 in units of symbols, and supplies the result to a SISO / MISO decoder 162 .

[0765] The SISO / MISO decoder 162 performs space-time decoding on the data from the frequency deinterleaver 161 and supplies the result to a time deinterleaver 163 .

[0766] The time deinterleaver 163 performs time deinterleaving on the data from the SISO / MISO decoder 162 in units of symbols, and supplies the result to a demapper 164 .

[0767] The demapper 164 performs orthogonal demodulation by demapping (signal point arrangement decoding) the data (data on a constellation) from the time deinterleaver 163 based on the signal point arrangement (constellation) determined by the orthogonal modulation performed on the transmitting device 11 side, and supplies the resulting data to a bit deinterleaver 165.

[0768] The bit deinterleaver 165 performs bit deinterleaving on the data from the demapper 164 and supplies the LDPC code (likelihood), which is the bit deinterleaved data, to the LDPC decoder 166.

[0769] The LDPC decoder 166 performs LDPC decoding on the LDPC code from the bit deinterleaver 165 and supplies the resulting LDPC target data (here, BCH code) to the BCH decoder 167.

[0770] The BCH decoder 167 performs BCH decoding on the LDPC target data from the LDPC decoder 155 and supplies the resulting data to a BB descrambler 168 .

[0771] The BB descrambler 168 performs BB descrambling on the data from the BCH decoder 167 and supplies the resulting data to a null deletion unit (Null Deletion) 169 .

[0772] The null deletion unit 169 deletes the nulls inserted by the padder 112 in FIG. 8 from the data from the BB descrambler 168 and supplies the data to a demultiplexer 170 .

[0773] The demultiplexer 170 separates one or more streams (target data) multiplexed into the data from the null deletion unit 169, performs necessary processing, and outputs the result as an output stream.

[0774] The receiving device 12 can be configured without some of the blocks shown in Fig. 204. That is, for example, when the transmitting device 11 (Fig. 8) is configured without the time interleaver 118, the SISO / MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124, the receiving device 12 can be configured without the time deinterleaver 163, the SISO / MISO decoder 162, the frequency deinterleaver 161, and the frequency deinterleaver 153, which are blocks corresponding to the time interleaver 118, the SISO / MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124 of the transmitting device 11, respectively.

[0775] <Configuration example of bit deinterleaver 165>

[0776] FIG. 205 is a block diagram showing an example of the configuration of the bit deinterleaver 165 of FIG. 204.

[0777] The bit deinterleaver 165 is made up of the block deinterleaver 54 and the group-wise deinterleaver 55, and performs (bit) deinterleaving of the symbol bits of the symbols that are the data from the demapper 164 (FIG. 204).

[0778] That is, the block deinterleaver 54 performs block deinterleaving (the reverse process of block interleaving) corresponding to the block interleaving performed by the block interleaver 25 of Figure 9 on the symbol bits of the symbol from the demapper 164, that is, block deinterleaving that returns the positions of the code bits (of the likelihoods) of the LDPC code rearranged by block interleaving to their original positions, and supplies the resulting LDPC code to the group-wise deinterleaver 55.

[0779] The group-wise deinterleaver 55 performs group-wise deinterleaving (the reverse process of group-wise interleaving) on ​​the LDPC code from the block deinterleaver 54, which corresponds to the group-wise interleaving performed by the group-wise interleaver 24 in Figure 9. That is, the group-wise deinterleaver 55 performs group-wise deinterleaving to restore the original arrangement by rearranging the code bits of the LDPC code, whose arrangement has been changed on a bit group basis by the group-wise interleaving described in Figure 119, on a bit group basis.

[0780] Here, when the LDPC code supplied from the demapper 164 to the bit deinterleaver 165 has been subjected to parity interleaving, group-wise interleaving, and block interleaving, the bit deinterleaver 165 can perform all of the following: parity deinterleaving corresponding to parity interleaving (the inverse process of parity interleaving, i.e., parity deinterleaving that returns the code bits of the LDPC code whose order has been changed by parity interleaving to their original order), block deinterleaving corresponding to block interleaving, and group-wise deinterleaving corresponding to group-wise interleaving.

[0781] However, in the bit deinterleaver 165 of Figure 205, a block deinterleaver 54 that performs block deinterleaving corresponding to block interleaving and a group-wise deinterleaver 55 that performs group-wise deinterleaving corresponding to group-wise interleaving are provided, but a block that performs parity deinterleaving corresponding to parity interleaving is not provided, and parity deinterleaving is not performed.

[0782] Therefore, the LDPC decoder 166 is supplied with an LDPC code that has been block deinterleaved and group-wise deinterleaved, but not parity deinterleaved, from the bit deinterleaver 165 (the group-wise deinterleaver 55 thereof).

[0783] The LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using a transformed parity check matrix obtained by performing at least column permutation equivalent to parity interleaving on the parity check matrix H of the Type B method used for LDPC encoding by the LDPC encoder 115 of FIG. 8, or a transformed parity check matrix (FIG. 29) obtained by performing row permutation on the parity check matrix of the Type A method (FIG. 27), and outputs the resulting data as the decoded result of the LDPC target data.

[0784] FIG. 206 is a flowchart illustrating the processing performed by the demapper 164, the bit deinterleaver 165, and the LDPC decoder 166 in FIG.

[0785] In step S111, the demapper 164 demaps and orthogonally demodulates the data from the time deinterleaver 163 (data on the constellation mapped to signal points), and supplies the data to the bit deinterleaver 165, and the process proceeds to step S112.

[0786] In step S112, the bit deinterleaver 165 deinterleaves (bit deinterleaves) the data from the demapper 164, and the process proceeds to step S113.

[0787] That is, in step S112, in the bit deinterleaver 165, the block deinterleaver 54 performs block deinterleaving on the data (symbols) from the demapper 164, and supplies the resulting code bits of the LDPC code to the group-wise deinterleaver 55.

[0788] The group-wise deinterleaver 55 performs group-wise deinterleaving on the LDPC code from the block deinterleaver 54, and supplies the resulting LDPC code (the likelihood of the LDPC code) to the LDPC decoder 166.

[0789] In step S113, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the group-wise deinterleaver 55 using the parity-check matrix H that the LDPC encoder 115 in FIG. 8 used for LDPC encoding. That is, for example, it is performed using a transformed parity-check matrix obtained from the parity-check matrix H, and the resulting data is output to the BCH decoder 167 as the decoding result of the LDPC target data.

[0790] Note that in FIG. 205 as well, for the sake of convenience of explanation, similar to the case of FIG. 9, the block deinterleaver 54 that performs block deinterleaving and the group-wise deinterleaver 55 that performs group-wise deinterleaving are configured separately. However, the block deinterleaver 54 and the group-wise deinterleaver 55 can be integrally configured.

[0791] Also, in the transmission device 11, when group-wise interleaving is not performed, the reception device 12 can be configured without providing the group-wise deinterleaver 55 that performs group-wise deinterleaving.

[0792] <LDPC decoding>

[0793] The LDPC decoding performed by the LDPC decoder 166 in FIG. 204 will be further described.

[0794] In the LDPC decoder 166 in FIG. 204, as described above, for the LDPC code from the group-wise deinterleaver 55 where block deinterleaving and group-wise deinterleaving are performed and parity deinterleaving is not performed, LDPC decoding is performed using a transformed parity-check matrix obtained by performing at least column permutation corresponding to parity deinterleaving on the type B parity-check matrix H that the LDPC encoder 115 in FIG. 8 used for LDPC encoding, or a transformed parity-check matrix (FIG. 29) obtained by performing row permutation on the type A parity-check matrix (FIG. 27).

[0795] Here, LDPC decoding has previously been proposed in which LDPC decoding is performed using a conversion check matrix, making it possible to suppress the circuit size while keeping the operating frequency within a sufficiently feasible range (see, for example, Patent No. 4224777).

[0796] First, the previously proposed LDPC decoding using a transformed parity check matrix will be described with reference to FIGS.

[0797] FIG. 207 is a diagram showing an example of a parity check matrix H of an LDPC code having a code length N of 90 and a coding rate of 2 / 3.

[0798] In FIG. 207 (as well as in FIGS. 208 and 209 described later), 0 is represented by a period (.).

[0799] In the check matrix H in FIG. 207, the parity matrix has a staircase structure.

[0800] FIG. 208 is a diagram showing a parity check matrix H' obtained by performing row permutation of equation (11) and column permutation of equation (12) on the parity check matrix H of FIG. 207. In FIG.

[0801] Line replacement: 6s+t+1st line → 5t+s+1st line ···(11)

[0802] Column replacement: 6x+y+61st column → 5y+x+61st column ···(12)

[0803] In the formulas (11) and (12), s, t, x, and y are integers in the ranges of 0≦s<5, 0≦t<6, 0≦x<5, and 0≦t<6, respectively.

[0804] According to the row permutation of equation (11), lines 1, 7, 13, 19, and 25, which have a remainder of 1 when divided by 6, are permuted into lines 1, 2, 3, 4, and 5, respectively, and lines 2, 8, 14, 20, and 26, which have a remainder of 2 when divided by 6, are permuted into lines 6, 7, 8, 9, and 10, respectively.

[0805] Furthermore, according to the column permutation in equation (12), for columns 61 and beyond (parity matrix), columns 61, 67, 73, 79, and 85, which have a remainder of 1 when divided by 6, are permuted as columns 61, 62, 63, 64, and 65, respectively, and columns 62, 68, 74, 80, and 86, which have a remainder of 2 when divided by 6, are permuted as columns 66, 67, 68, 69, and 70, respectively.

[0806] In this way, the matrix obtained by permuting rows and columns of the parity check matrix H in FIG. 207 is the parity check matrix H' in FIG. 208.

[0807] Here, even if row permutation is performed on the check matrix H, it does not affect the arrangement of code bits of the LDPC code.

[0808] Furthermore, the column permutation in equation (12) corresponds to the parity interleaving described above, in which the K+qx+y+1th code bit is interleaved at the K+Py+x+1th code bit position, when the information length K is 60, the unit size P is 5, and the divisor q (=M / P) of the parity length M (here, 30) is 6.

[0809] Therefore, the check matrix H' in Figure 208 is a transformed check matrix obtained by at least performing column permutation to replace the K+qx+y+1-th column of the check matrix H in Figure 207 (hereinafter referred to as the original check matrix, as appropriate) with the K+Py+x+1-th column.

[0810] For the converted parity check matrix H' in Figure 208, when the LDPC code of the original parity check matrix H in Figure 207 is multiplied by the same permutation as in equation (12), a zero vector is output. That is, when the row vector c as the LDPC code (1 codeword) of the original parity check matrix H is subjected to the column permutation in equation (12) and the row vector obtained is expressed as c', from the properties of the parity check matrix, Hc T is a 0 vector, so H'c' T Naturally, this also becomes a zero vector.

[0811] From the above, the converted parity check matrix H' in FIG. 208 is a parity check matrix of an LDPC code c' obtained by performing column permutation of equation (12) on the LDPC code c of the original parity check matrix H.

[0812] Therefore, by performing the column permutation of equation (12) on the LDPC code c of the original check matrix H, and then decoding (LDPC decoding) the LDPC code c' after the column permutation using the transformed check matrix H' in FIG. 208, and then performing the inverse permutation of the column permutation of equation (12) on the decoded result, it is possible to obtain the same decoding result as when the LDPC code of the original check matrix H is decoded using that check matrix H.

[0813] FIG. 209 is a diagram showing the converted parity check matrix H' of FIG. 208, with intervals provided in 5×5 matrix units.

[0814] In Figure 209, the conversion check matrix H' is represented as a combination of a 5x5 (=PxP) unit matrix, where P is the unit size; a matrix in which one or more of the 1s in the unit matrix have become 0 (hereinafter referred to as a quasi-unit matrix, as appropriate); a matrix in which a unit matrix or a quasi-unit matrix has been cyclically shifted (hereinafter referred to as a shift matrix, as appropriate); a sum of two or more unit matrices, quasi-unit matrices, or shift matrices (hereinafter referred to as a sum matrix, as appropriate); and a 5x5 0 matrix.

[0815] It can be said that the transformation check matrix H' in Figure 209 is composed of a 5x5 identity matrix, a quasi-identity matrix, a shift matrix, a sum matrix, and a 0 matrix. Therefore, these 5x5 matrices (identity matrix, quasi-identity matrix, shift matrix, sum matrix, and 0 matrix) that compose the transformation check matrix H' will hereinafter be referred to as constituent matrices as appropriate.

[0816] For decoding an LDPC code of a parity check matrix represented by a P×P constituent matrix, an architecture that simultaneously performs P check node operations and P variable node operations can be used.

[0817] FIG. 210 is a block diagram showing an example of the configuration of a decoding device that performs such decoding.

[0818] That is, FIG. 210 shows an example of the configuration of a decoding device that decodes an LDPC code using a transformed check matrix H′ in FIG. 209 obtained by performing at least the column permutation of equation (12) on the original check matrix H in FIG. 207.

[0819] The decoding device of FIG. 210 includes an edge data storage memory 300 consisting of six FIFOs 3001 to 3006, a selector 301 for selecting one of the FIFOs 3001 to 3006, a check node calculation unit 302, two cyclic shift circuits 303 and 308, and 18 FIFOs 3041 to 3044. 18 The edge data storage memory 304 includes FIFOs 3041 to 3044. 18 a receive data memory 306 for storing the receive data, a variable node calculation unit 307, a decoded word calculation unit 309, a receive data rearrangement unit 310, and a decoded data rearrangement unit 311.

[0820] First, the method of storing data in the edge data storage memories 300 and 304 will be described.

[0821] The edge data storage memory 300 is composed of six FIFOs 3001 to 3006, the number of which is obtained by dividing the number of rows of the conversion check matrix H' in FIG. 209 (30) by the number of rows of the constituent matrix (unit size P) (5). y (y=1,2,...,6) consists of a storage area of ​​multiple stages, and the storage area of ​​each stage can simultaneously read and write messages corresponding to five branches, which are the number of rows and columns (unit size P) of the constituent matrix. y The number of stages of the storage area is 9, which is the maximum number of 1s (Hamming weights) in the row direction of the conversion check matrix in FIG.

[0822] The FIFO 3001 stores data corresponding to the positions of 1 from the first row to the fifth row of the transformation check matrix H' in FIG. 209 (message v from the variable node). i) are stored in a form that is packed horizontally in each row (with zeros ignored). That is, if the j-th row and i-th column are represented as (j,i), the first-stage storage area of ​​FIFO 3001 stores data corresponding to the positions of 1 in the 5×5 identity matrix from (1,1) to (5,5) of the transformed parity check matrix H'. The second-stage storage area stores data corresponding to the positions of 1 in the shift matrix from (1,21) to (5,25) of the transformed parity check matrix H' (a shift matrix obtained by cyclically shifting the 5×5 identity matrix by three places to the right). Similarly, the third to eighth-stage storage areas store data in association with the transformed parity check matrix H'. Then, the ninth-stage storage area stores data corresponding to the positions of 1 in the shift matrix from (1,86) to (5,90) of the transformed parity check matrix H' (a shift matrix obtained by replacing the 1 in the first row of the 5×5 identity matrix with a 0 and cyclically shifting it by one place to the left).

[0823] FIFO3002 stores data corresponding to the positions of 1 in the sixth to tenth rows of the transformed parity check matrix H' in FIG. 209. That is, the first-stage storage area of ​​FIFO3002 stores data corresponding to the positions of 1 in the first shift matrix that constitutes the sum matrix of (6,1) to (10,5) of the transformed parity check matrix H' (the sum matrix is ​​the sum of a first shift matrix obtained by cyclically shifting a 5x5 identity matrix to the right by one position, and a second shift matrix obtained by cyclically shifting a 5x5 identity matrix to the right by two positions). Also, the second-stage storage area stores data corresponding to the positions of 1 in the second shift matrix that constitutes the sum matrix of (6,1) to (10,5) of the transformed parity check matrix H'.

[0824] That is, for a constituent matrix with a weight of 2 or more, when the constituent matrix is ​​expressed as a sum of a P×P identity matrix with a weight of 1, a quasi-identity matrix in which one or more of the 1 elements of the identity matrix have become 0, or a shift matrix obtained by cyclically shifting the identity matrix or quasi-identity matrix, data corresponding to the position of 1 in the identity matrix, quasi-identity matrix, or shift matrix with a weight of 1 (messages corresponding to branches belonging to the identity matrix, quasi-identity matrix, or shift matrix) is stored at the same address (the same FIFO among FIFOs 3001 to 3006).

[0825] Similarly, in the storage areas in the third to ninth stages, data is stored in association with the converted check matrix H'.

[0826] Similarly, FIFOs 3003 to 3006 store data in association with the conversion check matrix H'.

[0827] The edge data storage memory 304 has 18 FIFOs 3041 to 3044, which are obtained by dividing the number of columns of the conversion check matrix H' (90) by the number of columns of the constituent matrix (unit size P), 5. 18 It consists of FIFO304 x (x=1,2,...,18) consists of multiple stages of memory areas, and each stage of the memory area can simultaneously read and write messages corresponding to five branches, which are the number of rows and columns (unit size P) of the constituent matrix.

[0828] The FIFO 3041 stores data corresponding to the positions of 1 in the first to fifth columns of the conversion check matrix H' in FIG. 209 (message u from the check node). j ) are stored in a vertically packed manner (ignoring zeros) in each column. That is, the first-stage storage area of ​​FIFO 3041 stores data corresponding to the positions of 1 in the 5×5 identity matrix from (1,1) to (5,5) of transformed parity check matrix H'. The second-stage storage area stores data corresponding to the positions of 1 in the first shift matrix constituting the sum matrix from (6,1) to (10,5) of transformed parity check matrix H' (the sum matrix is ​​the sum of a first shift matrix obtained by cyclically shifting the 5×5 identity matrix by one position to the right and a second shift matrix obtained by cyclically shifting the 5×5 identity matrix by two positions to the right). The third-stage storage area stores data corresponding to the positions of 1 in the second shift matrix constituting the sum matrix from (6,1) to (10,5) of transformed parity check matrix H'.

[0829] That is, for a constituent matrix with a weight of 2 or more, when the constituent matrix is ​​expressed as a sum of a P×P identity matrix with a weight of 1, a quasi-identity matrix in which one or more of the 1 elements of the identity matrix are 0, or a shift matrix obtained by cyclically shifting the identity matrix or quasi-identity matrix, data corresponding to the position of 1 in the identity matrix, quasi-identity matrix, or shift matrix with a weight of 1 (messages corresponding to branches belonging to the identity matrix, quasi-identity matrix, or shift matrix) are stored at the same address (FIFO 3041 to 3044). 18 The data is stored in the same FIFO.

[0830] Similarly, data is stored in the fourth and fifth storage areas in association with the transformed check matrix H'. The number of storage areas in this FIFO 3041 is 5, which is the maximum number of 1s (Hamming weights) in the row direction in the first to fifth columns of the transformed check matrix H'.

[0831] FIFOs 3042 and 3043 similarly store data in association with the conversion check matrix H', and each has a length (number of stages) of 5. 12 Similarly, FIFO 304 stores data in association with the converted check matrix H′, and each has a length of 3. 13 or 304 18 Similarly, data is stored in association with the converted check matrix H′, and each has a length of 2.

[0832] Next, the operation of the decoding device shown in FIG. 210 will be described.

[0833] The edge data storage memory 300 consists of six FIFOs 3001 to 3006, and selects a FIFO from FIFOs 3001 to 3006 to store data in accordance with information (Matrix data) D312 indicating to which row of the conversion check matrix H' in FIG. 209 five messages D311 supplied from the preceding cyclic shift circuit 308 belong, and stores the five messages D311 collectively in the selected FIFO in order. Furthermore, when reading data, the edge data storage memory 300 reads five messages D3001 in order from FIFO 3001 and supplies them to the next-stage selector 301. After finishing reading the messages from FIFO 3001, the edge data storage memory 300 also reads messages in order from FIFOs 3002 to 3006 and supplies ...

Claims

1. a coding unit that performs LDPC coding based on a check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 4 / 16; a group-wise interleaving unit that performs group-wise interleaving of the LDPC code in units of 360-bit bit groups; a mapping unit that maps the LDPC code to one of 16 signal points of a 16QAM NUC (Non-Uniform Constellation) in 4-bit units; Equipped with In the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is defined as bit group i. 154, 83, 159, 153, 136, 6, 19, 73, 122, 40, 97, 144, 101, 106, 130, 174, 48, 176, 14, 27, 52, 152, 173, 63, 39, 92, 114, 98, 190, 149, 103, 160, 118, 13, 29, 51, 66, 168, 180, 23, 170, 24, 5, 157, 28, 45, 53, 68, 25, 191, 148, 139, 15, 67, 77, 100, 58, 91, 50, 131, 65, 17, 11, 123, 86, 135, 115, 120, 59, 162, 9, 189, 21, 12, 179, 178, 110, 35, 137, 3, 84, 177, 124, 186, 143, 26, 96, 80, 31, 169, 119, 33, 87, 140, 88, 171, 133, 150, 151, 72, 85, 89, 112, 126, 167, 56, 49, 187, 138, 145, 18, 32, 90, 158, 54, 104, 62, 165, 79, 1, 81, 102, 44, 61, 10, 166, 2, 116, 161, 60, 108, 142, 30, 78, 127, 111, 46, 43, 184, 163, 64, 22, 41, 156, 70, 20, 42, 182, 55, 95, 105, 132, 38, 69, 134, 74, 155, 141, 172, 57, 7, 175, 128, 75, 107, 109, 99, 147, 146, 117, 125, 185, 0, 76, 82, 129, 36, 34, 93, 188, 113, 71, 183, 121, 47, 16, 164, 4, 181, 94, 37, 8 Interleaved in a sequence of The check matrix is A matrix A in the upper left corner of the parity check matrix, which has M1 rows and K columns and is represented by a predetermined value M1 and an information length K=N×r of the LDPC code; A B matrix having a staircase structure adjacent to the right of the A matrix, with M1 rows and M1 columns; a Z matrix, which is a zero matrix adjacent to the right of the B matrix, having M1 rows and N-K-M1 columns; a C matrix adjacent below the A matrix and the B matrix, the C matrix having N−M1 rows and K+M1 columns; A D matrix, which is an identity matrix adjacent to the right of the C matrix and has N-K-M1 rows and N-K-M1 columns, Including, The predetermined value M1 is 1800, The A matrix and the C matrix are represented by a check matrix initial value table, The parity check matrix initial value table is a table representing positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 561 825 1718 4745 7515 13041 13466 18039 19065 21821 32596 32708 35323 36399 36450 41124 43036 43218 43363 44875 49948 56 102 1779 2427 5381 8768 15336 26473 35717 38748 39066 45002 50720 694 1150 1533 2177 5801 6610 7601 16657 18949 33472 47746 49581 50668 90 1122 1472 2085 2593 4986 8200 9175 15502 44084 46057 48546 50487 521 619 708 6915 8978 14211 17426 23058 23463 27440 29822 33443 42871 449 912 1471 8058 9344 11928 20533 20600 20737 26557 26970 27616 33791 355 700 1528 6478 9588 10790 20992 33122 34283 41295 43439 46249 47763 997 1543 1679 5874 7973 7975 11113 28275 28812 29864 35070 36864 50676 85 326 1392 4186 10855 11005 12913 19263 22984 31733 33787 37567 48173 986 1144 1508 19864 28918 29117 33609 36452 47975 48432 48842 49274 51533 437 1190 1413 3814 6695 17541 22060 25845 28431 37453 38912 44170 49231 327 1171 1204 6952 11880 16469 25058 28956 31523 36770 40189 43422 46481 123 605 619 8118 8455 19550 20529 21762 21950 28485 30946 34755 34765 113 896 971 6400 27059 33383 34537 35827 38796 40582 42594 43098 48525 162 854 1015 2938 10659 12085 13040 32772 33023 35878 49674 51060 51333 100 452 1703 1932 4208 5127 12086 14549 16084 17890 20870 41364 48498 1569 1633 1666 12957 18611 22499 38418 38719 42135 46815 48274 50947 51387 119 691 1190 2457 3865 7468 12512 30782 31811 33508 36586 41789 47426 867 1117 1666 4376 13263 13466 33524 37440 38136 39800 41454 41620 42510 378 900 1754 16303 25369 27103 28360 30958 35316 44165 46682 47016 50004 1321 1549 1570 16276 17284 19431 23482 23920 27386 27517 46253 48617 50118 37 383 1418 15792 22551 28843 36532 36718 38805 39226 45671 47712 51769 150 787 1441 17828 19396 21576 21805 24048 31868 32891 42486 43020 45492 1095 1214 1744 2445 5773 10209 11526 29604 30121 36526 45786 47376 49366 412 448 1281 11164 14501 15538 15773 23305 31960 32721 40744 45731 50269 183 626 837 4491 12237 13705 15177 15973 21266 25374 41232 44147 50529 618 1550 1594 5474 9260 16552 18122 26061 30420 30922 32661 34390 43236 135 496 757 9327 15659 20738 24327 26688 29063 38993 46155 49532 50001 64 126 1714 5561 8921 11300 12688 14454 16857 19585 20528 24107 27252 528 687 1730 9735 11737 16396 19200 33712 34271 38241 42027 44471 45581 69 646 1447 8603 19706 22153 22398 23840 24638 27254 29107 30368 41419 673 845 1285 9100 11064 14804 15425 17357 27248 31223 32410 35444 48018 124 1531 1677 3672 3673 3786 8886 9557 10003 11053 13053 22458 25413 102 1154 1758 5721 6034 14567 17772 28670 33380 34284 35356 47480 48123 48 351 760 2078 9797 22956 26120 34119 39658 41039 45237 47861 49022 254 445 841 6835 18340 19021 20053 22874 32639 36679 42004 45696 49530 16 802 903 6218 16206 22068 23049 28201 30377 33947 44358 44739 49303 153 1542 1629 7992 29900 34931 36927 38651 39981 41085 41327 50185 51484 525 1291 1765 9425 20271 31229 37444 38996 39145 41711 43188 45203 51255 2 244 1648 12321 14991 17426 18456 20126 29915 32581 38880 39516 49013 23 452 705 9414 11862 13764 18179 35458 37892 40471 46041 46494 48746 509 1201 1328 8921 9867 10947 19476 22693 32636 34301 38356 39238 51797 246 249 1390 12438 13266 24060 33628 37130 42923 43298 43709 43721 45413 117 257 748 9419 9461 11350 12790 16724 33147 34168 34683 37884 42699 619 646 740 7468 7604 8152 16296 19120 27614 27748 40170 40289 49366 914 1360 1716 10817 17672 18919 26146 29631 40903 46716 49502 51576 51657 68 702 1552 10431 10925 12856 24516 26440 30834 31179 32277 35019 44108 588 880 1524 6641 9453 9653 13679 14488 20714 25865 42217 42637 48312 6380 12240 12558 12816 21460 24206 26129 28555 41616 51767 8889 16221 21629 23476 33954 40572 43494 44666 44885 49813 16938 17727 17913 18898 21754 32515 35686 36920 39898 43560 9170 11747 14681 22874 24537 24685 26989 28947 33592 34621 2427 10241 29649 30522 37700 37789 41656 44020 49801 51268 is Transmitting device.

2. a coding step of performing LDPC coding based on a check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 4 / 16; a group-wise interleaving step of performing group-wise interleaving on the LDPC code in units of 360-bit bit groups; a mapping step of mapping the LDPC code to one of 16 signal points of a 16QAM NUC (Non-Uniform Constellation) in 4-bit units; Equipped with In the group-wise interleaving, the (i+1)th bit group from the beginning of the LDPC code is defined as bit group i, and the sequence of bit groups 0 to 191 of the 69120-bit LDPC code is defined as bit group i. 154, 83, 159, 153, 136, 6, 19, 73, 122, 40, 97, 144, 101, 106, 130, 174, 48, 176, 14, 27, 52, 152, 173, 63, 39, 92, 114, 98, 190, 149, 103, 160, 118, 13, 29, 51, 66, 168, 180, 23, 170, 24, 5, 157, 28, 45, 53, 68, 25, 191, 148, 139, 15, 67, 77, 100, 58, 91, 50, 131, 65, 17, 11, 123, 86, 135, 115, 120, 59, 162, 9, 189, 21, 12, 179, 178, 110, 35, 137, 3, 84, 177, 124, 186, 143, 26, 96, 80, 31, 169, 119, 33, 87, 140, 88, 171, 133, 150, 151, 72, 85, 89, 112, 126, 167, 56, 49, 187, 138, 145, 18, 32, 90, 158, 54, 104, 62, 165, 79, 1, 81, 102, 44, 61, 10, 166, 2, 116, 161, 60, 108, 142, 30, 78, 127, 111, 46, 43, 184, 163, 64, 22, 41, 156, 70, 20, 42, 182, 55, 95, 105, 132, 38, 69, 134, 74, 155, 141, 172, 57, 7, 175, 128, 75, 107, 109, 99, 147, 146, 117, 125, 185, 0, 76, 82, 129, 36, 34, 93, 188, 113, 71, 183, 121, 47, 16, 164, 4, 181, 94, 37, 8 Interleaved in a sequence of The check matrix is A matrix A in the upper left corner of the parity check matrix, which has M1 rows and K columns and is represented by a predetermined value M1 and an information length K=N×r of the LDPC code; A B matrix having a staircase structure adjacent to the right of the A matrix, with M1 rows and M1 columns; a Z matrix, which is a zero matrix adjacent to the right of the B matrix, having M1 rows and N-K-M1 columns; a C matrix adjacent below the A matrix and the B matrix, the C matrix having N−M1 rows and K+M1 columns; A D matrix, which is an identity matrix adjacent to the right of the C matrix and has N-K-M1 rows and N-K-M1 columns, Including, The predetermined value M1 is 1800, The A matrix and the C matrix are represented by a check matrix initial value table, The parity check matrix initial value table is a table representing positions of elements of 1 in the A matrix and the C matrix for every 360 columns, 561 825 1718 4745 7515 13041 13466 18039 19065 21821 32596 32708 35323 36399 36450 41124 43036 43218 43363 44875 49948 56 102 1779 2427 5381 8768 15336 26473 35717 38748 39066 45002 50720 694 1150 1533 2177 5801 6610 7601 16657 18949 33472 47746 49581 50668 90 1122 1472 2085 2593 4986 8200 9175 15502 44084 46057 48546 50487 521 619 708 6915 8978 14211 17426 23058 23463 27440 29822 33443 42871 449 912 1471 8058 9344 11928 20533 20600 20737 26557 26970 27616 33791 355 700 1528 6478 9588 10790 20992 33122 34283 41295 43439 46249 47763 997 1543 1679 5874 7973 7975 11113 28275 28812 29864 35070 36864 50676 85 326 1392 4186 10855 11005 12913 19263 22984 31733 33787 37567 48173 986 1144 1508 19864 28918 29117 33609 36452 47975 48432 48842 49274 51533 437 1190 1413 3814 6695 17541 22060 25845 28431 37453 38912 44170 49231 327 1171 1204 6952 11880 16469 25058 28956 31523 36770 40189 43422 46481 123 605 619 8118 8455 19550 20529 21762 21950 28485 30946 34755 34765 113 896 971 6400 27059 33383 34537 35827 38796 40582 42594 43098 48525 162 854 1015 2938 10659 12085 13040 32772 33023 35878 49674 51060 51333 100 452 1703 1932 4208 5127 12086 14549 16084 17890 20870 41364 48498 1569 1633 1666 12957 18611 22499 38418 38719 42135 46815 48274 50947 51387 119 691 1190 2457 3865 7468 12512 30782 31811 33508 36586 41789 47426 867 1117 1666 4376 13263 13466 33524 37440 38136 39800 41454 41620 42510 378 900 1754 16303 25369 27103 28360 30958 35316 44165 46682 47016 50004 1321 1549 1570 16276 17284 19431 23482 23920 27386 27517 46253 48617 50118 37 383 1418 15792 22551 28843 36532 36718 38805 39226 45671 47712 51769 150 787 1441 17828 19396 21576 21805 24048 31868 32891 42486 43020 45492 1095 1214 1744 2445 5773 10209 11526 29604 30121 36526 45786 47376 49366 412 448 1281 11164 14501 15538 15773 23305 31960 32721 40744 45731 50269 183 626 837 4491 12237 13705 15177 15973 21266 25374 41232 44147 50529 618 1550 1594 5474 9260 16552 18122 26061 30420 30922 32661 34390 43236 135 496 757 9327 15659 20738 24327 26688 29063 38993 46155 49532 50001 64 126 1714 5561 8921 11300 12688 14454 16857 19585 20528 24107 27252 528 687 1730 9735 11737 16396 19200 33712 34271 38241 42027 44471 45581 69 646 1447 8603 19706 22153 22398 23840 24638 27254 29107 30368 41419 673 845 1285 9100 11064 14804 15425 17357 27248 31223 32410 35444 48018 124 1531 1677 3672 3673 3786 8886 9557 10003 11053 13053 22458 25413 102 1154 1758 5721 6034 14567 17772 28670 33380 34284 35356 47480 48123 48 351 760 2078 9797 22956 26120 34119 39658 41039 45237 47861 49022 254 445 841 6835 18340 19021 20053 22874 32639 36679 42004 45696 49530 16 802 903 6218 16206 22068 23049 28201 30377 33947 44358 44739 49303 153 1542 1629 7992 29900 34931 36927 38651 39981 41085 41327 50185 51484 525 1291 1765 9425 20271 31229 37444 38996 39145 41711 43188 45203 51255 2 244 1648 12321 14991 17426 18456 20126 29915 32581 38880 39516 49013 23 452 705 9414 11862 13764 18179 35458 37892 40471 46041 46494 48746 509 1201 1328 8921 9867 10947 19476 22693 32636 34301 38356 39238 51797 246 249 1390 12438 13266 24060 33628 37130 42923 43298 43709 43721 45413 117 257 748 9419 9461 11350 12790 16724 33147 34168 34683 37884 42699 619 646 740 7468 7604 8152 16296 19120 27614 27748 40170 40289 49366 914 1360 1716 10817 17672 18919 26146 29631 40903 46716 49502 51576 51657 68 702 1552 10431 10925 12856 24516 26440 30834 31179 32277 35019 44108 588 880 1524 6641 9453 9653 13679 14488 20714 25865 42217 42637 48312 6380 12240 12558 12816 21460 24206 26129 28555 41616 51767 8889 16221 21629 23476 33954 40572 43494 44666 44885 49813 16938 17727 17913 18898 21754 32515 35686 36920 39898 43560 9170 11747 14681 22874 24537 24685 26989 28947 33592 34621 2427 10241 29649 30522 37700 37789 41656 44020 49801 51268 is Sending method.

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