Silicon carbide epitaxial substrate

Abstract

We provide high-quality silicon carbide epitaxial substrates with a silicon carbide epitaxial layer that has few defects. [Solution] The silicon carbide epitaxial substrate 10 comprises a silicon carbide substrate 20 having a first surface and a silicon carbide epitaxial layer 30 located on the first surface, wherein the first surface 20a is the (000-1)C surface, and the stacking fault density confirmed by photoluminescence imaging on the upper surface 30a of the silicon carbide epitaxial layer is 1.2 cm². -2 The ratio of the stacking fault density to the basal plane dislocation density on the first surface of the silicon carbide substrate is less than 0.05%, and the basal plane dislocation density on the first surface of the silicon carbide substrate is 3000 cm². -2 It is less than.

Description

[Technical Field]

[0001] This application relates to a silicon carbide epitaxial substrate. [Background technology]

[0002] Silicon carbide (SiC) semiconductors possess greater dielectric breakdown field strength, electron saturation drift velocity, and thermal conductivity than silicon semiconductors. Therefore, silicon carbide semiconductors can enable power devices capable of high-temperature, high-speed, and high-current operation compared to conventional silicon devices, and are attracting attention as semiconductors for realizing highly efficient switching elements that drive motors used in electric vehicles and hybrid cars.

[0003] Even with the same chemical composition, silicon carbide semiconductors differ in stacking direction. <0001> Multiple polytypes exist in which the arrangement of carbon and silicon atoms in the (orientation) direction differs. Furthermore, because the internal energy difference between these polytypes is small, heterogeneous polytypes are easily formed in a single crystal, and these heterogeneous polytypes become dislocations and stacking faults (SF). Generally, silicon carbide substrates contain more of these dislocations and stacking faults than silicon substrates. For this reason, when manufacturing semiconductor devices such as switching elements using silicon carbide semiconductors, a silicon carbide epitaxial layer with fewer of these defects is formed on the silicon carbide substrate, and the main structure of the semiconductor device is formed in the silicon carbide epitaxial layer.

[0004] However, dislocations and stacking faults are expansion defects, and dislocations and stacking faults that occur near the surface of the silicon carbide substrate propagate into the silicon carbide epitaxial layer during epitaxial growth, easily degrading the crystal quality of the silicon carbide epitaxial layer. For this reason, the development of technologies to improve the crystal quality of the silicon carbide substrate itself, and technologies to form high-quality silicon carbide epitaxial layers, are important for the widespread adoption of silicon carbide semiconductor devices.

[0005] Stacking faults are planar defects and are typical defects that occur in silicon carbide epitaxial layers. Furthermore, when a bipolar device using silicon carbide semiconductors contains basal plane dislocations (BPDs), the basal plane dislocations expand when the bipolar device is biased in the forward direction, leading to the formation of stacking faults. Since stacking faults are highly resistive, an increase in stacking faults increases the internal resistance of the device, resulting in greater heat generation due to power loss in the device, which can potentially lead to device failure. Such changes in device characteristics are known as bipolar degradation (Non-Patent Literature 1). Therefore, from the viewpoint of long-term reliability of electronic devices, it is necessary to suppress the occurrence of basal plane dislocations in silicon carbide epitaxial growth films, as well as the occurrence of stacking faults that form high-resistance layers.

[0006] Linear surface defects appear on the surface of the silicon carbide epitaxial layer. Since linear surface defects may be accompanied by stacking faults, it is preferable to suppress the occurrence of linear surface defects in epitaxially grown films. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Patent No. 6295969 specification [Patent Document 2] Patent No. 4539140 specification [Non-patent literature]

[0008] [Non-Patent Document 1] Noboru Otani, "Current Status of Development of Low-Resistivity SiC Single Crystals for Power Devices," Journal of the Japan Society for Crystal Growth, Vol. 45, No. 3 (2018) 45-3-01 [Non-Patent Document 2] Yuki Ishida, "Current Status of High-Speed ​​Epitaxial Growth Technology of SiC by Chemical Vapor Phase Method," J.Vac.Soc.Jpn., Vol.54, No.6, 2011. [Non-Patent Document 3] Shunichi Nakamura, et al., "Homoepitaxial Growth on the Near-Surface of 4H-SiC {0001}", "Materials", J.Soc.Mat.Sci., Japan, Vol.53, No.12, pp.1323-1327, Dec. 2004

Summary of the Invention

Problems to be Solved by the Invention

[0009] This application provides a silicon carbide epitaxial substrate having a silicon carbide epitaxial layer with few defects.

Means for Solving the Problems

[0010] A silicon carbide epitaxial substrate according to an embodiment of the present disclosure includes a silicon carbide substrate having a first surface, and a silicon carbide epitaxial layer located on the first surface. The first surface is a (000-1)C plane. On the upper surface of the silicon carbide epitaxial layer, the linear surface defect density is less than 1.0 cm -2 and the stacking defect density is less than 1.2 cm -2 less than.

[0011] The linear surface defect density may be less than 0.5 cm -2 less than.

[0012] The linear surface defect density may be less than 0.35 cm -2 less than.

[0013] The stacking defect density may be less than 1.0 cm -2 less than.

[0014] The stacking defect density may be less than 0.35 cm -2 less than.

[0015] The basal plane dislocation density on the first surface of the silicon carbide substrate may be less than 3000 cm -2 less than.

[0016] The basal plane dislocation density on the first surface of the silicon carbide substrate may be 2000 cm-2 It may be less than that.

[0017] The ratio of the linear surface defect density to the basal plane dislocation density on the first surface of the silicon carbide substrate may be less than 0.04%.

[0018] The ratio of the stacking defect density to the basal plane dislocation density on the first surface of the silicon carbide substrate may be less than 0.05%.

[0019] The first surface may have an off-angle of 4° or less.

[0020] The surface roughness Ra of the first surface may be 1 nm or less.

[0021] A method for manufacturing a silicon carbide epitaxial substrate according to an embodiment of the present disclosure includes a step of preparing a silicon carbide substrate having a first surface as a (000-1)C plane, holding the silicon carbide substrate in a growth chamber, introducing a gas containing carbon and silicon into the growth chamber at a ratio where the C / Si ratio is 1 or more and 1.6 or less, and growing a silicon carbide epitaxial layer on the first surface.

[0022] On the first surface of the silicon carbide substrate, the basal plane dislocation density is 3000 cm -2 It may be less than that.

[0023] On the first surface of the silicon carbide substrate, the basal plane dislocation density is 2000 cm -2 It may be less than that.

[0024] The first surface may have an off-angle of 4° or less.

[0025] The surface roughness Ra of the first surface may be 1 nm or less.

Advantages of the Invention

[0026] According to the embodiment of the present disclosure, a silicon carbide epitaxial substrate including a silicon carbide epitaxial layer with few defects can be provided. [Brief explanation of the drawing]

[0027] [Figure 1] Figure 1 is a schematic cross-sectional view of the silicon carbide epitaxial substrate of this embodiment. [Figure 2] Figure 2 is a schematic diagram showing the crystal orientation of the silicon carbide substrate used in the silicon carbide epitaxial substrate of this embodiment. [Figure 3] Figure 3 shows the relationship between basal plane dislocation density and linear surface defect density in the substrates of the examples and comparative examples. [Figure 4] Figure 4 shows the relationship between basal plane dislocation density and stacking fault density in the substrates of the examples and comparative examples. [Figure 5] Figure 5 shows the relationship between the basal plane dislocation density in the substrates of the examples and comparative examples and the ratio of the linear surface defect density to the basal plane dislocation density in the substrates. [Figure 6] Figure 6 shows the relationship between the basal plane dislocation density in the substrates of the examples and comparative examples and the ratio of the stacking fault density to the basal plane dislocation density in the substrates. [Figure 7] Figure 7 shows an example of differential interference optical microscopy images of linear surface defects observed on silicon carbide epitaxial substrates of the examples and comparative examples. [Figure 8] Figure 8 shows an example of PL (Plant-Low Light) images of stacking faults observed on silicon carbide epitaxial substrates of the examples and comparative examples, filtered using a near-ultraviolet filter. [Figure 9] Figure 9 shows an example of PL (Plant-Lens Refinement) images of stacking faults observed on silicon carbide epitaxial substrates of the examples and comparative examples, filtered using a visible light filter. [Modes for carrying out the invention]

[0028] (Structure of silicon carbide epitaxial substrate 10) Figure 1 is a schematic cross-sectional view of the silicon carbide epitaxial substrate 10 of this embodiment. The silicon carbide epitaxial substrate 10 comprises a silicon carbide substrate 20 and a silicon carbide epitaxial layer 30.

[0029] The silicon carbide substrate 20 has a first surface 20a and a second surface 20b located opposite the first surface 20a, with the silicon carbide epitaxial layer 30 located on the first surface 20a. The silicon carbide substrate 20 is composed of a silicon carbide single crystal. The polytype is preferably 4H. There are no particular restrictions on the size of the silicon carbide substrate 20. However, from the viewpoint of mass productionability of semiconductor devices made using the silicon carbide epitaxial substrate 10, the silicon carbide substrate 20 preferably has a diameter of 100 mm or more, and more preferably has a diameter of 150 mm. The silicon carbide substrate 20 has a thickness determined according to the diameter according to the standard. For example, if the diameter is 100 mm or 150 mm, the thickness of the silicon carbide substrate 20 is 350 μm ± 25 μm or 500 μm ± 25 μm.

[0030] Figure 2 is a schematic diagram showing the crystal orientation of the silicon carbide substrate used in the silicon carbide epitaxial substrate of this embodiment. The first surface 20a has the following surface orientation.

[0031]

number

[0032] Here, C stands for carbon, indicating that the outermost surface of the first surface 20a is a carbon surface where carbon is exposed.

[0033] Hereafter, for the sake of simplicity in the specification, it will be referred to as the (000-1)C surface. On the other hand, the second surface 20b is the (0001)Si surface, and the outermost surface of the second surface 20b is a silicon surface with exposed silicon.

[0034] It is known that silicon carbide substrates have a carbon surface and a silicon surface, but conventionally, silicon carbide epitaxial layers are formed on the silicon surface of the silicon carbide substrate. This is because it is easier to control the growth and doping when growing the silicon carbide epitaxial layer on the silicon surface. Therefore, when patent and non-patent literature does not specify whether the upper surface of the silicon carbide substrate is the carbon surface or the silicon surface, it is assumed that the silicon surface of the silicon carbide substrate is being used.

[0035] The inventors of this application have conducted detailed studies on techniques to suppress linear surface defects and stacking faults, which are major defects in silicon carbide semiconductors. As a result, they have found that by epitaxially growing a silicon carbide epitaxial layer on a carbon plane, it is possible to suppress linear surface defects and stacking faults, as will be explained below.

[0036] The silicon carbide substrate 20 is preferably an off-surface substrate. Figure 2 is a schematic diagram showing a cross-section of the silicon carbide substrate 20. The silicon carbide substrate 20 is preferably an off-surface substrate having an off-angle θ. Specifically, it is preferable that the first surface 20a, or the normal 20n of the first surface 20a, is inclined by θ from the [000-1] direction to the

[1120] direction. The off-angle θ is preferably 0.5° or more and 8° or less, and more preferably 0.5° or more and 5° or less.

[0037] The properties of the first surface 20a of the silicon carbide substrate 20 are described in detail. It is preferable that the first surface 20a is subjected to CMP (chemical mechanical polishing). Specifically, it is preferable that the first surface 20a is polished by CMP until its surface roughness Ra is 1 nm or less. More preferably, the Ra of the first surface 20a is 0.2 nm or less. Ra can be measured, for example, by a white light interference microscope. For example, it is a value obtained by measuring the first surface 20a at three locations over a length of 100 μm and calculating the average. Ideally, Ra can be 0 nm, but in reality, Ra is never 0 nm. Therefore, the lower limit of the preferred range for Ra is greater than 0.

[0038] Furthermore, the BPD density on surface 1, 20a, is 3000 cells / cm³. 2 Below (3000cm -2 Preferably the following, 2000cm -2 It is more preferable that the following conditions apply: 1000 cm -2 The following is even more preferable. The BPD density can be measured, for example, by etching the first surface 20a with molten KOH and measuring the number of BPDs that appear as etch pits using an optical microscope. Similar to Ra, the lower limit of the preferred range for BPD density is 0 cm². -2 Larger.

[0039] The silicon carbide epitaxial layer 30 is formed on the first surface 20a of the silicon carbide substrate 20 by epitaxial growth. The thickness of the silicon carbide epitaxial layer 30 can be arbitrarily set according to the performance required for the semiconductor device fabricated using the silicon carbide epitaxial substrate 10. For example, the thickness of the silicon carbide epitaxial layer 30 is approximately 1 μm to 100 μm.

[0040] On the upper surface 30a of the silicon carbide epitaxial layer 30, the linear surface defect density is 1.0 cm². -2 Preferably, it is less than 0.5 cm². The linear surface defect density is 0.5 cm². -2 It is more preferable to be less than 0.35 cm. -2 It is even more preferable that it be less than 0.1 cm. -2 It is even more preferable that the stacking fault density be less than 1.2 cm². Furthermore, on the upper surface 30a of the silicon carbide epitaxial layer 30, the stacking fault density is 1.2 cm². -2 It is preferable that it be less than 1.0 cm². The stacking fault density is 1.0 cm². -2 It is more preferable to be less than 0.35 cm. -2 It is even more preferable that it be less than 0.1 cm. -2 It is even more preferable that it be less than 0 cm. Similar to Ra, the lower limit of the preferred range for linear surface defect density and stacking fault density is 0 cm. 2 Larger.

[0041] In this embodiment, linear surface defects have an elongated linear shape and exhibit irregularities relative to the upper surface 30a of the silicon carbide epitaxial layer 30 when viewed from a direction perpendicular to it. The longitudinal direction (extension direction) of the linear surface defects may coincide with the step flow growth direction (off-angle direction), be inclined at approximately ±5° to 60° relative to the step flow growth direction, or extend in two directions in a V-shape relative to the step flow growth direction. In this embodiment, the linear surface defects originate from defects or scratches on the first surface 20a of the silicon carbide substrate 20. Therefore, the longitudinal length L of the linear surface defect depends on the thickness d of the silicon carbide epitaxial layer 30 and the off-angle θ of the silicon carbide substrate 20, with the relationship L = d / tanθ. Linear surface defects are also called carrot defects.

[0042] Linear surface defect density can be measured, for example, by a wafer inspection / review system capable of acquiring differential interference contrast microscopy images. Such a wafer inspection / review system can obtain the location and number of regions of linear brightness changes in the acquired differential interference contrast microscopy image and calculate the density of linear surface defects.

[0043] Stacking faults are planar defects that originate from a defect or scratch on the first surface 20a of the silicon carbide substrate 20, or from a defect within the silicon carbide epitaxial layer 30, and extend in a triangular shape toward the upper surface 30a of the silicon carbide epitaxial layer 30, reaching the upper surface 30a. The majority of stacking faults are located within the silicon carbide epitaxial layer 30. Stacking fault density can be measured, for example, by a wafer inspection / review system equipped with a 355 nm excitation light source and a near-ultraviolet filter, capable of acquiring photoluminescence images. Such a wafer inspection / review system can obtain the location and number of triangular brightness change regions in the acquired photoluminescence image and calculate the stacking fault density.

[0044] (Method for manufacturing silicon carbide epitaxial substrate 10) The manufacturing method for the silicon carbide epitaxial substrate 10 of this embodiment will be described below. First, a silicon carbide substrate 20 is prepared. The silicon carbide substrate 20 has a first surface 20a with the surface orientation and off-angle described above. The first surface 20a is also prepared to have a surface roughness Ra of 1 nm or less by CMP. A smaller surface roughness Ra value is preferable. For this reason, for example, a commercially available silicon carbide substrate 20 may be obtained and the first surface 20a may be subjected to CMP. For example, the first surface 20a may be subjected to CMP using the method described in Japanese Patent No. 6295969. Furthermore, in addition to the step of applying CMP, a step of wet etching the first surface 20a and a step of oxidizing the first surface 20a with gas may be performed, and these three steps may be appropriately combined and performed two or more times.

[0045] Next, a silicon carbide epitaxial layer 30 is formed. The formation method is not limited as long as the apparatus can epitaxially grow the silicon carbide epitaxial layer 30. From the viewpoint of forming a silicon carbide epitaxial layer 30 with uniform properties on a large-diameter silicon carbide substrate 20, it is preferable to form the silicon carbide epitaxial layer 30 using a CVD apparatus employing chemical vapor deposition.

[0046] For example, a silicon carbide substrate 20 is introduced into the growth chamber of a CVD apparatus and placed in a holder with the (000-1)C plane, which is the first surface 20a, facing upwards. The silicon carbide substrate 20 is heated to a temperature of 1500°C to 1800°C, and a carrier gas, a carbon source gas, a silicon source gas, and a dopant gas are introduced into the growth chamber to grow a silicon carbide epitaxial layer 30. For example, hydrogen (H2) can be used as the carrier gas. Propane (C3H8) can be used as the carbon source gas in the raw material gas. Silane (SiH4) can be used as the silicon source gas in the raw material gas. Nitrogen (N2) can be used as the dopant gas. Before growing the silicon carbide epitaxial layer 30, only the carrier gas may be introduced into the growth chamber to clean the first surface 20a of the silicon carbide substrate 20.

[0047] The ratio of carbon in the introduced carbon source gas to silicon in the silicon source gas, C / Si, is preferably 1 or greater. Specifically, C / Si is preferably between 1 and 1.6. As described later, if C / Si exceeds 1.6, the linear surface defect density on the first surface 20a of the growing silicon carbide epitaxial layer 30 increases. Furthermore, as described in the non-patent document "Current Status of High-Speed ​​Epitaxial Growth Technology of SiC by Chemical Vapor Phase Method (J.Vac.Soc.Jpn., Vol.54, No.6, 2011)", if C / Si becomes less than 1 and silane (SiH4) is supplied in excess, Si droplets, which are aggregates of Si, will form on the surface of the epitaxial layer during the epitaxial growth process. This is undesirable because it results in defects caused by Si droplets.

[0048] The pressure inside the growth chamber during the growth of the silicon carbide epitaxial layer 30 is preferably between 10 kPa and 50 kPa.

[0049] As will be described in detail in the following examples, according to the manufacturing method of the silicon carbide epitaxial substrate 10 of this embodiment, by growing a silicon carbide epitaxial layer 30 on the (000-1)C plane of the silicon carbide substrate 20, it is possible to suppress the generation of linear surface defects and stacking faults in the silicon carbide epitaxial layer 30, starting from linear surface defects, stacking faults, or scratches on the first surface 20a of the silicon carbide substrate 20. In particular, the stacking fault density can be reduced. Furthermore, by setting the C / Si ratio in the raw material gas to 1 or more and 1.6 or less during the growth of the silicon carbide epitaxial layer 30, the density of linear surface defects in the silicon carbide epitaxial layer 30 can be reduced in particular. C / Si is more preferably 1.5 or less, even more preferably 1.4 or less, and still more preferably 1.3 or less. Furthermore, by applying CMP to the first surface 20a, which is the (000-1)C surface, and keeping the surface roughness Ra of the first surface 20a to 1 nm or less, the propagation of linear surface defects and stacking faults from the silicon carbide substrate 20 to the silicon carbide epitaxial layer 30 can be suppressed.

[0050] (Examples) <Sample preparation> The following describes the results of measuring the linear surface defect density and stacking fault density of a silicon carbide epitaxial substrate 10, which was fabricated using the silicon carbide epitaxial substrate manufacturing method of this embodiment.

[0051] (Examples 1-6) A silicon carbide substrate 20 with a diameter of 150 mm was prepared, with the first surface 20a being the (000-1)C plane and an off-angle θ of 4°. CMP was performed on the first surface 20a until the surface roughness Ra was 1 nm or less. CMP was carried out using a slurry mainly composed of colloidal silica with an added oxidizing agent and a polishing pad. Subsequently, a silicon carbide epitaxial layer 30 was grown on the first surface 20a of the silicon carbide substrate 20. The growth temperature was set to 1600°C, the growth rate to 40 μm / h, and the pressure inside the growth chamber during growth to 30 kPa. As shown in Table 1, the C / Si ratio in the raw material gas was set to 1.25 or 1.4. Hydrogen was used as the carrier gas, and propane and silane were used as the raw material gases. Nitrogen was used as the dopant source. Examples 1 to 6 were each prepared using one silicon carbide substrate 20.

[0052] (Reference examples 1~3) The silicon carbide epitaxial substrate of Reference Example 1 was fabricated by setting the C / Si ratio in the source gas to 1.7 and keeping all other conditions the same as in Examples 1-6.

[0053] A silicon carbide substrate with a surface roughness of approximately 10 nm and no CMP treatment applied to the first surface was prepared, and the silicon carbide epitaxial substrate of Reference Example 2 was fabricated under the same conditions as in Examples 3 to 5.

[0054] A silicon carbide substrate with the first surface being the (0001)Si plane was prepared, and the silicon carbide epitaxial substrate of Reference Example 3 was fabricated under the same conditions as in Examples 3 to 5.

[0055] Reference Examples 1 and 2 were each fabricated using one silicon carbide substrate, while Reference Example 3 was fabricated using 33 silicon carbide substrates of various grades.

[0056] <Measurement> The basal plane dislocation density of the first surface of the silicon carbide substrate was based on the values ​​disclosed by the substrate manufacturer. The linear surface defect density on the upper surface of the silicon carbide epitaxial layer of the fabricated silicon carbide epitaxial substrate was measured. The equipment and measurement conditions used are as follows. The measurement was performed excluding the area from the outer edge of the substrate to 3 mm inward. Measurement device name: Lasertec Corporation SICA88 Measurement conditions: Optical inspection using a light source with a wavelength of 532 nm.

[0057] The acquired differential interference contrast microscopy images were analyzed using image analysis software included with the instrument. Because linear surface defects have irregularities on the surface, they appear with different brightness in the image compared to the flat, normal crystal regions. Figure 7 shows an example of a differential interference contrast microscopy image of a linear surface defect. The total number of linear surface defects was defined as the number of linear surface defects that are parallel to the step flow growth direction, linear surface defects that extend at an angle to the step flow growth direction, and V-shaped linear surface defects that extend outward from the step flow growth direction.

[0058] The stacking fault density on the upper surface of the silicon carbide epitaxial layer of the fabricated silicon carbide epitaxial substrate was measured. The equipment and measurement conditions used are as follows. The measurement was performed excluding the area from the outer edge of the substrate to 3 mm inward. Measurement device name: KLA TENCOR Candela CS920 Measurement conditions: Photoluminescence (PL) inspection using excitation light wavelength of 355 nm. Near-ultraviolet and visible light filters were used.

[0059] Figure 8 shows a PL image of stacking faults filtered by a near-ultraviolet filter. Figure 9 shows a PL image of stacking faults filtered by a visible light filter.

[0060] <Results and Discussion> Here, the basal plane dislocation density of the first surface of the silicon carbide substrate was used as an indicator of the crystal quality grade of the silicon carbide substrate. Table 1 shows the basal plane dislocation density of the first surface of the silicon carbide substrate for Examples 1-6 and Reference Examples 1-3, as well as the linear surface defect density and stacking fault density on the upper surface of the silicon carbide epitaxial layer. Figure 3 shows the relationship between the basal plane dislocation density and the linear surface defect density for these samples. Figure 4 shows the relationship between the basal plane dislocation density and the stacking fault density for these samples. Figure 5 shows the relationship between the basal plane dislocation density and the ratio of the linear surface defect density to the basal plane dislocation density for these samples. Figure 6 shows the relationship between the basal plane dislocation density and the ratio of the stacking fault density to the basal plane dislocation density for these samples.

[0061] [Table 1]

[0062] From a comparison of Examples 1-6 and Reference Examples 1 and 3, it can be seen that the stacking fault density and linear surface defect density on the upper surface of the silicon carbide epitaxial layer formed on the (000-1)C plane are significantly smaller than those on the upper surface of the silicon carbide epitaxial layer formed on the (0001)Si plane. In particular, the stacking fault density was 1.2 cm² in Examples 1-6. -2 The linear defect density is suppressed to less than 0.16 cm³, indicating that the propagation of basal plane dislocations from the first surface of the silicon carbide substrate to the silicon carbide epitaxial layer and resulting in stacking faults is effectively suppressed. In Examples 1, 4, and 6, the linear defect density was 0.16 cm³. -2 The following levels are kept in check. Furthermore, in Examples 1, 3, 4, and 6, the stacking fault density was 0.24 cm². -2 The following limits are observed. According to the inventor's research, the CMP described in Patent No. 6295969, along with a polishing method that includes oxidation and etching, and the substrate's basal plane dislocation density is 500 cm². -2 By using the following silicon carbide substrate, the linear defect density can be reduced to 0.1 cm³. -2It was found that it is possible to reduce it to less than 500 cm². Furthermore, by applying CMP described in Patent No. 6295969 and a polishing method that includes oxidation and etching, and by using a substrate basal plane dislocation density of 500 cm². -2 By using the following silicon carbide substrate, the stacking fault density can be reduced to 0.1 cm². -2 It was found that it is possible to reduce it to less than 3000 cm⁻¹. From Figure 6, it can be seen that this defect suppression effect is generally constant regardless of the basal plane dislocation density of the first surface of the silicon carbide substrate. Specifically, at least when the basal plane dislocation density of the first surface of the silicon carbide substrate is 3000 cm⁻¹ -2 Within the following range, the ratio of stacking fault density to basal plane dislocation density on the first surface of the silicon carbide substrate is less than 0.05%.

[0063] Furthermore, a comparison of Examples 1-6 with Reference Example 1 shows that by setting the C / Si ratio in the raw material gas to a range of 1 to 1.6, the linear surface defect density can be reduced to 1.0 cm². -2 It can be seen that it can be suppressed to less than 1.6. Conversely, it can be seen that if the C / Si ratio in the source gas is greater than 1.6, the linear surface defect density on the upper surface of the formed silicon carbide epitaxial layer becomes significantly larger. The linear surface defect density of the sample in Reference Example 1 exceeds 12, so it is not shown in Figure 3.

[0064] From Figure 5, the basal plane dislocation density of the first plane of the silicon carbide substrate is 3000 cm². -2 Within the following range, the ratio of linear surface defect density to basal plane dislocation density on the first surface of the silicon carbide substrate is less than 0.04%.

[0065] In other words, these results show that by forming a silicon carbide epitaxial layer on the (000-1)C plane and setting the C / Si ratio in the source gas to between 1 and 1.6, the influence of basal plane dislocations on the silicon carbide substrate can be effectively suppressed, and linear surface defects and stacking faults on the upper surface of the silicon carbide epitaxial layer can be reduced.

[0066] Furthermore, a comparison of Examples 1-6 with Reference Example 2 reveals that, in order to reduce linear surface defects and stacking faults on the upper surface of the silicon carbide epitaxial layer, it is important to smooth the first surface of the silicon carbide substrate by CMP, or to remove the processed and altered layer by mechanical polishing or the like using CMP.

[0067] Furthermore, Japanese Patent No. 4539140 discloses that by using the (000-1)C plane of a silicon carbide substrate for growing a silicon carbide epitaxial layer, a silicon carbide semiconductor layer can be epitaxially grown on a silicon carbide substrate with a low off-angle of less than 1°, and that the occurrence of step bunching can be reduced by using a substrate with a low off-angle. However, according to this patent document, the surface defect density of the resulting silicon carbide epitaxial layer is 100 cm². -2 This value is considerably larger than the linear surface defect density and stacking fault density in the samples of Examples 1-6 and Reference Examples 1-3 described above.

[0068] Furthermore, for example, the non-patent document "Homoepitaxial Growth on the Near-Facing Surface of 4H-SiC{0001}" ("Materials" (J.Soc.Mat.Sci.,Japan), Vol.53, No.12, pp.1323-1327, Dec.2004)) contains a description of surface defects in homoepitaxially grown films on the near-facing surface of (000-1)C. This non-patent document reports that the surface defect density was reduced by forming a thermal oxide film before epitaxial growth, but no specific numerical value for that density is given. Estimating the surface defect density from Fig. 4 "Surface observation image of homoepitaxially grown film on the near-facing surface of (000-1)C", the density is approximately 100 cm². -2 Degree (6mm 2 It contains 6 surface defects.

[0069] From these findings, it can be seen that the silicon carbide epitaxial substrate produced by the manufacturing method of the silicon carbide epitaxial substrate 10 of this embodiment has a significantly lower linear surface defect density and stacking fault density on the upper surface of the silicon carbide epitaxial layer compared to conventional methods, and that a silicon carbide epitaxial substrate with a high-quality silicon carbide epitaxial layer can be realized. [Industrial applicability]

[0070] The silicon carbide epitaxial substrate disclosed herein is a high-quality silicon carbide epitaxial substrate that can be used for various applications, and is particularly suitable for use in the manufacture of semiconductor devices such as power devices. [Explanation of symbols]

[0071] 10 Silicon carbide epitaxial substrate 20 Silicon carbide substrate 20a Page 1 20b 2nd side 20n normal 30 Silicon Carbide Epitaxial Layer 30a top surface

Claims

1. A silicon carbide substrate having a first surface, The silicon carbide epitaxial layer located on the first surface, Equipped with, On the upper surface of the silicon carbide epitaxial layer, the stacking fault density confirmed by photoluminescence imaging is 1.2 cm². －２ It is less than, The ratio of the stacking fault density to the basal plane dislocation density on the first surface of the silicon carbide substrate is less than 0.05%. On the upper surface of the silicon carbide epitaxial layer, the linear surface defect density is 1.0 cm². －２ It is less than, The ratio of the linear surface defect density to the basal plane dislocation density on the first surface of the silicon carbide substrate is less than 0.04%. The basal plane dislocation density on the first surface of the silicon carbide substrate is 3000 cm². －２ Less than, Silicon carbide epitaxial substrate.

2. The stacking fault density is 1.0 cm －２ A silicon carbide epitaxial substrate according to claim 1, wherein the value is less than [value missing].

3. The aforementioned stacking fault density is 0.35 cm². －２ A silicon carbide epitaxial substrate according to claim 1, wherein the value is less than [value missing].

4. The linear surface defect density is 0.5 cm －２ A silicon carbide epitaxial substrate according to claim 1, wherein the value is less than [value missing].

5. The linear surface defect density is 0.35 cm －２ A silicon carbide epitaxial substrate according to claim 1, wherein the value is less than [value missing].

6. The silicon carbide epitaxial substrate according to claim 1, wherein the diameter of the silicon carbide substrate is 100 mm or more.

7. The basal plane dislocation density on the first surface of the silicon carbide substrate is 2000 cm². －２ A silicon carbide epitaxial substrate according to claim 1, wherein the value is less than [value missing].

8. The silicon carbide epitaxial substrate according to claim 1, wherein the first surface has an off-angle of 4° or less.

9. The silicon carbide epitaxial substrate according to claim 1, wherein the surface roughness Ra of the first surface is 1 nm or less.

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