Information processing device, system, information processing method, and program

JP2026103081APending Publication Date: 2026-06-24RENESAS ELECTRONICS CORP
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
RENESAS ELECTRONICS CORP
Filing Date
2024-12-12
Publication Date
2026-06-24

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Benefits of technology

【0011】 上記の各実施の形態によれば、第1モデルと第2モデルとの間の等価性の検証に要する手間及び時間が削減される。

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Abstract

This reduces the effort and time required to verify the equivalence between the first and second models. [Solution] The setting unit 20 includes a storage unit 21 that stores RTL waveform data 21a showing the waveforms of multiple signals output from an RTL simulator 10 that simulates the operation of a first model representing a target circuit, a determination unit 25A, and a generation unit 26. The multiple signals include a clock signal. The determination unit 25A analyzes the RTL waveform data 21a to determine a mask time period in which one or more of the multiple signals other than the clock signal are not fluctuating. The generation unit 26 generates an input signal to a model simulator 12 that simulates the operation of a second model obtained by converting the first model. The generation unit 26 generates a masked clock signal as an input signal by masking the mask time period in the clock signal.
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Claims

1. An information processing device, The information processing device includes a storage unit that stores waveform data showing the waveforms of multiple signals output from a first simulator that simulates the operation of a first model representing a target circuit, wherein the multiple signals include a clock signal, and the information processing device further includes, A determination unit that analyzes the waveform data to determine a mask time period in which one or more of the multiple signals other than the clock signal are not fluctuating, The system includes a generation unit that generates an input signal to a second simulator that simulates the operation of a second model obtained by converting the first model, The generation unit generates a masked clock signal as the input signal by masking the mask time period in the clock signal.

2. The aforementioned determination unit, Access the first signal list, The information processing apparatus according to claim 1, wherein signals included in the first signal list are excluded from the one or more signals to be analyzed.

3. The information processing apparatus according to claim 2, wherein the first signal list includes a signal obtained by inverting the clock signal.

4. The determination unit further determines an additional time period in which one or more signals to be analyzed satisfy a predetermined first condition. The information processing apparatus according to any one of claims 1 to 3, wherein the generation unit generates the masked clock signal by masking the additional time period in addition to the mask time period in the clock signal.

5. The information processing apparatus according to any one of claims 1 to 3, wherein the determination unit excludes from the mask time period a time period in which one or more signals to be analyzed satisfy a predetermined second condition.

6. The system further includes an extraction unit that accesses a second signal list and extracts one or more target signals included in the second signal list from among the plurality of signals, The information processing apparatus according to any one of claims 1 to 3, wherein the input signal includes one or more signals to be extracted.

7. The information processing apparatus according to any one of claims 1 to 3, wherein the plurality of signals include signals at each of one or more nodes included in the target circuit.

8. The first model is an information processing device according to any one of claims 1 to 3, described at the register transfer level.

9. The second model is an information processing device according to any one of claims 1 to 3, described in SystemC or C++.

10. It is a system, A first simulator that simulates the operation of a first model representing the target circuit, A converter that converts the first model to the second model, A second simulator that simulates the operation of the second model, The system further comprises a storage unit that stores waveform data showing the waveforms of multiple signals output from the first simulator, wherein the multiple signals include a clock signal, and the system further comprises A determination unit that analyzes the waveform data to determine a mask time period in which one or more of the multiple signals other than the clock signal are not fluctuating, The system includes a generation unit that generates an input signal to the second simulator, The generation unit generates a masked clock signal as the input signal by masking the mask time period in the clock signal.

11. Information processing method, The information processing method further includes reading waveform data showing the waveforms of multiple signals output from a first simulator that simulates the operation of a first model representing a target circuit, wherein the multiple signals include a clock signal, and the information processing method further includes By analyzing the waveform data, a mask time period is determined in which one or more of the multiple signals other than the clock signal are not fluctuating. The method includes generating an input signal to a second simulator that simulates the operation of a second model obtained by converting the first model, The above generation includes generating a masked clock signal as the input signal by masking the mask time period in the clock signal.

12. A program for causing a computer to execute the information processing method described in claim 11.

Citation Information

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