Multilayer electronic components and their manufacturing methods

Abstract

To provide a multilayer electronic component that not only improves the voltage withstand capability of the multilayer electronic component, but also provides uniformly high insulation resistance between each internal electrode within the element body. [Solution] The outer region 15 is a stacked electronic component having a first outer region 15a containing more RB than RA, and a second outer region 15b containing more RA than the first outer region, which are continuous in the stacking direction. In the inner region 13, the concentration of RA contained in the inner dielectric layer is higher than the concentration of RA in the first outer region, the second outer region and the inner region are adjacent in the stacking direction, and the thickness of the second outer region is 2 to 50 μm.

Description

[Technical Field]

[0001] The present invention relates to a multilayer electronic component, such as a multilayer ceramic capacitor, and a method for manufacturing the same. [Background technology]

[0002] For example, Patent Document 1 below has been developed. According to the multilayer electronic component described in this document, it has been confirmed that it is possible to achieve both improved moisture resistance and reduced crack occurrence when high voltage is applied. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2024-76784 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] This invention has been made in view of the above circumstances, and its purpose is to provide a multilayer electronic component that not only improves the voltage withstand capability of the multilayer electronic component, but also provides a multilayer electronic component in which the insulation resistance between each internal electrode within the element body is uniformly high. [Means for solving the problem]

[0005] To achieve the above objective, a multilayer electronic component according to one aspect of the present invention is: An element body having an interior region in which an inner dielectric layer and an internal electrode layer are alternately stacked, and an exterior region located outside the stacking direction of the interior region, A multilayer electronic component having a pair of external electrodes connected to the internal electrode layer on the surface of the element body, The aforementioned exterior region is A first outer region containing a second rare earth element different from the first rare earth element in greater quantities than the first rare earth element, The first rare earth element is present in a second outer layer region that is present in a larger quantity than the first outer layer region, and these regions are continuous in the stacking direction. In the interior region, the concentration of the first rare earth element contained in the inner dielectric layer is higher than the concentration of the first rare earth element in the first exterior region. The second exterior region and the interior region are adjacent to each other in the stacking direction. The thickness of the second outer layer is 2 to 50 μm.

[0006] According to this multilayer electronic component, the outer layer consists of a first outer layer containing a second rare earth element different from the first rare earth element in greater quantities than the first rare earth element, and a second outer layer containing a second rare earth element in greater quantities than the first outer layer, both of which are continuous in the stacking direction. Furthermore, the second outer layer is adjacent to the inner layer in the stacking direction.

[0007] This second outer region prevents the diffusion of second rare earth elements, such as Y which are abundant in the first outer region, into the inner region. As a result, the concentration of first rare earth elements near the boundary between the second outer region and the inner region can be kept substantially the same as the concentration of first rare earth elements in the inner dielectric layer of the inner region.

[0008] As a result, the insulation resistance of the inner dielectric layer located at the end of the stacking direction in the interior region (interior IR at the outermost stacking edge) becomes approximately the same as that of the inner dielectric layer located near the center of the stacking direction in the interior region. Therefore, it becomes possible to provide a multilayer electronic component that not only improves the voltage withstand capability of the multilayer electronic component but also provides uniformly high insulation resistance between each internal electrode within the element body. The interior region comprises a first interior region in which the concentration of the second rare earth element contained in the inner dielectric layer is uniformly lower along the stacking direction than the concentration of the second rare earth element contained in the second exterior region, The stacking direction may include a second interior region in which the concentration of the second rare earth element contained in the inner dielectric layer gradually increases toward the outer region compared to the concentration of the second rare earth element contained in the inner dielectric layer of the first interior region.

[0009] Preferably, the second exterior region and the second interior region are adjacent to each other in the stacking direction. The concentration of the second rare earth element in the inner dielectric layer of the second interior region is lower than the concentration of the second rare earth element in the second exterior region.

[0010] Preferably, the concentration of the second rare earth element in the first exterior region is higher than the concentration of the second rare earth element in the second exterior region. Alternatively, the concentration of the first rare earth element in the second interior region may be less than or equal to the concentration of the first rare earth element in the first interior region.

[0011] For example, the boundary between the first outer region and the second outer region is defined as a position along the stacking direction of the outer region that indicates a concentration of the first rare earth element that is the average of the peak intensity corresponding to the concentration of the first rare earth element in the inner dielectric layer located near the center of the stacking direction of the element body in the inner region and the peak intensity corresponding to the concentration of the first rare earth element near the edge in the stacking direction of the outer region.

[0012] Preferably, the first rare earth element is at least one selected from the group consisting of Dy, Yb, Ho, Tb, Gd, and Eu, and the second rare earth element is Y.

[0013] A method for manufacturing a stacked electronic component according to one aspect of the present invention is: A method for manufacturing a multilayer electronic component, comprising the step of forming an element body having an interior region in which an inner dielectric layer and an internal electrode layer are alternately stacked, and an exterior region located outside the stacking direction of the interior region, The aforementioned exterior region is A first exterior green sheet corresponding to a first exterior region containing a second rare earth element different from the first rare earth element in greater quantities than the first rare earth element, A second exterior green sheet corresponding to a second exterior region containing more of the first rare earth element than the first exterior region, It is formed by continuously stacking and firing in the stacking direction, The aforementioned interior area is An interior green sheet containing more of the first rare earth than the first exterior green sheet is laminated together with an electrode paste film for the internal electrode layer, and is formed by firing together with the first exterior green sheet and the second exterior green sheet.

[0014] According to this method for manufacturing a multilayer electronic component, the multilayer electronic component according to one aspect of the present invention described above can be manufactured very easily.

[0015] Preferably, the thickness of the single or multiple sheets constituting the second exterior green sheet is 0.5 to 5 times the thickness of the single or multiple sheets constituting the interior green sheet located between adjacent electrode paste films.

Brief Description of the Drawings

[0016] [Figure 1A] FIG. 1A is a schematic cross-sectional view of a multilayer ceramic capacitor. [Figure 1B] FIG. 1B is a schematic cross-sectional view of the multilayer ceramic capacitor taken along line IB-IB of FIG. 1A. [Figure 2A] FIG. 2A is a mapping image of Dy in an example. [Figure 2B] FIG. 2B is a graph showing the change in the Dy content of FIG. 2A. [Figure 3A] FIG. 3A is a mapping image of Y in an example. [Figure 3B] FIG. 3B is a graph showing the change in the Y content of FIG. 3A.

Modes for Carrying Out the Invention

[0017] Hereinafter, embodiments will be described.

[0018] Overall configuration of a multilayer ceramic capacitor As shown in Figures 1A and 1B, a multilayer ceramic capacitor 2, which is an example of a multilayer electronic component according to this embodiment, has an element body 4, and the element body 4 has an internal region 13 and an external region 15.

[0019] The interior region 13 has an inner dielectric layer 10 and an internal electrode layer 12 that are substantially parallel to a plane containing the X and Y axes, and the inner dielectric layer 10 and the internal electrode layer 12 are stacked alternately in the Z-axis direction. The exterior region 15 is located outside the interior region 13 in the stacking direction (Z-axis direction). In the interior region 13, the internal electrode 12 of the stacking end is located at the outer end (stacking end) in the stacking direction, and in this embodiment, the surface along the outer surface of the internal electrode layer 12 of the stacking end becomes the boundary between the interior region 13 and the exterior region 15. The X, Y, and Z axes are perpendicular to each other.

[0020] Furthermore, "inside" refers to the side closer to the center of the multilayer ceramic capacitor 2, while "outside" refers to the side further away from the center of the multilayer ceramic capacitor 2.

[0021] Furthermore, "substantially parallel" means that most parts are parallel, but there may be some parts that are not parallel, and the inner dielectric layer 10 and the inner electrode layer 12 may have some irregularities or be tilted.

[0022] As shown in Figure 1A, in this embodiment, the end face of the element body 4 in the X-axis direction is flat, and the end face of the outer region 15 along the X-axis, the end face of the inner dielectric layer 10 along the X-axis, and the end face of the inner electrode layer 12 along the X-axis are stacked flush with each other. However, the end face of the element body 4 in the X-axis direction does not necessarily have to be flat and may have a non-flat portion. Also, the end face of the inner dielectric layer 10 along the X-axis and the end face of the inner electrode layer 12 along the X-axis do not have to be flush with each other; for example, a part of the end face of the inner dielectric layer 10 along the X-axis may be shaved off, and a part of the inner electrode layer 12 may protrude when stacked.

[0023] The outer region 15 is composed of an outer dielectric layer 11. The outer region 15 may be a single-layer structure consisting of only one outer dielectric layer 11, or it may be a laminated structure in which multiple outer dielectric layers 11 are stacked. In this embodiment, a laminated structure in which multiple outer dielectric layers 11 are stacked is preferred.

[0024] At both ends of the element body 4 along the X-axis, a pair of external electrodes 6 are formed, each of which is electrically connected to an internal electrode layer 12 that is alternately arranged inside the element body 4. There are no particular restrictions on the shape of the element body 4, but it is usually rectangular. There are also no particular restrictions on the dimensions of the element body 4, and it can be set to an appropriate size depending on the application.

[0025] In this embodiment, the vertical dimension L0 of the element body 4 (see Figure 1A) may be 7.5 to 0.4 mm. The width dimension W0 of the element body 4 (see Figure 1B) may be 6.3 to 0.2 mm. The height dimension H0 of the element body 4 (see Figure 1B) may be 6.3 to 0.05 mm.

[0026] Specific dimensions of the element body 4 include cases where L0 × W0 is (7.5±0.4) mm × (6.3±0.4) mm, (5.7±0.4) mm × (5.0±0.4) mm, (4.5±0.4) mm × (3.2±0.4) mm, (3.2±0.3) mm × (2.5±0.2) mm, (3.2±0.3) mm × (1.6±0.2) mm, (2.0±0.2) mm × (1.2±0.1) mm, (1.6±0.2) mm × (0.8±0.1) mm, (1.0±0.1) mm × (0.5±0.05) mm, (0.6±0.06) mm × (0.3±0.03) mm, (0.4±0.04) mm × (0.2±0.02) mm, etc. Furthermore, H0 is not particularly limited; for example, it can be equivalent to or less than W0.

[0027] internal electrode layer In this embodiment, the internal electrode layers 12 are stacked such that each end in the X-axis direction is alternately exposed from the surface of two opposing end faces of the element body 4.

[0028] The conductive material contained in the internal electrode layer 12 is not particularly limited. Examples of noble metals that can be used as conductive materials include Pd, Pt, and Ag-Pd alloys. Examples of base metals that can be used as conductive materials include Ni, Ni-based alloys, Cu, and Cu-based alloys. Note that Ni, Ni-based alloys, Cu, or Cu-based alloys may contain various trace components such as P and / or S in amounts of about 0.1 mass% or less. The internal electrode layer 12 may also be formed using commercially available electrode paste. The thickness of the internal electrode layer 12 can be appropriately determined according to the application and other factors.

[0029] external electrode The conductive material contained in the external electrode 6 is not particularly limited. For example, known conductive materials such as Ni, Cu, Sn, Ag, Pd, Pt, Au, or alloys thereof, or conductive resins may be used. The thickness of the external electrode 6 may be determined appropriately depending on the application.

[0030] Dielectric layer In this embodiment, the "inner dielectric layer 10" and the "outer dielectric layer 11" may be collectively referred to as the "dielectric layer".

[0031] The thickness of each inner dielectric layer 10 (interlayer thickness) is not particularly limited and can be arbitrarily set according to the desired characteristics and applications. Typically, the interlayer thickness may be 20 μm or less, 10 μm or less, or 5 μm or less. Furthermore, it is desirable that the number of layers of the inner dielectric layer 10 be 10 or more, for example, 50 or more, 100 or more, or 200 or more.

[0032] The thickness of each layer of the outer dielectric layer 11 (interlayer thickness) is not particularly limited and can be, for example, the same as the interlayer thickness of the inner dielectric layer 10. According to the multilayer ceramic capacitor 2 of this embodiment, even if the thickness of the outer dielectric layer 11 is reduced, it can still have moisture resistance and suppress cracks when high voltage is applied. Furthermore, the number of layers of the outer dielectric layer 11 is not particularly limited and may be, for example, 5 or more layers, or 20 or more layers.

[0033] The dielectric layers (inner dielectric layer 10 and outer dielectric layer 11) according to this embodiment include main phase particles (dielectric particles).

[0034] The main phase particles of this embodiment mainly contain a compound having a perovskite-type crystal structure represented by ABO3. The main component of the main phase particles is a component that accounts for 80 to 100 parts by mass, preferably 90 to 100 parts by mass, per 100 parts by mass of the main phase particles. The main phase particles may also contain components other than the main component mentioned above. For example, they may contain a barium (Ba) compound.

[0035] The A in ABO3, i.e., the A-site element, is at least one selected from Ba, strontium (Sr), and calcium (Ca), and A may be at least one selected from Ba and Sr. It may contain 80 moles or more of Ba per 100 moles of A, or 90 moles or more of Ba per 100 moles of A. A may consist of Ba alone.

[0036] The B in ABO3, i.e., the B-site element, is at least one selected from titanium (Ti), zirconium (Zr), and hafnium (Hf). B may also be at least one selected from Ti and Zr. It may contain 70 moles or more of Ti per 100 moles of B, or 80 moles or more of Ti per 100 moles of B. B may consist of Ti alone.

[0037] Assuming that A is at least one selected from Ba, Sr, and Ca, and B is at least one selected from Ti and Zr, the composition of the main components can be specifically described as {(Ba 1-x-y Ca x Sr y )O} u (Ti 1-z Zr z ) v It is O2.

[0038] Preferably x is 0 ≤ x ≤ 0.10, and more preferably 0 ≤ x ≤ 0.05. Preferably y is 0 ≤ y ≤ 0.10, and more preferably 0 ≤ y ≤ 0.05. Preferably z is 0 ≤ z ≤ 0.30, and more preferably 0 ≤ z ≤ 0.15. Preferably u / v is 1.000 ≤ u / v ≤ 1.030, and more preferably 1.000 ≤ u / v ≤ 1.015. When u / v is within the above range, sintering can be performed sufficiently compared to when it is above the above range, and the relative permittivity and reliability of the dielectric composition tend to improve. When u / v is within the above range, sintering stability is less likely to deteriorate compared to when it is below the above range, and the relative permittivity, reliability and temperature characteristics of the multilayer ceramic capacitor 2 tend to improve further.

[0039] The dielectric layer contains RE, M, and silicon (Si) as minor components. In addition to the above, Fe, Al, and / or Zr may also be included as minor components.

[0040] As described above, the minor components may exist in solid solution within the main phase particles. The minor components may be in solid solution within the main phase particles to form the shell portion of the core-shell structure, or they may be completely in solid solution within the main phase particles to form completely solid-solution main phase particles. In addition, the minor components may form segregated particles or exist at the grain boundaries of the main phase particles.

[0041] RE is at least one selected from ytterbium (Yb), yttrium (Y), holmium (Ho), dysprosium (Dy), terbium (Tb), gadolinium (Gd), and europium (Eu), preferably Dy, Ho, Yb, and / or Y.

[0042] Dy, Tb, Gd, and Eu have relatively large ionic radii among the above rare earth elements. On the other hand, Yb, Y, and Ho have relatively small ionic radii among the above rare earth elements. The larger the ionic radius of RE, the easier it tends to dissolve RE in the main phase particles.

[0043] Furthermore, when RE with a relatively large ionic radius is dissolved in the main phase particles, RE tends to mainly substitute for the A-site elements of the main components. On the other hand, when RE with a relatively small ionic radius is dissolved in the main phase particles, RE tends to mainly substitute for the B-site elements of the main components.

[0044] M is at least two elements selected from magnesium (Mg), manganese (Mn), vanadium (V), and chromium (Cr). M is mainly present in the dielectric layer as an oxide of M. In addition, M may substitute for the B-site element among the main components.

[0045] The composition range of the main components of the main phase particles constituting the inner dielectric layer 10 and the composition range of the main components of the main phase particles constituting the outer dielectric layer 11 may be the same or different. Furthermore, the composition range of the minor components of the inner dielectric layer 10 excluding RE and the composition range of the minor components of the outer dielectric layer 11 excluding RE may be the same or different.

[0046] As shown in Figure 1A, Tde is defined as the distance from the outermost surface 120 of the inner electrode layer 12 to the outer surface 40 of the element body 4, i.e., the outer surface of the outer casing region 15. The outer surface 40 of the element body 4 is a plane perpendicular to the stacking direction. Tde is not particularly limited, but is between 10 μm and 500 μm.

[0047] In this embodiment, the area outside the outer layer region 15 in the stacking direction is defined as the first outer layer region 15a. The range of the first outer layer region 15a is not particularly limited, but it can be, for example, the part of the outer layer region 15 other than the second outer layer region 15b, which is determined by the method described later.

[0048] The region on the inner side of the outer layer region 15 in the stacking direction is defined as the second outer layer region 15b. The second outer layer region 15b preferably has a thickness of 2 μm or more and 50 μm or less in the stacking direction, and more preferably 2 μm or more and 20 μm or less.

[0049] The center of the interior region 13 in the stacking direction is defined as the first interior region 13a, and the interior region 13 located outside the first interior region 13a along the stacking direction is defined as the second interior region 13b. That is, the second interior region 13b is the region included in the interior region 13. The range of the second interior region 13b is not particularly limited, but it is preferably the region from the first to the fifth layer toward the center, for example, from the inner dielectric layer 10 located at the stacking edge along the Z axis. The range of the first interior region 13a is not particularly limited, but it can be, for example, the part of the interior region 13 other than the second interior region 13b.

[0050] In this embodiment, the outermost layer of the inner dielectric layer 10, i.e., the outermost inner dielectric layer 10 in the stacking direction (stack edge), is designated as the 1st layer, and the layers are numbered 2nd, 3rd, and so on as they move inward in the stacking direction. Therefore, the outermost inner dielectric layer 10 in the stacking direction is designated as the "1st layer," and the other outermost inner dielectric layers 10 in the stacking direction are also designated as the "1st layer." Furthermore, the first interior region 13a and the second interior region 13b are regions that also include the internal electrode layer 12.

[0051] The rare earth element with the highest molar ratio among the REs contained in the inner dielectric layer 10 of the first inner region 13a is designated as the first rare earth element RA, and the rare earth element with the highest molar ratio among the REs contained in the first outer region 15a is designated as the second rare earth element RB.

[0052] In this embodiment, RA is one of Yb, Ho, Dy, Tb, Gd, and Eu, and RB is Y.

[0053] The RA content DRAa in the first outer layer region 15a, calculated as RA2O3 relative to 100 moles of the main component, may have portions that vary along the stacking direction and portions that remain substantially constant (outward along the stacking direction) (see, for example, Figure 2B). However, in the outer portion along the stacking direction, it may be 1.0 mole or less, more preferably 0.5 mole or less, or substantially 0. In this embodiment, it is preferable that the first outer layer region 15a contains more RB, which is different from RA, than RA.

[0054] In the second outer layer region 15b, the RA content DRAb, calculated as RA2O3 relative to 100 moles of the main component, decreases toward the outside in the stacking direction (see, for example, Figure 2B), but is preferably between 0.4 moles and 7.0 moles. In this embodiment, it is preferable that the second outer layer region 15b contains more RA than the first outer layer region 15a.

[0055] The RA content DRAc in terms of RA2O3 relative to 100 moles of the main component in the inner dielectric layer 10 of the second interior region 13b may change along the stacking direction, but preferably it does not change substantially (see, for example, Figure 2B), and is preferably between 0.4 moles and 7.0 moles.

[0056] The RA content DRAd in the inner dielectric layer 10 of the first interior region 13a, in terms of RA2O3 relative to 100 moles of the main component, may change along the stacking direction, but it is preferable that it does not change substantially (see, for example, Figure 2B), and is preferably between 4 moles and 7.0 moles.

[0057] The RB content DRBa in the first outer layer region 15a, calculated as RB2O3 relative to 100 moles of the main component, may have portions that vary along the stacking direction and portions that remain substantially constant (outward along the stacking direction) (see, for example, Figure 3B), but it is preferable that the content in the outer portion along the stacking direction is between 0.4 moles and 7.0 moles.

[0058] The RB content DRBb in the second outer layer region 15b, calculated as RB2O3 relative to 100 moles of the main component, may vary so as to increase toward the outside in the stacking direction (see, for example, Figure 3B), and is preferably between 0.4 moles and 7.0 moles.

[0059] The content DRBb of RB in terms of RB2O3 conversion with respect to 100 mol parts of the main component in the inner dielectric layer 10 of the second interior region 13b may change so as to increase toward the outside in the lamination direction (see, for example, FIG. 3B), but it is preferable that the amount of change is extremely small, 1.0 mol part or less, more preferably 0.5 mol part or less, or may be substantially 0.

[0060] The content DRBc of RB in terms of RB2O3 conversion with respect to 100 mol parts of the main component in the inner dielectric layer 10 of the first interior region 13a preferably has an extremely small amount of change along the lamination direction (see, for example, FIG. 3B), 1.0 mol part or less, more preferably 0.5 mol part or less, or may be substantially 0.

[0061] The above-described DRAa, DRAb, DRAc, and DRAd satisfy the relationship DRAa < DRAb < DRAc ≤ DRAd. Also, DRBa, DRBb, DRBc, and DRBd satisfy the relationship DRBa > DRBb > DRBc ≥ DRBd.

[0062] Furthermore, in the present embodiment, as shown in FIG. 2B, the concentrations DRAc and DRAd of the first rare earth RA contained in the inner dielectric layer are higher than the concentration DRAab of the first rare earth RA at the boundary between the first exterior region 15a and the second exterior region 15b. In the present embodiment, the concentration of RA or RB has the same meaning as the content in terms of oxide conversion with respect to 100 mol parts of the main component described above, or the peak intensity shown in FIG. 2B or FIG. 3B.

[0063] Also, the concentration DRAbc of the first rare earth element RA in the vicinity of the boundary between the second exterior region 15b and the interior region 13 (the second interior region 13b) (within a range of 0.5 μm on the second exterior region side near the boundary; the same applies hereinafter) is substantially the same as the concentration (DRAc and DRAd) of the first rare earth element RA in the inner dielectric layer in the interior region 13. Substantially the same means that, with the peak intensity shown in FIG. 2B and taking the range of DRAd - DRAa as 100%, the difference between the two is within the range of ±10%.

[0064] Furthermore, in this embodiment, as shown in Figure 3B, the concentrations of the second rare earth element RB contained in the inner dielectric layer, DRBc and DRBd, are lower than the concentration of the second rare earth element RB at the boundary between the first outer layer region 15a and the second outer layer region 15b, DRBab.

[0065] Furthermore, the concentration of the second rare earth element RB, DRBbc, near the boundary between the second outer region 15b and the inner region 13 (second inner region 13b), approaches substantially the same level as the concentration of the first rare earth element RB (DRBc and DRBd) in the inner dielectric layer of the inner region 13. "Approaching substantially the same level" means that, using the peak intensity shown in Figure 3B, with the range of DRBa-DRBd set to 100%, the difference between the two is within ±10%.

[0066] Figure 2A is a mapping image of RA(Dy) obtained by STEM-EDS for a field of view including the first outer region 15a, the second outer region 15b, the second inner region 13b, and the first inner region 13a. Figure 2B shows the change in contrast intensity along point S to point E in Figure 2A. In Figure 2B, the horizontal axis represents contrast intensity, the vertical axis represents distance, the unit of the vertical axis is μm, and the boundary between the inner electrode layer and the outer region 15 is set to 0.

[0067] Figure 3A is an elemental mapping image obtained by STEM-EDS for RB(Y) in the same field of view as Figure 2A, and Figure 3B is a graph showing the change in contrast intensity along point S to point E in Figure 3A. In Figure 3B, the horizontal axis represents contrast intensity, the vertical axis represents distance, the unit of the vertical axis is μm, and the boundary between the internal electrode layer and the outer region 15 is set to 0.

[0068] In this embodiment, as shown in Figures 2B and 3B, the concentrations of RA and RB gradually change from the first outer layer region 15a to the second outer layer region 15b.

[0069] In this embodiment, DRAa and DRBa can also be obtained as average values ​​obtained by analyzing the region within 50 μm from the outer surface in the stacking direction of the outer layer region 15. DRAc and DRBc can also be obtained as average values ​​obtained by analyzing the region from the 1st to the 5th layer of the inner layer region 13. DRBd and DRBd can also be obtained as average values ​​obtained by analyzing the region within 5 layers from the center of the base body outward of the inner layer region 13.

[0070] Furthermore, when calculating DRAc, DRBc, DRAd, and DRBd for the second and first internal regions, the average contrast intensity of the inner dielectric layer within the measurement range, i.e., the region within the measurement range that does not include the internal electrode layer, is used for the calculation.

[0071] In this embodiment, as shown in Figure 2B, the boundary between the first outer region 15a and the second outer region 15b can be defined as the position where the intensity of RA(Dy) is the average of DRAa and DRAd. The distance from the outside of the internal electrode layer in the stacking direction to the boundary, i.e., the thickness T of the second outer region 15b, is preferably 2 to 50 μm, 2 to 20 μm, or 4 to 15 μm. If the point where DRAa and DRAd are averaged is observed only on the side of the internal region 13, the thickness T is 0 and it is determined that the second outer region does not exist. Based on the average values ​​obtained by analyzing the range of the second outer region 15b determined in this way, DRAb and DRBb can be determined.

[0072] CREa is defined as the RE2O3 content of "RE" in the first outer layer region 15a, when the first outer layer region 15a is 100 parts by mass. As described above, in this embodiment, "RE" is at least one selected from Yb, Y, Ho, Dy, Tb, Gd, and Eu. Therefore, "RE" may include both RA and RB. CREa is preferably 0.4 parts by mass or more and 7.0 parts by mass or less.

[0073] In the first outer layer region 15a, the RB content (DRBa) in terms of RE2O3 relative to 100 moles of the main component is preferably 0.7 moles or more. In the second inner layer region 13b, the RA content (DRAc) in terms of RE2O3 relative to 100 moles of the main component is preferably 0.7 moles or more. It is preferable that DRAc and DRAa satisfy the relationship DRAAc / DRAa≧3.

[0074] Manufacturing method for multilayer ceramic capacitors Next, an example of a manufacturing method for the multilayer ceramic capacitor 2 shown in Figure 1A will be described below.

[0075] The multilayer ceramic capacitor 2 of this embodiment is manufactured by creating a green chip using a conventional printing method or sheet method with paste, similar to conventional multilayer ceramic capacitors, firing the green chip, and then printing or transferring external electrodes and firing them again. The manufacturing method will be described in detail below.

[0076] First, a dielectric material for forming the first interior region 13a is prepared, and this is turned into a paint to prepare the first interior paste.

[0077] As dielectric raw materials, raw materials for the main component ABO3 and raw materials for various other oxides are prepared. These raw materials can be oxides of the above-mentioned components, mixtures thereof, or complex oxides. In addition, various compounds that become the above-mentioned oxides or complex oxides upon firing, such as carbonates, oxalates, nitrates, hydroxides, organometallic compounds, etc., can be appropriately selected and mixed for use.

[0078] The particle size of the raw material powder for the main component, ABO3, is not particularly limited, but is, for example, 150 to 300 nm.

[0079] In this embodiment, it is preferable to use a mixture in which oxides of the above-mentioned components are uniformly dispersed in the main component, but dielectric raw materials in which the main component is coated with the above-mentioned components may also be used. Furthermore, in addition to the raw materials of the main component, for example, oxides of RE, oxides of M, and compounds of Si may be used.

[0080] Furthermore, the raw materials for the main component, ABO3, can be produced using various methods, including the so-called solid-phase method as well as various liquid-phase methods (for example, the oxalate method, hydrothermal synthesis method, alkoxide method, sol-gel method, etc.).

[0081] Furthermore, the mixture may contain BaCO3 powder in an amount of 0.1 to 2.0 moles per 100 moles of the main component, calculated as BaCO3.

[0082] Any two or more of the other oxide raw materials listed above may be mixed with the main component and calcined before mixing. For example, the raw materials for RE oxide, Si oxide, and A oxide (e.g., Ba oxide) which are included separately from the main component may be mixed in advance and calcined. The calcination temperature should be less than 1100°C. The compound powder obtained by calcination may then be mixed with the main component and the various oxide raw materials that were not calcined. Doing so changes the ease with which RE dissolves in the main phase particles.

[0083] In the first interior paste, the RE2O3 equivalent content of compounds that become RA after firing is greater than the RE2O3 equivalent content of rare earth compounds other than RA that become RE after firing. Furthermore, while RB(Y) may be included in the first interior paste, it is preferable that it is substantially absent. The content of each compound of elements other than RE in the first interior paste should be determined so that the dielectric layer composition after firing is as described above.

[0084] The first interior paste may be an organic paint obtained by kneading a dielectric raw material and an organic vehicle, or it may be a water-based paint.

[0085] An organic vehicle is a binder dissolved in an organic solvent. Any known binder and solvent may be used.

[0086] Furthermore, if the first interior paste is a water-based paint, a water-based vehicle, which is made by dissolving a water-soluble binder or dispersant in water, can be mixed with the dielectric raw material. The water-soluble binder is not particularly limited; for example, polyvinyl alcohol, cellulose, or water-soluble acrylic resin can be used.

[0087] Simultaneously, or before or after, a second interior paste is prepared. The second interior paste may preferably be exactly the same as the first interior paste, but it may also be different.

[0088] Simultaneously, or before or after, the first outer layer paste is prepared. The first outer layer paste may be the same as the first inner layer paste, except that it differs from the first inner layer paste in the following respects: The first outer layer paste contains more second rare earth element RB than first rare earth element RA, and preferably substantially no first rare earth element RA. The dielectric raw materials of the main components and minor components (additives) other than the rare earth elements in the first outer layer paste are preferably the same as those in the first outer layer paste, but may be different.

[0089] Simultaneously, or before or after, a second outer layer paste is prepared. The second outer layer paste may be the same as the first outer layer paste, except that it differs from the first outer layer paste in the following respects: The second outer layer paste contains more first rare earth element RA than second rare earth element RB, and preferably contains substantially no second rare earth element RB. The second outer layer green sheet formed by the second outer layer paste has the function of preventing the RB contained in the first outer layer green sheet formed by the first outer layer paste from diffusing into the interior region 13 during heat treatment.

[0090] The paste for the internal electrode layer can be prepared by kneading the conductive material made of Ni or Ni alloy as described above, or various oxides, organometallic compounds, resinates, etc., which become Ni or Ni alloy after firing, with the organic vehicle described above. The paste for the internal electrode layer may also contain a co-material. The co-material is not particularly limited, but may have a composition similar to that of the main component.

[0091] The paste for the external electrode can be prepared in the same manner as the paste for the internal electrode layer, using conductive materials such as Cu or Cu alloy as inorganic components.

[0092] There are no particular restrictions on the content of organic vehicles in each of the pastes described above; typical content, for example, about 1 to 15% by mass for the binder and about 10 to 60% by mass for the solvent, is sufficient. In addition, each paste may contain additives selected from various dispersants, plasticizers, dielectrics, insulators, etc., as needed. The total content of these additives may be 10% by mass or less.

[0093] A first outer layer green sheet is formed on a substrate film (substrate) such as PET using a first outer layer paste, and then peeled off the substrate to produce the first outer layer green sheet. Similarly, a second outer layer green sheet is formed on the substrate using a second outer layer paste, and then peeled off the substrate to produce the second outer layer green sheet. The second outer layer green sheet is then laminated on top of the first outer layer green sheet, and pressure is applied in the lamination direction to obtain an outer layer green laminate. The first and second outer layer green sheets may each consist of a single or multiple sheets.

[0094] The thickness of one or more sheets that can constitute the second exterior green sheet is preferably thinner than the thickness of one or more sheets that constitute the first exterior green sheet. Furthermore, the thickness of one or more sheets that constitute the second exterior green sheet is preferably 0.5 to 5 times the thickness of one or more sheets that constitute the interior green sheet located between adjacent paste films for internal electrodes.

[0095] Simultaneously, or before or after, a green sheet is formed on the substrate using a second interior paste, and an internal electrode pattern layer is formed on this using an internal electrode layer paste. The green sheet is then peeled off the substrate to produce a second interior green sheet having an internal electrode pattern layer.

[0096] Simultaneously, or before or after, a green sheet is formed on the substrate using a first interior paste, and an internal electrode pattern layer is formed on this using an internal electrode layer paste. The first interior green sheet having an internal electrode pattern layer is then produced by peeling the green sheet from the substrate.

[0097] The method for forming the internal electrode pattern layer is not particularly limited and may be used by printing, transfer, or thin-film formation methods such as vapor deposition or sputtering.

[0098] Next, multiple second interior green sheets having an internal electrode pattern layer are laminated on a substrate, multiple first interior green sheets having an internal electrode pattern layer are laminated on top of the first, and multiple second interior green sheets having an internal electrode pattern layer are laminated on top of the first, and an interior green laminate is obtained by applying pressure and bonding as needed.

[0099] Next, the inner green laminate is sandwiched between a pair of outer green laminates and pressed in the lamination direction to obtain the green laminate of the element body 4. When sandwiching the inner green laminate between the pair of outer green laminates, the second outer green sheet side of the outer green laminate is made to contact each end of the inner green laminate in the lamination direction.

[0100] In the example described above, the exterior green laminate and the interior green laminate were formed separately and then combined. However, the method is not limited to this; the exterior green laminate may be formed first, followed by the interior green laminate, and then the exterior green laminate may be formed consecutively.

[0101] The green laminate of the element body 4 is cut into a predetermined shape, then peeled off the substrate to form a green chip.

[0102] Before firing, the green chip is subjected to a debinding treatment. The debinding conditions are not particularly limited. For example, the heating rate is preferably 5 to 300 °C / hour, the debinding temperature is preferably 180 to 900 °C, and the holding time is preferably 0.5 to 48 hours. Also, the atmosphere in the debinding treatment is air or a reducing atmosphere (e.g., a humidified N2 gas atmosphere or a humidified N2 + H2 mixed gas atmosphere).

[0103] After debinding, the green chip is fired. The firing conditions are not particularly limited. For example, the heating rate may be 200 to 20000 °C / hour, the firing temperature may be 1150 to 1350 °C, and the holding time may be 0.1 to 10 hours.

[0104] The atmosphere during firing is also not particularly limited. It may be air or a reducing atmosphere. When using a reducing atmosphere, as the atmosphere gas, for example, a mixed gas of N2 and H2 can be humidified and used. Also, the oxygen partial pressure may be 1.0×10 -14 ~1.0×10 -9 MPa.

[0105] In this embodiment, it is preferable to perform an annealing treatment (oxidation treatment of the dielectric layer) on the element body 4 after firing. Specifically, the annealing temperature may be 950 to 1100 °C. The holding time may be 0.1 to 20 hours. The atmosphere during the oxidation treatment may be a humidified N2 gas (oxygen partial pressure: 1.0×10 -9 ~1.0×10 -6 MPa).

[0106] In the above-described debinding treatment, firing, and annealing treatment, when humidifying N2 gas, a mixed gas, etc., for example, a wetter or the like may be used. In this case, the water temperature is preferably about 5 to 75 °C.

[0107] The debinding treatment, firing, and annealing treatment may be performed continuously or independently.

[0108] The obtained element body 4 is subjected to end face polishing by, for example, barrel polishing or sandblasting, and an external electrode paste is applied and fired to form an external electrode 6. Then, if necessary, a coating layer is formed on the surface of the external electrode 6 by plating or the like.

[0109] The multilayer ceramic capacitor 2 of the present embodiment manufactured in this way is mounted on a printed board or the like by soldering or the like and used in various electronic devices and the like.

[0110] In a conventional multilayer ceramic capacitor, there has been a tendency for voids to occur more easily in the exterior region than in the interior region. The reason is considered to be that the interior region contains an internal electrode layer with high thermal conductivity, while the exterior region does not contain an internal electrode layer, so sintering tends to proceed less easily in the exterior region.

[0111] On the other hand, in the multilayer ceramic capacitor 2 according to the present embodiment, by making the compositions of the inner dielectric layer and the outer dielectric layer, particularly the type and content of RE, conform to the above conditions, the exterior region 15 can be sufficiently fired, the porosity of the exterior region 15 can be reduced, and the exterior region 15 can be densified. As a result, the moisture resistance can be improved.

[0112] Further, in the multilayer ceramic capacitor 2 according to the present embodiment, the concentrations of RA and RB gradually change from the exterior region 15 to the interior region 13 so as to satisfy the relationships DRAa < DRAb < DRAc ≤ DRAd and DRBa > DRBb > DRBc ≥ DRBd. As a result, the sintering behavior gradually changes from the exterior region 15 to the interior region 13, so the stress difference between the exterior region 15 and the interior region 13 can be reduced, and as a result, the electrostriction crack can be reduced.

[0113] Furthermore, in this embodiment, the outer layer region 15 has a first outer layer region 15a containing a larger amount of the second rare earth element RB, which is different from the first rare earth element RA, than the first rare earth element RA, and a second outer layer region 15b containing a larger amount of the first rare earth element RA than the first outer layer region 15a, both of which are continuous in the stacking direction. Moreover, the second outer layer region 15b is adjacent to the inner layer region 13 in the stacking direction.

[0114] This second outer region 15b prevents the diffusion of the second rare earth element RB, which is largely composed of Y and other elements present in the first outer region 15a, into the inner region 13. Therefore, as shown in Figure 2B, for example, the concentration DRAbc of the first rare earth element RA near the boundary between the second outer region 15b and the inner region 13 can be kept substantially the same as the concentration DRAAd of the first rare earth element RA in the inner dielectric layer of the inner region 13. Also, as shown in Figure 3B, the concentration DRBbc of the second rare earth element RB near the boundary between the second outer region 15b and the inner region 13 can be kept substantially the same as the concentration DRBd of the second rare earth element RB in the inner dielectric layer of the inner region 13.

[0115] As a result, the insulation resistance of the inner dielectric layer located at the end of the stacking direction in the interior region 13 (interior IR at the outermost stacking edge) becomes approximately the same as the insulation resistance of the inner dielectric layer located near the center of the stacking direction in the interior region 13. Therefore, it becomes possible to provide a multilayer ceramic capacitor that not only improves the voltage withstand capability of the multilayer ceramic capacitor but also provides uniformly high insulation resistance between each internal electrode within the element body.

[0116] [ Variation ] Although embodiments of the present invention have been described above, the present invention is not limited in any way to the embodiments described above, and may be modified in various ways within the scope of the present invention.

[0117] For example, some of the inorganic components of the paste for the internal electrode layer may be replaced with RA or RB. By including an appropriate amount of RA or RB in the paste for the internal electrode layer, the content of RA and RB in the inner dielectric layer 10 of the interior region 13 can be controlled, and DRAa <DRAb<DRAc≦DRAdおよびDRBa> This makes it easier to satisfy the relationship DRBb > DRBc ≥ DRBd.

[0118] Furthermore, although the above-described embodiment described the case in which the multilayer electronic component according to the present invention is a multilayer ceramic capacitor, the multilayer electronic component according to the present invention is not limited to a multilayer ceramic capacitor, but may be any multilayer electronic component having the above-described configuration. [Examples]

[0119] The present invention will be described in more detail below with reference to examples and comparative examples. However, the present invention is not limited to the following examples.

[0120] Example 1 The first interior paste was prepared as follows.

[0121] First, BaTiO3 powder was prepared as the main component raw material powder. The Ba / Ti ratio of the BaTiO3 powder was 1.000. As the secondary component raw material powders, SiO2, BaCO3, MgO powder, MnCO3 powder, V2O5 powder, and oxide powder of the first rare earth element (Dy) were prepared.

[0122] Each prepared raw material powder was weighed so that, per 100 moles of the main component, the amounts were 1.0 mole of SiO2, 1.0 mole of BaCO3, and 0.7 moles of a mixture of MgO powder, MnCO3 powder, and V2O5 powder, calculated on an oxide basis. The raw material powder for RE was also weighed so that, per 100 moles of the main component, the amounts were calculated on an oxide basis as shown in Table 1. Each weighed raw material powder was wet-mixed and ground in a ball mill for 20 hours, then dried to obtain dielectric raw materials.

[0123] Next, 100 parts by mass of dielectric material, 10 parts by mass of polyvinyl butyral resin, 5 parts by mass of dioctyl phthalate (DOP) as a plasticizer, and 100 parts by mass of alcohol as a solvent were mixed in a ball mill to form a paste, thereby obtaining the first interior paste.

[0124] The second interior paste, first outer packaging paste, and second outer packaging paste were prepared in the same manner as the first interior paste, except that the type and content of the raw material powder for the oxide of RE were changed as shown in Table 1.

[0125] Ni powder, terpineol, ethylcellulose, and benzotriazole were prepared in a mass ratio of 44.6:52.0:3.0:0.4. These were then kneaded using a three-roll mill to form a paste, which was used to prepare the paste for the internal electrode layer.

[0126] Using the first outer layer paste prepared as described above, a first outer layer green sheet was formed on a PET film so that its thickness after drying was 6.0 μm. A second outer layer green sheet was also formed on a PET film using the second outer layer paste so that its thickness after drying was 2.0 μm. Multiple first outer layer green sheets were laminated together, and then a single second outer layer green sheet was laminated on top of them. Pressure was then applied in the lamination direction to obtain an outer layer green laminate.

[0127] Simultaneously, or before or after, a green sheet was formed using the first interior paste prepared as described above, with a drying thickness of 4.0 μm. An electrode layer was then printed on this sheet using the paste for the internal electrode layer in a predetermined pattern. Finally, the sheet was peeled from the PET film to produce a first interior green sheet having an internal electrode pattern layer.

[0128] Furthermore, using the second interior paste prepared as described above, a green sheet was formed with a drying thickness of 4.0 μm. An electrode layer was then printed on this sheet using the paste for the internal electrode layer in a predetermined pattern. After that, the sheet was peeled from the PET film to produce a second interior green sheet having an internal electrode pattern layer.

[0129] Next, five second interior green sheets were laminated on top of the second exterior green sheet of the above-mentioned exterior green laminate, then thirty first interior green sheets were laminated on top of that, and then five more second interior green sheets were laminated on top of that. Finally, the above-mentioned exterior green laminate was laminated on top of the second interior green sheets so that its second exterior green sheet side was in contact with the second interior green sheet, and the green laminate of the element body 4 was obtained by pressurizing and bonding. Green chips were obtained by cutting this green laminate to a predetermined size.

[0130] Next, the obtained green chips were subjected to binder removal, firing, and oxidation treatments to obtain the element body, which is a sintered body.

[0131] The debinder removal conditions were as follows: heating rate of 25°C / hour, debinder removal temperature of 235°C, holding time of 8 hours, and atmosphere of air.

[0132] The firing conditions were a heating rate of 200°C / hour, a holding temperature of 1280°C, a holding time of 2 hours, and a cooling rate of 200°C / hour. The atmosphere was a humidified N2+H2 mixed gas atmosphere. The oxygen partial pressure was 5.0 × 10⁻⁶. -11 It was set to approximately MPa.

[0133] The oxidation treatment conditions were as follows: heating rate and cooling rate of 200°C / hour, oxidation treatment temperature of 1050°C, holding time of 3 hours, humidified N2 gas atmosphere, and oxygen partial pressure of 1.0 × 10⁻⁶. -7 The pressure was set to MPa. A wetter was used to humidify the atmosphere during firing and oxidation treatment.

[0134] Next, the end faces of the obtained element bodies were barrel polished, Cu paste was applied as an external electrode, and a baking treatment was performed in a reducing atmosphere to obtain the multilayer ceramic capacitor samples shown in Figures 1A and 1B. The obtained capacitor samples had dimensions of 3.2 mm × 1.6 mm × 0.7 mm, with an inner dielectric layer thickness of 3.0 μm, an internal electrode layer thickness of 1.0 μm, and an outer region thickness (Tde) of 270 μm. The number of inner dielectric layers was 40.

[0135] (STEM-EDS Analysis) The element body 4 was cut along the stacking direction, and the cut surface was polished to obtain a polished surface. Then, a thinning process was performed on the polished surface using a focused ion beam (FIB). Mapping analysis was performed on the thinned measurement sample using a scanning transmission electron microscope (STEM) equipped with an energy dispersive X-ray analyzer (EDS). From the results of the mapping analysis, it was confirmed that RA is Dy and RB is Y. Then, data on the intensity of RA along the stacking direction as shown in FIG. 2B and intensity data of RB as shown in FIG. 3B were obtained.

[0136] Based on the obtained data, DRAa and DRBa were determined. Similarly, DRAc and DRBc, DRAd and DRBd were determined. The position giving the intermediate intensity between DRAa and DRAd was defined as the boundary between the first exterior region 15a and the second exterior region 15b, the thickness T of the second exterior region 15b was determined, and DRAb and DRBb were determined. Furthermore, intensity data of RA near the boundary between the second exterior region 15b and the interior region 13 (the second interior region 13b) were also obtained.

[0137] In Table 2, regarding each relationship of "DRAa < DRBa", "DRAa < DRAb", "DRAa < DRAc", "DRAbc ≒ DRAd (substantially equal or not)", "DRAa < DRAb < DRAc ≦ DRAd", "DRBa > DRBb > DRBc ≧ DRBd", when the relationship is satisfied, it is marked as "Y", and when it is not satisfied, it is marked as "N".

[0138] (Breakdown Voltage) A DC voltage was applied to the obtained multilayer ceramic capacitor sample, and the voltage at which it short-circuited when the applied voltage was increased was defined as the breakdown voltage. Samples with VB less than 150 were evaluated as "NG", samples with a breakdown voltage of 150 V or more and less than 200 V were evaluated as "B", and samples with a breakdown voltage of 200 V or more were evaluated as "A". It can be judged that the higher the breakdown voltage, the higher the effect of reducing electrostrictive cracks. The results are shown in Table 2.

[0139] (Inner IR at the Maximum Stacking End) For the obtained multilayer ceramic capacitor samples, the external electrodes were polished to expose the internal electrodes. Using a pin probe, the electrical resistance (IR) was measured by contacting the terminals with a pair of internal electrodes adjacent to the inner dielectric layer located on the outside in the stacking direction. Specifically, at room temperature (20°C), a DC voltage of 50V was applied to the capacitor sample for 30 seconds, and the resistance value (Ω) of the outermost layer of the capacitor sample thereafter was measured using an insulation resistance meter. This measurement was performed on 10 capacitor samples for each condition, and the average value of the measurement results (average resistance value) was calculated as the inner IR (Ω) at the outermost stacking edge. Furthermore, for these capacitor samples, the electrical resistance at the center was similarly measured by contacting a pin probe with a pair of internal electrodes adjacent to the inner dielectric layer located closest to the center in the stacking direction. At this time, samples with a resistance value of less than 80% of the average resistance value at the center of the same chip were classified as "NG," and samples with a resistance value of 80% or more were classified as "A." The results are shown in Table 2.

[0140] (judgement) Multilayer ceramic capacitor samples (Comparative Example) that were evaluated as "NG" in either "Withstand Voltage" or "Internal IR at the Outermost Layer" were evaluated as "NG". Multilayer ceramic capacitor samples (Example) that were evaluated as "B" for "Withstand Voltage" and "A" for "Internal IR at the Outermost Layer" were evaluated as "A".

[0141] Multilayer ceramic capacitor samples (examples) that were evaluated as "A" for "Withstand Voltage" and "Inner IR at the outermost layer" were evaluated as "AA". The results are shown in Table 2.

[0142] Comparative Example 1 As shown in Table 1, a multilayer ceramic capacitor sample was obtained in the same manner as in Example 1, except that the type and content of RE in the first outer paste were the same as those in the first inner paste, and the same evaluation as in Example 1 was performed. The results are shown in Table 2.

[0143] Comparative Example 2 A multilayer ceramic capacitor sample was obtained in the same manner as in Example 1, except that a green sheet with the same composition as the first outer layer green sheet was used as the second outer layer green sheet, and the same evaluation as in Example 1 was performed. The results are shown in Table 2.

[0144] Examples 2-6, Comparative Example 3 Except for adjusting the interlayer ratio of the sheets shown in Table 1, i.e., the number of layers of the second outer green sheet relative to the first inner green sheet, so that the thickness T of the second outer region was the value shown in Table 2, a multilayer ceramic capacitor sample was obtained in the same manner as in Example 1, and evaluated in the same manner as in Example 1. The results are shown in Table 2.

[0145] Comparative Example 4 As shown in Table 1, a multilayer ceramic capacitor sample was obtained in the same manner as in Comparative Example 1, except that Dy2O3 was replaced with Tb7O4 in order to change the type of RE from Dy to Tb, and the same evaluation as in Example 1 was performed. The results are shown in Table 2.

[0146] Example 7 As shown in Table 1, a multilayer ceramic capacitor sample was obtained in the same manner as in Example 2, except that Dy2O3 was replaced with Tb7O4, and the same evaluation as in Example 1 was performed. The results are shown in Table 2.

[0147] [Table 1]

[0148] [Table 2]

[0149] From the results shown in Table 1 and Table 2, it was confirmed that in each example satisfying the relationships of DRAa < DRBa, DRAa < DRAb, and DRAa < DRAc and where the thickness T of the second exterior region 15b is within a predetermined range, the withstand voltage and IR characteristics are good. Alternatively, in each example satisfying the relationships of DRAa < DRAb < DRAc ≦ DRAd and DRBa > DRBb > DRBc ≧ DRBd and where the thickness T of the second exterior region 15b is within a predetermined range, it was confirmed that the withstand voltage and IR characteristics (the IR of the innermost stacked end) are good.

[0150] As shown in FIGS. 2A, 2B, 3A, and 3B, particularly in Example 3, it was confirmed that the concentration of RA(Dy) and the concentration of RB(Y) gradually change from the first exterior region 15a to the second exterior region 15b so as to satisfy the above relationships.

[0151] Also, as shown in FIG. 2B, it was confirmed that the concentration DRAbc of the first rare earth element RA near the boundary between the second exterior region 15b and the interior region 13 is maintained substantially the same as the concentration DRAd of the first rare earth element RA in the inner dielectric layer in the interior region 13 (DRAbc ≒ DRAd). Further, as shown in FIG. 3B, it was confirmed that the concentration DRbc of the second rare earth element RB near the boundary between the second exterior region 15b and the interior region 13 is maintained substantially the same as the concentration DRBd of the second rare earth element RB in the inner dielectric layer in the interior region 13. It was confirmed that such a tendency also results in the same results in other Examples 1, 2, and 4 to 7.

[0152] Thus, in Examples 1 to 7, since the sintering behavior gradually changes from the first exterior region 15a to the second exterior region 15b, it is considered that the stress difference between the exterior region 15 and the interior region 13 can be reduced, and as a result, the withstand voltage is good, that is, the electrostriction crack can be reduced. Also, in the examples, it is considered that the diffusion of Y into the interior region 13 is prevented and the IR characteristics (the IR of the innermost stacked end) can be kept high.

[0153] In Comparative Example 1, both the elemental species corresponding to RA and the elemental species corresponding to RB were Dy. In Comparative Example 1, this prevented the formation of a concentration gradient of RA and RB from the outer region to the inner region, making it impossible to reduce the difference in sintering behavior between the outer and inner regions. As a result, it is believed that stress remained inside the chip, leading to a "NG" voltage resistance characteristic.

[0154] In Comparative Example 2, DRAa <DRAb<DRAc≦DRAdならびにDRBa> While the relationship DRBb > DRBc ≥ DRBd was satisfied, the thickness T of the second outer layer region was smaller. In Comparative Example 2, it is thought that Y in the first outer layer paste diffused into the second inner layer region 13b, resulting in a deterioration of the inner layer IR at the outermost layer. Also, in Comparative Example 2, DRAbc was not substantially identical to DRAd.

[0155] In Comparative Example 3, DRAa <DRAb<DRAc≦DRAdならびにDRBa> While the relationship DRBb > DRBc ≥ DRBd was satisfied, the thickness T of the second outer region was large. In Comparative Example 3, similar to Comparative Example 1, a concentration gradient of RA and RB was not formed from the outer region to the inner region, and the difference in sintering behavior between the outer and inner regions could not be reduced. Therefore, it is thought that the voltage withstand characteristics became "NG" due to residual stress inside the chip.

[0156] In Comparative Example 4, both the elemental species corresponding to RA and the elemental species corresponding to RB were Tb. Therefore, similar to Comparative Example 1, in Comparative Example 4, a concentration gradient of RA and RB was not formed from the outer region to the inner region, and the difference in sintering behavior between the outer and inner regions could not be reduced. As a result, it is thought that stress remained inside the chip, leading to a "NG" (Not Good) voltage withstand test.

[0157] The results from Example 7 show that even when RA is Tb, it is possible to achieve both high withstand voltage characteristics and IR characteristics, similar to the example where RA is Dy. [Explanation of Symbols]

[0158] 2… Multilayer ceramic capacitor 4… Element body 13… Interior Design Area 10… Inner dielectric layer 12… Internal electrode layer 13a... 1st interior area 13b…Second interior area 15…Exterior area 11... Outer dielectric layer 15a... 1st exterior area 15b... 2nd exterior area 6... External electrode

Claims

1. An element body having an interior region in which an inner dielectric layer and an internal electrode layer are alternately stacked, and an exterior region located outside the stacking direction of the interior region, A multilayer electronic component having a pair of external electrodes connected to the internal electrode layer on the surface of the element body, The aforementioned exterior region is A first outer region containing a second rare earth element different from the first rare earth element in greater quantities than the first rare earth element, The first rare earth element is present in a second outer layer region that contains a larger amount of the first outer layer region than the first outer layer region, and these regions are continuous in the stacking direction. In the interior region, the concentration of the first rare earth element contained in the inner dielectric layer is higher than the concentration of the first rare earth element in the first exterior region. The second exterior region and the interior region are adjacent to each other in the stacking direction. A multilayer electronic component having a thickness of 2 to 50 μm in the second outer casing region.

2. The interior region comprises a first interior region in which the concentration of the second rare earth element contained in the inner dielectric layer is uniformly lower along the stacking direction than the concentration of the second rare earth element contained in the second exterior region, The stacking direction includes a second interior region in which the concentration of the second rare earth element contained in the inner dielectric layer gradually increases toward the outer region compared to the concentration of the second rare earth element contained in the inner dielectric layer of the first interior region, and the stacking direction includes a second interior region in which the concentration gradually increases toward the outer region. The second exterior region and the second interior region are adjacent to each other in the stacking direction. The multilayer electronic component according to claim 1, wherein the concentration of the second rare earth element in the inner dielectric layer of the second inner region is lower than the concentration of the second rare earth element in the second outer region.

3. The concentration of the second rare earth element in the first outer region is higher than the concentration of the second rare earth element in the second outer region. The multilayer electronic component according to claim 2, wherein the concentration of the first rare earth element in the second interior region is less than or equal to the concentration of the first rare earth element in the first interior region.

4. The stacked electronic component according to any one of claims 1 to 3, wherein the boundary between the first outer region and the second outer region is defined as a position along the stacking direction of the outer region that indicates a concentration of the first rare earth element that is the average of the peak intensity corresponding to the concentration of the first rare earth element in the inner dielectric layer located near the center of the stacking direction of the element body in the inner region and the peak intensity corresponding to the concentration of the first rare earth element near the end of the outer region in the stacking direction.

5. The first rare earth element is at least one selected from the group consisting of Dy, Yb, Ho, Tb, Gd, and Eu. The multilayer electronic component according to any one of claims 1 to 3, wherein the second rare earth element is Y.

6. A method for manufacturing a multilayer electronic component, comprising the step of forming an element body having an interior region in which an inner dielectric layer and an internal electrode layer are alternately stacked, and an exterior region located outside the stacking direction of the interior region, The aforementioned exterior region is A first exterior green sheet corresponding to a first exterior region containing a second rare earth element different from the first rare earth element in greater quantities than the first rare earth element, A second exterior green sheet corresponding to a second exterior region containing a larger amount of the first rare earth element than the first exterior region, It is formed by continuously stacking and firing in the stacking direction, The aforementioned interior area is A method for manufacturing a laminated electronic component, comprising laminating an interior green sheet containing a larger amount of the first rare earth element than the first exterior green sheet together with an electrode paste film for the interior electrode layer, and firing the laminated sheet together with the first exterior green sheet and the second exterior green sheet.

7. The method for manufacturing a laminated electronic component according to claim 6, wherein the thickness of one or more sheets constituting the second outer green sheet is 0.5 to 5 times the thickness of one or more sheets constituting the inner green sheet located between adjacent electrode paste films.

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