Hardware-optimized symmetric high-performance automated parallelization system with loop-level parallelization and method thereof

The compiler system addresses inefficiencies in multiprocessor code parallelization by partitioning code into compute block nodes and using matrices/tensors to optimize latency and parallelism, achieving improved throughput and hardware adaptation.

JP2026516776APending Publication Date: 2026-05-26マイナティックス アーゲー
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Patent Information

Application Number
JP2025562086
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2023-04-24
Publication Date
2026-05-26

AI Technical Summary

Technical Problem

Conventional compilers struggle to efficiently parallelize code for multiprocessor systems, particularly in managing latency and data dependencies, leading to suboptimal performance in modern computing architectures with increasing core counts and heterogeneous hardware.

Method used

A compiler system that automatically optimizes code for multiprocessor systems by partitioning it into compute block nodes, using matrices and tensors to minimize latency and maximize parallelism across multiple processing units, incorporating a parser, matrix builder, and optimizer to generate optimized machine code.

Benefits of technology

Enhances throughput by efficiently managing processor and data dependencies, optimizing low-level parallelism, and adapting to hardware-specific requirements, overcoming limitations of prior art systems.

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Abstract

A symmetric automatic compiler system (1) and method for high-performance, hardware-optimized automatic parallelization of program code (3) for execution by a multicore or multiprocessor parallel processing system (2) having multiple processing units (21) that simultaneously process instructions for data in a parallel processing system (2) by executing program code (3). The automatic compiler system (1) converts the sequential source code (31) of program code (3) into parallel processing machine code (32) which includes several instructions that can be executed by multiple processing units (21) of the parallel processing system (2) or that control the operation of multiple processing units (21).
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