Switching power supply and control method for switching power supply

Abstract

To provide a switching power supply device and a control method for the switching power supply device which can improve power supply transient response are provided.SOLUTION: A current mode control type switching power supply device according to an embodiment has a changeable overcurrent protection value, and an error amplifier that outputs an error voltage corresponding to the difference between the output current of the switching power supply and a reference current, a PWM control unit that performs PWM control by comparing an error voltage with the voltage of a carrier signal for PWM, and a voltage limiter that limits the output upper limit voltage of the error amplifier on the basis of the overcurrent protection value.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a switching power supply and a method for controlling a switching power supply. [Background technology]

[0002] Conventionally, in typical current-mode controlled switching power supplies, the output voltage is divided by a feedback resistor, and the difference voltage from the reference voltage is amplified and output by an error amplifier. Based on the output of the error amplifier, the duty cycle is determined by PWM modulation, and the power MOSFETs that perform switching are driven to control the output voltage to a constant level.

[0003] In such current-mode controlled switching power supplies, the current flowing through an inductor (e.g., a smoothing coil) is detected, and the detected current is used as the carrier signal for a PWM comparator to perform PWM modulation. Therefore, the carrier signal voltage increased as the load current increased.

[0004] Furthermore, conventional switching power supplies performed pulse-bi-pulse control to protect against overload conditions by forcibly turning off the switching element when the peak value of the current flowing through the inductor reached a predetermined current limit value (overcurrent limit value).

[0005] In this case, some proposals involve changing the value of an external resistor to set a predetermined current limit, or using SPI (Serial Peripheral Interface) or I2C (Inter-Integrated Circuit), which are synchronous serial communication interfaces, to set a predetermined current limit (overcurrent limit) in the switching power supply IC via communication. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2019-092306 [Patent Document 2] Japanese Patent Publication No. 2015-216763 [Overview of the project] [Problems that the invention aims to solve]

[0007] However, when the input voltage is low and the desired output voltage cannot be obtained, a sudden increase in the input voltage can cause a large overshoot in the output voltage, potentially exceeding the load's voltage rating. In such cases, there is a risk that the load may suffer irreversible damage.

[0008] In particular, in current-mode controlled switching power supplies, as mentioned above, the voltage of the PWM carrier signal increases in proportion to the output current, so the output voltage range of the error amplifier must also be wide. Especially in high-current current-mode controlled switching power supplies, the output voltage range of the error amplifier is designed to be wide, which leads to a problem where the settling time of the error amplifier is long and the overshoot in the output voltage of the switching power supply becomes large. Furthermore, in switching power supplies where a predetermined current limit can be arbitrarily set, the output voltage range of the error amplifier must be widened even further, which leads to the problem of even greater overshoot.

[0009] Therefore, the present invention aims to provide a switching power supply device and a control method for a switching power supply device that can improve the power supply transient response. [Means for solving the problem]

[0010] The switching power supply device of the embodiment is a current mode control type switching power supply device capable of changing the overcurrent protection value. In the switching power supply device, an error amplifier that outputs an error voltage corresponding to the difference between the output voltage of the switching power supply device and the reference voltage, an error voltage, and a PWM control unit that performs PWM control by comparing the voltage of the carrier signal for PWM, and based on the overcurrent protection value The lower the overcurrent protection value, the better. the output upper limit voltage of the error amplifier is Lower a voltage limiting unit that limits it, and is provided with.

Advantages of the Invention

[0011] According to the present invention, even when the input voltage rapidly rises, an overshoot does not occur in the output voltage of the switching power supply, and it is possible to provide a switching power supply device and a control method for the switching power supply device that improve the power supply transient response.

Brief Description of the Drawings

[0012] [Figure 1] FIG. 1 is a schematic configuration block diagram of a switching power supply IC according to the first embodiment. [Figure 2] FIG. 2 is a schematic configuration diagram of a voltage variable power supply for an error amplifier according to the first embodiment. [Figure 3] FIG. 3 is an explanatory diagram of the first modification of the first embodiment. [Figure 4] FIG. 4 is an explanatory diagram of the second modification of the first embodiment. [Figure 5] FIG. 5 is an explanatory diagram of a specific example of a variable clamper. <000008`3>FIG. 6 is an explanatory diagram of the second embodiment. [Figure 7] FIG. 7 is an explanatory diagram of a specific example of a carrier amplitude magnification changing unit. [Figure 8] FIG. 8 is an explanatory diagram of the third embodiment. [Figure 9] FIG. 9 is a specific example and an operation explanatory diagram of a peak detection variable clamper. [Figure 10] FIG. 10 is a modification example and an operation explanatory diagram of a peak detection variable clamper.

Best Mode for Carrying Out the Invention

[0013] Next, embodiments will be described with reference to the drawings. [1] First Embodiment FIG. 1 is a schematic configuration block diagram of a switching power supply IC 10 according to the first embodiment. The switching power supply IC 10 constitutes a current-mode switching power supply device. A load LD is connected to an output terminal SW via an output section FL, and an output voltage V OUT is supplied to the load LD. The output section FL includes an inductor L1, a resistor for detecting the current flowing through the inductor L1, and a capacitor C. A capacitor C is connected to the other end on the load LD side of the power supply output line to which the inductor L1 is connected, and the other end of the capacitor C is grounded.

[0014] The switching power supply IC 10 includes a low dropout linear regulator (LDO) 11, a diode 12, a first switching transistor 13, a second switching transistor 14, a first driver (DRV) 15, a second driver (DRV) 16, a driver control section 17, a variable overcurrent detection section 18, and a PWM control section 19.

[0015] The variable overcurrent detection unit 18 detects the current flowing through the inductor L1 by monitoring the potential difference across the current detection resistor of the output unit FL, and outputs to the driver control unit 17 whether or not an overcurrent has flowed based on a variable overcurrent detection threshold. The driver control unit 17 controls the first or second driver to turn off the first switching transistor 13 or the second switching transistor 14 until the next switching cycle when an overcurrent is detected (pulse-by-pulse control). The PWM control section 19 includes a slope compensation signal generation section 21, a current detection section 22, an addition circuit 23, a PWM comparator 24, a voltage division circuit 25, a voltage variable power supply for error amplifier 26, an error amplifier 2'7, and a phase compensation circuit 28.

[0016] The slope compensation signal generation section 21 generates a ramp wave voltage having the same period as the control signals of the first switching transistor 13 and the second switching transistor 14, and outputs it to the addition circuit 23 as a slope compensation signal.

[0017] The current detection unit 22 detects the output current of the switching power supply IC 10 flowing through the inductor L1 and outputs it to the adder circuit 23 as the original carrier signal for the PWM comparator 24.

[0018] The summing circuit 23 adds the slope compensation signal output by the slope compensation signal generation unit and the original carrier signal output by the current detection unit 22, and outputs the resulting carrier signal to the inverting input terminal of the PWM comparator 24 for use in PWM modulation. By adding the slope compensation signal to the original carrier signal in this way, measures are taken to address subharmonic oscillation, which is characteristic of current-mode switching power supplies.

[0019] The voltage divider circuit 25 divides the output voltage of the switching power supply IC 10, which is input from the feedback terminal FB of the switching power supply IC 10, and outputs it to the error amplifier 27. The variable voltage power supply 26 for the error amplifier limits the output voltage range of the error amplifier 27 by varying the supply voltage according to the overcurrent protection value SOCP and outputting it to the error amplifier 27.

[0020] As mentioned above, the original carrier signal detected by the current detection unit 22 increases in voltage as the current flowing through the load LD increases. Therefore, the output voltage range of the error amplifier is appropriately limited according to the overcurrent protection value SOCP, thereby shortening the settling time of the error amplifier.

[0021] The error amplifier 27 amplifies the voltage difference between the output voltage of the switching power supply IC 10, which has been divided by the voltage divider circuit 25, and the reference voltage Vref, and outputs it to the non-inverting input terminal of the PWM comparator 24.

[0022] As a result, when the output voltage of the error amplifier 27 exceeds the voltage of the carrier signal, the PWM comparator 24 controls the first driver 15 and the second driver 16 to control the on / off state of the first switching transistor 13 and the second switching transistor 14 via the first driver 15 and the second driver 16.

[0023] Figure 2 is a schematic diagram of the variable voltage power supply for the error amplifier according to the first embodiment. The variable voltage power supply 26 for the error amplifier includes an operational amplifier 31, a transistor 32, and a voltage divider circuit 33. The non-inverting input terminal of the operational amplifier 31 is connected to a reference voltage Vref1, and its output terminal is connected to the gate terminal of transistor 32. Transistor 32 has an external power supply PW supplied to its drain terminal, and its source terminal is connected to the high-potential power supply terminal of the error amplifier 27. Furthermore, the source terminal of transistor 32 is connected to the voltage divider circuit 33.

[0024] The voltage divider circuit 33 includes a variable resistor 34 whose resistance value is varied according to the overcurrent protection value SOCP, and a fixed resistor 35 whose resistance value is fixed and whose one end is connected to the variable resistor 34 and the other end is grounded. Furthermore, the connection point between the variable resistor 34 and the fixed resistor 35 is connected to the inverting input terminal of the operational amplifier 31, and the variable voltage power supply 26 for the error amplifier outputs a variable voltage corresponding to the reference voltage Vref1 and the resistance value of the variable resistor 34 as power supply PE1 to the power supply terminal of the error amplifier 27. In this case, the variable resistor 34 is set to a value proportional to the resistance value corresponding to the overcurrent protection value SOCP, and is controlled to have a lower resistance value so as the overcurrent protection value SOCP decreases, the output voltage decreases. As a result, according to the first embodiment, the upper limit of the output voltage range of the error amplifier becomes lower as the overcurrent protection value SOCP decreases, and therefore the output voltage of the switching power supply V OUT This makes it possible to suppress the overshoot.

[0025] [1.1] First modified example of the first embodiment Figure 3 is an explanatory diagram of a first modified example of the first embodiment. The variable voltage power supply 26 for the error amplifier shown in Figure 2 lowers the power supply voltage supplied to the entire error amplifier 27 when the overcurrent protection value SOCP is reduced. In this modified version, a two-stage amplification circuit is used as the error amplifier 27A instead of the error amplifier 27, with the power supply voltage of the first stage amplification circuit remaining fixed, while the power supply voltage of the second stage amplification circuit is made variable. The first stage amplifier circuit includes a constant current source CS with one end connected to a fixed voltage power supply PE0, a P-channel MOS transistor TR1 with its source terminal connected to the constant current source CS and its gate terminal connected to the non-inverting input terminal +, a P-channel MOS transistor TR2 with its source terminal connected to the constant current source CS and its gate terminal connected to the inverting input terminal -, an N-channel MOS transistor TR3 with its drain terminal connected to the drain terminal of the P-channel MOS transistor TR1, its gate terminal connected to the drain terminal, and its source terminal grounded, and an N-channel MOS transistor TR4 with its drain terminal connected to the drain terminal of the P-channel MOS transistor TR2, its gate terminal connected to the drain terminal, and its source terminal grounded.

[0026] The second stage amplifier circuit includes a P-channel MOS transistor TR11 connected to the output terminal of the variable voltage power supply 26 for the error amplifier, with a variable voltage power supply PE1 supplied to its source terminal and its gate and drain terminals connected; a P-channel MOS transistor TR12 whose source terminal is connected to the source terminal of the P-channel MOS transistor TR11, whose gate terminal is connected to the gate terminal of the P-channel MOS transistor TR11, and whose drain terminal is connected to the output terminal OUT of the error amplifier 27A; an N-channel MOS transistor TR13 whose drain terminal is connected to the drain terminal of the P-channel MOS transistor TR11, whose gate terminal is connected to the gate terminal of the N-channel MOS transistor TR4, and whose source terminal is grounded; and an N-channel MOS transistor TR14 whose drain terminal is connected to the output terminal OUT of the error amplifier 27A, whose gate terminal is connected to the gate terminal of the N-channel MOS transistor TR3, and whose source terminal is grounded.

[0027] In the above configuration, the P-channel MOS transistor TR1 carries a current proportional to the voltage at the non-inverting input terminal of the error amplifier 27A, and the N-channel MOS transistor TR3 carries a current proportional to the voltage at the inverting input terminal of the error amplifier 27A. The sum of the currents flowing through the P-channel MOS transistor TR1 and the N-channel MOS transistor TR3 is equal to the current flowing through the constant current source CS.

[0028] Furthermore, N-channel MOS transistors TR4 and TR13 constitute a current mirror circuit, and a current proportional to the current flowing between the drain terminal and source terminal of transistor TR2 of error amplifier 27A flows through them.

[0029] Similarly, N-channel MOS transistors TR3 and TR14 also constitute a current mirror circuit, and a current proportional to the current flowing between the drain and source terminals of transistor TR1 of error amplifier 27A flows through them.

[0030] Furthermore, P-channel MOS transistors TR11 and TR12 also constitute a current mirror circuit.

[0031] As a result, the current flowing through the P-channel MOS transistor TR11 is proportional to the current flowing through the N-channel MOS transistor TR13, i.e., the current flowing through the P-channel MOS transistor TR2, and is also proportional to the voltage of the power supply PE1.

[0032] Similarly, the current flowing through the P-channel MOS transistor TR12 is proportional to the current flowing through the N-channel MOS transistor TR14, that is, the current flowing through the P-channel MOS transistor TR1, and is also proportional to the voltage of the power supply PE1.

[0033] Therefore, without affecting the input voltage range of the error amplifier 27A, the upper limit of the output voltage of the output terminal OUT of the error amplifier 27A is lower as the overcurrent protection value SOCP is lower, similar to the first embodiment shown in Figure 2, and thus the output voltage V of the switching power supply OUT This makes it possible to suppress the overshoot.

[0034] [1.2] Second modified example of the first embodiment Next, a second modified example of the first embodiment will be described. The difference between the second modification of the first embodiment and the first embodiment is that while the first embodiment reduced the upper limit of the output voltage of the error amplifier by changing the power supply voltage of the error amplifier, the second modification limits the upper limit of the output voltage of the error amplifier by a variable clamper corresponding to the overcurrent protection value SOCP. Figure 4 is an explanatory diagram of a second modified example of the first embodiment. In Figure 4, the same reference numerals are used for parts that are the same as those in Figure 1, and detailed explanations should be consulted. The PWM control unit 19A of the second modified embodiment of the first embodiment includes a slope compensation signal generation unit 21, a current detection unit 22, an adder circuit 23, a PWM comparator 24, a voltage divider circuit 25, a variable clamper 41, and an error amplifier 27.

[0035] The slope compensation signal generation unit 21 generates ramp wave voltages with the same period as the control signals of the first switching transistor 13 and the second switching transistor 14, and outputs them to the summing circuit 23 as slope compensation signals.

[0036] The current detection unit 22 detects the output current of the switching power supply IC 10 flowing through the inductor L1 and outputs it to the adder circuit 23 as the original carrier signal for the PWM comparator 24.

[0037] The summing circuit 23 adds the slope compensation signal output by the slope compensation signal generation unit and the original carrier signal output by the current detection unit 22, and outputs the resulting carrier signal to the inverting input terminal of the PWM comparator 24 for use in PWM modulation. By adding the slope compensation signal to the original carrier signal in this way, measures are taken to address subharmonic oscillation, which is characteristic of current-mode switching power supplies.

[0038] The voltage divider circuit 25 divides the output voltage of the switching power supply IC 10, which is input from the feedback terminal FB of the switching power supply IC 10, and outputs it to the error amplifier 27.

[0039] The error amplifier 27 amplifies the voltage difference between the output voltage of the switching power supply IC 10, which has been divided by the voltage divider circuit 25, and the reference voltage Vref, and outputs it to the non-inverting input terminals of the variable clamper 41 and the PWM comparator 24.

[0040] The variable clamper 41 limits the output voltage range of the error amplifier 27 with a clamp voltage that is set to a limit by varying the supply voltage according to the overcurrent protection value SOCP, and outputs it to the PWM comparator 24.

[0041] Here, we will explain a specific example of the variable clamper 41. Figure 5 is an explanatory diagram illustrating a specific example of a variable clamper. The variable clamper 41 includes a P-channel MOS transistor TR21 whose body terminal is connected to the power supply terminal VDD, whose source terminal is connected to the input terminal IN to which the variable power supply VPS is connected, and whose gate terminal and drain terminal are connected; a constant current source CS1 whose one end is connected to the drain terminal of the P-channel MOS transistor TR21 and whose other end is grounded; and a P-channel MOS transistor TR22 whose body terminal is connected to the power supply terminal VDD, whose source terminal is connected to the output terminal OUT of the error amplifier 27 via the output terminal OUT of the variable clamper 41, whose gate terminal is connected to the gate terminal of the P-channel MOS transistor TR21, and whose drain terminal is grounded.

[0042] In the above configuration, the voltage at the input terminal IN is set by the variable power supply VPS to a voltage proportional to the overcurrent protection value SOCP. Furthermore, since P-channel MOS transistors TR21 and TR22 constitute a current mirror circuit, the voltage at the output terminal OUT is clamped with a voltage proportional to the voltage of the variable power supply VPS.

[0043] As a result, when the output voltage of the error amplifier 27 exceeds the voltage of the carrier signal, the PWM comparator 24 controls the first driver 15 and the second driver 16 to control the on / off state of the first switching transistor 13 and the second switching transistor 14 via the first driver 15 and the second driver 16.

[0044] As a result, even with the second modification of the first embodiment, the upper limit of the output voltage range of the error amplifier is effectively limited, and the voltage input to the non-inverting input terminal of the PWM comparator 24 becomes lower as the overcurrent protection value SOCP decreases, thus the output voltage V of the switching power supply OUT This makes it possible to suppress the overshoot.

[0045] [2] Second embodiment Next, a second embodiment will be described. The difference between the second embodiment and the first embodiment is that while the first embodiment limited the upper limit of the output voltage of the error amplifier, the second embodiment changes the amplitude multiplier of the carrier signal for PWM control according to the overcurrent protection value SOCP, thereby controlling the output voltage V of the switching power supply. OUT The key point is to suppress the overshoot.

[0046] Figure 6 is an explanatory diagram of the second embodiment. In Figure 6, the same reference numerals are used for parts that are the same as those in Figure 1, and detailed explanations are provided below.

[0047] The PWM control unit 19B of the second embodiment includes a slope compensation signal generation unit 21, a current detection unit 22, a carrier amplitude magnification changing unit 50, a PWM comparator 24, a voltage divider circuit 25, and an error amplifier 27.

[0048] The slope compensation signal generation unit 21 generates ramp wave voltages with the same period as the control signals of the first switching transistor 13 and the second switching transistor 14, and outputs them to the summing circuit 23 as slope compensation signals.

[0049] The current detection unit 22 detects the output current of the switching power supply IC 10 flowing through the inductor L1 and outputs it to the adder circuit 23 as the original carrier signal for the PWM comparator 24.

[0050] The voltage divider circuit 25 divides the output voltage of the switching power supply IC 10, which is input from the feedback terminal FB of the switching power supply IC 10, and outputs it to the error amplifier 27.

[0051] The error amplifier 27 amplifies the voltage difference between the output voltage of the switching power supply IC 10, which has been divided by the voltage divider circuit 25, and the reference voltage Vref, and outputs it to the non-inverting input terminal of the PWM comparator 24.

[0052] The carrier amplitude multiplier changing unit (amplitude control unit) 50 includes an adder circuit 23 and a multiplier variable unit 51. The summing circuit 23 adds the slope compensation signal, which is the output signal of the slope compensation signal generation unit, and the original carrier signal, which is the output signal of the current detection unit 22, and outputs the resulting carrier signal used for PWM modulation to the input terminal of the variable magnification unit 51. By adding the slope compensation signal to the original carrier signal in this way, measures are taken to address subharmonic oscillation, which is characteristic of current-mode switching power supplies.

[0053] The variable magnification unit 51 changes the amplitude magnification of the carrier signal based on the overcurrent protection value SOCP and outputs it to the inverting input terminal of the PWM comparator 24. In other words, the variable magnification unit 51 controls the output voltage of the error amplifier 27 to decrease the difference between the output voltage of the error amplifier 27 and the voltage of the carrier signal by decreasing the magnification when the overcurrent protection value SOCP is large, and increasing the magnification when the overcurrent protection value SOCP is small.

[0054] Here, a specific example of the carrier amplitude magnification changing unit 50 will be described. Figure 7 is an explanatory diagram of a specific example of the carrier amplitude magnification changing unit. The adder circuit 23 of the carrier amplitude magnification changing unit 50 includes a P-channel MOS transistor TR31 whose source terminal is connected to the high-potential side power supply terminal VDD and whose gate terminal and drain terminal are connected; a P-channel MOS transistor TR32 whose source terminal is connected to the high-potential side power supply terminal VDD, whose gate terminal is connected to the gate terminal of the P-channel MOS transistor TR31, and whose drain terminal is connected to the output of the adder circuit 23; a first operational amplifier OP1 whose non-inverting input terminal is connected to the first input terminal IN1; an N-channel MOS transistor TR33 whose drain terminal is connected to the drain terminal of the P-channel MOS transistor TR31, whose gate terminal is connected to the output terminal of the first operational amplifier OP1, and whose source terminal is connected to the inverting input terminal of the first operational amplifier OP1; and a resistor R31 whose one end is connected to the source terminal of the N-channel MOS transistor TR33 and whose other end is grounded.

[0055] Furthermore, the adder circuit 23 of the carrier amplitude magnification changing unit 50 includes a P-channel MOS transistor TR41 whose source terminal is connected to the high-potential side power supply terminal VDD and whose gate terminal and drain terminal are connected; a P-channel MOS transistor TR42 whose drain terminal is connected to the high-potential side power supply terminal VDD, whose gate terminal is connected to the gate terminal of the P-channel MOS transistor TR41, and whose drain terminal is connected to the output of the adder circuit 23; a second operational amplifier OP2 whose non-inverting input terminal is connected to the second input terminal IN2; an N-channel MOS transistor TR43 whose drain terminal is connected to the drain terminal of the P-channel MOS transistor TR41, whose gate terminal is connected to the output terminal of the second operational amplifier OP2, and whose source terminal is connected to the inverting input terminal of the second operational amplifier OP2; and a resistor R32 whose one end is connected to the source terminal of the N-channel MOS transistor TR43 and whose other end is grounded.

[0056] The variable magnification unit 51 includes a current-voltage conversion resistor R50, one end of which is connected to the output of the summing circuit 23 and the other end of which is grounded; first switches SW1 to nth switches SWn, one end of which is connected to the output of the summing circuit 23; and first current-voltage conversion resistors R51 to R5n, one end of which is connected to the other end of each of the first switches SW1 to nth switches SWn and the other end of which is grounded. In this case, the first switch SW1 to the nth switch SWn are set to the ON state one or more times based on the overcurrent protection value SOCP, and the current-voltage conversion resistors connected to the ON switches among the first current-voltage conversion resistors R51 to R5n are connected in parallel with current-voltage conversion resistor R50, thereby effectively changing the resistance value of the current-voltage conversion resistors and changing the amplitude conversion ratio of the carrier signal.

[0057] As a result, according to the second embodiment, by changing the multiplier of the carrier signal according to the overcurrent protection value SOCP, the difference with the voltage of the carrier signal is reduced without changing the output voltage range of the error amplifier 27, so that the output voltage V of the switching power supply OUT This makes it possible to suppress the overshoot.

[0058] [3] Third embodiment Next, a third embodiment will be described. The difference between the third embodiment and the first embodiment is that, while the first embodiment statically limited the upper limit of the output voltage of the error amplifier according to the overcurrent protection value SOCP by changing the power supply voltage of the error amplifier 27 or by limiting the output voltage of the error amplifier 27 with a variable clamper, the third embodiment dynamically limits the output upper limit voltage of the switching power supply V by detecting the peak voltage of the carrier signal and based on the peak voltage. OUT The key point is to suppress the overshoot.

[0059] Figure 8 is an explanatory diagram of the third embodiment. In Figure 8, the same reference numerals are used for parts that are the same as those in Figure 1, and detailed explanations are provided below. The PWM control unit 19C of the third embodiment includes a slope compensation signal generation unit 21, a current detection unit 22, an adder circuit 23, a peak detection variable clamper 60, a PWM comparator 24, a voltage divider circuit 25, and an error amplifier 27.

[0060] The slope compensation signal generation unit 21 generates ramp wave voltages with the same period as the control signals of the first switching transistor 13 and the second switching transistor 14, and outputs them to the summing circuit 23 as slope compensation signals.

[0061] The current detection unit 22 detects the output current of the switching power supply IC 10 flowing through the inductor L1 and outputs it to the adder circuit 23 as the original carrier signal for the PWM comparator 24.

[0062] The summing circuit 23 adds the slope compensation signal output by the slope compensation signal generation unit and the original carrier signal output by the current detection unit 22, and outputs the resulting carrier signal for PWM modulation to the inverting input terminal of the PWM comparator 24 and the peak detection variable clamper 60. By adding the slope compensation signal to the original carrier signal in this way, measures are taken to address subharmonic oscillation, which is characteristic of current-mode switching power supplies.

[0063] The peak detection variable clamper 60 comprises a peak detection unit 61 and a variable clamper 62. The peak detection unit 61 detects the peak value of the carrier signal and outputs it to the variable clamper 62.

[0064] The variable clamper 62 effectively limits the output voltage range of the error amplifier 27 by using a clamp voltage that is the peak value of the carrier signal detected by the peak detection unit 61 plus a predetermined margin value α.

[0065] Here, we will describe specific examples and operations of the peak detection unit 61 and the variable clamper 62. Figure 9 shows a specific example and an explanatory diagram of the operation of a peak detection variable clamper. As shown in Figure 9(A), the peak detection unit 61 of the peak detection variable clamper 60 is configured as a peak hold circuit and includes an N-channel MOS transistor TR51 whose drain terminal is connected to the high-potential side power supply terminal VDD and whose gate terminal is connected to the input terminal IN of the peak detection variable clamper 60, a resistor R61 whose one end is connected to the source terminal of the N-channel MOS transistor TR51 and whose other end is grounded, and a peak hold capacitor PHC whose one end is connected to the source terminal of the N-channel MOS transistor TR51 and whose other end is grounded.

[0066] The variable clamper 62 includes a constant current source CS2, one end of which is connected to the high-potential side power supply terminal VDD and the other end of which is connected to the output terminal OUT of the peak detection variable clamper 60; a diode D1, whose anode terminal is connected to the output terminal OUT of the peak detection variable clamper 60; and a P-channel MOS transistor TR52, whose source terminal is connected to the cathode terminal of diode D1, whose gate terminal is connected to one end of the peak hold capacitor PHC, and whose drain terminal is grounded.

[0067] When a carrier signal is input to the input terminal IN of the peak detection variable clamper 60, the peak hold capacitor PHC is charged with a voltage that is lower than the carrier signal by the gate-source voltage of transistor TR51, and is discharged by resistor R61 when the carrier signal voltage drops.

[0068] As a result, the voltage at the source terminal of the P-channel MOS transistor TR52 of the variable clamper 62 is maintained near the voltage corresponding to the peak value of the carrier signal. As a result, the voltage at the anode terminal of diode D1, i.e., the voltage at the output terminal OUT of the peak detection variable clamper 60, becomes the peak voltage of the carrier signal plus the voltage α (= approximately 0.7V) representing the voltage drop across diode D1, as shown in Figure 9(B).

[0069] In other words, the maximum output voltage of the error amplifier 27 is clamped to the peak voltage of the carrier signal by a voltage α higher than the voltage drop across diode D1. Therefore, the upper limit of the output voltage range of the error amplifier is effectively limited, and regardless of the setting of the overcurrent protection value SOCP, the output voltage V of the switching power supply remains constant. OUT This makes it possible to suppress the overshoot.

[0070] [3.1] Modified form of the third embodiment Next, a modified example of the third embodiment will be described. Figure 10 shows a modified example and an explanatory diagram of the operation of a peak detection variable clamper. In Figure 10, the same reference numerals are used for parts that are the same as those in Figure 9. As shown in Figure 10(A), the peak detection unit 61A of the peak detection variable clamper 60A is configured as a peak hold circuit and includes an N-channel MOS transistor TR51 whose drain terminal is connected to the high-potential side power supply terminal VDD and whose gate terminal is connected to the input terminal IN of the peak detection variable clamper 60; a resistor R61 whose one end is connected to the source terminal of the N-channel MOS transistor TR51; an N-channel MOS transistor TR53 whose drain terminal is connected to the other end of the resistor R61 and whose source terminal is grounded; an inverter INV whose input terminal is connected to the output terminal of the PWM comparator 24 via the input terminal PWM-IN of the peak detection variable clamper 60 and whose output terminal is connected to the gate terminal of the P-channel MOS transistor TR53; and a peak hold capacitor PHC whose one end is connected to the source terminal of the N-channel MOS transistor TR51 and whose other end is grounded.

[0071] The variable clamper 62 includes a constant current source CS2, one end of which is connected to the high-potential side power supply terminal VDD and the other end of which is connected to the output terminal OUT of the peak detection variable clamper 60; a diode D1, whose anode terminal is connected to the output terminal OUT of the peak detection variable clamper 60; and a P-channel MOS transistor TR52, whose source terminal is connected to the cathode terminal of diode D1, whose gate terminal is connected to one end of the peak hold capacitor PHC, and whose drain terminal is grounded.

[0072] When a carrier signal is input to the input terminal IN of the peak detection variable clamper 60, the peak hold capacitor PHC is charged with a voltage that is lower than the carrier signal by the gate-source voltage of transistor TR51, and is discharged by resistor R61 and NMOS transistor TR53 when the carrier signal voltage drops.

[0073] In parallel with this, the inverter INV outputs a "L" level signal to the gate terminal of the N-channel MOS transistor TR53 while the output signal of the PWM comparator 24 is at a "H" level. As a result, N-channel MOS transistor TR53 is turned off during the period when the output signal of PWM comparator 24 is at the "H" level.

[0074] This blocks the discharge path of the peak hold capacitor PHC, suppresses the decrease in the hold voltage of the peak hold capacitor PHC, and makes it possible to extend the peak hold time.

[0075] Therefore, since the hold voltage can be prevented from falling below the carrier signal due to the discharge of the peak hold capacitor PHC, malfunction of the switching power supply device can be prevented. In this state, the voltage at the source terminal of P-channel MOS transistor TR52 of variable clamper 62 is maintained near the voltage corresponding to the peak value of the carrier signal.

[0076] As a result, the voltage at the anode terminal of diode D1, that is, the voltage at the output terminal OUT of peak detection variable clamper 60, becomes the voltage obtained by adding the voltage drop α (= about 0.7V) of diode D1 to the peak voltage of the carrier signal, as shown in FIG. 10(B).

[0077] That is, the maximum value of the output voltage of error amplifier 27 is clamped to a voltage higher by the voltage drop α of diode D1 than the peak voltage of the carrier signal. Therefore, regardless of the setting of the overcurrent protection value SOCP, the overshoot of the output voltage V OUT of the switching power supply can be suppressed.

[0078] [4] Effects of the Embodiment As described above, according to each embodiment, in a current mode control type switching power supply device, by limiting the output voltage of an error amplifier according to the peak value of a carrier signal for PWM, the output voltage V OUTThis suppresses overshoot and improves the power supply transient response. Furthermore, even in current-mode controlled switching power supplies where the overcurrent protection value can be arbitrarily set, the output voltage of the error amplifier is limited based on the overcurrent protection value, thereby controlling the output voltage V of the switching power supply. OUT This makes it possible to suppress overshoot and improve power supply transient response.

[0079] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0080] 10 Switching power supply ICs 12 diodes 13. First Switching Transistor 14. Second switching transistor 15. First Driver 16. Second Driver 17 Driver Control Unit 18 Variable overcurrent detection unit 19, 19A~19C PWM control unit 21 Slope Compensation Signal Generation Unit 22 Current detection unit 23 Adding Circuit 24 PWM Comparators 25 Voltage divider circuit 26 Variable voltage power supply for error amplifier 27, 27A Error Amplifier 31 Comparator 32 transistors 33. Voltage divider circuit 34 Variable resistor 35 fixed resistance 41 Variable Clamp 50 Carrier Amplitude Magnification Section 51. Variable Magnification Section 52 load 60 Peak Detection Variable Clamper 60A Peak Detection Variable Clamper 61, 61A Peak detection unit 62 Variable Clamp R50 Current-to-voltage conversion resistor CM1 First Comparator CM2 Second Comparator C Capacitor CS, CS1, CS2 Constant current source D1 diode EPS variable power supply IN input terminal INV Inverter LD load IN1 First Input Terminal L1 Inductor OUT output terminal PHC Peak Hold Capacitor PW External power supply R51 First current-to-voltage conversion resistor SOCP Overcurrent Protection Value SW1~SWn: Switch 1~n TR11, TR12, TR21, TR22 P-Channel MOS Transistors TR31, TR32, TR41, TR42 P-channel MOS transistors TR13, TR14, TR33, TR43 N-channel MOS transistors TR51, TR53 N-channel MOS transistors TR52 P-channel MOS transistor PE0 power supply PE1 power supply SW1 1st switch TR1, TR2, TR3 P-channel MOS transistors TR3 N-channel MOS transistor TR4 N-channel MOS transistor Vref1 Reference voltage VDD High-potential side power supply terminal VDD power terminal VOUT output voltage Vref Reference Voltage

Claims

1. A current-mode controlled switching power supply has an overcurrent protection function that shuts off the switching element when the peak value of the current flowing through the inductor exceeds a predetermined current limit value, and the overcurrent protection value used in the overcurrent protection function can be changed, An error amplifier that outputs an error voltage corresponding to the difference between the output voltage of the switching power supply and the reference voltage, A PWM control unit that performs PWM control by comparing the error voltage with the voltage of the carrier signal for PWM, A voltage limiting unit that, based on the overcurrent protection value, limits the output upper limit voltage of the error amplifier to be lower as the overcurrent protection value decreases, A switching power supply equipped with this device.

2. The voltage limiting unit controls the power supply voltage of the error amplifier to limit the upper limit output voltage of the error amplifier. A switching power supply device according to claim 1.

3. The error amplifier employs a multi-stage amplification configuration. The voltage limiting unit controls the power supply voltage of the output stage of the error amplifier to limit the upper limit voltage of the error amplifier's output. The switching power supply device according to claim 2.

4. The voltage limiting unit is configured as a clamping circuit that clamps the output voltage of the error amplifier at a predetermined voltage. A switching power supply device according to claim 1.

5. In a switching power supply, An error amplifier that outputs an error voltage corresponding to the difference between the output voltage of the switching power supply and the reference voltage, A PWM control unit that performs PWM control by comparing the error voltage with the voltage of the carrier signal for PWM, A voltage limiting unit detects the peak voltage of the carrier signal and limits the upper output voltage of the error amplifier based on the peak voltage, Equipped with, The voltage limiting unit includes a peak hold circuit that detects and holds the peak voltage of the carrier signal, A clamping circuit that clamps the output voltage of the error amplifier with a voltage obtained by adding a predetermined voltage to the peak voltage. Equipped with, The peak hold circuit comprises an N-channel MOS transistor whose gate terminal is connected to the input terminal, A peak hold capacitor connected to the source terminal of the aforementioned N-channel MOS transistor, A resistor connected in parallel with the aforementioned peak hold capacitor, Equipped with, When a carrier signal is input to the input terminal, the peak hold capacitor is charged, and when the voltage of the carrier signal decreases, it is discharged through the resistor. The peak hold circuit interrupts the discharge path through the resistor of the peak hold circuit when the output of the PWM control unit is at the "H" level. Switching power supply.

6. A current-mode controlled switching power supply has an overcurrent protection function that shuts off the switching element when the peak value of the current flowing through the inductor exceeds a predetermined current limit value, and the overcurrent protection value used in the overcurrent protection function can be changed, An error amplifier that outputs an error voltage corresponding to the difference between the output voltage of the switching power supply and the reference voltage, A PWM control unit that performs PWM control by comparing the error voltage with the voltage of the carrier signal for PWM, An amplitude control unit controls the amplitude of the carrier signal based on the overcurrent protection value, A switching power supply equipped with this device.

7. A control method for a switching power supply that is performed on a current-mode controlled switching power supply that has an overcurrent protection function that shuts off a switching element when the peak value of the current flowing through the inductor exceeds a predetermined current limit value, and on which the overcurrent protection value used in the overcurrent protection function can be changed, The process of outputting an error voltage corresponding to the difference between the output voltage of the switching power supply and the reference voltage, The process involves comparing the error voltage with the voltage of the carrier signal for PWM to perform PWM control, A process to limit the upper limit voltage of the error voltage to be lowered as the overcurrent protection value decreases, based on the overcurrent protection value, A control method for a switching power supply equipped with a power supply.

Images