Semiconductor memory devices and memory systems
The bridge chip with a controller manages data transfer based on size information, addressing inefficiencies in semiconductor memory devices by optimizing data-in and data-out operations, enhancing overall efficiency.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- KIOXIA CORP
- Filing Date
- 2022-06-21
- Publication Date
- 2026-06-22
AI Technical Summary
Existing semiconductor memory devices face inefficiencies in data transfer due to the lack of size information in command sequences, leading to prolonged data-in and data-out operations.
Incorporating a bridge chip with a controller that includes a command decoder, register, transfer circuit, mask circuit, and counter to manage data transfer based on size information, allowing precise timing control and efficient data handling.
Improves data transfer efficiency by ensuring data is transferred only as needed, reducing operation times and aligning with the toggle DDR standard without additional waiting periods.
Smart Images
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Abstract
Description
[Technical Field]
[0001] This embodiment relates to a semiconductor memory device and a memory system. [Background technology]
[0002] There is a semiconductor memory device that has a semiconductor integrated circuit called a bridge chip placed between a group of external terminals connected to an external controller (hereinafter referred to as the memory controller) and multiple memory chips. In this semiconductor memory device, data transfer between the memory controller and the multiple memory chips is performed via the bridge chip. [Prior art documents] [Patent Documents]
[0003] [Patent Document 1] Japanese Patent Publication No. 2008-158938 [Overview of the project] [Problems that the invention aims to solve]
[0004] One embodiment aims to provide a semiconductor memory device and memory system with high data transfer efficiency. [Means for solving the problem]
[0005] According to one embodiment, the semiconductor memory device comprises a first chip and a second chip. The second chip is connected to the first chip and is connectable to a first device. The second chip receives a first command sequence from the first device, which includes a command to transfer data to and from the first chip and size information, and starts controlling the data transfer to and from the first chip in accordance with the first command sequence. The second chip terminates the control of the data transfer at a timing corresponding to the size information. [Brief explanation of the drawing]
[0006] [Figure 1]A schematic diagram showing an example of the configuration of a memory system to which the semiconductor memory device according to the embodiment is applied. [Figure 2] A schematic diagram showing an example of the configuration of a memory chip according to the embodiment. [Figure 3] A timing chart showing an example of the waveform of a signal transferred during a data-in operation in a memory system according to an embodiment. [Figure 4] A timing chart showing an example of the waveform of a signal transferred during a data-out operation in a memory system according to an embodiment. [Figure 5] A flowchart illustrating an example of the operation of a bridge chip according to an embodiment when it receives a command sequence for data transfer. [Figure 6] A diagram showing an example of a method for transferring size information according to an embodiment. [Figure 7] A diagram showing another example of a method for transferring size information according to an embodiment. [Figure 8] A diagram showing yet another example of a method for transferring size information according to an embodiment. [Modes for carrying out the invention]
[0007] The semiconductor memory device and memory system according to the embodiments will be described in detail below with reference to the attached drawings. However, the present invention is not limited to these embodiments.
[0008] (Embodiment) Figure 1 is a schematic diagram showing an example of the configuration of a memory system SYS to which the semiconductor memory device 1 according to the embodiment is applied.
[0009] The memory system SYS includes a memory controller MC and a semiconductor storage device 1. The semiconductor storage device 1 comprises an external terminal group 10, a bridge chip BC, and a plurality of memory chips CP1-0 to CP1-3, CP2-0 to CP2-3.
[0010] Note that the memory controller MC is an example of a first device. Each of the memory chips CP1-0 to CP1-3 and CP2-0 to CP2-3 is an example of a first chip. The bridge chip BC is an example of a second chip.
[0011] The semiconductor memory device 1 can be implemented as an MCP (Multi Chip Package) in which the memory chips CP1-0 to CP1-3 and the memory chips CP2-0 to CP2-3 are stacked respectively. When the semiconductor memory device 1 is implemented as an MCP, in the semiconductor memory device 1, the periphery of the bridge chip BC and the plurality of memory chips CP1-0 to CP1-3, CP2-0 to CP2-3 may be sealed with a molding resin.
[0012] In FIG. 1, a configuration is illustrated in which four memory chips CP1-0 to CP1-3 are connected to the bridge chip BC via the channel CH1, and four memory chips CP2-0 to CP2-3 are connected to the bridge chip BC via the channel CH2. That is, the semiconductor memory device 1 can be configured as a multi-memory chip module including a plurality of (here, eight) memory chips CP1-0 to CP1-3, CP2-0 to CP2-3.
[0013] Each of the memory chips CP1-0 to CP1-3, CP2-0 to CP2-3 is a memory chip of a non-volatile memory such as a NAND type flash memory. Note that the number of memory chips CP included in the semiconductor memory device 1 is not limited to eight. Also, the number of channels connecting the bridge chip BC and the plurality of memory chips CP is not limited to two.
[0014] The semiconductor memory device 1 can be connected to the memory controller MC via a wired communication path. This wired communication path is denoted as the channel CH0. The channel CH0 is configured based on a predetermined standard. When each of the memory chips CP1-0 to CP1-3, CP2-0 to CP2-3 is a NAND type flash memory, the predetermined standard is, for example, the toggle DDR standard.
[0015] The bridge chip BC is electrically connected to a plurality (here, two) of channels CH1 and CH2. The memory chips CP1-0 to CP1-3 are connected to the bridge chip BC via channel CH1, and CP2-0 to CP2-3 are connected to the bridge chip BC via channel CH2. The memory chips CP1-0 to CP1-3 are connected to channel CH1 configured based on a predetermined standard. The memory chips CP2-0 to CP2-3 are connected to channel CH2 configured based on a predetermined standard. When each memory chip CP is a NAND-type flash memory, the predetermined standard is, for example, the toggle DDR standard. Hereinafter, it is assumed that each memory chip CP is a NAND-type flash memory and the predetermined standard is the toggle DDR standard.
[0016] Channel CH0 includes signal lines for transferring a chip enable signal CEn, a command latch enable signal CLE, an address latch signal ALE, a write enable signal WEn, a read enable signal RE / REn, a data strobe signal DQS / DQSn, a data signal DQ[7:0] having a predetermined bit width (here, 8 bits as an example), a ready / busy signal R / Bn_1, and a ready / busy signal R / Bn_2. Note that the "n" written at the end of the symbol representing a signal indicates that the signal operates in negative logic. Whether each signal operates in negative logic or positive logic can be arbitrarily designed.
[0017] The chip enable signal CEn is a signal that enables the memory chip CP to be accessed. The data strobe signals DQS / DQSn are signals that instruct the other device to capture the data transmitted by the data signal DQ[7:0]. The data strobe signals DQS / DQSn are differential signals composed of the data strobe signals DQS and DQSn. The command latch enable signal CLE is a signal that indicates that the data signal DQ[7:0] is a command. The address latch enable signal ALE is a signal that indicates that the data signal DQ[7:0] is an address. The write enable signal WEn is a signal that instructs the other device to capture the command or address transmitted by the data signal DQ[7:0]. The read enable signals RE / REn are signals that instruct the other device to output the data signal DQ[7:0]. The read enable signals RE / REn are differential signals composed of the read enable signal RE and the read enable signal REn. The ready-busy signals R / Bn_1 and R / Bn_2 indicate whether the system is in a ready state, waiting for a command to be received, or in a busy state, unable to execute a command even if one is received. Note that the configuration of the signal lines that transfer the ready-busy signals R / Bn included in channel CH0 is not limited to the example described above. For example, channel CH0 may have one signal line for transferring one ready-busy signal R / Bn generated from two ready-busy signals R / Bn connected to channel CH1, such as a wired OR connection.
[0018] Channels CH1 and CH2 can each transmit and receive the same set of signals as channel CH0. Specifically, channels CH1 and CH2 each have a signal line for transferring the chip enable signal CEn, a signal line for transferring the command latch enable signal CLE, a signal line for transferring the address latch signal ALE, a signal line for transferring the write enable signal WEn, a signal line for transferring the read enable signals RE / REn, a signal line for transferring the data strobe signals DQS / DQSn, a group of signal lines for transferring the data signal DQ[7:0], and a signal line for transferring the ready busy signal R / Bn.
[0019] The bridge chip BC comprises a first interface 101, two second interfaces 102, a controller 103, and a buffer memory 104.
[0020] The first interface 101 is a PHY circuit that transmits and receives electrical signals to and from the memory controller MC via channel CH0.
[0021] Of the two second interfaces 102, second interface 102-1 is a PHY circuit that transmits and receives electrical signals to and from four memory chips CP1-0 to CP1-3 via channel CH1. Of the two second interfaces 102, second interface 102-2 is a PHY circuit that transmits and receives electrical signals to and from four memory chips CP2-0 to CP2-3 via channel CH2.
[0022] The buffer memory 104 is a memory that temporarily stores data transferred between the memory controller MC and the memory chip CP. The buffer memory 104 may be composed of DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). However, the type of memory that constitutes the buffer memory 104 is not limited to these.
[0023] The controller 103 is positioned between the first interface 101 and the two second interfaces 102. The controller 103 uses a buffer memory 104 to control the exchange of information between the first interface 101 and the two second interfaces 102.
[0024] The controller 103 includes a command decoder 111, a transfer circuit 112, a register 113, a mask circuit 114, a counter 115, and an oscillator 116.
[0025] The command decoder 111 analyzes the command received from the memory controller MC via channel CH0. Based on the analysis results, the command decoder 111 can issue a command to the memory chip CP.
[0026] When the memory controller MC performs data transfer with the semiconductor memory device 1, it issues a command sequence to the bridge chip BC that includes a command to instruct the data transfer and address information. In this embodiment, the memory controller MC may add size information corresponding to the size of the data to be transferred to such a command sequence for data transfer. If the command decoder 111 contains size information in the command sequence for data transfer, it stores the size information in the register 113.
[0027] Register 113 is a memory that stores various information for controlling the operation of the bridge chip BC. In particular, in this embodiment, register 113 is used as a memory for storing size information. The size information received from the memory controller MC is stored in register 113 as size information 120.
[0028] The transfer circuit 112 includes a pipeline that transfers signals between the first interface 101 and the two second interfaces 102.
[0029] The mask circuit 114 masks the size information when a command sequence containing size information is transferred. This prevents the size information from being transferred to the memory chip CP.
[0030] The counter 115 is used to measure the amount (or size) of data being transferred during data transfer in accordance with the command sequence for data transfer. The controller 103 determines the timing of the end of the data transfer based on the size information 120 stored in the register 113 and the value of the counter 115.
[0031] Data transfer includes a data-in operation, which is the operation of inputting data into the memory chip CP, and a data-out operation, which is the operation of acquiring data from the memory chip CP.
[0032] During data-in operation, the bridge chip BC receives the data to be transferred from the memory controller MC as a data signal DQ[7:0], and the data strobe signals DQS / DQSn supplied from the memory controller MC are toggled. During the period when the data strobe signals DQS / DQSn are toggled, the transfer circuit 112 uses the data strobe signals DQS / DQSn as a drive signal to pass the data through the pipeline.
[0033] The data strobe signals DQS / DQSn supplied to the bridge chip BC are toggled only a number of times corresponding to the size of the data being transferred. On the other hand, the pipeline included in the transfer circuit 112 has one or more flip-flops. In order for all the data received from the memory controller MC to pass through the transfer circuit 112, the drive signal needs to be toggled a number of times equal to the size of the received data plus at least a number of times corresponding to the number of flip-flops in the transfer circuit 112. In other words, the number of times the data strobe signals DQS / DQSn supplied from the memory controller MC are toggled is insufficient to pass all the data to be transferred through the transfer circuit 112. When the toggling of the data strobe signals DQS / DQSn supplied from the memory controller MC is finished, some of the data to be transferred received from the memory controller MC remains in the pipeline without being transferred to the memory chip CP.
[0034] The controller 103 counts the amount (or size) of data to be transferred received from the memory controller MC using the counter 115, and determines the end of data reception from the memory controller MC based on the value of the counter 115 and the size information 120. When data reception from the memory controller MC is complete, the controller 103 uses the clock signal oscillated by the oscillator 116 as a drive signal for the transfer circuit 112, thereby transferring all remaining data in the pipeline to the memory chip CP. The process of transferring all remaining data in the transfer circuit 112 to the memory chip CP using the clock signal oscillated by the oscillator 116 is referred to as post-processing.
[0035] During data-out operation, the bridge chip BC receives a command sequence for data-out operation from the memory controller MC. After the command sequence for data-out operation, the bridge chip BC toggles the read-enable signal RE / REn supplied by the memory controller MC a number of times corresponding to the size of the data to be transferred.
[0036] In the bridge chip BC, the controller 103 autonomously starts toggling the read enable signal RE / REn to the memory chip CP before the memory controller MC starts toggling the read enable signal RE / REn. The memory chip CP starts outputting data in response to the start of the toggling of the read enable signal RE / REn supplied from the bridge chip BC, and also starts toggling the data strobe signal DQS / DQSn to the bridge chip BC. The memory chip CP generates the data strobe signal DQS / DQSn based on the read enable signal RE / REn supplied from the bridge chip BC, for example. In the bridge chip BC, the controller 103 captures the data received from the memory chip CP based on the data strobe signal DQS / DQSn, and sequentially stores the captured data in the buffer memory 104. The controller 103 then outputs the data sequentially stored in the buffer memory 104 to the memory controller MC in response to the read enable signal RE / REn supplied from the memory controller MC.
[0037] The bridge chip BC must toggle the read enable signal RE / REn to the memory chip CP at least a number of times corresponding to the size of the data desired by the memory controller MC. If the read enable signal RE / REn is toggled more times than the number of times corresponding to the size of the data desired by the memory controller MC, more data than the memory controller MC desires will be output from the memory chip CP, resulting in a longer time spent on data output operations.
[0038] The controller 103 uses a counter 115 to count the number of times the read enable signal RE / REn supplied to the memory chip CP is toggled. When the value of the counter 115 reaches a value corresponding to the size information 120, the controller 103 terminates the toggling of the read enable signal RE / REn supplied to the memory chip CP. This makes it possible to output only the data desired by the memory controller MC to the memory chip CP.
[0039] In this way, the controller 103 terminates control of data transfer at a timing corresponding to the size information. In the case of data-in operation, the control of data transfer referred to here is post-processing. In the case of data-out operation, the control of data transfer referred to here is the toggling of the read enable signal RE / REn supplied to the memory chip CP.
[0040] A comparison of the embodiment with other technologies will be described. Technologies compared with the embodiment will be referred to as comparative examples. According to the comparative examples, the command sequence for data transfer does not include size information.
[0041] In the comparative example, during a data-in operation, the bridge chip receives the data to be transferred after receiving a command sequence for the data-in operation from the memory controller. At this time, the bridge chip determines whether or not the reception of the data to be transferred is complete based on a change in a signal operated by the memory controller after the data reception is complete (e.g., chip enable signal CEn or command latch enable signal CLE).
[0042] In contrast, according to this embodiment, the command sequence for data-in operation issued by the memory controller MC may include size information. When the command sequence for data-in operation includes size information, the bridge chip BC determines the completion of data reception based on this size information. Therefore, it becomes possible to start post-processing without waiting for a change in the signal operated by the memory controller MC after data reception is complete. In other words, the total time required for data-in operation is shortened, and the efficiency of data-in operation is improved.
[0043] Furthermore, according to the comparative example, in the case of data-out operation, the bridge chip does not know the size of the data to be transferred. Therefore, the bridge chip toggles the read-enable signal RE / REn to the memory chip up to the maximum number of times determined by the memory chip's specifications (for example, the number of times corresponding to the page size). As a result, the bridge chip retrieves more data from the memory chip than the memory controller desires, and the total time spent on data-out operation increases.
[0044] In contrast, according to this embodiment, the command sequence for data-out operation issued by the memory controller MC may include size information. When the command sequence for data-out operation includes size information, the bridge chip BC determines the timing of the end of the toggle of the read-enable signal RE / REn based on the size information. Therefore, the bridge chip BC can acquire only the data desired by the memory controller MC from the memory chip CP, thereby reducing the total time spent on data-out operation.
[0045] In other words, according to the embodiment, the efficiency of data transfer is improved.
[0046] Furthermore, according to the embodiment, size information is transferred during the waiting time defined by the toggle DDR standard. Specifically, the memory chip CP prepares for data transfer in accordance with the command sequence for data transfer, and data transfer becomes possible after the completion of said preparation. Therefore, the toggle DDR standard stipulates that there must be a waiting period (postpone) of at least a predetermined time for preparation (referred to as the specified waiting period) between the end of command sequence transfer and the start of data transfer. Size information is transferred during the specified waiting period. Therefore, no additional time is required to transfer size information, and the transfer of size information does not degrade the efficiency of data transfer. Details such as the specified waiting period will be described later.
[0047] Figure 2 is a schematic diagram showing an example of the configuration of a memory chip CP according to an embodiment.
[0048] The memory chip CP comprises a memory cell array 201, a page buffer 202, and a data cache 203. The page buffer 202 and the data cache 203 are composed of, for example, SRAM (Static Random Access Memory). The page buffer 202 and the data cache 203 may also be composed of flip-flops.
[0049] Access to the memory cell array 201 includes writing (also called programming), reading, and erasing.
[0050] In this specification, the series of operations in which the memory chip CP receives data input from an external source and writes the input data to the memory cell array 201 is referred to as a write operation. The data input to the memory chip CP from an external source is also referred to as write data. The series of operations in which the memory chip CP reads data from the memory cell array 201 and outputs it to the outside is referred to as a read operation. The data output from the memory chip CP to the outside is also referred to as read data.
[0051] During a write operation, the memory chip CP receives the write data input from an external source into the data cache 203. The operation of inputting write data into the data cache 203 corresponds to the data-in operation described above. After the data-in operation, the memory chip CP transfers the write data received in the data cache 203 to the page buffer 202, and after the transfer is complete, writes the data from the page buffer 202 to the memory cell array 201. The operation of writing data from the page buffer 202 to the memory cell array 201 is also called a program operation.
[0052] In a read operation, the memory chip CP first transfers the read data from the memory cell array 201 to the page buffer 202. This transfer of read data from the memory cell array 201 to the page buffer 202 is also called a sense operation. The memory chip CP then transfers the read data stored in the page buffer 202 by the sense operation from the page buffer 202 to the data cache 203. Finally, the memory chip CP outputs the read data from the data cache 203 to the outside. This output of read data from the data cache 203 corresponds to the data-out operation described above.
[0053] The memory cell array 201 comprises multiple blocks. Data written to one block is erased collectively. Each block comprises multiple pages. A page is a storage area representing a unit of data write operation and data read operation on the memory cell array 201. The data cache 203 and page buffer 202 have a storage capacity of at least one page so that program and sense operations can be performed on the memory cell array 201 on a page-by-page basis. In other words, the maximum amount of data that can be transferred by a single command sequence is, in this case, the amount of one page (i.e., the page size).
[0054] Next, we will describe the signals that are transferred during various data transfers according to the embodiment.
[0055] Figure 3 is a timing chart showing an example of the waveforms of signals transferred during a data-in operation in the memory system SYS according to the embodiment. Here, as an example, the case in which a memory chip CP1 connected to channel CH1 is the target of the data-in operation is described. Figure 3 shows the waveforms of the chip enable signal CEn, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, data strobe signal DQS (one of the data strobe signals DQS / DQSn), and data signal DQ[7:0] in channels CH0 and CH1, while the waveforms of other signals are omitted.
[0056] First, the memory controller MC transitions the chip enable signal CEn for channel CH0 to the active state (L level) (S101). In response, the chip enable signal CEn for channel CH1 also transitions to the active state (L level) (S102).
[0057] Subsequently, the memory controller MC transfers a command sequence for data-in operation, including size information, to the bridge chip BC (S103). Specifically, the memory controller MC transfers the command C0 instructing the data-in operation, the address value ADD0 representing the access destination, and the data D0, which is size information, in this order as data signals DQ[7:0]. When transferring command C0, the memory controller MC maintains the command latch enable signal CLE in an active state (H level) and toggles the write enable signal WEn. When transferring the address value ADD0, the memory controller MC maintains the address latch enable signal ALE in an active state (H level) and toggles the write enable signal WEn. When transferring data D0, the memory controller MC toggles the write enable signal WEn. Note that when transferring data D0, the state of the command latch enable signal CLE and the address latch enable signal ALE is arbitrary, a so-called "Don't care" state. In the example shown in Figure 3, the address value ADD0 is transmitted as a 6-byte data signal DQ[7:0]. Note that the amount of information in the address value ADD0 is not limited to 6 bytes.
[0058] In the bridge chip BC, when size information is received from the memory controller MC, the controller 103 stores the received size information in register 113 (S104).
[0059] In the bridge chip BC, the controller 103 forwards the command sequence for data input operation received from the memory controller MC to the memory chip CP1 via the transfer circuit 112 (S105). However, the mask circuit 114 masks the size information included in the command sequence received from the memory controller MC. Therefore, the command sequence that does not include size information is forwarded from the bridge chip BC to the memory chip CP1.
[0060] In the toggle DDR standard, during data-in operation, there is a specified waiting period t between the completion of address value input and the start of operation of the data strobe signal DQS. ADL A waiting period of the above amount of time is required. The memory controller MC waits for a specified period t from the time t0 when the last byte of address value ADD0 is transferred. ADL The system waits, and at timing t1, when the waiting period is complete, it transitions the data strobe signal DQS to the L level (S106). Then, the memory controller MC transfers the write data as the data signal DQ[7:0] and toggles the data strobe signal DQS (S107).
[0061] In the bridge chip BC, when the reception of write data begins, the controller 103 starts measuring the amount (or size) of the received write data using the counter 115 (S108). The method for measuring the amount of received write data can be arbitrarily changed. For example, the controller 103 may measure the amount of data received as the data signal DQ[7:0]. Alternatively, the controller 103 may count the number of times the data strobe signal DQS supplied from the memory controller MC is toggled, and treat the number of times the data strobe signal DQS is toggled as a measure of the amount of received data.
[0062] In the bridge chip BC, the transfer circuit 112 waits for a specified period t from the time t2 when the last byte of address value ADD0 is transferred. ADL The device waits, and at timing t3, when the waiting period is complete, it transitions the data strobe signal DQS to the L level (S109). Then, the bridge chip BC transfers the write data as the data signal DQ[7:0] and toggles the data strobe signal DQS (S110).
[0063] The memory chip CP1 stores the data received from the bridge chip BC in the data cache 203.
[0064] In the bridge chip BC, once the memory controller MC has completed the transfer of the write data, the controller 103 determines that the reception of the write data is complete based on the size information 120 stored in the register 113 and the value of the counter 115 (S111). Then, the transfer circuit 112 performs post-processing (S112). That is, the transfer circuit 112 uses the clock signal oscillated by the oscillator 116 as a drive signal instead of the data strobe signal DQS supplied from the memory controller MC, thereby pushing (i.e., transferring) the write data remaining in the transfer circuit 112 to the memory chip CP1 (S112).
[0065] Once the memory controller MC has finished transferring the write data, it sends command C1 to the bridge chip BC instructing it to start program operation (S113). In the bridge chip BC, the transfer circuit 112 transfers command C1 received from the memory controller MC to the memory chip CP1 (S114).
[0066] The memory chip CP starts program operation in response to command C1.
[0067] Figure 4 is a timing chart showing an example of the waveforms of signals transferred during a data-out operation in the memory system SYS according to the embodiment. Here, as an example, the case in which a memory chip CP1 connected to channel CH1 is the target of the data-out operation will be described. Figure 4 shows the waveforms of the chip enable signal CEn, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, read enable signal REn from the read enable signals RE / REn, data strobe signal DQS from the data strobe signals DQS / DQSn, and data signal DQ[7:0] in channels CH0 and CH1, while the waveforms of other signals are omitted.
[0068] First, the memory controller MC transitions the chip enable signal CEn for channel CH0 to the active state (L level) (S201). In response, the chip enable signal CEn for channel CH1 also transitions to the active state (L level) (S202).
[0069] Subsequently, the memory controller MC transfers a command sequence for data-out operation, including size information, to the bridge chip BC (S203). Specifically, the memory controller MC transfers the command C2 instructing the data-out operation, the address value ADD1 representing the access destination, the command C3 instructing the start of preparation for the data-out operation, and the data D1, which is size information, in this order as data signals DQ[7:0]. When transferring commands C2 and C3, the memory controller MC maintains the command latch enable signal CLE in an active state (H level) and toggles the write enable signal WEn. When transferring the address value ADD1, the memory controller MC maintains the address latch enable signal ALE in an active state (H level) and toggles the write enable signal WEn. When transferring data D1, the memory controller MC toggles the write enable signal WEn. Note that when transferring data D1, the state of the command latch enable signal CLE and the address latch enable signal ALE is arbitrary.
[0070] In the bridge chip BC, when the command decoder 111 receives size information from the memory controller MC, it stores the received size information in register 113 (S204).
[0071] Furthermore, in the bridge chip BC, the transfer circuit 112 transfers the command sequence for data output operation received from the memory controller MC to the memory chip CP1 (S205). However, the mask circuit 114 masks the size information included in the command sequence received from the memory controller MC. Therefore, the command sequence that does not include size information is transferred from the bridge chip BC to the memory chip CP1.
[0072] In the toggle DDR standard, during data-out operation, there is a specified waiting period t between transferring command C3 and initiating the operation of the read-enable signal REn. WHR2 A waiting period of the above amount of time is required. The controller 103 of the bridge chip BC waits for a specified period t from the time t10 when command C3 was transferred. WHR2 The controller 103 then waits. At timing t11, when the waiting period is complete, the controller 103 autonomously transitions the read enable signal REn to the memory chip CP1 to the L level (S206). The controller 103 then acquires read data from the memory chip CP1 by toggling the read enable signal REn to the memory chip CP1 (S207).
[0073] When the read enable signal REn supplied by the bridge chip BC is toggled, the memory chip CP1 starts outputting read data that has been previously stored in the data cache 203 by a sense operation. The memory chip CP1 outputs the read data as a data signal DQ[7:0] and also outputs a data strobe signal DQS based on the read enable signal REn supplied by the bridge chip BC to the bridge chip BC. The controller 103 of the bridge chip BC takes the read data output as a data signal DQ[7:0] from the memory chip CP1 based on the data strobe signal DQS output from the memory chip CP1 and stores the taken read data in the buffer memory 104.
[0074] Furthermore, in the bridge chip BC, when the controller 103 starts toggling the read enable signal REn to the memory chip CP1, it starts measuring the number of times the read enable signal REn has been toggled using the counter 115 (S208).
[0075] The memory controller MC waits for a specified period t from the time t12 when command C3 was transferred. WHR2 Delay time t L Wait for the period including the delay time t. L This can be set to any value, as long as it allows sufficient time for the bridge chip BC to prepare to output the read data output from the memory chip CP1. Then, at timing t13 when the waiting period is complete, the memory controller MC transitions the read enable signal REn to the bridge chip BC to the L level (S209). Then, the memory controller MC obtains the read data from the bridge chip BC by toggling the read enable signal REn to the bridge chip BC (S210).
[0076] In the bridge chip BC, when the controller 103 starts toggling the read enable signal REn supplied from the memory controller MC, it begins outputting the read data stored in the buffer memory 104. The controller 103 outputs the read data as a data signal DQ[7:0] and also outputs a data strobe signal DQS based on the read enable signal REn supplied from the memory controller MC to the memory controller MC. The memory controller MC captures the read data output from the bridge chip BC as a data signal DQ[7:0] based on the data strobe signal DQS output from the bridge chip BC.
[0077] In the bridge chip BC, the controller 103 determines, based on the value of the counter 115 and the size information 120, whether the number of times the read enable signal REn to the memory chip CP1 has been toggled has reached a number corresponding to the size of the read data. When the number of times the read enable signal REn to the memory chip CP1 has been toggled has reached a number corresponding to the size of the read data, the controller 103 stops toggling the read enable signal REn to the memory chip CP1 (S211). This allows the controller 103 to stop toggling the read enable signal REn to the memory chip CP1 before the toggling of the read enable signal REn supplied by the memory controller MC is stopped. In other words, the controller 103 can determine the timing of the end of the read data transfer before the toggling of the read enable signal REn supplied by the memory controller MC is stopped.
[0078] Furthermore, the bridge chip BC can execute the processing of a command sequence received from the memory controller MC even if the command sequence does not contain size information.
[0079] For example, when the bridge chip BC receives a command sequence containing size information from the memory controller MC, it stores that size information in register 113. Subsequently, when the bridge chip BC receives a new command sequence from the memory controller MC that does not contain size information, it applies the size information 120 previously obtained and stored in register 113 when transferring the new command sequence. In this way, the bridge chip BC may be configured to use the size information 120 stored in register 113 once it has stored the size information included in a command sequence, until it obtains size information included in another command sequence.
[0080] Alternatively, the bridge chip BC may be configured to operate by assuming the maximum amount specified in the standard (e.g., page size) as the size of the data to be transferred when it receives a command sequence from the memory controller MC that does not contain size information.
[0081] In this embodiment, the bridge chip BC can operate in either a first mode or a second mode. In the first mode, the bridge chip BC uses size information previously obtained from a command sequence. In the second mode, if the bridge chip BC receives a command sequence that does not contain size information, it operates by considering the maximum amount specified in the standard (e.g., page size) as the size of the data to be transferred.
[0082] Figure 5 is a flowchart showing an example of the operation of the bridge chip BC according to the embodiment when it receives a command sequence for data transfer. In a certain state (for example, immediately after startup), the size information 120 of the maximum value (for example, page size) is stored in register 113.
[0083] When the reception of a command sequence for data transfer transmitted from the memory controller MC begins (S301), the controller 103 of the bridge chip BC determines whether the first mode is set as its operating mode (S302). The command sequence that has just been received is referred to as the target command sequence in the explanation of Figure 5.
[0084] If the first mode is not set as the operating mode (S302: No), in other words, if the second mode is set as the operating mode, the controller 103 stores size information indicating the page size in register 113 (S303). As a result, even if size information 120 is already stored in register 113, the value of said size information 120 will be overwritten with the value indicating the page size.
[0085] When the first mode is set as its own operation mode (S302: Yes), or after S303, the controller 103 determines whether size information is included in the target command sequence (S304).
[0086] When size information is included in the target command sequence (S304: Yes), the controller 103 stores this size information in the register 113 as size information 120 (S305). As a result, even if the size information 120 has already been stored in the register 113, the value of the size information 120 is overwritten with the value of the size information included in the target command sequence.
[0087] The controller 103 transfers the target command sequence with the size information masked to the memory chip CP (S306).
[0088] Then, the controller 103 determines whether the start timing of data transfer has arrived (S307).
[0089] For example, when the target command sequence is a command sequence for data-in operation, the timing when the last 1 byte of the address value ADD0 is transferred is the start timing of data transfer after the elapse of the specified waiting period t ADL For the above time. When the target command sequence is a command sequence for data-out operation, it is required to leave the above time after transferring the command C3. Therefore, the timing when the above time has elapsed from the timing t10 when the command C3 is transferred is the start timing of data transfer. WHR2 For the above time. When the target command sequence is a command sequence for data-out operation, it is required to leave the above time after transferring the command C3. Therefore, the timing when the above time has elapsed from the timing t10 when the command C3 is transferred is the start timing of data transfer. WHR2 For the above time. When the target command sequence is a command sequence for data-out operation, it is required to leave the above time after transferring the command C3. Therefore, the timing when the above time has elapsed from the timing t10 when the command C3 is transferred is the start timing of data transfer.
[0090] When the start timing of data transfer has not arrived (S307: No), the controller 103 executes the determination process of S307 again.
[0091] If the target command sequence does not contain size information (S304: No), the controller 103 determines whether the data transfer start timing has arrived, similar to the process in S307 (S308). If the data transfer start timing has not arrived (S308: No), the controller 103 executes the determination process in S304 again.
[0092] When the timing to start data transfer arrives (S307: Yes or S308: Yes), the controller 103 clears the value of the counter 115 (S309) and starts data transfer (S310).
[0093] The controller 103 measures the amount (or size) of data to be transferred using the counter 115 (S311). For example, in the case of data-in operation, the controller 103 measures the amount of data received from the memory controller MC as the data signal DQ[7:0]. Alternatively, the controller 103 may measure the number of times the data strobe signal DQS supplied from the memory controller MC is toggled as the amount of data transferred. In the case of data-out operation, the controller 103 measures the number of times the read-enable signal REn to the memory chip CP is toggled.
[0094] The controller 103 then determines whether the value of the counter 115 has reached the value corresponding to the size information 120 (S312). If the value of the counter 115 has not reached the value corresponding to the size information 120 (S312: No), the controller 103 executes the process in S311 again.
[0095] If the value of counter 115 reaches the value corresponding to size information 120 (S312: Yes), and the target command sequence is a command sequence for data input operation (S313: Yes), the controller 103 performs post-processing (S314). If the target command sequence is a command sequence for data output operation (S313: No), the controller 103 stops acquiring read data by stopping the toggling of the read enable signal REn to the memory chip CP (S315). After S314 or S315, the data transfer is completed (S316), and the controller 103 terminates processing related to the target command sequence.
[0096] In the explanation above, the size information included in the command sequence was transferred as the data signal DQ[7:0]. The state of other signals when the size information is transferred as the data signal DQ[7:0] can be arbitrarily set by the designer.
[0097] For example, as shown in Figure 6, when size information is transmitted as data signal DQ[7:0] (D2 in Figure 6), the command latch enable signal CLE and the address latch enable signal ALE may be in the "Don't care" state. This example is the same as the state shown in Figures 3 and 4.
[0098] Alternatively, as shown in Figure 7, when the size information is transferred as the data signal DQ[7:0] (D3 in Figure 7), both the command latch enable signal CLE and the address latch enable signal ALE may remain inactive (L level).
[0099] Alternatively, as shown in Figure 8, when the size information is transmitted as the data signal DQ[7:0] (D4 in Figure 8), the command latch enable signal CLE and the address latch enable signal ALE may both remain inactive (L level), the write enable signal WEn may not be toggled, and the data strobe signal DQS may be toggled.
[0100] As described above, according to the embodiment, when the bridge chip BC receives a command sequence containing size information from the memory controller MC, it starts controlling data transfer between the memory controller MC and the memory chip CP in accordance with the command sequence. The bridge chip BC then terminates the control of data transfer at a timing corresponding to the size information.
[0101] Therefore, the efficiency of data transfer improves.
[0102] Furthermore, according to the embodiment, when the bridge chip BC receives write data from the memory controller MC and performs a data-in operation for the write data, it measures the amount (or size) of the write data received from the memory controller MC. When the measured amount reaches the amount corresponding to the size information 120, the bridge chip BC performs post-processing.
[0103] Therefore, the bridge chip BC can begin post-processing without waiting for changes in signals operated by the memory controller MC (e.g., chip enable signal CEn or command latch enable signal CLE) after the reception of write data is complete. In other words, the total time required for the data-in operation is reduced, and the efficiency of the data-in operation is improved.
[0104] Furthermore, according to the embodiment, the bridge chip BC instructs the memory chip CP to output read data by toggling the read enable signal REn to the memory chip CP, obtains the read data from the memory chip CP, and transfers the read data to the memory controller MC. At this time, the bridge chip BC measures the number of times the read enable signal REn to the memory chip CP is toggled, and stops toggling the read enable signal REn to the memory chip CP when the measured number of toggles reaches the number corresponding to the size information 120.
[0105] Therefore, the bridge chip BC can obtain only the read data desired by the memory controller MC from the memory chip CP. In other words, the total time spent on data output operations can be reduced, and the efficiency of data output operations can be improved.
[0106] Furthermore, according to this embodiment, the bridge chip BC includes a register 113. When the bridge chip BC receives a command sequence containing size information, it stores the size information as size information 120 in the register 113. When the bridge chip BC receives a command sequence that does not contain size information, it terminates control of the data transfer at a timing corresponding to the size information 120 obtained from the previous command sequence and stored in the register 113.
[0107] Therefore, it becomes possible to reduce the frequency with which the memory controller MC transfers size information to the bridge chip BC.
[0108] Furthermore, according to the embodiment, the bridge chip BC is configured to receive size information during a predetermined waiting time provided between the start timing of command sequence transfer and the start timing of data transfer.
[0109] Therefore, the deterioration of data transfer efficiency due to the transfer of size information is prevented.
[0110] Furthermore, according to the embodiment, when the bridge chip BC receives a command sequence containing size information, it masks the size information and transfers the command sequence to the memory chip CP.
[0111] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]
[0112] 1 Semiconductor memory device, 10 External terminals, 101 First interface, 102 Second interface, 103 Controller, 104 Buffer memory, 111 Command decoder, 112 Transfer circuit, 113 Register, 114 Mask circuit, 115 Counter, 116 Oscillator, 120 Size information, 201 Memory cell array, 202 Page buffer, 203 Data cache, BC Bridge chip, CP Memory chip, MC Memory controller, SYS Memory system.
Claims
1. The first chip and, The system includes a second chip connected to the first chip and connectable to a first device, which receives a first command sequence from the first device including a command for data transfer to and from the first chip and size information, starts controlling the data transfer to and from the first chip in accordance with the first command sequence, and ends the control of the data transfer at a timing corresponding to the size information, The second chip is The system is configured to receive the aforementioned size information during the waiting period. The aforementioned waiting time is a standardized period from the end of the transfer of the first command sequence to the start of the data transfer. Semiconductor memory device.
2. The aforementioned data transfer is an operation in which first data is received from the first device and input into the first chip. The second chip comprises a pipeline for transferring the first data and an oscillator, measures the amount of the first data received from the first device, and after the measured amount of the first data reaches an amount corresponding to the size information, transfers the second data remaining in the pipeline from the first data to the first chip using a clock signal oscillated by the oscillator. The semiconductor memory device according to claim 1.
3. The data transfer described above involves instructing the first chip to output first data, supplying a read-enable signal to the first chip in a toggled manner, acquiring the first data from the first chip corresponding to the toggled read-enable signal, and transferring the first data to the first device. The second chip measures the number of times the read enable signal is toggled, and when the measured number of times the read enable signal is toggled reaches the number corresponding to the size information, it stops toggling the read enable signal. The semiconductor memory device according to claim 1.
4. The second chip is equipped with memory, After receiving the first command sequence, a second command sequence that does not include the size information is received. When the first command sequence is received, the size information is stored in the memory. When the second command sequence is received, control of the data transfer between the first device and the first chip is started in accordance with the second command sequence, and the control of the data transfer is terminated at a timing corresponding to the size information stored in the memory. The semiconductor memory device according to claim 1.
5. When the second chip receives the first command sequence, it masks the size information in the first command sequence and transfers the first command sequence with the size information masked to the first chip. The semiconductor memory device according to claim 1.
6. A semiconductor memory device according to any one of claims 1 to 5, The first apparatus and, A plurality of signal lines connecting the semiconductor memory device and the first device, A memory system equipped with the following features.