Wafer inspection and verification

Abstract

Wafer Inspection and Verification A method is provided comprising the step of acquiring a first reference image of a first wafer. The method comprises the step of acquiring a first image of the first wafer in a manufacturing state. The first wafer has a first verification structure. The method comprises the step of acquiring a first physical measurement when the first wafer is in a manufacturing state. The first physical measurement corresponds to the first verification structure. The method comprises the step of acquiring an electrical parameter measurement corresponding to the verification structure of the wafer received in a post-manufacturing state. The method comprises the step of calculating a physical parameter value based on the electrical parameter measurement. The method comprises the step of generating a verification response by comparing the physical parameter value with the first physical measurement.

Description

Technology Field

[0001] The present invention relates to a wafer fabrication process, and more specifically, to wafer inspection and verification. Background Technology

[0002] A wafer manufacturing process may include the step of forming layers of various materials on a wafer to create a plurality of electronic circuits on the wafer (e.g., a silicon wafer). The wafer may be separated into a set of dies, and each set of dies may be integrated into various electronic devices. means of solving the problem

[0003] According to embodiments of the present invention, a method is provided, which may include the step of acquiring a first reference image of a first wafer. The method may include the step of acquiring a first reference image of the first wafer in a fabrication state. In a fabrication state, the first wafer may have a number of fabrication layers less than a threshold number. The first wafer may have a first verification structure. The method may include the step of acquiring a first physical measurement when the first wafer is in a fabrication state. The first physical measurement may correspond to the first verification structure. The method may include the step of determining whether the first image matches the first reference image by comparing the first image and the first reference image at a first time. The method may include the step of acquiring an electrical parameter measurement at a second time following the first time. The electrical parameter measurement described above may correspond to a verification structure of a wafer received in a post-fabrication state. In a post-fabrication state, the received wafer may have a second number of fabrication layers equal to the threshold number. The method may include a step of calculating a physical parameter value based on the electrical parameter measurement. The method may include a step of generating a verification response by comparing the physical parameter value with the first physical measurement.

[0004] System and computer program products corresponding to the above method are also included herein.

[0005] According to embodiments of the present invention, a method is provided, wherein the method may include the step of obtaining a first physical measurement. The first physical measurement may correspond to a first verification structure of a first wafer in a manufacturing state. In a manufacturing state, the first wafer may have a number of manufacturing layers less than a threshold number. The method may include the step of obtaining an electrical parameter measurement. The electrical parameter measurement may correspond to a verification structure of a wafer received in a post-manufacturing state. In a post-manufacturing state, the received wafer may have a second number of manufacturing layers equal to the threshold number. The method may include the step of calculating a physical parameter value based on the electrical parameter measurement. The method may include the step of generating a verification response by comparing the physical parameter value with the first physical measurement.

[0006] Embodiments of the present invention may be exemplified as a device having a wafer. The wafer may have a first verification structure in a first region of the wafer. The first verification structure may include a first target component. The first verification structure may have a first measurable electrical parameter. The first measurable electrical parameter may correspond to a first physical characteristic of the first target component.

[0007] The above summary is not intended to describe each of the illustrated embodiments or all embodiments of the present invention. Brief explanation of the drawing

[0008] The drawings included in this application are incorporated into and form part of the specification. They serve to illustrate embodiments of the invention and, together with the description, explain the principles of the invention. The drawings are merely examples of specific embodiments and do not limit the invention.

[0009] FIG. 1 illustrates an example computing environment having a wafer verification system according to embodiments of the present invention.

[0010] FIG. 2 illustrates a flowchart of an exemplary method for performing wafer inspection and verification according to embodiments of the present invention.

[0011] FIG. 3a illustrates a plan view of an exemplary wafer according to embodiments of the present invention.

[0012] FIG. 3b illustrates a plan view of an exemplary die of the wafer of FIG. 3a and a corresponding reference image according to embodiments of the present invention, each having a first manufacturing process layer.

[0013] FIG. 3c illustrates the exemplary die and the corresponding reference image according to embodiments of the present invention, each having the first manufacturing process layer and the second manufacturing process layer.

[0014] FIG. 3d illustrates a cross-sectional view of an exemplary target component in the wafer region of FIG. 3A according to embodiments of the present invention.

[0015] FIG. 3e illustrates a cross-sectional view of an exemplary verification structure including the target component of FIG. 3d according to embodiments of the present invention.

[0016] FIG. 3f illustrates a cross-sectional view of an exemplary target component in the wafer region of FIG. 3a according to embodiments of the present invention.

[0017] FIG. 3g illustrates a plan view of an exemplary verification structure including the target component of FIG. 3f according to embodiments of the present invention.

[0018] FIG. 3h illustrates a cross-sectional view of an exemplary target component in the region of the wafer of FIG. 3a according to embodiments of the present invention.

[0019] FIG. 3i illustrates a plan view of an exemplary verification structure including the target component of FIG. 3h according to embodiments of the present invention.

[0020] FIG. 4 illustrates the representative major components of a computer system that can be used according to embodiments of the present invention.

[0021] FIG. 5 illustrates a cloud computing environment according to embodiments of the present invention.

[0022] FIG. 6 illustrates abstraction model layers according to embodiments of the present invention.

[0023] The present invention may be adapted into various modifications and alternative forms, but specific details are illustrated by example in the drawings and will be described in detail. However, it should be understood that the invention is not intended to be limited to the specific embodiments described. On the contrary, the intention is to include all modifications, equivalents, and alternatives that fall within the spirit and scope of the invention. Specific details for implementing the invention

[0024] Embodiments of the present invention relate to wafer manufacturing, and more specific embodiments relate to wafer inspection and verification. Although the present invention is not necessarily limited to these applications, various embodiments of the present invention can be understood through the discussion of various examples using this context.

[0025] A wafer manufacturing process may include the step of forming layers of various materials on a wafer (e.g., silicon wafer) to create multiple electronic circuits on the wafer. Such layers may be formed according to a design plan that includes detailed specifications for each layer of the wafer (e.g., size, shape, location, and / or material composition). In some cases, a designing entity may submit such a design plan to a manufacturing entity for production. Such submission may result in one or more security risks. For example, a malicious actor within the manufacturing entity could potentially modify the design plan to omit functions or add functions to one or more electronic circuits. Such modifications could cause damage, failure, and / or destruction to the electronic circuits and / or devices subsequently containing the electronic circuits. Therefore, the designing entity must have effective means to verify that each wafer has been manufactured according to the detailed specifications.

[0026] Obtaining such verification can present difficulties. For example, circuit designs may include many layers and functions where malicious design modifications can be difficult to detect during wafer inspection. Furthermore, in some cases, a malicious actor may attempt to bypass the inspection process by replacing a genuine wafer that has passed inspection with a modified or non-genuine wafer.

[0027] To address these difficulties and other challenges, embodiments of the present invention include a wafer verification system. In some embodiments, the wafer verification system may perform layer-by-layer inspection of the wafer during manufacturing. In some embodiments, after such layer-by-layer inspection, the wafer verification system may confirm that the finished wafer is a wafer that has undergone layer-by-layer inspection during manufacturing. More specifically, in some embodiments, to perform layer-by-layer inspection, the wafer verification system may acquire a set of images of the wafer in the manufacturing state. The images may include manufacturing layers formed on the wafer according to one or more pattern transfer processes. In these embodiments, the wafer verification system may confirm that one or more layers of the wafer have been formed according to predetermined specifications by comparing the set of images with a set of reference images. In some embodiments, the wafer verification system may acquire physical measurements corresponding to the verification structure of the wafer while the wafer is in the manufacturing state. In these embodiments, the wafer verification system may confirm that the received and finished wafer is identical to the wafer for which the physical measurements were acquired. In some embodiments, the wafer verification system may perform such verification by comparing a physical measurement with a calculated physical parameter value corresponding to a verification structure. In some embodiments, the wafer verification system may perform such verification by comparing the plurality of physical measurements with a plurality of calculated physical parameter values ​​corresponding to each verification structure of the wafer.

[0028] Accordingly, embodiments of the present invention can perform thorough and accurate inspection and / or verification of a wafer. By comparing images of multiple manufacturing layers of a wafer, embodiments of the present invention can identify deviations from predetermined wafer specifications at the layer-by-layer level. Accordingly, embodiments of the present invention can increase the possibility of detecting design modifications to the wafer. Embodiments of the present invention capable of verifying / certifying a wafer based on measurements of one or more verification structures can provide several advantages. For example, a verification structure of a first wafer can provide unique physical measurements of the first wafer. Accordingly, embodiments of the present invention can verify the first wafer and / or distinguish the first wafer from another second wafer based on these unique physical measurements. Additionally, embodiments of the present invention may include multiple verification structures at multiple wafer locations, and each verification structure can provide such unique physical measurements. Accordingly, said verification structures, locations, and / or the unique physical measurements they can provide can effectively serve as a fingerprint of the wafer. Embodiments of the present invention can identify and / or distinguish the wafer based on such fingerprints. Accordingly, embodiments of the present invention can help detect cases where a modified or unauthenticated wafer is provided as a genuine wafer.

[0029] Returning to the drawings, FIG. 1 illustrates a computing environment (100) comprising one or more of a wafer verification system (105), a patterning device (125), a measuring device (135), an image capture device (140), a computing device (145) and / or a network (150). In some embodiments, at least one wafer verification system (105), a patterning device (125), a measuring device (135), an image capture device (140) and / or a computing device (145) may exchange at least one data with each other through at least one network (150). Each of one or more of the wafer verification system (105), patterning device (125), measurement device (135), image capture device (140), computing device (145) and / or network (150) may include a computer system such as the computer system (401) discussed in relation to FIG. 4.

[0030] In some embodiments, the wafer verification system (105) may be included in software installed in at least one computer system among the patterning device (125), the measurement device (135), the image capture device (140), and / or the computing device (145). For example, in some embodiments, the wafer verification system (105) may be included as a plug-in-in software component of the software installed in the patterning device (125). The wafer verification system (105) may include program instructions implemented by a processor, such as a processor of the computing device (145), to perform one or more operations discussed in relation to FIG. 2.

[0031] In some embodiments, the wafer verification system (105) may include one or more modules such as a data manager (110), an image analyzer (115), and / or a device manager (120). In some embodiments, the data manager (110), the image analyzer (115), and / or the device manager (120) may be integrated into a single module. In some embodiments, the data manager (110) may initiate the acquisition, interpretation, analysis, storage, and / or storage of data such as reference data for the wafer (130). In some embodiments, the image analyzer (115) may acquire and analyze images of the wafer (130). In some embodiments, the image analyzer (115) may include a neural network and / or a set of image analysis software to identify matches between images of the wafer (130) and reference images of the wafer (130). In some embodiments, the device manager (120) may transmit commands to one or more patterning devices (125), measurement devices (135), image capture devices (140) and / or computing devices (145). For example, in some embodiments, the device manager (120) may transmit commands to the measurement device (135) to obtain measurements of electrical parameters of a received wafer. In some embodiments, one or more of the data manager (110), image analyzer (115) and / or device manager (120) may include program instructions implemented by a processor, such as the processor of the computing device (145), to perform one or more operations discussed in relation to FIG. 2. For example, in some embodiments, the data manager (110) may include program instructions for performing operations (205 and 240 to 255, FIG. 2).In some embodiments, the image analyzer (115) may include program instructions for performing operations (210 and 220 to 230, FIG. 2). In some embodiments, the device manager (120) may include program instructions for performing operations (215 and 235, FIG. 2).

[0032] In some embodiments, the one or more patterning devices (125) may include machines and / or sets of equipment configured to perform processes such as photolithography, etching, deposition, etc., to form manufacturing layers on a wafer (130). The wafer (130) may mean a substrate on which a set of electronic circuits can be formed. In some embodiments, the wafer (130) may be composed of a semiconductor material such as silicon.

[0033] In some embodiments, one or more measuring devices (135) may include machines and / or sets of equipment configured to obtain physical measurements and / or electrical parameter measurements of the wafer (130). For example, in some embodiments, one or more measuring devices (135) may include a precision ellipsometer configured to measure the thickness of a material formed on the wafer (130). In some embodiments, one or more measuring devices (135) may be configured to measure registration accuracy between features printed at different manufacturing levels or the same manufacturing level on the wafer (130). In some embodiments, one or more measuring devices (135) may include a scanning electron microscope configured to measure dimensions related to the wafer (130). In some embodiments, one or more measuring devices may include a precision multimeter configured to obtain electrical parameter measurements of the wafer (130).

[0034] In some embodiments, one or more image capture devices (140) may include a camera, a scanning electron microscope, etc. One or more image capture devices may be configured to capture a set of images of the wafer (130). In some embodiments, the set of images may include images of one or more regions of the wafer (130) and / or manufacturing layers. In some embodiments, the patterning device (125), the measurement device (135), and / or the image capture device (140) may be integrated into a single device.

[0035] In some embodiments, one or more computing devices (145) may include a computer or a server. For example, in some embodiments, one or more computing devices (145) may include a computer of an entity, such as a manufacturing facility, that operates the patterning device (125). One or more computing devices (145) may be configured to store and / or process data, such as one or more thresholds, measurements, and / or images of the wafer (130). In some embodiments, the network (180) may be a wide area network (WAN), a local area network (LAN), the Internet, or an intranet. In some embodiments, the network (180) may be substantially similar or identical to the cloud computing environment (50) discussed in relation to FIG. 5.

[0036] FIG. 2 illustrates a flowchart of an exemplary method (200) for performing wafer inspection and verification according to an embodiment of the present invention. The method (200) may be performed by a wafer verification system such as the wafer verification system (105) discussed in relation to FIG. 1.

[0037] In operation (205), the wafer verification system may obtain reference data for one or more wafers. The reference data may include information regarding the manufacture of one or more wafers. For example, in some embodiments, the reference data may include design specifications for manufacturing one or more wafers. Such specifications may include information such as sizes, shapes, patterns, locations, orientations, and / or materials related to features such as trenches, leads, conductors, insulators, pillars, and / or layers for forming electronic circuits on one or more wafers. In some embodiments, the reference data may include a set of reference images (e.g., digital photographs, scanning electron microscope images, etc.). In some embodiments, the set of reference images may include images from an electronic model of the wafer (e.g., a set of computer-aided design drawings of the wafer). A set of reference images can represent the appropriate manufacturing characteristics of the wafer, that is, the characteristics of the wafer manufactured according to the wafer's design specifications. For example, the reference images can exemplify characteristics such as the appropriate sizes, shapes, patterns, locations, orientations, and / or materials of features such as trenches, leads, conductors, insulators, fillers, and / or layers on the wafer. As discussed in more detail below, a wafer verification system may employ such reference images to identify deviations from design specifications that occur during wafer manufacturing.

[0038] In some embodiments, the set of reference images may include images of a wafer following one or more pattern transfer processes. For example, in some embodiments, design specifications may include a plurality of pattern transfer processes (e.g., etching, deposition, and / or doping processes) to form a threshold number of fabrication layers on the wafer. In this example, the pattern transfer processes may form a total of 50 fabrication layers on the wafer. In this example, the set of reference images may include one or more images of the 50 fabrication layers formed in each pattern transfer process. In one example, the set of reference images may include images of a first wafer layer formed after etching the wafer and images of a second wafer layer formed after subsequently depositing material on the wafer. In some embodiments, the set of reference images may include one or more images for each fabrication layer of the wafer. In some embodiments, the set of reference images may include one or more images of predetermined manufacturing layers of a wafer (e.g., images of the first, third, and seventh manufacturing layers of a wafer having a total of 10 manufacturing layers). In some embodiments, the set of reference images may include images of the entire surface of the wafer and / or images of predetermined regions of the wafer. In some embodiments, such predetermined manufacturing layers and / or predetermined regions may be selected by an entity, such as a programmer or operator of a wafer verification system, or by the wafer verification system itself (e.g., the wafer verification system may randomly select manufacturing layers and / or regions for which images may be included in the set of reference images).

[0039] In operation (210), the wafer verification system may acquire one or more images of the wafer in the manufacturing state. When the wafer is in the manufacturing state, the wafer may have fewer than a threshold number of layers. In some embodiments, the threshold number of layers may be the total number of manufacturing layers associated with the finished wafer (e.g., a wafer in which all pattern transfer processes have been completed). For example, in some embodiments, multiple pattern transfer processes may form a total of 25 manufacturing layers or manufacturing levels on the wafer. In this example, when the wafer has a first manufacturing layer, a second manufacturing layer, a third manufacturing layer, etc., the wafer is in the manufacturing state until all 25 manufacturing layers are formed on the wafer. In some embodiments, the wafer may be in the post-manufacturing state when the wafer has a number of manufacturing layers equal to the threshold number of manufacturing layers associated with the finished wafer. Thus, in the above example, the wafer may be in the post-manufacturing state when the wafer has a total of 25 manufacturing layers.

[0040] In some embodiments, the operation (210) may include a wafer verification system that acquires a set of images of one or more manufacturing layers of a wafer. The set of images may illustrate actual manufacturing characteristics of the wafer. For example, the images may show characteristics such as the actual sizes, shapes, patterns, locations, orientations, and / or materials of features such as trenches, leads, conductors, insulators, fillers, and / or layers of the wafer. Such characteristics may or may not match design specifications for the wafer. In some embodiments, the set of images may include images of the entire surface of the wafer and / or images of predetermined regions of the wafer. In some embodiments, such predetermined manufacturing layers and / or predetermined regions may be selected by an entity such as a programmer or operator of the wafer verification system or by the wafer verification system itself (for example, the wafer verification system may randomly select manufacturing layers and / or regions for which images may be included in the set of images).

[0041] In some embodiments, the operation (210) may include a wafer verification system that obtains a set of images from an image capture device (e.g., image capture device (140), FIG. 1). In some embodiments, the operation (210) may include a wafer verification system that commands one or more images to be captured. For example, in some embodiments, the wafer verification system may command a digital camera to capture an image of a first region of the wafer and a scanning electron microscope to capture images of ten other regions of the wafer. In some embodiments, the wafer verification system may obtain a set of images from a patterning device (e.g., patterning device (125), FIG. 1). In some embodiments, the wafer verification system may obtain a set of images stored in a computing device (e.g., computing device (145), FIG. 1).

[0042] In operation (215), the wafer verification system may acquire physical measurement data of the wafer in the manufacturing state. The physical measurement data may include measurements of at least one physical characteristic of the wafer. In some embodiments, such physical characteristics may include characteristics that are visually recognizable, such as distance (e.g., length, width, height, and / or thickness) when the wafer is in the manufacturing state. For example, in some embodiments, when the wafer is in the manufacturing state, the width of a conductor formed on a manufacturing layer may be visually recognizable, but the conductor may become less visible (e.g., invisible) in the post-manufacturing state because it is obstructed by subsequent manufacturing layers. Therefore, in some embodiments, an optical measurement device may be able to measure the width of the conductor when the wafer is in the manufacturing state, but it may be impossible to measure such width when the wafer is in the post-manufacturing state due to reduced visibility of the conductor.

[0043] In some embodiments, the physical properties being measured may correspond to a target component of a verification structure. The verification structure may refer to a wafer structure in a post-manufacturing state. Such a verification structure may be configured to provide measurable electrical parameters corresponding to the physical properties of the target component. For example, continuing the example, the verification structure may include a conductor formed on the fifth manufacturing layer of the wafer and a pair of conductive probe pads formed on the 50th, final manufacturing layer of the wafer. In this example, the conductor may be the target component of the verification structure. As the target component, the conductor may have a physical property (width in this example) corresponding to a measurable electrical parameter (e.g., resistance). The measurable electrical parameter may be measured across the pair of conductive probe pads formed on the 50th manufacturing layer of the wafer (this aspect is further discussed in relation to the operation (235) described below). Continuing with this example, the operation (215) may include a wafer verification system that obtains a width measurement of the conductor after the conductor is formed on the fifth manufacturing layer and before the visibility of the conductor is blocked by a subsequent manufacturing layer.

[0044] In some embodiments, operative features of electronic circuits formed on a wafer (e.g., trenches, leads, conductors, insulators, and / or fillers) may be components of a verification structure (e.g., target components). In these embodiments, the verification structures may be integrated into the design of the electronic circuit. In some embodiments, the verification structures may be independent of the design of the electronic circuit and may function solely for verification as discussed in the present invention. For example, in some embodiments, the verification structures may not contribute to the operational performance of the computer chip formed on the wafer, but rather may perform only the function of verifying whether the wafer is genuine when the wafer is in a post-manufacturing state.

[0045] In some embodiments, the operation (215) may include a wafer verification system that obtains physical measurement data from a measurement device (e.g., measurement device (135), FIG. 1). In some embodiments, the operation (215) may include a wafer verification system that commands one or more measurement devices to obtain physical measurement data from a wafer. In some embodiments, an image capture device (e.g., image capture device (140), FIG. 1) and / or a patterning device (e.g., patterning device (135), FIG. 1) may be configured to obtain physical measurement data from a wafer. In these embodiments, the operation (215) may include a wafer verification system that obtains physical measurement data from an image capture device and / or a patterning device. In some embodiments, the operation (215) may include a wafer verification system that commands one or more image capture devices and / or patterning devices to obtain physical measurement data from a wafer.

[0046] By acquiring physical specific data in operation (215), the wafer verification system can acquire a set of unique physical measurements of the wafer from one or more manufacturing layers of the wafer. For example, in some embodiments, operation (215) may include a wafer verification system that acquires a first physical measurement of a first target component on a second manufacturing layer of the wafer. In this example, the first physical measurement may be measured with precision (e.g., the first physical measurement may be measured in nanometers). Thus, the first physical measurement may be unique in that it is unlikely that other wafers will provide the same physical measurement for each corresponding first target component. Continuing this example, operation (215) may further include a wafer verification system that acquires a second physical measurement of a second target component on a tenth manufacturing layer of the wafer. Thus, in this example, the set of physical measurements (i.e., the first physical measurement together with the second physical measurement) may be unique in that it is unlikely that other wafers will provide the same set of physical measurements for each first target component and the second target component. Accordingly, in some embodiments, the physical measurement data obtained in operation (215) can effectively function as a fingerprint that facilitates the identification and / or distinction of the wafer. Such identification and / or distinction is discussed further below in relation to operation (245).

[0047] In operation (220), the wafer verification system may compare one or more images of the wafer obtained in operation (210) with one or more corresponding reference images of the wafer obtained in operation (205) and determine whether one or more matches exist. In some embodiments, the wafer verification system may determine that the image of the wafer matches the corresponding reference image of the wafer when the characteristics of the image have a threshold degree of similarity with the characteristics of the corresponding reference image. For example, in some embodiments, the wafer verification system may determine a match when the exemplified sizes, shapes, quantities, patterns, locations, directions, and / or materials of features such as trenches, leads, conductors, insulators, fillers, and / or layers of the wafer have a threshold degree of similarity between the image of the wafer and the corresponding reference image of the wafer. In a more specific example, the wafer verification system may determine that the first orientation angle of a conductor exemplified in an image of the wafer matches the second orientation angle of a corresponding conductor exemplified in a reference image of the wafer when the percentage error between the first orientation angle and the second orientation angle does not exceed a threshold of 1%. In some embodiments, such threshold similarity may be selected by an entity, such as a programmer or operator of the wafer verification system, or by the wafer verification system itself. In some embodiments, operation (220) may include a wafer verification system that uses a set of image analysis techniques and / or neural networks to identify one or more matches between one or more images of the wafer and one or more reference images of the wafer. If the wafer verification system determines that one or more images of the wafer match one or more corresponding reference images of the wafer, the wafer verification system may proceed to operation (230).Alternatively, if the wafer verification system determines that one or more images of the wafer do not match one or more corresponding reference images of the wafer, the wafer verification system may proceed to operation (225).

[0048] In operation (225), the wafer verification system may initiate a notification indicating that one or more images of the wafer obtained in operation (210) do not match one or more corresponding reference images of the wafer obtained in operation (205). In some embodiments, the non-matching images may indicate that the wafer contains malicious design modifications. In some embodiments, such a notification may indicate that one or more manufacturing layers of the wafer are not formed according to predetermined specifications for the wafer. In some embodiments, operation (225) may include a wafer verification system that generates an alphabet-numeric text message, an audible alarm, and / or a visual alarm. In some embodiments, operation (225) may include a wafer verification system that issues a command to a device, such as a computing device, that generates and / or issues such text messages and / or alarms.

[0049] In operation (230), the wafer verification system may determine whether a threshold number of manufacturing layers have been formed on the wafer. The threshold number of manufacturing layers may be the total number of manufacturing layers associated with a finished wafer (e.g., a wafer that has completed all pattern transfer processes). In some embodiments, operation (230) may include a wafer verification system that analyzes reference data and / or images of the wafer to determine whether the wafer is in a manufacturing state. For example, in some embodiments, the wafer verification system may determine whether the wafer is in a manufacturing state by identifying a difference between images of the wafer in a post-manufacturing state and reference images of the wafer. In this example, such a difference may indicate that one or more manufacturing layers must be formed on the wafer before the wafer has a threshold number of manufacturing layers. In some embodiments, operation (230) may include a wafer verification system that obtains information about additional layers to be formed on the wafer from a device such as a patterning device (e.g., patterning device (125), FIG. 1) or a computing device (e.g., computing device (145), FIG. 1). Based on such information, the wafer verification system can determine whether a critical number of manufacturing layers are formed on the wafer. If the wafer verification system determines that a critical number of manufacturing layers are formed on the wafer, the wafer verification system can proceed to operation (235). Alternatively, if the wafer verification system determines that a critical number of manufacturing layers are not formed on the wafer, the wafer verification system can proceed to operation (210).

[0050] In operation (235), the wafer verification system may obtain a set of electrical parameter measurements for the received wafer. "Received wafer" may mean a wafer in a post-manufacturing state that is to be verified or certified. In some embodiments, the received wafer may be received by a measurement device (e.g., measurement device (135), FIG. 1) capable of obtaining a set of electrical parameter measurements from the received wafer and transmitting such measurements to the wafer verification system. In some embodiments, the step of verifying the received wafer may include the step of identifying the received wafer as a wafer inspected in operation (220). In some embodiments, the step of verifying the received wafer may include the step of distinguishing the received wafer from the wafer inspected in operation (220). As discussed below, the wafer verification system may use a set of electrical parameter measurements to verify the received wafer.

[0051] In an exemplary scenario, at the first time, the wafer verification system can inspect the first wafer by image comparison as discussed in relation to operation (220). Additionally, at the first time, the wafer verification system can obtain physical measurements corresponding to the verification structure as discussed in relation to operation (215). Continuing this example, at the second time following the first time, the measurement device can receive the wafer to be verified. The measurement device can measure electrical parameters (e.g., capacitance, resistance, current, etc.) of the verification structure on the received wafer. Then, in operation (235), the wafer verification system can obtain electrical parameter measurements from the measurement device.

[0052] In operation (240), the wafer verification system may calculate a set of physical parameter values ​​based on a set of electrical parameter measurements obtained in operation (235). In some embodiments, the physical parameter values ​​calculated in operation (240) may correspond to physical measurements of the target structure. For example, in some embodiments, operation (235) may include a wafer verification system that obtains a capacitance measurement of the verification structure of the received wafer. In this example, the capacitance measurement may correspond to the thickness of the electrical insulator of the verification structure. Thus, in this example, operation (240) may include a wafer verification system that uses known scientific principles to calculate the thickness of the electrical insulator.

[0053] In operation (245), the wafer verification system may determine whether one or more matches exist by comparing one or more physical parameter values ​​calculated in operation (240) with one or more physical measurements obtained in operation (215). The presence of a match may verify that the received wafer has the physical measurements obtained by the wafer verification system in operation (215). Thus, the presence of a match may indicate that the received wafer was inspected by the wafer verification system in operation (220). The absence of a match may mean that the received wafer does not have the physical measurements obtained by the wafer verification system in operation (215). Thus, the absence of a match may mean that the received wafer was not inspected by the wafer verification system in operation (220). If the wafer verification system determines that one or more physical parameter values ​​match one or more physical measurements, the wafer verification system may proceed to operation (250). Alternatively, if the wafer verification system determines that one or more physical parameter values ​​do not match one or more physical measurements, the wafer verification system may proceed to operation (255).

[0054] In operation (250), the wafer verification system may generate a match verification response. The match verification response may indicate that the received wafer is a wafer that has been inspected by the wafer verification system in operation (220). In some embodiments, operation (250) may include a wafer verification system that generates an alphabet-numeric text message, an audible alarm, and / or a visual alarm to indicate a match. In some embodiments, operation (250) may include a wafer verification system that issues a command to a device, such as a computing device, that generates and / or issues such text messages and / or alarms.

[0055] In operation (255), the wafer verification system may generate a mismatch verification response. The mismatch verification response may indicate that the received wafer is not the wafer inspected by the wafer verification system in operation (220). In some embodiments, operation (255) may include a wafer verification system that generates an alphabetical-numeric text message, an audible alarm, and / or a visual alarm to indicate a lack of match. In some embodiments, operation (255) may include a wafer verification system that issues a command to a device, such as a computing device, that generates and / or issues such text messages and / or alarms.

[0056] FIG. 3a illustrates a top view of an exemplary wafer (300) according to an embodiment of the present invention. The wafer (300) includes dies (301, 304, 308, and 312). Die (301) is located in a first region (302) of the wafer (300). Die (312) includes a second region (314) where a verification structure discussed in relation to FIG. 3d and FIG. 3e is located. Die (308) includes a third region (310) where a verification structure discussed in relation to FIG. 3f and FIG. 3g is located. Die (304) includes a fourth region (306) where a verification structure discussed in relation to FIG. 3h and FIG. 3i is located.

[0057] FIG. 3b illustrates an image (316) of a die (301) and a reference image (318) corresponding to the die (301). The image (316) can be obtained by a wafer verification system in operation (210, FIG. 2). The reference image (318) can be obtained by a wafer verification system in operation (205, FIG. 2). Both the image (316) and the reference image (318) illustrate a region (302) of the wafer (300) in a manufacturing state. The image (316) illustrates a set of conductors (320) of a first manufacturing layer formed on the wafer (300). In some embodiments, the conductors (320) may be operative features of an electronic circuit design. The reference image (318) illustrates a set of reference conductors (322) of the first reference manufacturing layer of the wafer (300). Reference conductors (322) may exhibit appropriate characteristics for a set of conductors (320). For example, the reference conductors (322) may have sizes that match the design specifications for the wafer (300). Thus, in this example, the wafer verification system can compare the image (316) with the reference image (318) and determine whether the images match. In this example, the wafer verification system can determine such a match based on a percentage error between the sizes of the conductors (320) and the sizes of the reference conductors (322) that does not exceed a threshold of 5%.

[0058] FIG. 3c illustrates the corresponding image (324) and reference image (326) to the image (316) and reference image (318), respectively. The image (324) can be obtained by the wafer verification system in operation (210, FIG. 2). The reference image (326) can be obtained by the wafer verification system in operation (205, FIG. 2). The image (324) illustrates an area (302) of the wafer (300) after a set of conductors (328 and 330) of the second manufacturing layer has been formed on the wafer (300). In some embodiments, the conductors (328) may be operating features of an electronic circuit design. The reference image (326) illustrates a set of reference conductors (332 and 334) of the second reference manufacturing layer of the wafer (300). Similar to the reference conductors (322), the reference conductors (332 and 334) can exemplify appropriate characteristics for the set of conductors (328 and 330). For example, the reference conductors (332 and 334) may have lengths that match the design specifications for the wafer (300). Thus, in this example, the wafer verification system may compare the image (324) with the reference image (326) and determine that the images do not match. In this example, the wafer verification system may determine the lack of match based on a percentage error between the length of the conductor (330) and the length of the reference conductor (334) that exceeds a threshold of 2%. In this example, the mismatched images may indicate that the wafer (300) has malicious design modifications to the second manufacturing layer of the wafer (300).

[0059] FIG. 3d illustrates a cross-sectional view of an exemplary target component (338) in a region (314) of a wafer (300) according to embodiments of the present invention. The target component (338) may be an insulator formed on a conductive layer (340) of the wafer (300). In FIG. 3d, since the wafer (300) is in a manufacturing state, the target component (338) may have a top surface (350) that is not obscured by subsequent manufacturing layers. Because the top surface (350) of the target component (338) is not obstructed, the wafer verification system can obtain physical measurements (e.g., thickness measurements) of the target component (338). The wafer verification system can obtain physical measurements as described in relation to operation (215, FIG. 2). In some embodiments, the wafer verification system may employ an ellipsometer to obtain physical measurements.

[0060] FIG. 3e illustrates a cross-sectional view of an exemplary verification structure (342) including a target component (338) according to embodiments of the present invention. In FIG. 3e, the wafer (300) is in a post-manufacturing state. Accordingly, the verification structure (342) includes a conductor (344) and probe pads (348 and 346), as well as a target component (338) formed on the conductor (340). The probe pads (348 and 346) are included in a manufacturing layer formed on top of a manufacturing layer containing the target component (338). Additionally, when the wafer (300) is in a post-manufacturing state, the top surface (350) of the target component (338) may be obscured, so physical measurement of the target component (338) by a device such as an ellipsometer may not be possible. However, the verification structure (342) may be configured to provide electrical parameter measurements (e.g., capacitance between probe pads (348 and 346)). By using known scientific principles, the wafer verification system can calculate the thickness of the target component (338) based on such capacitance, as described in relation to operation (240, FIG. 2). Using the calculated thickness, the wafer verification system can verify the wafer, as described in relation to operation (245, FIG. 2).

[0061] FIG. 3f illustrates a cross-sectional view of an exemplary target component (356) of a region (310) of a wafer (300) according to embodiments of the present invention. The target component (356) may be a conductor formed on an insulator (358) of the wafer (300). In FIG. 3f, since the wafer (300) is in a manufactured state, the target component (356) may have a top surface (354) that is visible to the naked eye. Because the top surface (354) is visible, a wafer verification system can obtain a physical measurement (e.g., width (363)) of the target component (356).

[0062] FIG. 3g illustrates a top view of an exemplary verification structure (360) including a target component (356) according to embodiments of the present invention. In FIG. 3g, the wafer 300 is in a post-manufacturing state. Therefore, the target component (356) is covered by a subsequent layer of insulator (358) and is not visible. In this example, the verification structure (360) may be configured to provide electrical parameter measurements (e.g., resistance between probe pads (362 and 364)). By using known scientific principles, the wafer verification system can calculate the width (363) of the target component (356) based on such resistance, as described in relation to operation (240, FIG. 2). Using the calculated width (363), the wafer verification system can verify the wafer as described in relation to operation (245, FIG. 2).

[0063] FIG. 3h illustrates a cross-sectional view of an exemplary target component (378) in a region (306) of a wafer (300) according to embodiments of the present invention. The target component (378) may be the width of an insulator (370) between a first conductor (372) and a second conductor (368). In FIG. 3h, since the wafer (300) is in a manufacturing state, the target component (378) may be visible during one or more pattern transfer processes. Accordingly, a wafer verification system may obtain the width of the target component (378) by physical measurement.

[0064] FIG. 3i illustrates a top view of an exemplary verification structure (374) including a target component (378) according to embodiments of the present invention. In FIG. 3i, since the wafer (300) is in a post-manufacturing state, the target component (378) is not visible due to a subsequent layer of insulator (370). In this example, the verification structure (374) may be configured to provide electrical parameter measurements (e.g., leakage current or capacitance between probe pads (366 and 376)). By using known scientific principles, the wafer verification system can calculate the width of the target component (378) based on such leakage current, as described in relation to operation (240, FIG. 2). Using the calculated width, the wafer verification system can verify the wafer as described in relation to operation (245, FIG. 2).

[0065] In some embodiments, the wafer (300) may include at least one of the verification structures described in connection with FIG. 3a and FIG. 3d through 3i. In some embodiments, the wafer (300) may include verification structures having components (e.g., target components) on various manufacturing layers of the wafer (300). For example, in some embodiments, a target component for a first verification structure may be formed on a 10th manufacturing layer of the wafer (300), and a target component for a second verification structure may be formed on a 30th manufacturing layer of the wafer (300), and the 30th layer is formed on or above the 10th manufacturing layer. In some embodiments, probe pads of one or more verification structures of the wafer (300) may be formed on the same layer of the wafer (300).

[0066] FIG. 4 illustrates representative major components of an exemplary computer system (401) that may be used according to embodiments of the present invention. The specific components depicted are presented for illustrative purposes only and are not necessarily the only variations thereof. The computer system (401) may include a processor (410), memory (420), an input / output interface (also referred to herein as I / O or I / O interface) (430), and a main bus (440). The main bus (440) may provide communication paths to other components of the computer system (401). In some embodiments, the main bus (440) may be connected to other components, such as a specialized digital signal processor (not shown).

[0067] A processor (410) of a computer system (401) may include one or more CPUs (412). The processor (410) may additionally include one or more memory buffers or caches (not shown) that provide temporary storage of instructions and data for the CPU (412). The CPU (412) may execute instructions on inputs provided from the caches or memory (420) and output the results to the caches or memory (420). The CPU (412) may include one or more circuits configured to perform one or more methods according to an embodiment of the present invention. In some embodiments, the computer system (401) may include a number of processors (410) typical of a relatively large system. However, in other embodiments, the computer system (401) may be a single processor having a single CPU (412).

[0068] The memory (420) of the computer system (401) may include a memory controller (422) for temporarily or permanently storing data and one or more memory modules (not shown). In some embodiments, the memory (420) may include a random-access semiconductor memory, a storage device, or a storage medium (volatile or non-volatile) for storing data and programs. The memory controller (422) may communicate with the processor (410) to facilitate the storage and retrieval of information in the memory modules. The memory controller (422) may communicate with the I / O interface (430) to facilitate the storage and retrieval of inputs or outputs of the memory modules. In some embodiments, the memory modules may be dual in-line memory modules.

[0069] The I / O interface (430) may include an I / O bus (450), a terminal interface (452), a storage interface (454), an I / O device interface (456), and a network interface (458). The I / O interface (430) may connect the main bus (440) to the I / O bus (450). The I / O interface (430) may transmit commands and data from the processor (410) and memory (420) to various interfaces of the I / O bus (450). The I / O interface (430) may also direct commands and data from various interfaces of the I / O bus (450) to the processor (410) and memory (420). Various interfaces may include a terminal interface (452), a storage interface (454), an I / O device interface (456), and a network interface (458). In some embodiments, various interfaces may include a subset of the aforementioned interfaces (e.g., an embedded computer system for an industrial application may not include a terminal interface (452) and a storage interface (454)).

[0070] The logic modules of the entire computer system (401)—including, but not limited to, memory (420), processor (410), and I / O interface (430)—can transmit failures and changes to one or more components to a hypervisor or operating system (not shown). The hypervisor or operating system can allocate various resources available in the computer system (401) and track data locations within memory (420) and process locations assigned to various CPUs (412). In embodiments that combine or rearrange elements, the functional features of the logic modules may also be combined or redistributed. These variations will be obvious to those skilled in the art.

[0071] Although the present invention includes detailed descriptions regarding cloud computing, it should be understood that the implementation of such technical ideas described herein is not limited to a cloud computing environment. Rather, embodiments of the present invention may be implemented with all other types of computing environments that are now known or will be developed later.

[0072] Cloud computing is a service delivery model that enables convenient on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provided and released with minimal management effort or interaction with a service provider. This cloud model may include at least five characteristics, at least three service models, and at least four deployment models.

[0073] The characteristics are as follows: On-demand self-service: Cloud consumers can unilaterally provision computing capacities, such as server time and network storage, automatically as needed without requiring human interaction with the service provider. Broad network access: Functions accessed through standard mechanisms that encourage use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs) can be utilized through the network. Resource Pooling: A provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, which dynamically allocates and reallocates different physical and virtual resources according to demand. Consumers generally cannot control or have knowledge of the exact location of the provided resources, but there is location independence in that they can specify the location at a higher level of abstraction (e.g., country, state, or data center). Rapid elasticity: Capabilities are provided agilely and elastically, allowing for rapid scale-out (sometimes automatically) and elastic release to rapid scale-in. The potential to be provided to consumers is often unlimited, and it appears as though any desired quantity can be purchased at any time. Measured service: Cloud systems automatically control and optimize resource usage by utilizing metering capabilities at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, thereby providing transparency to both service providers and users.

[0074] The service models are as follows: Software as a Service (SaaS): The service provided to consumers enables the use of a provider's applications running on cloud infrastructure. Applications are accessible from multiple client devices through thin client interfaces, such as web browsers (e.g., web-based email). Consumers do not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, storage, or individual application capabilities, except for limited user-specific application configuration settings. Platform as a Service (PaaS): The service provided to consumers enables the deployment of consumer-generated or acquired applications, created using programming languages ​​and tools supported by the provider, onto cloud infrastructure. Consumers do not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage. However, they can control the deployed applications and, where possible, the configurations of the application hosting environment. Infrastructure as a Service (IaaS): The service provided to the consumer offers processing, storage, networking, and other basic computing resources, whereby the consumer can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but can exercise limited control over operating systems, storage, deployed applications, and, where possible, selected networking components (e.g., host firewalls).

[0075] The deployment models are as follows: Private cloud: Cloud infrastructure operates for only one organization, can be managed by that organization or a third party, and can be located on-premises or off-premises. Community Cloud: The cloud infrastructure is shared by multiple organizations and supports specific communities that share common interests (e.g., missions, security requirements, policies, and compliance audits); it can be managed by multiple organizations or third parties and can be located on-premises or off-premises. Public cloud: Cloud infrastructure is available to the general public or large industrial groups and is owned by the organization selling the cloud services. Hybrid cloud: A cloud infrastructure is a mixed configuration of two or more clouds (private, community, or public), which are distinct entities but are coupled together by standardized or proprietary technologies (e.g., cloud bursting for load balancing between clouds) that enable data and application portability. Cloud computing environments aim for services focused on statelessness, low coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure comprising a network of interconnected nodes.

[0076] Now, referring to FIG. 5, an exemplary cloud computing environment (50) is illustrated. As illustrated, the cloud computing environment (50) includes one or more cloud computing nodes (10) used by a local computing device that can communicate with, for example, a personal digital assistant (PDA) or mobile phone (54A), a desktop computer (54B), a laptop computer (54C), and / or a computer system for a vehicle (54N). The nodes (10) can communicate with each other. They may be physically or virtually grouped in one or more networks, such as private, community, public, or hybrid clouds or combinations thereof, as described herein (not illustrated). This allows the cloud computing environment (50) to provide infrastructure, platforms, and / or software as a service so that the cloud consumer does not need to maintain resources on the local computing device. It should be understood that the types of computing devices (54A-N) illustrated in FIG. 9 are described for illustrative purposes only, and that computing nodes (10) and the cloud computing environment (50) can communicate with all types of computerized devices through all types of networks and / or network addressable connections (e.g., using a web browser).

[0077] Now, referring to FIG. 6, a set of functional abstraction layers provided by the cloud computing environment (50) (Fig. 5) is illustrated. It should be understood in advance that the components, layers, and functions illustrated in FIG. 6 are for illustrative purposes only and preferred embodiments of the invention are not limited thereto. As illustrated, the following layers and corresponding functions are provided:

[0078] The hardware and software layer (60) includes hardware and software components. Examples of hardware components include: mainframes (61); RISC (Reduced Instruction Set Computer) architecture-based servers (62); servers (63); blade servers (64); storage devices (65); and network and networking components (66). In some embodiments, software components include network application server software (67) and database software (68).

[0079] The virtualization layer (70) provides an abstraction layer from which examples of the following virtual subjects may be provided: virtual servers (71); virtual storage (72); virtual networks (73), including virtual private networks; virtual applications and operating systems (1074); and virtual clients (75).

[0080] In one example, the management layer (80) provides the functions described below. Resource provisioning (81) provides the dynamic procurement of computing resources and other resources used to perform tasks within the cloud computing environment. Metering and pricing (82) provides cost tracking when resources are used within the cloud computing environment, and billing or invoices for the consumption of these resources. In one example, these resources may include application software licenses. Security provides protection for data and other resources, as well as identity verification for cloud consumers and tasks. The user portal (83) provides access to the cloud computing environment to consumers and system administrators. Service level management (84) provides the allocation and management of cloud computing resources to ensure that the required service level is met. Service level agreement (SLA) planning and fulfillment (85) provides the pre-arrangement and procurement of cloud computing resources to meet anticipated future requirements that comply with the SLA.

[0081] The workload layer (90) provides examples of functions for which the cloud computing environment can be utilized. Examples of workloads and functions that can be provided in this layer include: mapping and navigation (91); software development and lifecycle management (92); virtual classroom training delivery (93); data analysis processing (94); transaction processing (95); and inspection / verification logic (96).

[0082] As discussed in more detail in this specification, it is considered that some or all of the operations of some embodiments of the methods described herein may be performed in alternative sequences or not performed at all; additionally, multiple operations may occur simultaneously or as part of a larger process.

[0083] The present invention may be a system, method, and / or computer program product at all technical detail levels of integration. The computer program product may include a computer-readable storage medium (or media), the computer-readable storage medium (or media) having computer-readable program instructions, the computer-readable program instructions are intended to enable a processor to execute aspects of the present invention.

[0084] A computer-readable storage medium may be a tangible device capable of holding and storing instructions for use in an instruction execution device. A computer-readable storage medium may be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing, but is not limited to these. A list of more specific examples of computer-readable storage media (not all of them) may also include portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, punch cards, or mechanically encoded devices such as structures convex in grooves having written instructions, and any suitable combination of the foregoing. As used herein, computer-readable storage media are not composed of transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0085] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing unit, or to an internal computer or external storage device, via a network such as, for example, the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing unit receives computer-readable program instructions from the network and transmits the computer-readable program instructions to be stored on a computer-readable storage medium within each computing / processing unit.

[0086] Computer-readable program instructions for performing the operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuitry, or source code or object code written in any combination of one or more programming languages. The programming languages ​​include object-oriented programming languages ​​such as Smalltalk, C++, etc., and procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely or partially on a user's computer as a stand-alone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (e.g., via the Internet using an Internet Service Provider).In some embodiments, to carry out aspects of the present invention, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute computer-readable program instructions by utilizing state information of computer-readable program instructions to customize the electronic circuitry.

[0087] Embodiments of the present invention are described herein with reference to flowchart descriptions and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the invention. It is understood that in the flowchart descriptions and / or block diagrams, each block of the flowchart descriptions and / or block diagrams, and combinations of blocks, may be implemented by computer-readable program instructions.

[0088] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or another programmable data processing unit to create a machine, and thus, when executed through the processor of the computer or other programmable data processing unit, the instructions create means for implementing the functions / operations specified in the blocks or blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in computer-readable storage, and the computer-readable storage may instruct the computer, the programmable data processing unit, and / or other devices to function in a specific manner. Thus, a computer-readable storage medium having instructions stored therein comprises a manufactured article containing instructions that implement aspects of the functions / operations specified in the blocks or blocks of a flowchart and / or block diagram.

[0089] Computer-readable program instructions can also be loaded onto a computer, another programmable data processing unit, or another device to create a computer-implemented process of a series of operational steps to be performed on the computer, another programmable device, or another device. Thus, instructions executed on the computer, another programmable device, or another device enable the implementation of functions / operations specified in blocks or blocks of a flowchart and / or block diagram.

[0090] In the drawings, flowcharts and block diagrams illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or part of instructions, which includes one or more executable instructions for implementing the specified logical function(s). In some other implementations, the functions described in the blocks may occur out of the order described in the drawings. For example, two blocks shown in succession may, in fact, occur substantially simultaneously, or the blocks may sometimes be executed in reverse order according to the related functions. It may also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by dedicated hardware-based systems that perform the specified functions or acts or perform combinations of dedicated hardware and computer instructions.

[0091] The description of various embodiments of the present invention is provided for illustrative purposes only, but is not intended to be limited to or exhaustive. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been chosen to best describe the principles of the embodiments, actual applications of the technology found in the market, or technical improvements, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

Claim 1 In a computer-implemented method, the method comprises: a first reference image of a first wafer; a first image of the first wafer in a fabrication state, wherein in the fabrication state, the first wafer has fewer fabrication layers than a threshold number; A computer-implemented method comprising: the first wafer having a first verification structure; acquiring a first physical measurement corresponding to the first verification structure when the first wafer is in a manufacturing state; determining whether the first image matches the first reference image by comparing the first image with the first reference image at a first time; acquiring an electrical parameter measurement corresponding to the verification structure of the wafer received in a post-fabrication state at a second time following the first time, wherein the received wafer has a second number of manufacturing layers equal to the threshold number; calculating a physical parameter value based on the electrical parameter measurement; and generating a verification response by comparing the physical parameter value with the first physical measurement. Claim 2 In claim 1, the method further comprises the step of determining that the physical parameter value matches the first physical measurement based on comparing the physical parameter value with the first physical measurement, and in response to determining that the physical parameter value matches the first physical measurement, the step of generating the verification response comprises indicating that the received wafer is the first wafer in the post-manufacturing state, wherein in the post-manufacturing state, the first wafer has a second number of manufacturing layers equal to the threshold number. Claim 3 In claim 2, the first verification structure comprises a target component; the first physical measurement is a measurement of the physical properties of the target component; when the first wafer is in a manufacturing state, the target component has a first visibility; when the first wafer is in a post-manufacturing state, the target component has a second visibility; and the second visibility is smaller than the first visibility. Claim 4 A computer-implemented method according to claim 1, wherein the first physical measurement is selected from the group consisting of the thickness of the insulating material, the width of the conductor, and the distance between the first conductor and the second conductor. Claim 5 In claim 1, the method further comprises the step of determining, based on comparing the physical parameter value with the first physical measurement, that the physical parameter value does not match the first physical measurement, and in response to determining that the physical parameter value does not match the first physical measurement, the step of generating the verification response comprises the step of indicating that the received wafer is not the first wafer. Claim 6 A computer-implemented method according to claim 1, wherein the first reference image depicts a first reference manufacturing layer of the first wafer; the first image depicts a first manufacturing layer of the first wafer; and comparing the first image with the first reference image includes comparing the first manufacturing layer with the first reference manufacturing layer. Claim 7 In claim 6, the method further comprises: a step of acquiring a second image of the first wafer in a manufacturing state, wherein the second image depicts the first manufacturing layer and the second manufacturing layer of the first wafer; a step of acquiring a second reference image of the first wafer, wherein the second reference image depicts the first reference manufacturing layer and the second reference manufacturing layer of the first wafer; and a step of determining that the second image matches the second reference image by comparing the second image with the second reference image. Claim 8 In a system, the system comprises: one or more processors; and one or more computer-readable storage media storing program instructions configured to cause the one or more processors to perform a method when executed by the one or more processors, and the method comprises: a step of acquiring a first reference image of a first wafer; a step of acquiring a first image of the first wafer in a fabrication state, wherein in the fabrication state, the first wafer has a number of fabrication layers less than a threshold number; A system comprising: the first wafer having a first verification structure; the first physical measurement corresponding to the first verification structure when the first wafer is in a manufacturing state; the first image being compared with the first reference image at a first time to determine whether the first image matches the first reference image; the second time following the first time, the electrical parameter measurement corresponding to the verification structure of the wafer received in a post-fabrication state (in the post-fabrication state, the received wafer has a second number of manufacturing layers equal to the threshold number); the physical parameter value being calculated based on the electrical parameter measurement; and the step of generating a verification response by comparing the physical parameter value with the first physical measurement. Claim 9 In claim 8, the method further comprises the step of determining that the physical parameter value matches the first physical measurement based on comparing the physical parameter value with the first physical measurement, and in response to determining that the physical parameter value matches the first physical measurement, the step of generating the verification response comprises indicating that the received wafer is the first wafer in the post-manufacturing state, wherein in the post-manufacturing state, the first wafer has a second number of manufacturing layers equal to the threshold number. Claim 10 In claim 9, the first verification structure comprises a target component; the first physical measurement is a measurement of the physical properties of the target component; when the first wafer is in a manufacturing state, the target component has a first visibility; when the first wafer is in a post-manufacturing state, the target component has a second visibility; and the system is smaller than the first visibility. Claim 11 In claim 8, the first physical measurement is a system selected from the group consisting of the thickness of the insulating material, the width of the conductor, and the distance between the first conductor and the second conductor. Claim 12 In claim 8, the method further comprises the step of determining, based on comparing the physical parameter value with the first physical measurement, that the physical parameter value does not match the first physical measurement, and in response to determining that the physical parameter value does not match the first physical measurement, the step of generating the verification response includes the step of indicating that the received wafer is not the first wafer. Claim 13 In claim 8, the first reference image depicts a first reference manufacturing layer of the first wafer; the first image depicts a first manufacturing layer of the first wafer; and the system comprising comparing the first image with the first reference image and comparing the first manufacturing layer with the first reference manufacturing layer. Claim 14 A computer program stored in one or more computer-readable storage media, wherein the computer program comprises program instructions collectively stored in the one or more computer-readable storage media, and the program instructions comprise instructions configured for one or more processors to perform a method, the method comprising: a first reference image of a first wafer; a first image of the first wafer in a fabrication state, wherein in the fabrication state, the first wafer has a number of fabrication layers less than a threshold number; A computer program comprising: the first wafer having a first verification structure; the first wafer having a first physical measurement corresponding to the first verification structure when the first wafer is in a manufacturing state; the first image having a first physical measurement corresponding to the first verification structure when the first wafer is in a manufacturing state; the first image having a first reference image having a first physical measurement corresponding to the first reference image when the first image is compared with the first reference image when the first image is compared with the first reference image when the first image is compared with the first reference image when the first image is compared with the first reference image when the first image is compared with the second time at a second time at a second time at a post-fabrication state when the first time at a second time at a post-fabrication state when the first time at a second time at a post-fabrication state when the first time at a post-fabrication state when the first wafer has a second number of manufacturing layers equal to the threshold number; the first time at a second time at a second time at a post-fabrication state when the first Claim 15 In claim 14, the method further comprises the step of determining that the physical parameter value matches the first physical measurement based on comparing the physical parameter value with the first physical measurement, and in response to determining that the physical parameter value matches the first physical measurement, the step of generating the verification response comprises the step of indicating that the received wafer is the first wafer in the post-manufacturing state, wherein in the post-manufacturing state, the first wafer has a second number of manufacturing layers equal to the threshold number. Claim 16 In claim 15, the first verification structure comprises a target component; the first physical measurement is a measurement of the physical properties of the target component; when the first wafer is in a manufacturing state, the target component has a first visibility; when the first wafer is in a post-manufacturing state, the target component has a second visibility; and the second visibility is smaller than the first visibility. Claim 17 In claim 14, the first physical measurement is a computer program selected from the group consisting of the thickness of the insulating material, the width of the conductor, and the distance between the first conductor and the second conductor. Claim 18 In claim 14, the method further comprises the step of determining, based on comparing the physical parameter value with the first physical measurement, that the physical parameter value does not match the first physical measurement, and in response to determining that the physical parameter value does not match the first physical measurement, the step of generating the verification response includes the step of indicating that the received wafer is not the first wafer. Claim 19 In claim 14, the first reference image depicts a first reference manufacturing layer of the first wafer; the first image depicts a first manufacturing layer of the first wafer; and a computer program comprising comparing the first image with the first reference image and comparing the first manufacturing layer with the first reference manufacturing layer. Claim 20 A computer-implemented method comprising: a step of obtaining a first physical measurement corresponding to a first verification structure of a first wafer in a manufacturing state, wherein in the manufacturing state, the first wafer has a number of manufacturing layers less than a threshold number; a step of obtaining an electrical parameter measurement corresponding to a verification structure of a wafer received in a post-manufacturing state, wherein in the post-manufacturing state, the received wafer has a second number of manufacturing layers equal to the threshold number; a step of calculating a physical parameter value based on the electrical parameter measurement; and a step of generating a verification response by comparing the physical parameter value with the first physical measurement. Claim 21 A device comprising: a wafer having a first verification structure in a first region of the wafer and a second verification structure in a second region of the wafer, wherein the first verification structure comprises a first target component and the second verification structure comprises a second target component, and wherein the first verification structure comprises a first measurable electrical parameter corresponding to a first physical characteristic of the first target component and the second verification structure comprises a second measurable electrical parameter corresponding to a second physical characteristic of the second target component, and wherein the first physical measurement of the first target component corresponding to the first measurable electrical parameter and the second physical measurement of the second target component corresponding to the second measurable electrical parameter together form a unique identifier of the wafer. Claim 22 In claim 21, the wafer comprises a first manufacturing layer and a second manufacturing layer, the second manufacturing layer is formed on the first manufacturing layer, the first target component is included in the first manufacturing layer, the first verification structure further comprises a first pair of pads included in the second manufacturing layer, and the first measurable electrical parameter is measurable through the first pair of pads. Claim 23 In claim 22, the wafer further comprises a third manufacturing layer, said third manufacturing layer formed on the first manufacturing layer, said second manufacturing layer formed on the third manufacturing layer, said second target component included in the third manufacturing layer, said second verification structure further comprises a second pair of pads included in the second manufacturing layer, and said second measurable electrical parameter is measurable through said second pair of pads. Claim 24 delete Claim 25 A device according to claim 21, wherein the first target component is an insulator, the first measurable electrical parameter is capacitance, the first physical characteristic is thickness, the second target component is a conductor, the second measurable electrical parameter is resistance, and the second physical characteristic is width.

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