Semiconductor device

Abstract

This invention provides a semiconductor device. The semiconductor device includes: a lower nanosheet; an upper nanosheet disposed on the lower nanosheet; gate electrodes disposed on a substrate and surrounding each of the nanosheets; a first lower source / drain region disposed on a first side of the first gate electrode and a second gate electrode; a second lower source / drain region disposed on a second side of the first gate electrode and the second gate electrode; a first upper source / drain region disposed on the first lower source / drain region; and a second upper source / drain region disposed on the second lower source / drain region. The first length of the second lower source / drain region is greater than the second length of the second upper source / drain region.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Cross-reference of related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0136202, filed with the Korean Intellectual Property Office on October 14, 2021, the disclosure of which is incorporated herein by reference in its entirety. Prior Technology

[0003] The integration density of semiconductor devices can be increased by using multi-gate transistors, in which a silicon body in the shape of fins or nanowires is formed on a substrate and a gate is formed on the surface of the silicon body.

[0004] Because these multi-gate transistors use three-dimensional channels, they are easy to scale. Furthermore, the current control capability of multi-gate transistors can be improved without increasing the gate length. Additionally, multi-gate transistors can effectively suppress the short-channel effect (SCE) caused by the drain voltage affecting the channel region potential. Summary of the Invention

[0005] One or more embodiments provide a semiconductor device having the following structure: wherein a lower source / drain region and an upper source / drain region are stacked in a vertical direction such that the length of the upper source / drain region is longer than the length of the lower source / drain region, thereby improving the integration of the device.

[0006] One or more embodiments provide a semiconductor device having the following structure: a lower source / drain region and an upper source / drain region are stacked in a vertical direction, such that buried contacts electrically connected to the lower source / drain region are disposed below the upper source / drain region, thereby improving the integration of the device.

[0007] According to an embodiment, a semiconductor device includes: a substrate; a plurality of lower nanosheets located on the substrate and extending in a first horizontal direction, wherein the plurality of lower nanosheets are stacked in a vertical direction and spaced apart from each other; a plurality of upper nanosheets located on the plurality of lower nanosheets and extending in the first horizontal direction, wherein the plurality of upper nanosheets are stacked in the vertical direction and spaced apart from each other; a first gate electrode to a fourth gate electrode located on the substrate and extending in a second horizontal direction different from the first horizontal direction, wherein the first gate electrode to the fourth gate electrode are disposed around each of the plurality of lower nanosheets and each of the plurality of upper nanosheets, a second gate electrode is spaced apart from the first gate electrode in the second horizontal direction, and a third gate electrode is spaced apart from the first gate electrode in the first horizontal direction. The electrodes are spaced apart, and the fourth gate electrode is spaced apart from the third gate electrode in the second horizontal direction; a first lower source / drain region is located on a first side of the first gate electrode and the second gate electrode; a second lower source / drain region is located on a second side of the first gate electrode and the second gate electrode in the first horizontal direction opposite to the first side, wherein the second side of the first gate electrode and the second gate electrode faces the third gate electrode and the fourth gate electrode; a first upper source / drain region is located on the first lower source / drain region; a second upper source / drain region is located on the second lower source / drain region; and an interlayer insulating layer is located between the first lower source / drain region and the first upper source / drain region and between the second lower source / drain region and the second upper source / drain region. The first length of the second lower source / drain region in the second horizontal direction is greater than the second length of the second upper source / drain region in the second horizontal direction.

[0008] According to an embodiment, a semiconductor device includes: a substrate; a plurality of lower nanosheets disposed on the substrate and extending in a first horizontal direction, wherein the plurality of lower nanosheets are stacked in a vertical direction and spaced apart from each other; a plurality of upper nanosheets disposed on the plurality of lower nanosheets and extending in the first horizontal direction, wherein the plurality of upper nanosheets are stacked in the vertical direction and spaced apart from each other; a first gate electrode disposed on the substrate and extending in a second horizontal direction different from the first horizontal direction, wherein the first gate electrode is disposed around each of the plurality of lower nanosheets and each of the plurality of upper nanosheets; a second gate electrode... A second gate electrode is located on the substrate and extends in the second horizontal direction, wherein the second gate electrode is spaced apart from the first gate electrode in the second horizontal direction and is disposed around each of the plurality of lower nanosheets and each of the plurality of upper nanosheets; a lower source / drain region is located on a first side and a second side of the first gate electrode and the second gate electrode; an upper source / drain region is located on the lower source / drain region on the first side and the second side of the first gate electrode and the second gate electrode; and an interlayer insulating layer is located between the lower source / drain region and the upper source / drain region. On at least one side of the first side and the second side of the first gate electrode and the second gate electrode, the first length of the lower source / drain region in the second horizontal direction is greater than the second length of the upper source / drain region in the second horizontal direction.

[0009] According to an embodiment, a semiconductor device includes: a substrate; a plurality of lower nanosheets located on the substrate and extending in a first horizontal direction, wherein the plurality of lower nanosheets are stacked in a vertical direction and spaced apart from each other; a plurality of upper nanosheets located on the plurality of lower nanosheets and extending in the first horizontal direction, wherein the plurality of upper nanosheets are stacked in the vertical direction and spaced apart from each other; a first gate electrode located on the substrate and extending in a second horizontal direction different from the first horizontal direction, wherein the first gate electrode is disposed around each of the plurality of lower nanosheets and each of the plurality of upper nanosheets; a second gate electrode located on the substrate and extending in the second horizontal direction, wherein the second gate electrode is spaced apart from the first gate electrode in the second horizontal direction and surrounds the substrate. Each of a plurality of lower nanosheets and each of a plurality of upper nanosheets are provided with: a first lower source / drain region located on a first side of the first gate electrode and the second gate electrode; a second lower source / drain region located on a second side of the first gate electrode and the second gate electrode in the first horizontal direction opposite to the first side; a first upper source / drain region located on the first lower source / drain region; a second upper source / drain region located on the second lower source / drain region; an interlayer insulating layer located between the first lower source / drain region and the first upper source / drain region and between the second lower source / drain region and the second upper source / drain region; and embedded contacts electrically connected to one of the first lower source / drain region and the second lower source / drain region and extending into the interior of the substrate.

[0010] The embodiments are not limited to the above description. Other variations and advantages not mentioned can be understood based on the following description. Simple Explanation of the Diagram

[0011] The above and other embodiments will be more clearly understood from the following description of the embodiments in conjunction with the accompanying drawings, in which: Figure 1 is a circuit diagram illustrating a semiconductor device according to some embodiments. Figure 2 is a layout diagram illustrating contacts connected to the lower source / drain region in a semiconductor device according to some embodiments. Figure 3 is a layout diagram illustrating contacts connected to the upper source / drain region in a semiconductor device according to some embodiments. Figure 4 is a cross-sectional view taken along line A-A' in each of Figures 2 and 3. Figure 5 is a cross-sectional view taken along line B-B' in each of Figures 2 and 3. Figure 6 is a cross-sectional view taken along line C-C' in each of Figures 2 and 3. Figure 7 is a cross-sectional view taken along line D-D' in each of Figures 2 and 3. Figure 8 is a cross-sectional view taken along line E-E' in each of Figures 2 and 3. Figure 9 is a cross-sectional view taken along line F-F' in each of Figures 2 and 3. Figure 10 is a layout diagram illustrating contacts connected to the lower source / drain region in a semiconductor device according to some other embodiments. Figure 11 is a layout diagram illustrating contacts connected to the upper source / drain region in a semiconductor device according to some other embodiments. Figure 12 is a cross-sectional view taken along line B-B' in each of Figures 10 and 11. Figure 13 is a cross-sectional view taken along line C-C' in each of Figures 10 and 11. Figure 14 is a cross-sectional view taken along line D-D' in each of Figures 10 and 11. Figure 15 is a cross-sectional view taken along line E-E' in each of Figures 10 and 11. Figure 16 is a cross-sectional view taken along line F-F' in each of Figures 10 and 11. Figure 17 is a layout diagram illustrating contacts connected to the lower source / drain region in a semiconductor device according to some other embodiments. Figure 18 is a layout diagram illustrating contacts connected to the upper source / drain region in a semiconductor device according to some other embodiments. Figure 19 is a cross-sectional view taken along line G-G' in each of Figures 17 and 18. Figure 20 is a cross-sectional view taken along line H-H' in each of Figures 17 and 18. Figure 21 is a cross-sectional view taken along line I-I' in each of Figures 17 and 18. Figure 22 is a cross-sectional view taken along line J-J' in each of Figures 17 and 18. Figure 23 is a cross-sectional view taken along line K-K' in each of Figures 17 and 18. Figure 24 is a cross-sectional view taken along line L-L' in each of Figures 17 and 18. Figure 25 is a cross-sectional view taken along line M-M' in each of Figures 17 and 18. Figure 26 is a layout diagram illustrating contacts connected to the lower source / drain region in a semiconductor device according to some other embodiments. Figure 27 is a layout diagram illustrating contacts connected to the upper source / drain region in a semiconductor device according to some other embodiments. Figure 28 is a cross-sectional view taken along line H-H' in each of Figures 26 and 27. Figure 29 is a cross-sectional view taken along line I-I' in each of Figures 26 and 27. Figure 30 is a cross-sectional view taken along line J-J' in each of Figures 26 and 27. Figure 31 is a cross-sectional view taken along line K-K' in each of Figures 26 and 27. Figure 32 is a cross-sectional view taken along line L-L' in each of Figures 26 and 27. Figure 33 is a cross-sectional view taken along line M-M' in each of Figures 26 and 27. Figure 34 is a layout diagram illustrating a semiconductor device according to some other embodiments. Figure 35 is a cross-sectional view taken along line N-N' in Figure 34. Figure 36 is a cross-sectional view taken along line O-O' in Figure 34. Figure 37 is a cross-sectional view taken along line P-P' in Figure 34. Implementation

[0012] In the following description, embodiments will be described in detail with reference to the accompanying drawings. Throughout this specification, similar components are indicated by similar reference numerals, and repeated descriptions thereof are omitted. The embodiments described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto, and various other forms may be implemented. Each embodiment provided in the following description does not exclude association with one or more features of another example or embodiment also provided herein or not provided herein but consistent with this disclosure. It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When phrases such as "at least one of..." precede the component list, they modify the entire component list, not individual components within it. For example, the phrase "at least one of a, b, and c" should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0013] Figure 1 is a circuit diagram illustrating a semiconductor device according to some embodiments. Figure 2 is a layout diagram illustrating contacts connected to the lower source / drain region in a semiconductor device according to some embodiments. Figure 3 is a layout diagram illustrating contacts connected to the upper source / drain region in a semiconductor device according to some embodiments. Figure 4 is a cross-sectional view taken along line A-A' in each of Figures 2 and 3. Figure 5 is a cross-sectional view taken along line B-B' in each of Figures 2 and 3. Figure 6 is a cross-sectional view taken along line C-C' in each of Figures 2 and 3. Figure 7 is a cross-sectional view taken along line D-D' in each of Figures 2 and 3. Figure 8 is a cross-sectional view taken along line E-E' in each of Figures 2 and 3. Figure 9 is a cross-sectional view taken along line F-F' in each of Figures 2 and 3.

[0014] Referring to Figures 1 to 9, a semiconductor device according to some embodiments includes a substrate 100, a field insulating layer 105, a first active pattern F1 to a sixth active pattern F6, a plurality of lower nanosheets BNW, a plurality of upper nanosheets TNW, a first gate electrode G1 to a fourth gate electrode G4, a gate insulating layer 111, a gate spacer 112, a capping pattern 113, a first gate notch GC1, a second gate notch GC2, a first lower source / drain region BSD1 to a fifth lower source / drain region BSD5, a first upper source / drain region TSD1 to a fifth upper source / drain region TSD5, and a third... Gate contacts CB1 to CB4, first buried contacts BC1 and BC2, first lower source / drain contacts BCA1 and BCA2, first upper source / drain contacts TCA1 to 3 upper source / drain contacts TCA3, first through-hole V1 to eleventh through-hole V11, first interlayer insulating layer 120, second interlayer insulating layer 130, etch stop layer 140, third interlayer insulating layer 150, fourth interlayer insulating layer 160, fifth interlayer insulating layer 170, first line pattern 180 and second line pattern 190.

[0015] The substrate 100 may be a silicon substrate or silicon-on-insulator (SOI). Alternatively, the substrate 100 may comprise silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. However, the embodiments are not limited thereto.

[0016] Each of the first active patterns F1 to the sixth active patterns F6 may protrude from the base 100 in the vertical direction DR3. Each of the first active patterns F1 to the sixth active patterns F6 may extend in the first horizontal direction DR1. The second active pattern F2 may be spaced apart from the first active pattern F1 in a second horizontal direction DR2, different from the first horizontal direction DR1. The third active pattern F3 may be spaced apart from the second active pattern F2 in the second horizontal direction DR2. The fourth active pattern F4 may be spaced apart from the third active pattern F3 in the second horizontal direction DR2. The fifth active pattern F5 may be spaced apart from the fourth active pattern F4 in the second horizontal direction DR2. The sixth active pattern F6 may be spaced apart from the fifth active pattern F5 in the second horizontal direction DR2.

[0017] For example, the first active pattern F1, the second active pattern F2, and the third active pattern F3 can be spaced apart by the same distance. The fourth active pattern F4, the fifth active pattern F5, and the sixth active pattern F6 can be spaced apart by the same distance. For example, the distance between the third active pattern F3 and the fourth active pattern F4 can be greater than the distance between the second active pattern F2 and the third active pattern F3.

[0018] Each of the first active patterns F1 to the sixth active patterns F6 may be part of the substrate 100, or may include an epitaxial layer grown from the substrate 100. Each of the first active patterns F1 to the sixth active patterns F6 may include, for example, silicon or germanium as an elemental semiconductor material. Furthermore, each of the first active patterns F1 to the sixth active patterns F6 may include a compound semiconductor. For example, each of the first active patterns F1 to the sixth active patterns F6 may include a Group IV-IV compound semiconductor or a Group III-V compound semiconductor.

[0019] A field insulating layer 105 may be disposed on a substrate 100. The field insulating layer 105 may surround the sidewalls of each of the first active patterns F1 to the sixth active patterns F6. For example, each of the first active patterns F1 to the sixth active patterns F6 may protrude beyond the top surface of the field insulating layer 105 in the vertical direction DR3. The field insulating layer 105 may comprise, for example, an oxide film, a nitride film, an oxide oxynitride film, or a combination thereof.

[0020] Multiple lower nanosheets (BNWs) may be disposed on the substrate 100. The multiple lower nanosheets (BNWs) may be disposed on each of the first active patterns F1 to the sixth active patterns F6. The multiple lower nanosheets (BNWs) may extend in a first horizontal direction DR1. The multiple lower nanosheets (BNWs) may comprise multiple nanosheets stacked and spaced apart from each other in a vertical direction DR3.

[0021] Multiple lower nanosheets BNW disposed on each of the first active patterns F1 to the sixth active patterns F6 may be spaced apart from each other in the second horizontal direction DR2. In addition, multiple lower nanosheets BNW surrounded by each of the first gate electrode G1 to the fourth gate electrode G4 may be spaced apart from each other in the first horizontal direction DR1.

[0022] Multiple upper nanosheets (TNWs) may be disposed on multiple lower nanosheets (BNWs). Multiple upper nanosheets (TNWs) may be disposed on each of the first active patterns F1 to the sixth active patterns F6. Multiple upper nanosheets (TNWs) may extend in a first horizontal direction DR1. Multiple upper nanosheets (TNWs) may comprise multiple nanosheets stacked and spaced apart from each other in a vertical direction DR3.

[0023] Multiple upper nanosheets TNW disposed on each of the first active patterns F1 to the sixth active patterns F6 may be spaced apart from each other in the second horizontal direction DR2. In addition, multiple upper nanosheets TNW surrounded by each of the first gate electrode G1 to the fourth gate electrode G4 may be spaced apart from each other in the first horizontal direction DR1.

[0024] In Figure 4, there are three lower nanosheets (BNWs) spaced apart from each other in the vertical direction DR3, and three upper nanosheets (TNWs) spaced apart from each other in the vertical direction DR3. However, this is for ease of description, and the embodiments are not limited thereto. In some embodiments, the number of lower nanosheets (BNWs) spaced apart from each other in the vertical direction DR3 may be at least four, and the number of upper nanosheets (TNWs) spaced apart from each other in the vertical direction DR3 may be at least four.

[0025] For example, a region with multiple lower nanosheets (BNW) can be an NMOS region. Conversely, a region with multiple upper nanosheets (TNW) can be a PMOS region.

[0026] The first gate electrode G1 can extend along the second horizontal direction DR2 and can be disposed on the first active pattern F1, the second active pattern F2, and the third active pattern F3. The second gate electrode G2 can extend along the second horizontal direction DR2 and can be disposed on the fourth active pattern F4, the fifth active pattern F5, and the sixth active pattern F6. The second gate electrode G2 can be spaced apart from the first gate electrode G1 along the second horizontal direction DR2. The third gate electrode G3 can extend along the second horizontal direction DR2 and can be disposed on the first active pattern F1, the second active pattern F2, and the third active pattern F3. The third gate electrode G3 can be spaced apart from the first gate electrode G1 along the first horizontal direction DR1. The fourth gate electrode G4 can extend along the second horizontal direction DR2 and can be disposed on the fourth active pattern F4, the fifth active pattern F5, and the sixth active pattern F6. The fourth gate electrode G4 can be spaced apart from the third gate electrode G3 along the second horizontal direction DR2.

[0027] Each of the first gate electrode G1, the second gate electrode G2, the third gate electrode G3, and the fourth gate electrode G4 may surround each of the plurality of lower nanosheets BNW and each of the plurality of upper nanosheets TNW. Each of the first gate electrode G1, the second gate electrode G2, the third gate electrode G3, and the fourth gate electrode G4 may include at least one of the following: titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiA) TiC, titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. The embodiments are not limited thereto. Each of the first gate electrode G1, the second gate electrode G2, the third gate electrode G3, and the fourth gate electrode G4 may comprise a conductive metal oxide, a conductive metal nitride, or the like, or may comprise an oxidation product of the above materials.

[0028] A semiconductor device according to some embodiments may include eight transistors. For example, a semiconductor device according to some embodiments may include a first transistor TR1 through an eighth transistor TR8.

[0029] For example, the first transistor TR1 may include multiple upper nanosheets TNW and a second gate electrode G2. The second transistor TR2 may include multiple upper nanosheets TNW and a first gate electrode G1. The third transistor TR3 may include multiple upper nanosheets TNW and a fourth gate electrode G4. The fourth transistor TR4 may include multiple upper nanosheets TNW and a third gate electrode G3.

[0030] Furthermore, the fifth transistor TR5 may include multiple lower nanosheets (BNW) and a second gate electrode G2. The sixth transistor TR6 may include multiple lower nanosheets (BNW) and a fourth gate electrode G4. The seventh transistor TR7 may include multiple lower nanosheets (BNW) and a first gate electrode G1. The eighth transistor TR8 may include multiple lower nanosheets (BNW) and a third gate electrode G3.

[0031] For example, the power node VDD can be connected to each of the first transistor TR1 and the second transistor TR2. The ground node VSS can be connected to each of the seventh transistor TR7 and the eighth transistor TR8.

[0032] A first gate cutout GC1 may be disposed between a first gate electrode G1 and a second gate electrode G2. The first gate cutout GC1 may space the first gate electrode G1 and the second gate electrode G2 apart from each other in a second horizontal direction DR2. A second gate cutout GC2 may be disposed between a third gate electrode G3 and a fourth gate electrode G4. The second gate cutout GC2 may space the third gate electrode G3 and the fourth gate electrode G4 apart from each other in a second horizontal direction DR2. Each of the first gate cutout GC1 and the second gate cutout GC2 may include at least one of the following: silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), boron silicon nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0033] Gate insulating layer 111 may be disposed along the sidewall of each of the first gate electrode G1 to the fourth gate electrode G4. Gate insulating layer 111 may be disposed between each of the first gate electrode G1, the second gate electrode G2, the third gate electrode G3, and the fourth gate electrode G4 and each of the plurality of lower nanosheets BNW. Gate insulating layer 111 may be disposed between each of the first gate electrode G1, the second gate electrode G2, the third gate electrode G3, and the fourth gate electrode G4 and each of the plurality of upper nanosheets TNW. Gate insulating layer 111 may be disposed between each of the first gate electrode G1, the second gate electrode G2, the third gate electrode G3, and the fourth gate electrode G4 and the field insulating layer 105. The gate insulating layer 111 may be disposed between each of the first gate electrode G1, the second gate electrode G2, the third gate electrode G3 and the fourth gate electrode G4 and each of the first active pattern F1 to the sixth active pattern F6.

[0034] Although Figure 4 illustrates that the gate insulating layer 111 is not disposed between the first gate cutout GC1 and each of the first gate electrode G1 and the second gate electrode G2, the embodiment is not limited thereto. In some embodiments, the gate insulating layer 111 may also be disposed between the first gate cutout GC1 and each of the first gate electrode G1 and the second gate electrode G2.

[0035] The gate insulating layer 111 may comprise at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a higher dielectric constant than silicon oxide. The high dielectric constant material may comprise at least one of, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0036] The semiconductor device according to some other embodiments may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating layer 111 may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0037] Ferroelectric films can have negative capacitance, and paraelectric films can have positive capacitance. For example, when two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance is less than the capacitance of each individual capacitor. Conversely, when at least one of the capacitances of two or more capacitors connected in series has a negative capacitance, the total capacitance can be positive and greater than the absolute value of each individual capacitor.

[0038] When a ferroelectric material film with negative capacitance and a paraelectric material film with positive capacitance are connected in series, the total capacitance of the two films connected in series can be increased. Using this increase in total capacitance, a transistor containing a ferroelectric material film can exhibit a subthreshold swing (SS) of less than approximately 60 mV / 100 at room temperature.

[0039] Ferroelectric material films can possess ferroelectric properties. Ferroelectric material films may include at least one of, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. In one instance, hafnium zirconium oxide may refer to a material obtained by doping hafnium oxide with zirconium (Zr). In another instance, hafnium zirconium oxide may refer to a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0040] Ferroelectric films may further contain doped agents. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), thorium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant contained in the ferroelectric film may vary depending on the type of ferroelectric material contained in the ferroelectric film.

[0041] When the ferroelectric material film contains hafnium oxide, the dopant contained in the ferroelectric material film may include at least one of, for example, thorium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) and yttrium (Y).

[0042] When the dopant is aluminum (Al), the ferroelectric film can contain approximately 3 atomic% to approximately 8 atomic% (at%) of aluminum. In this regard, the dopant content can be considered as the aluminum content based on the sum of hafnium and aluminum.

[0043] When the dopant is silicon (Si), the ferroelectric film may contain about 2 atomic% to about 10 atomic% silicon. When the dopant is yttrium (Y), the ferroelectric film may contain about 2 atomic% to about 10 atomic% yttrium. When the dopant is gypsum (Gd), the ferroelectric film may contain about 1 atomic% to about 7 atomic% gypsum. When the dopant is zirconium (Zr), the ferroelectric film may contain about 50 atomic% to about 80 atomic% zirconium.

[0044] The paraelectric material film may possess paraelectric properties. The paraelectric material film may contain at least one of silicon oxide and metal oxides, for example, those having a high dielectric constant. Although the metal oxide contained in the paraelectric material film may contain at least one of hafnium oxide, zirconium oxide, and aluminum oxide, the embodiments are not limited thereto.

[0045] Ferroelectric and paraelectric films can contain the same material but have different properties. Ferroelectric films may possess ferroelectric properties, but paraelectric films may not. For example, when each of the ferroelectric and paraelectric films contains hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric film is different from the crystal structure of the hafnium oxide contained in the paraelectric film.

[0046] Ferroelectric material films can have a thickness set to exhibit ferroelectric properties, and can be, for example, in the range of about 0.5 nanometers to about 10 nanometers, but the embodiments are not limited thereto. Because the critical thickness for exhibiting ferroelectric properties can vary based on the type of ferroelectric material, the thickness of the ferroelectric material film can vary depending on the type of ferroelectric material.

[0047] In one example, the gate insulating layer 111 may comprise a ferroelectric material film. In another example, the gate insulating layer 111 may comprise a plurality of ferroelectric material films spaced apart from each other. The gate insulating layer 111 may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are stacked alternately on top of each other.

[0048] Gate spacer 112 may extend along the sidewall of each of the first gate electrode G1 to the fourth gate electrode G4 in the second horizontal direction DR2 and may be disposed on the topmost nanosheet of the plurality of upper nanosheets TNW and the field insulating layer 105. Gate spacer 112 may comprise at least one of, for example: silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon oxycarbonate (SiOC), and combinations thereof.

[0049] The capping pattern 113 may be disposed on each of the first gate electrodes G1 to the fourth gate electrodes G4. For example, the capping pattern 113 may surround the sidewall of each of the first gate cutout GC1 and the second gate cutout GC2. The capping pattern 113 may include at least one of the following: silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and combinations thereof.

[0050] The lower source / drain regions BSD1 to BSD5 can be respectively disposed on both sides of each of the first gate electrode G1 to the fourth gate electrode G4 and can be disposed on each of the first active pattern F1 to the sixth active pattern F6. The lower source / drain regions BSD1 to BSD5 can be disposed in the NMOS region.

[0051] For example, a first lower source / drain region BSD1 may be disposed on a first side of a first gate electrode G1 and may be disposed on each of a first active pattern F1 to a third active pattern F3. A second lower source / drain region BSD2 may be disposed on a first side of a second gate electrode G2 and may be disposed on each of a fourth active pattern F4 to a sixth active pattern F6. The second lower source / drain region BSD2 may be spaced apart from the first lower source / drain region BSD1 in a second horizontal direction DR2.

[0052] The third lower source / drain region BSD3 can be disposed on the second side of the first gate electrode G1 on the first horizontal direction DR1, opposite to the first side of the first gate electrode G1, and can be disposed on each of the first active patterns F1 to the third active patterns F3. That is, the third lower source / drain region BSD3 can be disposed between the first gate electrode G1 and the third gate electrode G3, and can be disposed on each of the first active patterns F1 to the third active patterns F3.

[0053] The fourth lower source / drain region BSD4 can be disposed on the second side of the second gate electrode G2 on the first horizontal direction DR1, opposite to the first side of the second gate electrode G2, and can be disposed on each of the fourth active patterns F4 to the sixth active patterns F6. That is, the fourth lower source / drain region BSD4 can be disposed between the second gate electrode G2 and the fourth gate electrode G4, and can be disposed on each of the fourth active patterns F4 to the sixth active patterns F6. The fourth lower source / drain region BSD4 can be spaced apart from the third lower source / drain region BSD3 on the second horizontal direction DR2.

[0054] Each of the third gate electrode G3 and the fourth gate electrode G4 may have a first side facing the second side of each of the first gate electrode G1 and the second gate electrode G2, and a second side on the first horizontal direction DR1 opposite to the first side of each of the third gate electrode G3 and the fourth gate electrode G4. The fifth lower source / drain region BSD5 may be disposed on the second side of the third gate electrode G3 and may be disposed on each of the first active patterns F1 to the third active patterns F3. Furthermore, the sixth lower source / drain region may be disposed on the second side of the fourth gate electrode G4 and may be disposed on each of the fourth active patterns F4 to the sixth active patterns F6. The sixth lower source / drain region may be spaced apart from the fifth lower source / drain region BSD5 on the second horizontal direction DR2.

[0055] The upper source / drain regions TSD1 to TSD5 can be disposed on each of the first active patterns F1 to the sixth active patterns F6, and can be disposed on both sides of each of the first gate electrodes G1 to the fourth gate electrodes G4. The upper source / drain regions TSD1 to TSD5 can be disposed on the lower source / drain regions BSD1 to BSD5. The upper source / drain regions TSD1 to TSD5 can be disposed within the PMOS region.

[0056] For example, a first upper source / drain region TSD1 may be disposed on a first lower source / drain region BSD1 and on a first side of the first gate electrode G1. The first upper source / drain region TSD1 may overlap with each of the first active patterns F1 to the third active patterns F3 in the vertical direction DR3. A second upper source / drain region TSD2 may be disposed on a second lower source / drain region BSD2 and on a first side of the second gate electrode G2. The second upper source / drain region TSD2 may overlap with each of the fourth active patterns F4 to the sixth active patterns F6 in the vertical direction DR3. The second upper source / drain region TSD2 may be spaced apart from the first upper source / drain region TSD1 in the second horizontal direction DR2.

[0057] The third upper source / drain region TSD3 can be disposed on the third lower source / drain region BSD3 and between the first gate electrode G1 and the third gate electrode G3. The third upper source / drain region TSD3 can overlap with each of the second active pattern F2 and the third active pattern F3 in the vertical direction DR3. The fourth upper source / drain region TSD4 can be disposed on the fourth lower source / drain region BSD4 and between the second gate electrode G2 and the fourth gate electrode G4. The fourth upper source / drain region TSD4 can overlap with each of the fourth active pattern F4 and the fifth active pattern F5 in the vertical direction DR3. The fourth upper source / drain region TSD4 can be spaced apart from the third upper source / drain region TSD3 in the second horizontal direction DR2.

[0058] The fifth upper source / drain region TSD5 can be disposed on the fifth lower source / drain region BSD5 and on the second side of the third gate electrode G3. The fifth upper source / drain region TSD5 can overlap with each of the first active patterns F1 to the third active patterns F3 in the vertical direction DR3. Furthermore, the sixth upper source / drain region can be disposed on the sixth lower source / drain region and on the second side of the fourth gate electrode G4. The sixth upper source / drain region can overlap with each of the fourth active patterns F4 to the sixth active patterns F6 in the vertical direction DR3. The sixth upper source / drain region can be spaced apart from the fifth upper source / drain region TSD5 in the second horizontal direction DR2.

[0059] Between the first gate electrode G1 and the third gate electrode G3, the third upper source / drain region TSD3 may not be placed on the first active pattern F1. Furthermore, between the second gate electrode G2 and the fourth gate electrode G4, the fourth upper source / drain region TSD4 may not be placed on the sixth active pattern F6.

[0060] The length along the second horizontal direction DR2 from the sidewall of the third lower source / drain region BSD3 mounted on the first active pattern F1 to the sidewall of the fourth lower source / drain region BSD4 mounted on the sixth active pattern F6 can be referred to as the first length L1. Furthermore, the length along the second horizontal direction DR2 from the sidewall of the third upper source / drain region TSD3 mounted on the second active pattern F2 to the sidewall of the fourth upper source / drain region TSD4 mounted on the fifth active pattern F5 can be referred to as the second length L2.

[0061] Between the first gate electrode G1 and the second gate electrode G2 and the third gate electrode G3 and the fourth gate electrode G4, the first length L1 of the lower source / drain region in the second horizontal direction DR2 may be greater than the second length L2 of the upper source / drain region in the second horizontal direction DR2. Furthermore, between the first gate electrode G1 and the second gate electrode G2 and the third gate electrode G3 and the fourth gate electrode G4, the first length L1 of the lower source / drain region in the second horizontal direction DR2 may be shorter than three times the second length L2 of the upper source / drain region in the second horizontal direction DR2.

[0062] The second interlayer insulation layer 130 can be disposed between the lower source / drain regions BSD1 to BSD5 and the upper source / drain regions TSD1 to TSD5. The lower source / drain regions BSD1 to BSD5 and the upper source / drain regions TSD1 to TSD5 can be insulated from each other.

[0063] The first interlayer insulating layer 120 may be disposed on the field insulating layer 105. The first interlayer insulating layer 120 may surround the sidewalls of each of the lower source / drain regions BSD1 to BSD5. For example, the top surface of the first interlayer insulating layer 120 may be coplanar with the top surfaces of the lower source / drain regions BSD1 to BSD5. However, the embodiments are not limited thereto.

[0064] The first interlayer insulating layer 120 may comprise at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. Low dielectric constant materials may include, for example, fluorinated tetraethyl orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bis-benzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethyleyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditertiarybutosiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), and tonene. SilaZen (TOSZ), fluoride silicate glass (FSG), polyimide nanofoams such as polyoxypropylene, carbon-doped silicon oxide (CDO), organosilte glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica degel, mesoporous silica, or combinations thereof. However, the examples are not limited thereto.

[0065] A second interlayer insulating layer 130 may be disposed on the first interlayer insulating layer 120. The second interlayer insulating layer 130 may surround each of the upper source / drain regions TSD1 to TSD5. The second interlayer insulating layer 130 may be disposed between the lower source / drain regions BSD1 to BSD5 and the upper source / drain regions TSD1 to TSD5. The second interlayer insulating layer 130 may comprise at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0066] The etch stop layer 140 may be disposed on the second interlayer insulating layer 130. Although the etch stop layer 140 is illustrated as a single film in Figures 3 through 9, the embodiments are not limited thereto. In some embodiments, the etch stop layer 140 may be multilayered. The etch stop layer 140 may comprise at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and low dielectric constant materials.

[0067] A third interlayer insulating layer 150 may be disposed on an etch stop layer 140. A fourth interlayer insulating layer 160 may be disposed on a third interlayer insulating layer 150. A fifth interlayer insulating layer 170 may be disposed on a fourth interlayer insulating layer 160. Each of the third interlayer insulating layer 150, the fourth interlayer insulating layer 160, and the fifth interlayer insulating layer 170 may comprise at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0068] The first line pattern 180 may be disposed within the fourth interlayer insulation layer 160. The second line pattern 190 may be disposed within the fifth interlayer insulation layer 170. Each of the first line pattern 180 and the second line pattern 190 may contain conductive material.

[0069] A first gate contact CB1 may be disposed on a first gate electrode G1. The first gate contact CB1 may extend vertically along DR3 through the cover pattern 113, and is therefore electrically connected to the first gate electrode G1. A second gate contact CB2 may be disposed on a second gate electrode G2. The second gate contact CB2 may extend vertically along DR3 through the cover pattern 113, and is therefore electrically connected to the second gate electrode G2. A third gate contact CB3 may be disposed on a third gate electrode G3. The third gate contact CB3 may extend vertically along DR3 through the cover pattern 113, and is therefore electrically connected to the third gate electrode G3. A fourth gate contact CB4 may be disposed on a fourth gate electrode G4. The fourth gate contact CB4 may extend vertically along DR3 through the cover pattern 113, and is therefore electrically connected to the fourth gate electrode G4.

[0070] The first embedded contact BC1 may be disposed on the first side of each of the first gate electrode G1 and the second gate electrode G2. The first embedded contact BC1 may be disposed between the third active pattern F3 and the fourth active pattern F4. The first embedded contact BC1 may protrude beyond the distal end of each of the third active pattern F3 and the fourth active pattern F4 in a direction opposite to the first horizontal direction DR1.

[0071] A first embedded contact BC1 may be disposed between a first lower source / drain region BSD1 and a second lower source / drain region BSD2. The first embedded contact BC1 may be electrically connected to each of the first lower source / drain region BSD1 and the second lower source / drain region BSD2. The first embedded contact BC1 may contain a conductive material. At least a portion of the first embedded contact BC1 may not overlap with each of the first lower source / drain region BSD1 and the second lower source / drain region BSD2 in the second horizontal direction DR2.

[0072] The second embedded contact BC2 may be disposed on the second side of each of the third gate electrode G3 and the fourth gate electrode G4. The second embedded contact BC2 may be disposed between the third active pattern F3 and the fourth active pattern F4. The second embedded contact BC2 may protrude beyond the distal end of each of the third active pattern F3 and the fourth active pattern F4 in the first horizontal direction DR1.

[0073] A second embedded contact BC2 may be disposed between the fifth lower source / drain region BSD5 and the sixth lower source / drain region. The second embedded contact BC2 may be electrically connected to each of the fifth lower source / drain region BSD5 and the sixth lower source / drain region. The second embedded contact BC2 may contain a conductive material. At least a portion of the second embedded contact BC2 may not overlap with each of the fifth lower source / drain region BSD5 and the sixth lower source / drain region in the second horizontal direction DR2.

[0074] Each of the first embedded contact BC1 and the second embedded contact BC2 may extend in the vertical direction DR3 through the first interlayer insulation layer 120 and the field insulation layer 105, and then extend into the interior of the substrate 100. That is, the bottom surface of each of the first embedded contact BC1 and the second embedded contact BC2 may be formed inside the substrate 100. However, the embodiments are not limited thereto. In some embodiments, each of the first embedded contact BC1 and the second embedded contact BC2 may extend in the vertical direction DR3 through the first interlayer insulation layer 120 and then extend into the field insulation layer 105. That is, the bottom surface of each of the first embedded contact BC1 and the second embedded contact BC2 may be formed inside the field insulation layer 105.

[0075] The top surface of each of the first embedded contact BC1 and the second embedded contact BC2 may be coplanar with the top surfaces of the lower source / drain regions BSD1 to BSD5. However, the embodiments are not limited thereto. In some embodiments, the vertical hierarchy of the top surface of each of the first embedded contact BC1 and the second embedded contact BC2 may be lower than the vertical hierarchy of the top surfaces of the lower source / drain regions BSD1 to BSD5.

[0076] The first lower source / drain contact BCA1 can be disposed on the first active pattern F1 and between the first gate electrode G1 and the third gate electrode G3. The first lower source / drain contact BCA1 can extend through the second interlayer insulating layer 130 in the vertical direction DR3, and is therefore electrically connected to the third lower source / drain region BSD3. The first lower source / drain contact BCA1 can be spaced apart from the third upper source / drain region TSD3.

[0077] The second lower source / drain contact BCA2 may be disposed on the sixth active pattern F6 and between the second gate electrode G2 and the fourth gate electrode G4. The second lower source / drain contact BCA2 may extend through the second interlayer insulating layer 130 in the vertical direction DR3, and is therefore electrically connected to the fourth lower source / drain region BSD4. The second lower source / drain contact BCA2 may be spaced apart from the fourth upper source / drain region TSD4. Each of the first lower source / drain contact BCA1 and the second lower source / drain contact BCA2 may contain conductive material.

[0078] A first upper source / drain contact TCA1 may be disposed on a first side of each of the first gate electrode G1 and the second gate electrode G2, and on the third active pattern F3 and the fourth active pattern F4. The first upper source / drain contact TCA1 may extend in the second horizontal direction DR2. The first upper source / drain contact TCA1 may extend in the vertical direction DR3 through a portion of the second interlayer insulation layer 130, and is therefore electrically connected to each of the first upper source / drain region TSD1 and the second upper source / drain region TSD2.

[0079] The second upper source / drain contact TCA2 may be disposed between the first gate electrode G1 and the second gate electrode G2 and the third gate electrode G3 and the fourth gate electrode G4, and on the third active pattern F3 and the fourth active pattern F4. The second upper source / drain contact TCA2 may extend in the second horizontal direction DR2. The second upper source / drain contact TCA2 may extend in the vertical direction DR3 through a portion of the second interlayer insulation layer 130, and is therefore electrically connected to each of the third upper source / drain region TSD3 and the fourth upper source / drain region TSD4.

[0080] The third upper source / drain contact TCA3 may be disposed on the second side of each of the third gate electrode G3 and the fourth gate electrode G4, and on the third active pattern F3 and the fourth active pattern F4. The third upper source / drain contact TCA3 may extend in the second horizontal direction DR2. The third upper source / drain contact TCA3 may extend in the vertical direction DR3 through a portion of the second interlayer insulation layer 130, and is therefore electrically connected to each of the fifth upper source / drain region TSD5 and the sixth upper source / drain region. Each of the first upper source / drain contacts TCA1 to the third upper source / drain contact TCA3 may contain conductive material.

[0081] A first through-hole V1 can be disposed on the first gate contact CB1. The first through-hole V1 can extend in the vertical direction DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the first gate contact CB1 and the first line pattern 180 to each other. A second through-hole V2 can be disposed on the second gate contact CB2. The second through-hole V2 can extend in the vertical direction DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the second gate contact CB2 and the first line pattern 180 to each other. A third through-hole V3 can be disposed on the third gate contact CB3. The third through-hole V3 can extend in the vertical direction DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the third gate contact CB3 and the first line pattern 180 to each other. A fourth through-hole V4 can be disposed on the fourth gate contact CB4. The fourth through-hole V4 can extend through the third interlayer insulating layer 150 and the etch stop layer 140 in the vertical direction DR3, thereby electrically connecting the fourth gate contact CB4 and the first line pattern 180 to each other.

[0082] A fifth via V5 can be disposed on the first lower source / drain contact BCA1. The fifth via V5 can extend vertically along DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the first lower source / drain contact BCA1 and the first line pattern 180 to each other. A sixth via V6 can be disposed on the second lower source / drain contact BCA2. The sixth via V6 can extend vertically along DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the second lower source / drain contact BCA2 and the first line pattern 180 to each other.

[0083] A seventh through-hole V7 may be disposed on the first embedded contact BC1. The seventh through-hole V7 may be disposed on a portion of the first embedded contact BC1 that protrudes beyond the distal end of each of the third active pattern F3 and the fourth active pattern F4 in a direction opposite to the first horizontal direction DR1. The seventh through-hole V7 may extend in the vertical direction DR3 through the fourth interlayer insulating layer 160, the third interlayer insulating layer 150, the etch stop layer 140, and the second interlayer insulating layer 130, thereby electrically connecting the first embedded contact BC1 and the second line pattern 190 to each other.

[0084] An eighth through-hole V8 may be disposed on the second embedded contact BC2. The eighth through-hole V8 may be disposed on a portion of the second embedded contact BC2 that protrudes beyond the distal ends of each of the third active pattern F3 and the fourth active pattern F4 in the first horizontal direction DR1. The eighth through-hole V8 may extend in the vertical direction DR3 through the fourth interlayer insulating layer 160, the third interlayer insulating layer 150, the etch stop layer 140, and the second interlayer insulating layer 130, thereby electrically connecting the second embedded contact BC2 and the second line pattern 190 to each other. The first embedded contact BC1 and the second embedded contact BC2 may be electrically connected to each other via the second line pattern 190.

[0085] A ninth via V9 can be disposed on the first upper source / drain contact TCA1. The ninth via V9 can extend vertically along DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the first upper source / drain contact TCA1 and the first line pattern 180 to each other. A tenth via V10 can be disposed on the second upper source / drain contact TCA2. The tenth via V10 can extend vertically along DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the second upper source / drain contact TCA2 and the first line pattern 180 to each other. An eleventh via V11 can be disposed on the third upper source / drain contact TCA3. The eleventh via V11 can extend vertically along DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the third upper source / drain contact TCA3 and the first line pattern 180 to each other.

[0086] In a semiconductor device according to some embodiments, in a structure where the lower source / drain region and the upper source / drain region are stacked vertically, the length of the upper source / drain region is longer than the length of the lower source / drain region, thereby improving the integration of the semiconductor device.

[0087] Furthermore, in a semiconductor device according to some embodiments, in a structure where the lower source / drain region and the upper source / drain region are stacked in the vertical direction, the buried contacts electrically connected to the lower source / drain region are disposed below the upper source / drain region, thereby improving the integration of the semiconductor device.

[0088] In the following description, a semiconductor device according to some other embodiments will be described with reference to FIG1 and FIGS10 through 16. The following description will be based on the differences from those descriptions of the semiconductor device illustrated in FIGS1 through 9.

[0089] Figure 10 is a layout diagram illustrating contacts connected to the lower source / drain region in a semiconductor device according to some other embodiments. Figure 11 is a layout diagram illustrating contacts connected to the upper source / drain region in a semiconductor device according to some other embodiments. Figure 12 is a cross-sectional view taken along line B-B' in each of Figures 10 and 11. Figure 13 is a cross-sectional view taken along line C-C' in each of Figures 10 and 11. Figure 14 is a cross-sectional view taken along line D-D' in each of Figures 10 and 11. Figure 15 is a cross-sectional view taken along line E-E' in each of Figures 10 and 11. Figure 16 is a cross-sectional view taken along line F-F' in each of Figures 10 and 11.

[0090] Referring to Figures 1, 10 to 16, in a semiconductor device according to some other embodiments, the region where a plurality of lower nanosheets (BNW) are disposed may be referred to as a PMOS region, and the region where a plurality of upper nanosheets (TNW) are disposed may be referred to as an NMOS region.

[0091] The first transistor TR1 may include multiple lower nanosheets (BNW) and a second gate electrode G2. The second transistor TR2 may include multiple lower nanosheets (BNW) and a first gate electrode G1. The third transistor TR3 may include multiple lower nanosheets (BNW) and a fourth gate electrode G4. The fourth transistor TR4 may include multiple lower nanosheets (BNW) and a third gate electrode G3.

[0092] Furthermore, the fifth transistor TR5 may include multiple upper nanosheets TNW and a second gate electrode G2. The sixth transistor TR6 may include multiple upper nanosheets TNW and a fourth gate electrode G4. The seventh transistor TR7 may include multiple upper nanosheets TNW and a first gate electrode G1. The eighth transistor TR8 may include multiple upper nanosheets TNW and a third gate electrode G3.

[0093] The third upper source / drain region TSD23 can be disposed on the third lower source / drain region BSD3 and between the first gate electrode G1 and the third gate electrode G3. The third upper source / drain region TSD23 can overlap with each of the first active pattern F1, the second active pattern F2, and the third active pattern F3 in the vertical direction DR3. The fourth upper source / drain region TSD24 can be disposed on the fourth lower source / drain region BSD4 and between the second gate electrode G2 and the fourth gate electrode G4. The fourth upper source / drain region TSD24 can overlap with each of the fourth active pattern F4, the fifth active pattern F5, and the sixth active pattern F6 in the vertical direction DR3.

[0094] The third upper source / drain region TSD23 can be disposed on the first active pattern F1 and between the first gate electrode G1 and the third gate electrode G3. In addition, the fourth upper source / drain region TSD24 can be disposed on the sixth active pattern F6 and between the second gate electrode G2 and the fourth gate electrode G4.

[0095] The third embedded contact BC23 can be disposed between the first gate electrode G1 and the second gate electrode G2 and the third gate electrode G3 and the fourth gate electrode G4. The third embedded contact BC23 can be disposed between the third active pattern F3 and the fourth active pattern F4. The third embedded contact BC23 can extend in the vertical direction DR3 through the first interlayer insulating layer 120 and the field insulating layer 105, and can extend into the interior of the substrate 100. The top surface of the third embedded contact BC23 can be coplanar with the top surface of each of the lower source / drain regions BSD1 to BSD5.

[0096] The fourth upper source / drain contact TCA24 can be disposed on the first active pattern F1 and between the first gate electrode G1 and the third gate electrode G3. The fourth upper source / drain contact TCA24 can extend in the vertical direction DR3 through a portion of the second interlayer insulation layer 130, and is therefore electrically connected to the third upper source / drain region TSD23.

[0097] The fifth upper source / drain contact TCA25 can be disposed on the sixth active pattern F6 and between the second gate electrode G2 and the fourth gate electrode G4. The fifth upper source / drain contact TCA25 can extend in the vertical direction DR3 through a portion of the second interlayer insulation layer 130, and is therefore electrically connected to the fourth upper source / drain region TSD24.

[0098] A fifth via V25 can be disposed on the fourth upper source / drain contact TCA24. The fifth via V25 can extend vertically along DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the fourth upper source / drain contact TCA24 and the first line pattern 180 to each other. A sixth via V26 can be disposed on the fifth upper source / drain contact TCA25. The sixth via V26 can extend vertically along DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the fifth upper source / drain contact TCA25 and the first line pattern 180 to each other.

[0099] A seventh via V27 may be disposed on the first embedded contact BC1. The seventh via V27 may be disposed on a portion of the first embedded contact BC1 that protrudes beyond the distal ends of each of the third active pattern F3 and the fourth active pattern F4 in a direction opposite to the first horizontal direction DR1. The seventh via V27 may extend in the vertical direction DR3 through the third interlayer insulating layer 150, the etch stop layer 140, and the second interlayer insulating layer 130, thereby electrically connecting the first embedded contact BC1 and the first line pattern 180 to each other.

[0100] An eighth through-hole V28 may be disposed on the second embedded contact BC2. The eighth through-hole V28 may be disposed on a portion of the second embedded contact BC2 that protrudes beyond the distal ends of each of the third active pattern F3 and the fourth active pattern F4 in the first horizontal direction DR1. The eighth through-hole V28 may extend in the vertical direction DR3 through the third interlayer insulating layer 150, the etch stop layer 140, and the second interlayer insulating layer 130, thereby creating an electrical connection between the second embedded contact BC2 and the first line pattern 180. A tenth through-hole V210 may be disposed on the third embedded contact BC23. The tenth through-hole V210 may extend in the vertical direction DR3 through the third interlayer insulating layer 150, the etch stop layer 140, and the second interlayer insulating layer 130, thereby creating an electrical connection between the third embedded contact BC23 and the first line pattern 180.

[0101] A ninth via V29 can be disposed on the first upper source / drain contact TCA1. The ninth via V29 extends vertically along DR3 through the fourth interlayer insulating layer 160, the third interlayer insulating layer 150, and the etch stop layer 140, thereby electrically connecting the first upper source / drain contact TCA1 and the second line pattern 190. An eleventh via V211 can be disposed on the third upper source / drain contact TCA3. The eleventh via V211 extends vertically along DR3 through the fourth interlayer insulating layer 160, the third interlayer insulating layer 150, and the etch stop layer 140, thereby electrically connecting the third upper source / drain contact TCA3 and the second line pattern 190. The first upper source / drain contact TCA1 and the third upper source / drain contact TCA3 can be electrically connected to each other via the second line pattern 190.

[0102] In the following description, a semiconductor device according to some other embodiments will be described with reference to Figures 1, 17 to 25. The following description will be based on the differences from those descriptions of the semiconductor device illustrated in Figures 1 to 9.

[0103] Figure 17 is a layout diagram illustrating contacts connected to the lower source / drain region in a semiconductor device according to some other embodiments. Figure 18 is a layout diagram illustrating contacts connected to the upper source / drain region in a semiconductor device according to some other embodiments. Figure 19 is a cross-sectional view taken along line G-G' in each of Figures 17 and 18. Figure 20 is a cross-sectional view taken along line H-H' in each of Figures 17 and 18. Figure 21 is a cross-sectional view taken along line I-I' in each of Figures 17 and 18. Figure 22 is a cross-sectional view taken along line J-J' in each of Figures 17 and 18. Figure 23 is a cross-sectional view taken along line K-K' in each of Figures 17 and 18. Figure 24 is a cross-sectional view taken along line L-L' in each of Figures 17 and 18. Figure 25 is a cross-sectional view taken along line M-M' in each of Figures 17 and 18.

[0104] Referring to Figures 1, 17 to 25, in a semiconductor device according to some other embodiments, the first gate electrode G31 to the fourth gate electrode G34 may be disposed on the second horizontal direction DR2.

[0105] Each of the first active patterns F31 to the twelfth active patterns F312 may protrude from the base 100 in the vertical direction DR3. Each of the first active patterns F31 to the twelfth active patterns F312 may extend in the first horizontal direction DR1. The first active patterns F31 to the twelfth active patterns F312 may be arranged sequentially and spaced apart from each other in the second horizontal direction DR2.

[0106] For example, the first active pattern F31, the second active pattern F32, and the third active pattern F33 may be spaced apart by the same distance. The fourth active pattern F34, the fifth active pattern F35, and the sixth active pattern F36 may be spaced apart by the same distance. The seventh active pattern F37, the eighth active pattern F38, and the ninth active pattern F39 may be spaced apart by the same distance. The tenth active pattern F310, the eleventh active pattern F311, and the twelfth active pattern F312 may be spaced apart by the same distance.

[0107] For example, the spacing between the third active pattern F33 and the fourth active pattern F34, the spacing between the sixth active pattern F36 and the seventh active pattern F37, and the spacing between the ninth active pattern F39 and the tenth active pattern F310 may be greater than the spacing between the second active pattern F32 and the third active pattern F33.

[0108] The first gate electrode G31 can extend along the second horizontal direction DR2 and can be disposed on the first active pattern F31, the second active pattern F32, and the third active pattern F33. The second gate electrode G32 can extend along the second horizontal direction DR2 and can be disposed on the fourth active pattern F34, the fifth active pattern F35, and the sixth active pattern F36. The third gate electrode G33 can extend along the second horizontal direction DR2 and can be disposed on the seventh active pattern F37, the eighth active pattern F38, and the ninth active pattern F39. The fourth gate electrode G34 can extend along the second horizontal direction DR2 and can be disposed on the tenth active pattern F310, the eleventh active pattern F311, and the twelfth active pattern F312. The first gate electrode G31 to the fourth gate electrode G34 can be sequentially spaced apart from each other along the second horizontal direction DR2.

[0109] The first transistor TR1 may include multiple upper nanosheets TNW and a fourth gate electrode G34. The second transistor TR2 may include multiple upper nanosheets TNW and a third gate electrode G33. The third transistor TR3 may include multiple upper nanosheets TNW and a second gate electrode G32. The fourth transistor TR4 may include multiple upper nanosheets TNW and a first gate electrode G31.

[0110] Furthermore, the fifth transistor TR5 may include multiple lower nanosheets (BNW) and a fourth gate electrode G34. The sixth transistor TR6 may include multiple lower nanosheets (BNW) and a second gate electrode G32. The seventh transistor TR7 may include multiple lower nanosheets (BNW) and a third gate electrode G33. The eighth transistor TR8 may include multiple lower nanosheets (BNW) and a first gate electrode G31.

[0111] The first gate cutout GC31 can be positioned between the first gate electrode G31 and the second gate electrode G32. The second gate cutout GC32 can be positioned between the second gate electrode G32 and the third gate electrode G33. The third gate cutout GC33 can be positioned between the third gate electrode G33 and the fourth gate electrode G34.

[0112] The first lower source / drain region BSD31 can be disposed on the first side of the first gate electrode G31 and on each of the first active patterns F31 to the third active patterns F33. The second lower source / drain region BSD32 can be disposed on the first side of the second gate electrode G32 and on each of the fourth active patterns F34 to the sixth active patterns F36. The third lower source / drain region BSD33 can be disposed on the first side of the third gate electrode G33 and on each of the seventh active patterns F37 to the ninth active patterns F39. The fourth lower source / drain region BSD34 can be disposed on the first side of the fourth gate electrode G34 and on each of the tenth active patterns F10 to the twelfth active patterns F12. The first lower source / drain regions BSD31 to the fourth lower source / drain regions BSD34 can be spaced apart from each other in the second horizontal direction DR2.

[0113] The fifth lower source / drain region BSD35 can be disposed on the second side of the first gate electrode G31 and on each of the first active patterns F31 to the third active patterns F33. The sixth lower source / drain region BSD36 can be disposed on the second side of the second gate electrode G32 and on each of the fourth active patterns F34 to the sixth active patterns F36. The seventh lower source / drain region BSD37 can be disposed on the second side of the third gate electrode G33 and on each of the seventh active patterns F37 to the ninth active patterns F39. The eighth lower source / drain region BSD38 can be disposed on the second side of the fourth gate electrode G34 and on each of the tenth active patterns F10 to the twelfth active patterns F12. The fifth lower source / drain regions BSD35 to the eighth lower source / drain regions BSD38 can be spaced apart from each other in the second horizontal direction DR2.

[0114] The first upper source / drain region TSD31 can be disposed on the first side of the first gate electrode G31 and on the first lower source / drain region BSD31. The first upper source / drain region TSD31 can be disposed off-center from the first active pattern F31. The second upper source / drain region TSD32 can be disposed on the first side of the second gate electrode G32 and on the second lower source / drain region BSD32. The second upper source / drain region TSD32 can be disposed off-center from the sixth active pattern F36. The third upper source / drain region TSD33 can be disposed on the first side of the third gate electrode G33 and on the third lower source / drain region BSD33. The third upper source / drain region TSD33 can be disposed off-center from the seventh active pattern F37. The fourth upper source / drain region TSD34 can be disposed on the first side of the fourth gate electrode G34 and on the fourth lower source / drain region BSD34. The fourth upper source / drain region TSD34 may not be placed on the twelfth active pattern F312. The first upper source / drain region TSD31 to the fourth upper source / drain region TSD34 may be spaced apart from each other in the second horizontal direction DR2.

[0115] The fifth upper source / drain region TSD35 can be disposed on the second side of the first gate electrode G31 and on the fifth lower source / drain region BSD35. The sixth upper source / drain region TSD36 can be disposed on the second side of the second gate electrode G32 and on the sixth lower source / drain region BSD36. The seventh upper source / drain region TSD37 can be disposed on the second side of the third gate electrode G33 and on the seventh lower source / drain region BSD37. The eighth upper source / drain region TSD38 can be disposed on the second side of the fourth gate electrode G34 and on the eighth lower source / drain region BSD38. The fifth upper source / drain region TSD35 to the eighth upper source / drain region TSD38 can be spaced apart from each other in the second horizontal direction DR2.

[0116] The length along the second horizontal direction DR2 from the sidewall of the first lower source / drain region BSD31 mounted on the first active pattern F31 to the sidewall of the second lower source / drain region BSD32 mounted on the sixth active pattern F36 can be referred to as the fourth length L4. Furthermore, the length along the second horizontal direction DR2 from the sidewall of the first upper source / drain region TSD31 mounted on the second active pattern F32 to the sidewall of the second upper source / drain region TSD32 mounted on the fifth active pattern F35 can be referred to as the third length L3.

[0117] On the first side of each of the first gate electrode G31 and the second gate electrode G32, the fourth length L4 of the lower source / drain region in the second horizontal direction DR2 may be longer than the third length L3 of the upper source / drain region in the second horizontal direction DR2. Furthermore, the fourth length L4 of the lower source / drain region in the second horizontal direction DR2 may be shorter than three times the third length L3 of the upper source / drain region in the second horizontal direction DR2.

[0118] Each of the third lower source / drain region BSD33, the fourth lower source / drain region BSD34, the third upper source / drain region TSD33, and the fourth upper source / drain region TSD34 may have a structure similar to that of each of the first lower source / drain region BSD31, the second lower source / drain region BSD32, the first upper source / drain region TSD31, and the second upper source / drain region TSD32.

[0119] The first gate contact CB31 can be disposed on the first gate electrode G31. The second gate contact CB32 can be disposed on the second gate electrode G32. The third gate contact CB33 can be disposed on the third gate electrode G33. The fourth gate contact CB34 can be disposed on the fourth gate electrode G34.

[0120] The first embedded contact BC31 may be disposed on the second side of each of the first gate electrode G31 and the second gate electrode G32. The first embedded contact BC31 may be disposed between the third active pattern F33 and the fourth active pattern F34. The first embedded contact BC31 may protrude in the first horizontal direction DR1 beyond the distal ends of each of the third active pattern F33 and the fourth active pattern F34.

[0121] The second embedded contact BC32 may be disposed on the second side of each of the third gate electrode G33 and the fourth gate electrode G34. The second embedded contact BC32 may be disposed between the ninth active pattern F39 and the tenth active pattern F310. The second embedded contact BC32 may protrude in the first horizontal direction DR1 beyond the distal ends of each of the ninth active pattern F39 and the tenth active pattern F310.

[0122] Each of the first embedded contact BC31 and the second embedded contact BC32 may extend in the vertical direction DR3 through the first interlayer insulation layer 120 and the field insulation layer 105, and then extend into the interior of the substrate 100. The top surface of each of the first embedded contact BC31 and the second embedded contact BC32 may be coplanar with the top surface of each of the lower source / drain regions BSD31 to BSD38.

[0123] The first lower source / drain contact BCA31 can be disposed on the first active pattern F31 and on the first side of the first gate electrode G31. The first lower source / drain contact BCA31 can extend through the second interlayer insulating layer 130 in the vertical direction DR3 and can be electrically connected to the first lower source / drain region BSD31. The first lower source / drain contact BCA31 can be spaced apart from the first upper source / drain region TSD31.

[0124] The second lower source / drain contact BCA32 can be disposed on the first side of the second gate electrode G32 and on the sixth active pattern F36. The second lower source / drain contact BCA32 can extend through the second interlayer insulating layer 130 in the vertical direction DR3 and can be electrically connected to the second lower source / drain region BSD32. The second lower source / drain contact BCA32 can be spaced apart from the second upper source / drain region TSD32.

[0125] The third lower source / drain contact BCA33 can be disposed on the first side of the third gate electrode G33 and on the seventh active pattern F37. The third lower source / drain contact BCA33 can extend through the second interlayer insulating layer 130 in the vertical direction DR3 and can be electrically connected to the third lower source / drain region BSD33. The third lower source / drain contact BCA33 can be spaced apart from the third upper source / drain region TSD33.

[0126] The fourth lower source / drain contact BCA34 can be disposed on the twelfth active pattern F312 and on the first side of the fourth gate electrode G34. The fourth lower source / drain contact BCA34 can extend through the second interlayer insulating layer 130 in the vertical direction DR3 and can be electrically connected to the fourth lower source / drain region BSD34. The fourth lower source / drain contact BCA34 can be spaced apart from the fourth upper source / drain region TSD34.

[0127] The first upper source / drain contact TCA31 may be disposed on the first side of each of the first gate electrode G31 and the second gate electrode G32, and on the third active pattern F33 and the fourth active pattern F34. The first upper source / drain contact TCA31 may extend in the vertical direction DR3 through a portion of the second interlayer insulating layer 130, and may be electrically connected to each of the first upper source / drain region TSD31 and the second upper source / drain region TSD32.

[0128] The second upper source / drain contact TCA32 may be disposed on the first side of each of the third gate electrode G33 and the fourth gate electrode G34, and on the ninth active pattern F39 and the tenth active pattern F310. The second upper source / drain contact TCA32 may extend in the vertical direction DR3 through a portion of the second interlayer insulation layer 130, and may be electrically connected to each of the third upper source / drain region TSD33 and the fourth upper source / drain region TSD34.

[0129] The third upper source / drain contact TCA33 may be disposed on the second side of each of the first gate electrode G31 and the second gate electrode G32, and on the third active pattern F33 and the fourth active pattern F34. The third upper source / drain contact TCA33 may extend in the vertical direction DR3 through a portion of the second interlayer insulation layer 130, and may be electrically connected to each of the fifth upper source / drain region TSD35 and the sixth upper source / drain region TSD36.

[0130] The fourth upper source / drain contact TCA34 may be disposed on the second side of each of the ninth active pattern F39 and the tenth active pattern F310, and the third gate electrode G33 and the fourth gate electrode G34. The fourth upper source / drain contact TCA34 may extend in the vertical direction DR3 through a portion of the second interlayer insulation layer 130, and may be electrically connected to each of the seventh upper source / drain region TSD37 and the eighth upper source / drain region TSD38.

[0131] The first through hole V31 can be installed on the first gate contact CB31. The second through hole V32 can be installed on the second gate contact CB32. The third through hole V33 can be installed on the third gate contact CB33. The fourth through hole V34 can be installed on the fourth gate contact CB34.

[0132] A fifth via V35 can be disposed on the first lower source / drain contact BCA31. The fifth via V35 extends vertically along DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the first lower source / drain contact BCA31 and the first line pattern 180 to each other. A sixth via V36 can be disposed on the second lower source / drain contact BCA32. The sixth via V36 extends vertically along DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the second lower source / drain contact BCA32 and the first line pattern 180 to each other.

[0133] A seventh via V37 can be disposed on the third lower source / drain contact BCA33. The seventh via V37 can extend vertically along DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the third lower source / drain contact BCA33 and the first line pattern 180 to each other. An eighth via V38 can be disposed on the fourth lower source / drain contact BCA34. The eighth via V38 can extend vertically along DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the fourth lower source / drain contact BCA34 and the first line pattern 180 to each other.

[0134] A ninth through-hole V39 may be disposed on the first embedded contact BC31. The ninth through-hole V39 may be disposed on a portion of the first embedded contact BC31 that protrudes beyond the distal ends of each of the third active pattern F33 and the fourth active pattern F34 in the first horizontal direction DR1. The ninth through-hole V39 may extend in the vertical direction DR3 through the fourth interlayer insulating layer 160, the third interlayer insulating layer 150, the etch stop layer 140, and the second interlayer insulating layer 130, thereby electrically connecting the first embedded contact BC31 and the second line pattern 190 to each other.

[0135] A tenth through-hole V310 may be disposed on the second embedded contact BC32. The tenth through-hole V310 may be disposed on a portion of the second embedded contact BC32 that protrudes beyond the distal ends of each of the ninth active pattern F39 and the tenth active pattern F310 in the first horizontal direction DR1. The tenth through-hole V310 may extend in the vertical direction DR3 through the fourth interlayer insulating layer 160, the third interlayer insulating layer 150, the etch stop layer 140, and the second interlayer insulating layer 130, such that the second embedded contact BC32 and the second line pattern 190 can be electrically connected to each other via the tenth through-hole V310. The first embedded contact BC31 and the second embedded contact BC32 can be electrically connected to each other via the second line pattern 190.

[0136] An eleventh via V311 can be disposed on the first upper source / drain contact TCA31. The eleventh via V311 extends vertically along DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the first upper source / drain contact TCA31 and the first line pattern 180 to each other. A twelfth via V312 can be disposed on the second upper source / drain contact TCA32. The twelfth via V312 extends vertically along DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the second upper source / drain contact TCA32 and the first line pattern 180 to each other.

[0137] The thirteenth via V313 can be disposed on the third upper source / drain contact TCA33. The thirteenth via V313 can extend in the vertical direction DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the third upper source / drain contact TCA33 and the first line pattern 180 to each other. The fourteenth via V314 can be disposed on the fourth upper source / drain contact TCA34. The fourteenth via V314 can extend in the vertical direction DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the fourth upper source / drain contact TCA34 and the first line pattern 180 to each other.

[0138] In the following description, a semiconductor device according to some other embodiments will be described with reference to Figures 1, 26 to 33. The following description will be based on the differences from those descriptions of the semiconductor device illustrated in Figures 17 to 25.

[0139] Figure 26 is a layout diagram illustrating contacts connected to the lower source / drain region in a semiconductor device according to some other embodiments. Figure 27 is a layout diagram illustrating contacts connected to the upper source / drain region in a semiconductor device according to some other embodiments. Figure 28 is a cross-sectional view taken along line H-H' in each of Figures 26 and 27. Figure 29 is a cross-sectional view taken along line I-I' in each of Figures 26 and 27. Figure 30 is a cross-sectional view taken along line J-J' in each of Figures 26 and 27. Figure 31 is a cross-sectional view taken along line K-K' in each of Figures 26 and 27. Figure 32 is a cross-sectional view taken along line L-L' in each of Figures 26 and 27. Figure 33 is a cross-sectional view taken along line M-M' in each of Figures 26 and 27.

[0140] Referring to Figures 1, 26 to 33, in a semiconductor device according to some other embodiments, the region where a plurality of lower nanosheets BNW are disposed may be referred to as a PMOS region, and the region where a plurality of upper nanosheets TNW are disposed may be referred to as an NMOS region.

[0141] The first transistor TR1 may include multiple lower nanosheets (BNW) and a fourth gate electrode G34. The second transistor TR2 may include multiple lower nanosheets (BNW) and a third gate electrode G33. The third transistor TR3 may include multiple lower nanosheets (BNW) and a second gate electrode G32. The fourth transistor TR4 may include multiple lower nanosheets (BNW) and a first gate electrode G31.

[0142] Furthermore, the fifth transistor TR5 may include multiple upper nanosheets TNW and a fourth gate electrode G34. The sixth transistor TR6 may include multiple upper nanosheets TNW and a second gate electrode G32. The seventh transistor TR7 may include multiple upper nanosheets TNW and a third gate electrode G33. The eighth transistor TR8 may include multiple upper nanosheets TNW and a first gate electrode G31.

[0143] The first upper source / drain region TSD41 can be disposed on the first side of the first gate electrode G31 and on the first lower source / drain region BSD31. The first upper source / drain region TSD41 can overlap with the first active pattern F31 to the third active pattern F33 in the vertical direction DR3. The second upper source / drain region TSD42 can be disposed on the first side of the second gate electrode G32 and on the second lower source / drain region BSD32. The second upper source / drain region TSD42 can overlap with the fourth active pattern F34 to the sixth active pattern F36 in the vertical direction DR3.

[0144] The third upper source / drain region TSD43 can be disposed on the first side of the third gate electrode G33 and on the third lower source / drain region BSD33. The third upper source / drain region TSD43 can overlap with the seventh active pattern F37 to the ninth active pattern F39 in the vertical direction DR3. The fourth upper source / drain region TSD44 can be disposed on the first side of the fourth gate electrode G34 and on the fourth lower source / drain region BSD34. The fourth upper source / drain region TSD44 can overlap with the tenth active pattern F310 to the twelfth active pattern F312 in the vertical direction DR3. The first upper source / drain region TSD41 to the fourth upper source / drain region TSD44 can be spaced apart from each other in the second horizontal direction DR2.

[0145] The third embedded contact BC43 may be disposed on the first side of each of the first gate electrode G31 and the second gate electrode G32. The third embedded contact BC43 may be disposed between the third active pattern F33 and the fourth active pattern F34. The third embedded contact BC43 may protrude beyond the distal ends of each of the third active pattern F33 and the fourth active pattern F34 in a direction opposite to the first horizontal direction DR1.

[0146] The fourth embedded contact BC44 may be disposed on the first side of each of the third gate electrode G33 and the fourth gate electrode G34. The fourth embedded contact BC44 may be disposed between the ninth active pattern F39 and the tenth active pattern F310. The fourth embedded contact BC44 may protrude beyond the distal ends of each of the ninth active pattern F39 and the tenth active pattern F310 in a direction opposite to the first horizontal direction DR1.

[0147] Each of the third embedded contact BC43 and the fourth embedded contact BC44 may extend in the vertical direction DR3 through the first interlayer insulation layer 120 and the field insulation layer 105, and then extend into the interior of the substrate 100. Each of the third embedded contact BC43 and the fourth embedded contact BC44 may have a top surface that is coplanar with the top surface of each of the lower source / drain regions BSD31 to BSD38.

[0148] The fifth upper source / drain contact TCA45 can be disposed on the first active pattern F31 and on the first side of the first gate electrode G31. The fifth upper source / drain contact TCA45 can extend vertically in the direction DR3 through a portion of the second interlayer insulating layer 130 and can be electrically connected to the first upper source / drain region TSD41. The sixth upper source / drain contact TCA46 can be disposed on the sixth active pattern F36 and on the first side of the second gate electrode G32. The sixth upper source / drain contact TCA46 can extend vertically in the direction DR3 through a portion of the second interlayer insulating layer 130 and can be electrically connected to the second upper source / drain region TSD42.

[0149] The seventh upper source / drain contact TCA47 can be disposed on the seventh active pattern F37 and on the first side of the third gate electrode G33. The seventh upper source / drain contact TCA47 can extend vertically in the direction DR3 through a portion of the second interlayer insulation layer 130, and is therefore electrically connected to the third upper source / drain region TSD43. The eighth upper source / drain contact TCA48 can be disposed on the twelfth active pattern F312 and on the first side of the fourth gate electrode G34. The eighth upper source / drain contact TCA48 can extend vertically in the direction DR3 through a portion of the second interlayer insulation layer 130, and is electrically connected to the fourth upper source / drain region TSD44.

[0150] A ninth via V49 may be disposed on the first embedded contact BC31. The ninth via V49 may be disposed on a portion of the first embedded contact BC31 that protrudes beyond the distal ends of each of the third active pattern F33 and the fourth active pattern F34 in the first horizontal direction DR1. The ninth via V49 may extend in the vertical direction DR3 through the third interlayer insulating layer 150, the etch stop layer 140, and the second interlayer insulating layer 130, thereby electrically connecting the first embedded contact BC31 and the first line pattern 180 to each other.

[0151] A tenth through-hole V410 may be disposed on the second embedded contact BC32. The tenth through-hole V410 may be disposed on a portion of the second embedded contact BC32 that protrudes beyond the distal ends of each of the ninth active pattern F39 and the tenth active pattern F310 in the first horizontal direction DR1. The tenth through-hole V410 may extend in the vertical direction DR3 through the third interlayer insulating layer 150, the etch stop layer 140, and the second interlayer insulating layer 130, thereby electrically connecting the second embedded contact BC32 and the first line pattern 180 to each other.

[0152] The eleventh via V411 may be disposed on the third embedded contact BC43. The eleventh via V411 may be disposed on a portion of the third embedded contact BC43 that protrudes beyond the distal ends of each of the third active pattern F33 and the fourth active pattern F34 in a direction opposite to the first horizontal direction DR1. The eleventh via V411 may extend in the vertical direction DR3 through the third interlayer insulating layer 150, the etch stop layer 140, and the second interlayer insulating layer 130, thereby creating an electrical connection between the third embedded contact BC43 and the first line pattern 180.

[0153] A twelfth through-hole V412 may be disposed on the fourth embedded contact BC44. The twelfth through-hole V412 may be disposed on a portion of the fourth embedded contact BC44 that protrudes beyond the distal ends of each of the ninth active pattern F39 and the tenth active pattern F310 in a direction opposite to the first horizontal direction DR1. The twelfth through-hole V412 may extend in the vertical direction DR3 through the third interlayer insulating layer 150, the etch stop layer 140, and the second interlayer insulating layer 130, thereby electrically connecting the fourth embedded contact BC44 and the first line pattern 180 to each other.

[0154] A thirteenth via V413 can be disposed on the third upper source / drain contact TCA33. The thirteenth via V413 extends vertically along DR3 through the fourth interlayer insulating layer 160, the third interlayer insulating layer 150, and the etch stop layer 140, thereby electrically connecting the third upper source / drain contact TCA33 to the second line pattern 190. A fourteenth via V414 can be disposed on the fourth upper source / drain contact TCA34. The fourteenth via V414 extends vertically along DR3 through the fourth interlayer insulating layer 160, the third interlayer insulating layer 150, and the etch stop layer 140, thereby electrically connecting the fourth upper source / drain contact TCA34 to the second line pattern 190. The third upper source / drain contact TCA33 and the fourth upper source / drain contact TCA34 can be electrically connected to each other via the second line pattern 190.

[0155] In the following description, a semiconductor device according to some other embodiments will be described with reference to Figures 34 to 37. The following description will be based on the differences from those descriptions of the semiconductor devices illustrated in Figures 1 to 9.

[0156] Figure 34 is a layout diagram illustrating a semiconductor device according to some other embodiments. Figure 35 is a cross-sectional view taken along line N-N' in Figure 34. Figure 36 is a cross-sectional view taken along line O-O' in Figure 34. Figure 37 is a cross-sectional view taken along line P-P' in Figure 34.

[0157] Referring to Figures 34 to 37, a semiconductor device according to some other embodiments may include two gate electrodes G51 and G52.

[0158] Each of the first active patterns F51 to the eighth active patterns F58 may protrude from the base 100 in the vertical direction DR3. Each of the first active patterns F51 to the eighth active patterns F58 may extend in the first horizontal direction DR1. Each of the first active patterns F51 to the eighth active patterns F58 may be sequentially arranged and spaced apart from each other in the second horizontal direction DR2.

[0159] For example, the first active pattern F51, the second active pattern F52, the third active pattern F53, and the fourth active pattern F54 may be spaced apart by the same distance. The fifth active pattern F55, the sixth active pattern F56, the seventh active pattern F57, and the eighth active pattern F58 may be spaced apart by the same distance. For example, the distance between the fourth active pattern F54 and the fifth active pattern F55 may be greater than the distance between the third active pattern F53 and the fourth active pattern F54.

[0160] The first gate electrode G51 may extend along the second horizontal direction DR2 and may be disposed on the first active pattern F51, the second active pattern F52, the third active pattern F53, and the fourth active pattern F54. The second gate electrode G52 may extend along the second horizontal direction DR2 and may be disposed on the fifth active pattern F55, the sixth active pattern F56, the seventh active pattern F57, and the eighth active pattern F58. The second gate electrode G52 may be spaced apart from the first gate electrode G51 along the second horizontal direction DR2. The gate cutout GC51 may be disposed between the first gate electrode G51 and the second gate electrode G52.

[0161] The first lower source / drain region BSD51 may be disposed on the first side of the first gate electrode G51 and on each of the first active pattern F51, the second active pattern F52, the third active pattern F53, and the fourth active pattern F54. The second lower source / drain region BSD52 may be disposed on the first side of the second gate electrode G52 and on each of the fifth active pattern F55, the sixth active pattern F56, the seventh active pattern F57, and the eighth active pattern F58. The second lower source / drain region BSD52 may be spaced apart from the first lower source / drain region BSD51 in the second horizontal direction DR2.

[0162] The third lower source / drain region BSD53 may be disposed on the second side of the first gate electrode G51 and on each of the first active pattern F51, the second active pattern F52, the third active pattern F53, and the fourth active pattern F54. The fourth lower source / drain region BSD54 may be disposed on the second side of the second gate electrode G52 and on each of the fifth active pattern F55, the sixth active pattern F56, the seventh active pattern F57, and the eighth active pattern F58. The fourth lower source / drain region BSD54 may be spaced apart from the third lower source / drain region BSD53 in the second horizontal direction DR2.

[0163] The first upper source / drain region TSD51 can be disposed on the first side of the first gate electrode G51 and on the first lower source / drain region BSD51. The first upper source / drain region TSD51 may not be disposed on the first active pattern F51. The second upper source / drain region TSD52 can be disposed on the first side of the second gate electrode G52 and on the second lower source / drain region BSD52. The second upper source / drain region TSD52 may not be disposed on the eighth active pattern F58.

[0164] The third upper source / drain region TSD53 can be disposed on the second side of the first gate electrode G51 and on the third lower source / drain region BSD53. The third upper source / drain region TSD53 may not be disposed on the fourth active pattern F54. The fourth upper source / drain region TSD54 can be disposed on the second side of the second gate electrode G52 and on the fourth lower source / drain region BSD54. The fourth upper source / drain region TSD54 may not be disposed on the eighth active pattern F58.

[0165] The length along the second horizontal direction DR2 from the sidewall of the first lower source / drain region BSD51 mounted on the first active pattern F51 to the sidewall of the second lower source / drain region BSD52 mounted on the eighth active pattern F58 can be referred to as the sixth length L6. Furthermore, the length along the second horizontal direction DR2 from the sidewall of the first upper source / drain region TSD51 mounted on the second active pattern F52 to the sidewall of the second upper source / drain region TSD52 mounted on the seventh active pattern F57 can be referred to as the fifth length L5. Furthermore, the length along the second horizontal direction DR2 from the sidewall of the third upper source / drain region TSD53 mounted on the first active pattern F51 to the sidewall of the fourth upper source / drain region TSD54 mounted on the seventh active pattern F57 can be referred to as the seventh length L7.

[0166] On the first side of each of the first gate electrode G51 and the second gate electrode G52, the sixth length L6 of the lower source / drain region in the second horizontal direction DR2 may be longer than the fifth length L5 of the upper source / drain region in the second horizontal direction DR2. Furthermore, the sixth length L6 of the lower source / drain region in the second horizontal direction DR2 may be shorter than three times the fifth length L5 of the upper source / drain region in the second horizontal direction DR2.

[0167] On the second side of each of the first gate electrode G51 and the second gate electrode G52, the sixth length L6 of the lower source / drain region in the second horizontal direction DR2 may be longer than the seventh length L7 of the upper source / drain region in the second horizontal direction DR2. Furthermore, the sixth length L6 of the lower source / drain region in the second horizontal direction DR2 may be shorter than three times the seventh length L7 of the upper source / drain region in the second horizontal direction DR2.

[0168] A first gate contact CB51 may be disposed on a first gate electrode G51. A second gate contact CB52 may be disposed on a second gate electrode G52. A first lower source / drain contact BCA51 may be disposed on a first active pattern F51 and on a first side of the first gate electrode G51. The first lower source / drain contact BCA51 may extend through the second interlayer insulating layer 130 in the vertical direction DR3 and may be electrically connected to the first lower source / drain region BSD51. The first lower source / drain contact BCA51 may be spaced apart from the first upper source / drain region TSD51.

[0169] The second lower source / drain contact BCA52 can be disposed on the eighth active pattern F58 and on the first side of the second gate electrode G52. The second lower source / drain contact BCA52 can extend through the second interlayer insulating layer 130 in the vertical direction DR3 and can be electrically connected to the second lower source / drain region BSD52. The second lower source / drain contact BCA52 can be spaced apart from the second upper source / drain region TSD52.

[0170] The third lower source / drain contact BCA53 can be disposed on the fourth active pattern F54 and on the second side of the first gate electrode G51. The third lower source / drain contact BCA53 can extend through the second interlayer insulating layer 130 in the vertical direction DR3 and can be electrically connected to the third lower source / drain region BSD53. The third lower source / drain contact BCA53 can be spaced apart from the third upper source / drain region TSD53.

[0171] The fourth lower source / drain contact BCA54 can be disposed on the fifth active pattern F55 and on the second side of the second gate electrode G52. The fourth lower source / drain contact BCA54 can extend through the second interlayer insulating layer 130 in the vertical direction DR3 and can be electrically connected to the fourth lower source / drain region BSD54. The fourth lower source / drain contact BCA54 can be spaced apart from the fourth upper source / drain region TSD54.

[0172] The first upper source / drain contact TCA51 may be disposed on the first side of each of the first gate electrode G51 and the second gate electrode G52, as well as on the third active pattern F53 and the fourth active pattern F54. The first upper source / drain contact TCA51 may extend in the vertical direction DR3 through a portion of the second interlayer insulating layer 130 and may be electrically connected to the first upper source / drain region TSD51 and the second upper source / drain region TSD52.

[0173] The second upper source / drain contact TCA52 can be disposed on the first active pattern F51 and on the second side of the first gate electrode G51. The third upper source / drain contact TCA53 can extend in the vertical direction DR3 through a portion of the second interlayer insulation layer 130 and can be electrically connected to the third upper source / drain region TSD53.

[0174] A first through-hole V51 can be disposed on the first gate contact CB51. A second through-hole V52 can be disposed on the second gate contact CB52. A third through-hole V53 can be disposed on the first lower source / drain contact BCA51. The third through-hole V53 can extend in the vertical direction DR3 through the fourth interlayer insulating layer 160, the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the first lower source / drain contact BCA51 and the second line pattern 190 to each other.

[0175] A fourth via V54 can be disposed on the second lower source / drain contact BCA52. The fourth via V54 can extend in the vertical direction DR3 through the fourth interlayer insulating layer 160, the third interlayer insulating layer 150, and the etch stop layer 140, thereby electrically connecting the second lower source / drain contact BCA54 and the second line pattern 190 to each other. The first lower source / drain contact BCA51 and the second lower source / drain contact BCA52 can be electrically connected to each other via the second line pattern 190.

[0176] The fifth via V55 can be disposed on the third lower source / drain contact BCA53. The fifth via V55 can extend in the vertical direction DR3 through the fourth interlayer insulating layer 160, the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the third lower source / drain contact BCA53 and the second line pattern 190 to each other.

[0177] The sixth via V56 can be disposed on the fourth lower source / drain contact BCA54. The sixth via V56 can extend in the vertical direction DR3 through the fourth interlayer insulating layer 160, the third interlayer insulating layer 150, and the etch stop layer 140, thereby electrically connecting the fourth lower source / drain contact BCA54 and the second line pattern 190 to each other. The third lower source / drain contact BCA53 and the fourth lower source / drain contact BCA54 can be electrically connected to each other via the second line pattern 190.

[0178] A seventh via V57 can be disposed on the first upper source / drain contact TCA51. The seventh via V57 extends vertically along DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the first upper source / drain contact TCA51 and the first line pattern 180 to each other. An eighth via V58 can be disposed on the second upper source / drain contact TCA52. The eighth via V58 extends vertically along DR3 through the third interlayer insulating layer 150 and the etch stop layer 140, thereby electrically connecting the second upper source / drain contact TCA52 and the first line pattern 180 to each other.

[0179] Although various embodiments have been specifically illustrated and described, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0180] 100: Base 105: Field insulation layer 111: Gate insulation layer 112: Gate spacer 113: Cover pattern 120: First interlayer insulation layer 130: Second interlayer insulation layer 140: Etching stop layer 150: Third interlayer insulation layer 160: Fourth interlayer insulation layer 170: Fifth interlayer insulation layer 180: First line pattern 190: Second line pattern A-A', B-B', C-C', D-D', E-E', F-F', G-G', H-H', I-I', J-J', K-K', L-L', M-M', N-N', O-O', P-P': lines BC1, BC31: First embedded contact BC2, BC32: Second embedded contact BC23, BC43: Third embedded contact BC44: Fourth Embedded Contact Point BCA1, BCA31, BCA51: First lower source / drain contact BCA2, BCA32, BCA52: Second lower source / drain contact BCA33, BCA53: Third lower source / drain contact BCA34, BCA54: Fourth lower source / drain contact BNW: Lower Nanosheet BSD1, BSD31, BSD51: First Lower Source / Drain Region BSD2, BSD32, BSD52: Second Lower Source / Drain Region BSD3, BSD33, BSD53: Third Lower Source / Drain Region BSD4, BSD34, BSD54: Fourth Lower Source / Drain Region BSD5, BSD35: Fifth Lower Source / Drain Region BSD36: Sixth Lower Source / Drain Region BSD37: Seventh Lower Source / Drain Region BSD38: Eighth Lower Source / Drain Region CB1, CB31, CB51: First gate contact CB2, CB32, CB52: Second gate contact CB3, CB33: Third gate contact CB4, CB34: Fourth gate contact DR1: First horizontal direction DR2: Second horizontal direction DR3: Vertical direction F1, F31, F51: First active pattern F2, F32, F52: Second active pattern F3, F33, F53: Third active pattern F4, F34, F54: Fourth active pattern F5, F35, F55: Fifth active pattern F6, F36, F56: Sixth active pattern F37, F57: Seventh Active Pattern F38, F58: Eighth Active Pattern F39: Ninth Active Pattern F310: Tenth Active Pattern F311: Eleventh Active Pattern F312: Twelfth Active Pattern G1, G31, G51: First gate electrode G2, G32, G52: Second gate electrode G3, G33: Third gate electrode G4, G34: Fourth gate electrode GC1, GC31: First gate cutout GC2, GC32: Second gate cutout GC33: Third gate cutout GC51: Gate Cutout L1: First Length L2: Second Length L3: Third Length L4: Fourth Length L5: Fifth Length L6: Sixth Length L7: Seventh Length TNW: Upper Nanofilm TCA1, TCA31, TCA51: First upper source / drain contact TCA2, TCA32, TCA52: Second upper source / drain contact TCA3, TCA33, TCA53: Third upper source / drain contact TCA24, TCA34: Fourth upper source / drain contact TCA25, TCA45: Fifth upper source / drain contact TCA46: Sixth upper source / drain contact TCA47: Seventh Upper Source / Drain Contact TCA48: Eighth Upper Source / Drain Contact TR1: First transistor TR2: Second transistor TR3: Third transistor TR4: Fourth Transistor TR5: Fifth Transistor TR6: Sixth Transistor TR7: Seventh Transistor TR8: Eighth Transistor TSD1, TSD31, TSD41, TSD51: First upper source / drain region TSD2, TSD32, TSD42, TSD52: Second upper source / drain region TSD3, TSD23, TSD33, TSD43, TSD53: Third upper source / drain region TSD4, TSD24, TSD34, TSD44, TSD54: Fourth upper source / drain region TSD5, TSD35: Fifth upper source / drain region TSD36: Sixth Upper Source / Drain Region TSD37: Seventh Upper Source / Drain Region TSD38: Eighth Upper Source / Drain Region V1, V31, V51: First through hole V2, V32, V52: Second through hole V3, V33, V53: Third through hole V4, V34, V54: Fourth through hole V5, V25, V35, V55: Fifth through hole V6, V26, V36, V56: Sixth through hole V7, V27, V37, V57: Seventh through hole V8, V28, V38, V58: Eighth through hole V9, V29, V39, V49: Ninth through hole V10, V210, V310, V410: Tenth through hole V11, V211, V311, V411: Eleventh through hole V312, V412: Twelfth through hole V313, V413: Thirteenth through hole V314, V414: Fourteenth through hole VDD: Power Node VSS: Grounding node

Claims

1. A semiconductor device, comprising: Base; A plurality of lower nanosheets are located on the substrate and extend in a first horizontal direction, wherein the plurality of lower nanosheets are stacked in a vertical direction and spaced apart from each other; a plurality of upper nanosheets are located on the plurality of lower nanosheets and extend in the first horizontal direction, wherein the plurality of upper nanosheets are stacked in the vertical direction and spaced apart from each other; a first gate electrode to a fourth gate electrode are located on the substrate and extend in a second horizontal direction different from the first horizontal direction, wherein the first gate electrode to the fourth gate electrode are disposed around each of the plurality of lower nanosheets and each of the plurality of upper nanosheets, a second gate electrode is spaced apart from the first gate electrode in the second horizontal direction, a third gate electrode is spaced apart from the first gate electrode in the first horizontal direction, and a fourth gate electrode is spaced apart from the third gate electrode in the second horizontal direction; a first lower source / drain region is located on a first side of the first gate electrode and the second gate electrode; A second lower source / drain region is located on the second side of the first gate electrode and the second gate electrode in the first horizontal direction opposite to the first side, wherein the second side of the first gate electrode and the second gate electrode faces the third gate electrode and the fourth gate electrode; a first upper source / drain region is located on the first lower source / drain region; a second upper source / drain region is located on the second lower source / drain region; and an interlayer insulating layer is located between the first lower source / drain region and the first upper source / drain region and between the second lower source / drain region and the second upper source / drain region, wherein the first length of the second lower source / drain region in the second horizontal direction is greater than the second length of the second upper source / drain region in the second horizontal direction.

2. The semiconductor device of claim 1, wherein the first lower source / drain region includes a third lower source / drain region located on the first side of the first gate electrode and a fourth lower source / drain region located on the first side of the second gate electrode, wherein the second lower source / drain region includes a fifth lower source / drain region located on the second side of the first gate electrode and a sixth lower source / drain region located on the second side of the second gate electrode, wherein the fourth lower source / drain region is spaced apart from the third lower source / drain region in the second horizontal direction, and wherein the sixth lower source / drain region is spaced apart from the fifth lower source / drain region in the second horizontal direction.

3. The semiconductor device of claim 2 further includes a buried contact located between the third lower source / drain region and the fourth lower source / drain region, wherein the buried contact is electrically connected to each of the third lower source / drain region and the fourth lower source / drain region, and the buried contact extends into the interior of the substrate.

4. The semiconductor device of claim 3, wherein at least a portion of the buried contact does not overlap with the first lower source / drain region in the second horizontal direction.

5. The semiconductor device as claimed in claim 2, further comprising: The first lower source / drain contact is located on the second side of the first gate electrode and is electrically connected to the fifth lower source / drain region. And a second lower source / drain contact, located on the second side of the second gate electrode, and electrically connected to the sixth lower source / drain region, wherein the first lower source / drain contact and the second lower source / drain contact are spaced apart from the second upper source / drain region.

6. The semiconductor device of claim 1, wherein the first upper source / drain region includes a third upper source / drain region located on the first side of the first gate electrode and a fourth upper source / drain region located on the first side of the second gate electrode, wherein the second upper source / drain region includes a fifth upper source / drain region located on the second side of the first gate electrode and a sixth upper source / drain region located on the second side of the second gate electrode, wherein the fourth upper source / drain region is spaced apart from the third upper source / drain region in the second horizontal direction, and wherein the sixth upper source / drain region is spaced apart from the fifth upper source / drain region in the second horizontal direction.

7. The semiconductor device as claimed in claim 6, further comprising: A first upper source / drain contact is located on the first side of the first gate electrode and the second gate electrode, and is electrically connected to each of the third upper source / drain region and the fourth upper source / drain region; and a second upper source / drain contact is located on the second side of the first gate electrode and the second gate electrode, and is electrically connected to each of the fifth upper source / drain region and the sixth upper source / drain region.

8. The semiconductor device as claimed in claim 1, wherein the first length is less than three times the second length.

9. The semiconductor device of claim 1, wherein the plurality of lower nanosheets are located in an NMOS region and the plurality of upper nanosheets are located in a PMOS region.

10. A semiconductor device, comprising: Base; A plurality of lower nanosheets are located on the substrate and extend in a first horizontal direction, wherein the plurality of lower nanosheets are stacked in a vertical direction and spaced apart from each other; a plurality of upper nanosheets are located on the plurality of lower nanosheets and extend in the first horizontal direction, wherein the plurality of upper nanosheets are stacked in the vertical direction and spaced apart from each other; a first gate electrode is located on the substrate and extends in a second horizontal direction different from the first horizontal direction, wherein the first gate electrode is disposed around each of the plurality of lower nanosheets and each of the plurality of upper nanosheets; A second gate electrode is located on the substrate and extends in the second horizontal direction, wherein the second gate electrode is spaced apart from the first gate electrode in the second horizontal direction and is disposed around each of the plurality of lower nanosheets and each of the plurality of upper nanosheets; a lower source / drain region is located on a first side and a second side of the first gate electrode and the second gate electrode; an upper source / drain region is located on the lower source / drain region on the first side and the second side of the first gate electrode and the second gate electrode; and an interlayer insulating layer is located between the lower source / drain region and the upper source / drain region, wherein on at least one side of the first side and the second side of the first gate electrode and the second gate electrode, a first length of the lower source / drain region in the second horizontal direction is greater than a second length of the upper source / drain region in the second horizontal direction.

11. The semiconductor device as claimed in claim 10, further comprising: A third gate electrode is located on the substrate and extends in the second horizontal direction, wherein the third gate electrode is spaced apart from the first gate electrode in the first horizontal direction; and a fourth gate electrode, located on the substrate and extending in the second horizontal direction, wherein the fourth gate electrode is spaced apart from the third gate electrode in the second horizontal direction, wherein at least one side is located between the first gate electrode and the third gate electrode and between the second gate electrode and the fourth gate electrode.

12. The semiconductor device of claim 10, wherein the lower source / drain region includes a first lower source / drain region located on the first side of the first gate electrode and a second lower source / drain region located on the first side of the second gate electrode, and wherein the semiconductor device further includes a buried contact located between the first lower source / drain region and the second lower source / drain region, wherein the buried contact is electrically connected to each of the first lower source / drain region and the second lower source / drain region, and the buried contact extends into the interior of the substrate.

13. The semiconductor device as claimed in claim 10, further comprising: A third gate electrode is located on the substrate and extends in the second horizontal direction, wherein the third gate electrode is spaced apart from the second gate electrode in the second horizontal direction; And a fourth gate electrode, located on the substrate and extending in the second horizontal direction, wherein the fourth gate electrode is spaced apart from the third gate electrode in the second horizontal direction.

14. The semiconductor device of claim 10, wherein the lower source / drain region comprises: The first lower source / drain region is located on the first side of the first gate electrode and the second gate electrode; And a second lower source / drain region, located on the second side of the first gate electrode and the second gate electrode, wherein the upper source / drain region includes: a first upper source / drain region, located on the first lower source / drain region; And a second upper source / drain region, located on the second lower source / drain region, wherein the first length of the first lower source / drain region in the second horizontal direction is greater than the second length of the first upper source / drain region in the second horizontal direction, and wherein the third length of the second lower source / drain region in the second horizontal direction is greater than the fourth length of the second upper source / drain region in the second horizontal direction.

15. A semiconductor device, comprising: Base; A plurality of lower nanosheets are located on the substrate and extend in a first horizontal direction, wherein the plurality of lower nanosheets are stacked in a vertical direction and spaced apart from each other; a plurality of upper nanosheets are located on the plurality of lower nanosheets and extend in the first horizontal direction, wherein the plurality of upper nanosheets are stacked in the vertical direction and spaced apart from each other; a first gate electrode is located on the substrate and extends in a second horizontal direction different from the first horizontal direction, wherein the first gate electrode is disposed around each of the plurality of lower nanosheets and each of the plurality of upper nanosheets; A second gate electrode is located on the substrate and extends in the second horizontal direction, wherein the second gate electrode is spaced apart from the first gate electrode in the second horizontal direction, and the second gate electrode is disposed around each of the plurality of lower nanosheets and each of the plurality of upper nanosheets; a first lower source / drain region is located on a first side of the first gate electrode and the second gate electrode; a second lower source / drain region is located on a second side of the first gate electrode and the second gate electrode in the first horizontal direction opposite to the first side; a first upper source / drain region is located on the first lower source / drain region; a second upper source / drain region is located on the second lower source / drain region; An interlayer insulating layer is located between the first lower source / drain region and the first upper source / drain region, and between the second lower source / drain region and the second upper source / drain region; and an embedded contact is electrically connected to one of the first lower source / drain region and the second lower source / drain region and extends into the interior of the substrate.

16. The semiconductor device as claimed in claim 15, further comprising: A third gate electrode is located on the substrate and extends in the second horizontal direction, wherein the third gate electrode is spaced apart from the first gate electrode in the first horizontal direction; And a fourth gate electrode, located on the substrate and extending in the second horizontal direction, wherein the fourth gate electrode is spaced apart from the third gate electrode in the second horizontal direction.

17. The semiconductor device of claim 16, wherein between the first gate electrode and the third gate electrode and between the second gate electrode and the fourth gate electrode, a first length of the second lower source / drain region in the second horizontal direction is greater than a second length of the second upper source / drain region in the second horizontal direction.

18. The semiconductor device as claimed in claim 15, further comprising: A third gate electrode is located on the substrate and extends in the second horizontal direction, wherein the third gate electrode is spaced apart from the second gate electrode in the second horizontal direction; And a fourth gate electrode, located on the substrate and extending in the second horizontal direction, wherein the fourth gate electrode is spaced apart from the third gate electrode in the second horizontal direction.

19. The semiconductor device of claim 18, wherein on the first side of the first gate electrode and the second gate electrode, the third length of the first lower source / drain region in the second horizontal direction is greater than the fourth length of the first upper source / drain region in the second horizontal direction.

20. The semiconductor device of claim 15, wherein the embedded contact comprises: The first embedded contact is electrically connected to the first lower source / drain region and extends into the interior of the substrate; And a second embedded contact, electrically connected to the second lower source / drain region, and extending into the interior of the substrate.

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