Semiconductor device including fuses and manufacturing method of the same

Abstract

This disclosure provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a fused metal, a doped structure, a first dielectric layer, a second dielectric layer, and two doped portions. The first dielectric layer extends along a first direction and is disposed above the fused metal. The first dielectric layer includes a first recessed structure for accommodating the fused metal. The doped structure is formed above the first dielectric layer and extends along a second direction perpendicular to the first direction. The second dielectric layer extends along the first direction and is disposed above the doped structure. The doped portions are adjacent to two side surfaces of the doped structure and are spaced apart from the first and second dielectric layers.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 816,126 (i.e., priority date "August 27, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for fabricating the same. In particular, it relates to a semiconductor device comprising a fused metal and a method for fabricating the same. Prior Technology

[0003] As integrated circuit (IC) performance and miniaturization continue to improve, advancements in materials and design have resulted in generation after generation of smaller and more complex memory devices.

[0004] With the development of the semiconductor industry, detecting post-assembly faults in memory devices has become increasingly important. Weak bits can occur, affecting the function and performance of memory devices. However, because memory devices may be assembled and mounted on printed circuit boards, it can be difficult to obtain the high voltage required to burn out or blown fuses. Therefore, testing and repairing memory devices becomes very inconvenient. Thus, a new semiconductor device and method are needed to improve these issues.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a doped structure, a first dielectric layer, a second dielectric layer, and a first insulating structure. The first dielectric layer extends along a first direction and is disposed on an upper surface of the doped structure along a second direction perpendicular to the first direction. The second dielectric layer is disposed below a lower surface of the doped structure along the second direction. The first insulating structure extends along the second direction and is disposed adjacent to one side surface of the doped structure. A first end of the first insulating structure is at the same stepped plane as the lower surface of the doped structure, and the length of the first insulating structure is less than the length of the doped structure.

[0007] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a fused metal, a doped structure, a first dielectric layer, a second dielectric layer, and two doped portions. The first dielectric layer extends along a first direction and is disposed above the fused metal. The first dielectric layer includes a first recessed structure for accommodating the fused metal. The doped structure is formed above the first dielectric layer and extends along a second direction perpendicular to the first direction. The second dielectric layer extends along the first direction and is disposed above the doped structure. The doped portions are adjacent to two side surfaces of the doped structure and are spaced apart from the first dielectric layer and the second dielectric layer.

[0008] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming an insulating structure along one side of a recessed region of a well region; forming a doped structure covering the insulating structure, wherein the doped structure is longer than the insulating structure and the insulating structure is located between the well region and the doped structure; forming a doped portion located outside the doped structure and adjacent to the insulating structure and the doped structure; forming a first dielectric layer above the doped structure; forming a second dielectric layer below the doped structure, wherein the doped portion is between the first dielectric layer and the second dielectric layer and spaced apart from the first and second dielectric layers; and forming a fused metal below the second dielectric layer.

[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0010] A more complete understanding of this disclosure can be obtained by referring to the detailed description and the claims. This disclosure should also be understood to be associated with the element numbers in the drawings, which represent similar elements throughout the description. Figure 1A is a top view schematic diagram illustrating semiconductor elements of some embodiments of this disclosure. Figure 1B is a schematic diagram illustrating the unit cell of a semiconductor element in some embodiments of this disclosure. Figure 1C is a schematic diagram illustrating a unit cell with two fuses of a semiconductor element according to some embodiments of this disclosure. Figure 2A is a top view schematic diagram illustrating the main array of semiconductor elements in some embodiments of this disclosure. Figure 2B is a top view schematic diagram illustrating a spare array of semiconductor elements in some embodiments of this disclosure. Figure 3A is a cross-sectional schematic diagram illustrating semiconductor elements of some embodiments of this disclosure. Figure 3B is another cross-sectional schematic diagram illustrating semiconductor elements of some embodiments of this disclosure. Figure 4 is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure. Figure 5A is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. Figure 5B is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. Figure 5C is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. Figure 5D is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. Figure 5E is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. Figure 5F is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. Figure 5G is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. Figure 5H is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. Figure 5I is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. Figure 5J is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. Figure 5K is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. Figure 5L is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. Figure 5M is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. Figure 5N is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. Figure 50 is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. Figure 5P is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. Implementation

[0011] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components so that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplification and clarity, and unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0012] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0013] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0014] Figure 1A is a top view schematic diagram illustrating a semiconductor element 10 according to some embodiments of the present disclosure. The semiconductor element 10 may include at least one cell region in which a memory element is formed. For example, the memory element may include a dynamic random access memory (DRAM) element, an one-time programmable (OTP) memory element, a static random access memory (SRAM) element, or other suitable memory element. In some embodiments, for example, DRAM may include transistors, capacitors, and other components. During a read operation, a word line can be asserted, thereby turning on the transistor. The enabled transistor allows a sense amplifier to read the voltage across the capacitor via the bit line. During a write operation, when the word line is asserted, data to be written can be provided on the bit line.

[0015] In some embodiments, the semiconductor element 10 may include a peripheral region (not shown) for forming logic elements (e.g., system-on-a-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.), radio frequency (RF) elements, sensor elements, microelectromechanical systems (MEMS) elements, signal processing elements (e.g., digital signal processing (DSP) elements), front-end elements (e.g., analog front-end (AFE) elements) or other elements.

[0016] In some embodiments, semiconductor element 10 may include a primary array 110 and a backup array 120. The primary array 110 and backup array 120 may each include several cell regions, and each cell region may include one or more unit cells. As shown in FIG1A, the primary array 110 includes a unit cell 112, and the backup array 120 includes a unit cell 122. The backup array 120 may be similar to the primary array 110 to detect the performance and operation of the primary array 110. In some embodiments, redundant bit lines may be provided for the backup array 120. A backside power line may be used as an isolation path for enabling redundant bit lines in the backup array 120.

[0017] Figure 1B is a schematic diagram illustrating a unit cell 112 of a main array 110 of semiconductor elements according to some embodiments of this disclosure. Unit cell 112 may include a transistor 113 and a capacitor 114. Unit cell 112 may include an ITC cell. Capacitor 114 may be electrically connected to the drain or source of transistor 113. The source / drain region may refer to the source or drain, individually or collectively, depending on the context.

[0018] Figure 1C is a schematic diagram illustrating a standby array 120 of semiconductor element 10 according to some embodiments of the present disclosure, having a unit cell 122 with two fuses 12D and 12M. The unit cell 122 may include a transistor 123, a capacitor 124, and the two fuses 12D and 12M. The unit cell 122 may include an ITC cell. The capacitor 124 may be electrically connected to the drain or source of the transistor 123. The fuses 12D and 12M may be electrically connected to the other drain or source of the transistor 123. As shown in Figure 1C, the transistor 123 is electrically connected between the capacitor 124 and the two fuses 12D and 12M.

[0019] In some embodiments, fuse 12D may include a dielectric fuse, and the dielectric fuse may include a dielectric layer. Fuse 12D may be normally open. Fuse 12D may open or electrically disconnect before being burned by a high voltage or high current. In some embodiments, fuse 12M may include a fuse metal, and the fuse metal may include a metallic structure. Fuse 12M may be normally open. Fuse 12M may short-circuit or electrically conduct before being burned by a high voltage or high current. Fuse 12D may be electrically connected to fuse 12M.

[0020] Figure 2A is a top view schematic diagram illustrating a main array of semiconductor elements 20A according to some embodiments of this disclosure. The semiconductor elements 20A of Figure 2A may correspond to the main array 110 of semiconductor elements 10 of Figure 1A.

[0021] Semiconductor element 20A may include bit lines BL1, BL2, BL3, word lines WL1, WL2, active regions M1, M2, M3, shielding contacts C1, C2, C3, and capacitors CP1 and CP2. Bit lines BL1, BL2, and BL3 may be substantially perpendicular to word lines WL1 and WL2. Capacitors CP1 and CP2 may be disposed at both ends of active region M1. Bit line BL1 may be electrically connected to active region M1 via shielding contact C1. Bit line BL2 may be electrically connected to active region M2 via shielding contact C2. Bit line BL3 may be electrically connected to active region M3 via shielding contact C3.

[0022] Bit lines BL1, BL2, BL3 and word lines WL1, WL2 may each comprise a metal, such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), silver (Ag), gold (Au), their alloys, or combinations thereof. Each active region M1, M2, M3 may comprise an elemental semiconductor, comprising silicon or germanium in single-crystal, polycrystalline, or amorphous form; a compound semiconductor material, comprising at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material, comprising at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or combinations thereof. Active regions M1, M2, and M3 may comprise N-type dopants. The active regions M1, M2, and M3 can be doped with N-type dopants, such as phosphorus (P), arsenic (As), or antimony (Sb). Each shielding contact C1, C2, and C3 can comprise a metal, such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), silver (Ag), gold (Au), their alloy combinations, or any metallic material with suitable resistance and gap-filling capability.

[0023] Figure 2B is a top view schematic diagram illustrating a spare array of semiconductor element 20B according to some embodiments of this disclosure. Semiconductor element 20B of Figure 2B may correspond to spare array 120 of semiconductor element 10 of Figure 1A. Compared to semiconductor element 20A, semiconductor element 20B may include additional manufacturing processes 22 to provide redundant bit lines in spare array 120.

[0024] In some embodiments, metal structure 372 may be disposed between word lines WL1 and WL2. From a top view, fuse metal 360 may be disposed within metal structure 372 and shielding contact C1. In some embodiments, metal structure 372 may correspond to or be included by fuse 12D. In some embodiments, fuse metal 360 may correspond to or be included by fuse 12M. In some embodiments, fuses 12D and 12M are used to provide high-voltage and high-current paths in a backup array without affecting the main array. In some embodiments, a high-voltage path may be created, burning out or blowing fuse 12D. Subsequently, fuse 12D may burn out or blow, potentially becoming a short circuit for current flow. In some embodiments, a high-current path may pass through fuse 12D, thereby blowing out or burning out fuse 12M. Therefore, fuses 12D and 12M can provide power lines to melt redundant bit lines and repair the assembled semiconductor element 20B.

[0025] Figure 3A is a cross-sectional schematic diagram illustrating a semiconductor element 30 according to some embodiments of the present disclosure. The semiconductor element 20B of Figure 2B may correspond to the spare array 120 of the semiconductor element 10 of Figure 1A. The semiconductor element 30 may include a doped structure 310, two dielectric layers 320 and 330, three insulating structures 340, 342 and 540, two doped portions 350 and 352, a fused metal 360, three metal structures 370, 372 and 374, a well region 500, a doped layer 520, trioxide layers 530, 532 and 534, a gate structure 550, a metal structure 552, and a bonding layer 560.

[0026] In some embodiments, well region 500 may be formed above oxide layer 534. Well region 500 and oxide layer 534 may extend along a D1 direction. Oxide layer 534 may be formed between dielectric layer 330 and well region 500. Fuse metal 360 may be formed below and covered by dielectric layer 330. Dielectric layer 330 may be formed above fuse metal 360 and metal structure 370. Fuse metal 360 may be surrounded by dielectric layer 330 and metal structure 370.

[0027] Insulating structures 340 and 342, as well region 500, may be formed above oxide layer 534. Doped structure 310 may be formed above dielectric layer 330. Doped structure 310 may be disposed above dielectric layer 330 and below dielectric layer 320. Doped structure 310 may extend along a direction perpendicular to D1 (D2 direction). Insulating structures 340 and 342 may extend along D2 direction. Doped structure 310 may be disposed between two insulating structures 340 and 342. Insulating structures 340 and 342 may be adjacent to or in direct contact with the respective side surfaces of doped structure 310.

[0028] As shown in Figure 3A, a doped layer 520 may be disposed above the well region 500. The doped layer 520 may extend along the D1 direction. The doped structure 310 may penetrate the doped layer 520 or be surrounded by the doped layer 520. Furthermore, a doped portion 350 may be formed below the doped layer 520 and within the well region 500. The doped portion 350 may be adjacent to or in direct contact with the side surfaces of the doped structure 310 and the insulating structure 340. The doped portion 350 may be surrounded by the doped layer 520, the doped structure 310, the insulating structure 340, and the well region 500. Furthermore, a doped portion 352 may be formed below the doped layer 520 and within the well region 500. The doped portion 352 may be adjacent to or in direct contact with the side surfaces of the doped structure 310 and the insulating structure 342. The doped portion 352 may be surrounded by the doped layer 520, the doped structure 310, the insulating structure 342, and the well region 500.

[0029] A gate structure 550 may be formed between the well region 500 and the doped layer 520. The gate structure 550 may be semi-circular, facing the well region 500. An oxide layer may be disposed along the edge of the semi-circular area between the well region 500 and the doped layer 520. Furthermore, an insulating structure 540 may be disposed above the gate structure 550 along the D2 direction. The insulating structure 540 and the gate structure 550 may be surrounded by the doped layer 520 and the well region 500. The upper surfaces of the insulating structure 540 and the doped layer 520 are on the same stepped plane. The upper surface of the doped structure 310 may be higher than the upper surfaces of the insulating structure 540 and the doped layer 520.

[0030] An oxide layer 530 may be formed over the doped layer 520 and the insulating structure 540. The oxide layer 530 may extend along the D1 direction. A dielectric layer 320 may be disposed over the oxide layer 530 and the doped structure 310. The dielectric layer 320 may include a recessed structure for accommodating a metal structure 372. The metal structure 372 may be formed over the dielectric layer 320. Furthermore, a metal structure 552 may be disposed over the doped layer 520. The metal structure 552 may extend along the D2 direction and penetrate the dielectric layer 320 and the oxide layer 530. A metal structure 374 may be disposed over the metal structure 552.

[0031] In some embodiments, an oxide layer 532 may be disposed over the dielectric layer 320 and the metal structure 372. The oxide layer 532 may extend along the D1 direction. The metal structures 372 and 374 may be formed within or surrounded by the oxide layer 532. A bonding layer 560 may be formed over the oxide layer 532. The bonding layer 560 may extend along the D1 direction.

[0032] Figure 3B is another cross-sectional schematic diagram illustrating a semiconductor element 30 of some embodiments of this disclosure. The semiconductor element 30 of Figure 3B may be similar to the embodiment of Figure 3A, except for the high-voltage path HA, the high-current path HB, and the two fuses 12D and 12M as described below.

[0033] In some embodiments, fuse 12D may include at least a dielectric layer 320 formed between metal structure 372 and doped structure 310. Fuse 12M may include at least fuse metal 360 formed between dielectric layer 330 and metal structure 370.

[0034] In the back-end production line (BEOL) process of manufacturing semiconductor device 30, weak bits may appear, thereby affecting the function and performance of the memory device. However, since semiconductor device 30 may have already been assembled and mounted on a printed circuit board, it may be difficult to obtain the high voltage required to burn out or blown fuses. Therefore, testing and repairing semiconductor device 30 becomes inconvenient.

[0035] This disclosure provides a semiconductor element 30 for a backup array isolated from the main array. A high-voltage path HA and a high-current path HB can be created without affecting the main array by utilizing two fuses 12D and 12M. In some embodiments, the high-voltage path HA can be generated from the back side of the semiconductor element 30, and the high-voltage path HA can burn or blow fuse 12D. Subsequently, fuse 12D may burn or blow and may become a short circuit for current flow. In some embodiments, the high-current path HB can pass from fuse 12D to fuse 12M. Fuse 12M may be blown or burned by the high-current path HB and may become an open circuit, burning out redundant bit lines and repairing the semiconductor element 30 after assembly.

[0036] Figure 4 is a flowchart illustrating a method 40 for fabricating a semiconductor element 30 according to some embodiments of this disclosure.

[0037] Preparation method 40 may begin at step 402, wherein an insulating structure may be formed along one side surface of a recessed region of a well region. Preparation method 40 may continue to step 404, wherein a doped structure may be formed to cover the insulating structure. Preparation method 40 may continue to step 406, wherein a doped portion may be formed outside the doped structure and adjacent to the insulating structure and the doped structure.

[0038] In some embodiments, fabrication method 40 may continue to step 408, wherein a first dielectric layer may be formed above the doped structure. Fabrication method 40 may continue to step 410, wherein a first metal structure may be formed above the first dielectric layer. Fabrication method 40 may continue to step 412, wherein a second dielectric layer may be formed below the doped structure. Fabrication method 40 may continue to step 414, wherein a fused metal may be formed below the second dielectric layer. Fabrication method 40 may continue to step 416, wherein a second metal structure may be formed to cover the fused metal and the second dielectric layer.

[0039] Figure 5A is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of the present disclosure. Well region 500 may extend along the D1 direction. Well region 500 may include a P-type well region. Well region 500 may include a P-type dopant. Well region 500 may be doped with a P-type dopant, such as boron (B) or indium (In). Well region 500 may be formed on or within a substrate (not shown). The substrate may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate may include elemental semiconductors, including silicon or germanium in single-crystal, polycrystalline, or amorphous form; compound semiconductor materials, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductor materials, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable materials; or combinations thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy with a gradient Ge characteristic, wherein the Si and Ge composition changes from one ratio at one location of the gradient SiGe characteristic to another ratio at another location. In another embodiment, the SiGe alloy is formed over a silicon substrate. In some embodiments, the SiGe alloy may generate mechanical strain through another material in contact with the SiGe alloy. In some embodiments, the substrate may have a multilayer structure, or the substrate may include a multilayer compound semiconductor structure.

[0040] A doped layer 520 may be formed on well region 500. The doped layer 520 may extend along the D1 direction. The doped layer 520 may include elemental semiconductors, including silicon or germanium in single-crystal, polycrystalline, or amorphous form; compound semiconductor materials, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductor materials, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable materials; or combinations thereof. The doped layer 520 may include N-type dopants. The doped layer 520 may be doped with N-type dopants, such as phosphorus (P), arsenic (As), or antimony (Sb).

[0041] An oxide layer 530 may be disposed on the doped layer 520. The oxide layer 530 may extend along the D1 direction. In some embodiments, for example, the fabrication technology of the oxide layer 530 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), flow chemical vapor deposition (FCVD), or other suitable processes. For example, the oxide layer 530 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon nitride oxide (N2OSi2), or other suitable materials.

[0042] As shown in Figure 5A, an insulating structure 540 and a gate structure 550 may be formed within the doped layer 520 and the well region 500. The gate structure 550 may include a recessed gate. The insulating structure 540 may be formed on the gate structure 550. The insulating structure 540 may include a metal, such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), silver (Ag), gold (Au), alloys thereof, or any metallic material with suitable resistance and gap-filling capability. For example, the insulating structure 540 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, high-k materials, or combinations thereof.

[0043] In some embodiments, a recessed region 500A may be formed, as shown in FIG5A. The fabrication technique for the recessed region 500A may include etching portions of the doped layer 520, the oxide layer 530, and the well region 500. The recessed region 500A may have two side surfaces 500L along the D2 direction. The recessed region 500A may serve as a redundant bit line contact. The recessed region 500A may be spaced apart from or separated from the gate structure 550. The etching may include one or more stages, and each stage may be configured to etch at least one material.

[0044] Figure 5B is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of the present disclosure. An insulating layer may be disposed over the oxide layer 530 and the recessed region 500A of the well region 500. As shown in Figure 5B, the insulating layer may include a plurality of insulating structures 340, 341, 342, and 341A. In some embodiments, insulating structure 341 may be disposed on the oxide layer. Insulating structures 340 and 342 may be disposed adjacent to the side surface 500L of the recessed region 500A of the well region 500. Insulating structure 341A may be disposed on the bottom of the recessed region 500A of the well region 500.

[0045] For example, insulating structures 340, 341, 342, and 341A may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or combinations thereof. In some embodiments, for example, the fabrication techniques for insulating structures 340, 341, 342, and 341A may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), or other suitable processes.

[0046] Figure 5C is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of the present disclosure. The insulating structure 341A can be removed from the bottom of the recessed region 500A. The insulating structure 341A can be removed by etching. The insulating structure 341A can be removed by dry etching. Etching may include one or more stages, and each stage may be configured to etch at least one material.

[0047] Figure 5D is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor device according to some embodiments of the present disclosure. A spin-coated carbon (SOC) layer 511 may be formed on an insulating structure 341. A recessed region 500A may fill the SOC layer 511. For example, the fabrication techniques for the SOC layer 511 may include coating (e.g., spin coating), printing, or other suitable processes. For example, the SOC layer 511 may be patterned by soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, rinsing, and drying (e.g., hard baking). The SOC layer 511 may include a high-carbon-content polymer material.

[0048] Figure 5E is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor device according to some embodiments of this disclosure. In some embodiments, portions of the SOC layer 511 of Figure 5D may be removed to leave the remaining SOC structure 510 on the bottom of the recessed region 500A. The material of the SOC structure 510 may be substantially the same as the material of the SOC layer 511. The SOC layer 511 may be removed by etching to form the SOC structure 510. The SOC layer 511 may be removed by dry etching to form the SOC structure 510. Etching may include one or more stages, and each stage may be configured to etch at least one material.

[0049] In some embodiments, the doped layer 520 may have a thickness X. The depth of the SOC structure 510 is Y1. By adjusting the etching process associated with the n-type dopant of the doped layer 520, the depth of the SOC structure can be increased to a depth Y2. The depth of the SOC structure can be increased to the sum of depths Y1 and Y2. In some embodiments, the depth Y1 may be substantially equal to the thickness X. In some embodiments, the depth Y1 may be greater than the thickness X. In some embodiments, the depth Y1 may be less than the thickness X.

[0050] In some embodiments, depth Y2 may be substantially equal to 20% of thickness X. In some embodiments, depth Y2 may be less than 20% of thickness X. In some embodiments, depth Y2 may be substantially equal to 10% of thickness X. In some embodiments, depth Y2 may be less than 10% of thickness X. In some embodiments, depth Y2 may be substantially equal to 5% of thickness X. In some embodiments, depth Y2 may be less than 5% of thickness X.

[0051] Figure 5F is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of the present disclosure. The SOC structure 510 can be used as a block for etching insulating structures 340, 341, and 342. In some embodiments, insulating structure 341 can be stripped or removed by dry etching. A portion of insulating structure 340 can be stripped or removed by dry etching. A portion of insulating structure 342 can be stripped or removed by dry etching. Remaining insulating structures 340 and 342 adjacent to or in contact with the SOC structure 510 may not be stripped.

[0052] Figure 5G is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. In some embodiments, the SOC structure 510 between insulating structures 340 and 342 may be removed or stripped. The SOC structure 510 between insulating structures 340 and 342 may be removed by etching. The SOC structure 510 between insulating structures 340 and 342 may be removed by dry etching.

[0053] Figure 5H is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. A doped structure 310 may be disposed in a recessed region 500A. The fabrication technique for the doped structure 310 may include deposition and annealing. The doped structure 310 may include elemental semiconductors, comprising silicon or germanium in single-crystal, polycrystalline, or amorphous form; compound semiconductor materials, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductor materials, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable materials; or combinations thereof.

[0054] In some embodiments, the doped structure 310 may be doped with an N-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). In some embodiments, the doping concentration of the doped structure 310 may be greater than the doping concentration of the doped layer 520. In some embodiments, the dopant type of the doped structure 310 may be the same as the dopant type of the doped layer 520.

[0055] As shown in Figure 5H, the doped structure 310 may be surrounded by a doped layer 520. The doped structure 310 may be surrounded by a well region 500 and insulating structures 340 and 342. In some embodiments, the lower surface 310b of the doped structure 310 may be in direct contact with the well region 500. In some embodiments, the side surface 310a of the doped structure 310 may be in direct contact with the insulating structure 340. In some embodiments, the side surface 310c of the doped structure 310 may be in direct contact with the insulating structure 342. In some embodiments, the doped structure 310 may be exposed from the oxide layer 530. The doped structure 310 and the insulating structures 340 and 342 may be formed in a rectangular shape within the recessed region 500A.

[0056] In some embodiments, a doped portion 350 may be formed adjacent to the doped structure 310 and the insulating structure 340. A doped portion 352 may be formed adjacent to the doped structure 310 and the insulating structure 342. The fabrication techniques of the doped portions 350 and 352 may include diffusion of an N-type dopant from the doped layer 520. In some embodiments, the doped portions 350 and 352 may be used to provide a low-resistance electrical path for the fuse 12D, as shown in FIG3B. In some embodiments, the doped portions 350 and 352 may be used to provide a high electric field for the fuse 12D to melt or burn it out.

[0057] Doped portions 350 and 352, as well as doped layer 520, may have substantially the same material. Doped portions 350 and 352 may include elemental semiconductors, including silicon or germanium in single-crystal, polycrystalline, or amorphous form; compound semiconductor materials, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductor materials, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof.

[0058] In some embodiments, doped portions 350 and 352 may be doped with N-type dopants, such as phosphorus (P), arsenic (As), or antimony (Sb). In some embodiments, the doping concentration of doped portions 350 and 352 may be greater than the doping concentration of doped layer 520. In some embodiments, the doping concentration of doped portions 350 and 352 may be greater than the doping concentration of doped structure 310. In some embodiments, the doping concentration of doped portions 350 and 352 may be less than the doping concentration of doped structure 310. In some embodiments, the doping concentration of doped portions 350 and 352 may be substantially the same as the doping concentration of doped structure 310. In some embodiments, the dopant type of doped portions 350 and 352 may be the same as the dopant type of doped layer 520. In some embodiments, the dopant type of doped portions 350 and 352 may be the same as the dopant type of doped structure 310.

[0059] As shown in Figure 5H, the doped portion 350 can be formed within the well region 500 and below the doped layer 520. The doped portion 350 can be surrounded by the doped structure 310, the insulating structure 340, the well region 500, and the doped layer 520. The end portion 340e2 of the insulating structure 340 can be in direct contact with the doped structure 310 and is close to the doped portion 350. The end portion 340e1 of the insulating structure 340 can be on the same stepped plane as the lower surface 310b of the doped structure 310.

[0060] The doped portion 352 may be formed within the well region 500 and located below the doped layer 520. The doped portion 352 may be surrounded by the doped structure 310, the insulating structure 342, the well region 500, and the doped layer 520. The top end of the insulating structure 342 may be in direct contact with the doped structure 310 and is close to the doped portion 350. The bottom end of the insulating structure 342 may be on the same stepped plane as the lower surface 310b of the doped structure 310.

[0061] In some embodiments, doped portions 350 and 352 may have substantially the same size 350W. Doped portions 350 and 352 may have substantially the same shape. In some embodiments, the size 350W of each of the doped portions 350 and 352 may be substantially equal to 20% or one-fifth of the thickness X of the doped layer 520. In some embodiments, the size 350W of each of the doped portions 350 and 352 may be substantially less than 20% or one-fifth of the thickness X of the doped layer 520. In some embodiments, the size 350W of each of the doped portions 350 and 352 may be substantially equal to 10% of the thickness X of the doped layer 520. In some embodiments, the size 350W of each of the doped portions 350 and 352 may be substantially less than 10% of the thickness X of the doped layer 520. In some embodiments, the size 350W of each of the doped portions 350 and 352 may be substantially equal to 5% of the thickness X of the doped layer 520. In some embodiments, the size 350W of each of the doped portions 350 and 352 may be substantially less than 5% of the thickness X of the doped layer 520.

[0062] Figure 5I is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor device according to some embodiments of the present disclosure. A dielectric layer 320 may be disposed on an oxide layer 530 and a doped structure 310. In some embodiments, for example, the dielectric layer 320 may include silicon oxide (SiO₂), silicon nitride (Si₃N₄), silicon oxynitride (N₂OSi₂), silicon oxynitride (N₂OSi₂), a high-k material, or a combination thereof. Examples of high-k materials include dielectric materials with a dielectric constant greater than that of silicon dioxide (SiO₂), or dielectric materials with a dielectric constant greater than approximately 3.9. In some embodiments, the dielectric layer 320 may include at least one metallic element, such as hafnium oxide (HfO₂), silicon-doped hafnium oxide (HSO), lanthanum oxide (La₂O₃), lanthanum aluminum oxide (LaAlO₃), zirconium orthosilicate (ZrSiO₄), aluminum oxide (Al₂O₃), or a combination thereof. In some embodiments, for example, the fabrication technology of dielectric layer 320 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), flow chemical vapor deposition (FCVD) or other suitable processes.

[0063] In some embodiments, the dielectric layer 320 may extend along the D1 direction. In some embodiments, the dielectric layer 320 may include a continuous pattern or shape. The dielectric layer 320 may be in direct contact with the upper surfaces of the oxide layer 530 and the doped structure 310. The dielectric layer 320 may include a recessed structure 320R located above the doped structure 310. The recessed structure 320R may have a width 320W along the D1 direction. In some embodiments, the width 320W of the recessed structure 320R may be less than the length 340L of the insulating structures 340 and 342. In some embodiments, the width 320W of the recessed structure 320R may be substantially equal to the length 340L of the insulating structures 340 and 342. In some embodiments, the width 320W of the recessed structure 320R may be greater than the dimensions of the doped portions 350 and 352. In some embodiments, the width 320W of the recessed structure 320R may be less than the length 310L of the doped structure 310. In some embodiments, the length 340L of the insulating structures 340 and 342 may be less than the length 310L of the doped structure 310.

[0064] Figure 5J is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. A metal structure 372 may be disposed on the dielectric layer 320 and above the doped structure 310. The metal structure 372 may be accommodated by a recessed structure in the dielectric layer 320. The metal structure 372 may include metals such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), silver (Ag), gold (Au), alloys thereof, or any metallic material having suitable resistance and gap-filling capabilities.

[0065] In some embodiments, the metal structure 552 may be disposed on the doped layer 520. The metal structure 372 may penetrate the dielectric layer 320. The metal structure 372 may extend along the D2 direction. The metal structure 552 may include metals such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), silver (Ag), gold (Au), alloys thereof, or any metallic material having suitable resistance and gap-filling capability.

[0066] As shown in Figure 5J, a metal structure 374 can be disposed on a metal structure 552. The metal structure 374 can be spaced apart from the metal structure 372. The metal structure 374 can extend along the D1 direction. The metal structure 374 can include metals such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), silver (Ag), gold (Au), their alloy combinations, or any metallic material with suitable resistance and gap-filling capability.

[0067] In some embodiments, oxide layer 532 may be formed or disposed on dielectric layer 320. Oxide layer 532 may cover metal structures 372, 374, and 552. Oxide layer 532 may extend along the D1 direction. Oxide layer 532 and metal structures 374 and 552 may be used to form or provide a capacitor. In some embodiments, for example, the fabrication techniques of oxide layer 532 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), flow chemical vapor deposition (FCVD), or other suitable processes. For example, oxide layer 530 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon oxynitride (N2OSi2), or other suitable materials.

[0068] Figure 5K is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. A bonding layer 560 may be formed or bonded to the oxide layer 532 for back-side polishing. For example, the bonding layer 560 may include silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, insulating material, or a combination thereof.

[0069] In some embodiments, back-side grinding may be performed to thin the well region 500, the doped structure 310, and the insulating structures 340 and 342. After back-side grinding, the lower surfaces of the well region 500, the doped structure 310, and the insulating structures 340 and 342 may be substantially on the same stepped plane. In some embodiments, an oxide layer 534 may be formed below or directly in contact with the lower surfaces of the well region 500, the doped structure 310, and the insulating structures 340 and 342. In some embodiments, for example, the fabrication techniques of the oxide layer 534 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), flowing chemical vapor deposition (FCVD), or other suitable processes. For example, the oxide layer 534 may include silicon oxide (SiO 2), silicon nitride (Si 3N 4), silicon oxynitride (N 2OSi 2), silicon oxynitride (N 2OSi 2) or other suitable materials.

[0070] Figure 5L is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor device according to some embodiments of this disclosure. Photolithography can be performed on the oxide layer 534 to form a dielectric layer 330. The dielectric layer 330 may be disposed beneath the oxide layer 534 and the doped structure 310. In some embodiments, for example, the dielectric layer 330 may include, for example, silicon oxide (SiO₂), silicon nitride (Si₃N₄), silicon oxynitride (N₂OSi₂), silicon oxynitride (N₂OSi₂), a high-k material, or a combination thereof. Examples of high-k materials include dielectric materials with a dielectric constant greater than that of silicon dioxide (SiO₂), or dielectric materials with a dielectric constant higher than about 3.9. In some embodiments, the dielectric layer 330 may include at least one metallic element, such as hafnium oxide (HfO₂), silicon-doped hafnium oxide (HSO), lanthanum oxide (La₂O₃), lanthanum aluminum oxide (LaAlO₃), zirconium orthosilicate (ZrSiO₄), aluminum oxide (Al₂O₃), or combinations thereof. In some embodiments, for example, the fabrication technique of the dielectric layer 320 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), flowing chemical vapor deposition (FCVD), or other suitable processes.

[0071] In some embodiments, the dielectric layer 330 may extend along the D1 direction. In some embodiments, the dielectric layer 330 may include a continuous pattern or shape. The dielectric layer 330 may be in direct contact with the lower surfaces of the oxide layer 534 and the doped structure 310. The dielectric layer 330 may include a recessed structure 330R located below the doped structure 310. The recessed structure 330R may have a width 330W along the D1 direction. In some embodiments, the width 330W of the recessed structure 330R may be less than the lengths of the insulating structures 340 and 342. In some embodiments, the width 330W of the recessed structure 330R may be substantially equal to the lengths of the insulating structures 340 and 342. In some embodiments, the width 330W of the recessed structure 330R may be greater than the dimensions of the doped portions 350 and 352. In some embodiments, the width 330W of the recessed structure 330R may be less than the length of the doped structure 310.

[0072] In some embodiments, the distance 35D1 between the dielectric layer 320 and the doped portions 350 and 352 may be smaller than the distance 35D2 between the dielectric layer 330 and the doped portions 350 and 352. In some embodiments, the width 330W of the recessed structure 330R may be smaller than the distance 35D1 between the dielectric layer 320 and the doped portions 350 and 352. In some embodiments, the width 330W of the recessed structure 330R may be substantially the same as the distance 35D1 between the dielectric layer 320 and the doped portions 350 and 352. In some embodiments, the width 330W of the recessed structure 330R may be greater than the distance 35D1 between the dielectric layer 320 and the doped portions 350 and 352.

[0073] Figure 5M is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. Photosensitive layers 570 and 572 may be used to form or embed fused metal 360. Photosensitive layers 570 and 572 may include photoresist or other suitable materials. Photosensitive layers 570 and 572 may be patterned to expose a portion of dielectric layer 330. For example, fabrication techniques for photosensitive layers 570 and 572 may include coating (e.g., spin coating), printing, or other suitable processes. For example, fabrication techniques for photosensitive layers 570 and 572 may include soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking) for patterning.

[0074] In some embodiments, fuse metal 360 may be formed or implanted beneath dielectric layer 330 and doped structure 310. A recessed structure 330R in dielectric layer 330 may be filled with fuse metal 360. Fuse metal 360 may comprise metals such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), silver (Ag), gold (Au), alloys thereof, or any metallic material with suitable resistance and gap-filling capability.

[0075] Figure 5N is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. Photosensitive layers 570 and 572 can be removed or stripped to expose fuse metal 360. The size and shape of fuse metal 360 can be defined by photosensitive layers 570 and 572.

[0076] Figure 50 is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of the present disclosure. A photosensitive layer 574 may be formed beneath the dielectric layer 330. The photosensitive layer 574 may include photoresist or other suitable materials. In some embodiments, the photosensitive layer 574 may be patterned to form or embed a metal structure 370. For example, the fabrication techniques for the photosensitive layer 574 may include coating (e.g., spin coating), printing, or other suitable processes. For example, the fabrication techniques for the photosensitive layer 574 may include soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking) for patterning.

[0077] As shown in Figure 5O, a metal structure 370 may be formed or embedded beneath the dielectric layer 330 and the fused metal 360. A recessed structure 330R in the dielectric layer 330 may fill the fused metal 360 and the metal structure 370. The fused metal 360 may be surrounded by the dielectric layer 330 and the metal structure 370. The metal structure 370 may comprise a metal, such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), silver (Ag), gold (Au), alloys thereof, or any metallic material with suitable resistance and gap-filling capability. In some embodiments, the melting point of the fused metal 360 may be lower than the melting point of the metal structure 370.

[0078] Figure 5P is a cross-sectional schematic diagram illustrating one or more stages of an exemplary fabrication method for a semiconductor element according to some embodiments of this disclosure. The photosensitive layer 574 can be removed or stripped to expose the metal structure 370. The dimensions and thickness of the metal structure 370 can be defined by the photosensitive layer 574.

[0079] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a doped structure, a first dielectric layer, a second dielectric layer, and a first insulating structure. The first dielectric layer extends along a first direction and is disposed on an upper surface of the doped structure along a second direction perpendicular to the first direction. The second dielectric layer is disposed below a lower surface of the doped structure along the second direction. The first insulating structure extends along the second direction and is disposed adjacent to one side surface of the doped structure. A first end of the first insulating structure is at the same stepped plane as the lower surface of the doped structure, and the length of the first insulating structure is less than the length of the doped structure.

[0080] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a fused metal, a doped structure, a first dielectric layer, a second dielectric layer, and two doped portions. The first dielectric layer extends along a first direction and is disposed above the fused metal. The first dielectric layer includes a first recessed structure for accommodating the fused metal. The doped structure is formed above the first dielectric layer and extends along a second direction perpendicular to the first direction. The second dielectric layer extends along the first direction and is disposed above the doped structure. The doped portions are adjacent to two side surfaces of the doped structure and are spaced apart from the first dielectric layer and the second dielectric layer.

[0081] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming an insulating structure along one side of a recessed region of a well region; forming a doped structure covering the insulating structure, wherein the doped structure is longer than the insulating structure and the insulating structure is located between the well region and the doped structure; forming a doped portion located outside the doped structure and adjacent to the insulating structure and the doped structure; forming a first dielectric layer above the doped structure; forming a second dielectric layer below the doped structure, wherein the doped portion is between the first dielectric layer and the second dielectric layer and spaced apart from the first and second dielectric layers; and forming a fused metal below the second dielectric layer.

[0082] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0083] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0084] 10: Semiconductor components 110: Main Array 112: Unit 113: Transistor 114: Capacitor 120: Backup Array 122: Unit 123: Transistor 124: Capacitor 12D: Fuse 12M: Fuse 20A: Semiconductor Components 20B: Semiconductor components 22: Manufacturing Process 30: Semiconductor components 40: Preparation method 310: Doped Structure 310a: Side surface 310b: Lower surface 310c: Side surface 310L: Length 320, 330: Dielectric layer 320R: Recessed structure 320W: Width 330R: Recessed structure 330W: Width 340, 341, 341A, 342: Insulation structure 340e1: End 340e2: End 340L: Length 350, 352: Doped portions 350W: Size 35D1: Distance 35D2: Distance 360: Fuse Metal 370, 372, 374: Metal structures 402~416: Steps 500: Well Area 500A: Depression area 500L: Side surface 510: Spin-coated carbon structure 511: Spin-coated carbon layer 520: Doped layer 530, 532, 534: Oxide layer 540: Insulation structure 550: Gate structure 552: Metal Structure 560: Bonding layer 570, 572, 574: Photosensitive layer BL1, BL2, BL3: Bit lines C1, C2, C3: Shielding contacts CP1, CP2: Capacitors D1: Direction D2: Direction HA: High Voltage Path HB: High Current Path M1, M2, M3: Active Zone WL1, WL2: Character lines X: Thickness Y1: Depth Y2: Depth

Claims

1. A semiconductor device, comprising: One-doped structure; A first dielectric layer extends along a first direction and is disposed on an upper surface of the doped structure along a second direction perpendicular to the first direction; a second dielectric layer is disposed below a lower surface of the doped structure along the second direction; a first insulating structure extends along the second direction and is disposed adjacent to one side surface of the doped structure, wherein a first end of the first insulating structure is at the same stepped plane as the lower surface of the doped structure, and a length of the first insulating structure is less than a length of the doped structure; and a fused metal is formed on a recessed structure of the second dielectric layer.

2. The semiconductor device as claimed in claim 1, wherein the first insulating structure is spaced apart from the second dielectric layer.

3. The semiconductor device as claimed in claim 1, wherein the first dielectric layer includes a recessed structure.

4. The semiconductor device as claimed in claim 3, wherein the doped structure is formed between the recessed structures of the first dielectric layer and the second dielectric layer.

5. The semiconductor device as claimed in claim 3, wherein the width of the recessed structure of the second dielectric layer is smaller than the width of the recessed structure of the first dielectric layer.

6. The semiconductor device as claimed in claim 1 further includes a doped portion formed adjacent to a second end of the first insulating structure and the side surface of the doped structure.

7. The semiconductor device as claimed in claim 6 further includes a well region extending along the first direction, wherein the doped portion is formed within the well region, and the first insulating structure is formed between the doped structure and the well region.

8. The semiconductor device as claimed in claim 7 further includes a doped layer extending along the first direction and formed above the well region, wherein the doped structure is surrounded by the doped layer and the doped portion is in direct contact with the well region and the doped layer.

9. The semiconductor element as claimed in claim 8, wherein the doped layer is spaced apart from the first insulating structure.

10. The semiconductor device as claimed in claim 8, wherein a dimension of the doped portion is substantially equal to or less than 20% of the thickness of the doped layer.

11. The semiconductor device as claimed in claim 8, wherein a doping concentration of the doped structure is greater than a doping concentration of the doped layer, and a doping concentration of the doped portion is greater than the doping concentration of the doped layer.

12. The semiconductor device as claimed in claim 8 further includes a gate structure spaced apart from the doped structure and surrounded by the doped layer and the well region.

13. The semiconductor device as claimed in claim 12 further includes a second insulating structure formed above the gate structure, wherein an upper surface of the second insulating structure and an upper surface of the doped layer are on the same stepped plane.

14. The semiconductor device as claimed in claim 13 further includes a first oxide layer extending along the first direction and located between the doped layer and the first dielectric layer, wherein the first oxide layer is in direct contact with the doped structure.

15. The semiconductor device as claimed in claim 13 further includes a second oxide layer extending along the first direction and located between the well region and the second dielectric layer.

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