Voltage control and data reading for phase change memory

Abstract

Provided in the present disclosure are a voltage control method for a phase change memory (PCM), a data reading method therefor, and a device, a storage medium and a program product. The data reading method comprises: acquiring writing and reading interval description information when an application performs an operation of first writing data and then reading the data on a PCM; on the basis of the description information, determining an initial voltage gear and a gear switching policy which are required when reading data from a storage unit of the PCM; and on the basis of the initial voltage gear and the gear switching policy, reading the data from the PCM. Writing and reading interval description information is taken into consideration in an initial voltage gear and a gear switching policy, such that a voltage drift factor can be reflected; and the initial voltage gear and the corresponding gear switching policy are determined, such that data can be read from a PCM on the basis of the initial voltage gear, and when reading at the initial voltage gear fails, rational voltage gear switching is performed on the basis of the gear switching policy.

Description

Phase change memory voltage control and data reading technology field

[0001] The present disclosure relates to the field of cloud computing technology, and in particular to voltage control and data reading of phase change memory.

[0002] With the development of cloud computing and cloud storage technologies, the exploration of persistent memory application architectures has deepened, creating an urgent need for storage suitable for persistent memory. Phase change memory (PCM) offers advantages such as high read / write speed, non-volatility, and byte addressability. It also has the potential to serve as both main and external memory, thus meeting this requirement.

[0003] PCM uses the difference in conductivity exhibited by a special material when transitioning between its crystalline and amorphous states to store data. In the amorphous state, the higher the resistance, the more logical "0" is stored. In the crystalline state, the lower the resistance, the more logical "1" is stored. To read data, a read voltage is applied to the PCM. Since this voltage is relatively low, it does not change the stored state.

[0004] In practical applications, PCM has a voltage drift problem. That is, after writing data to the storage cell of the PCM, as the data retention time increases, the voltage actually required to read the data will continue to increase. This may cause the read voltage originally applied to the PCM to fail to successfully read the data from the PCM, reducing data reading efficiency.

[0005] Various aspects of the present disclosure provide a phase change memory voltage control and data reading method, device, storage medium, and program product for rationally configuring the initial voltage level required for reading data from PCM and the corresponding voltage level adjustment strategy, thereby increasing the probability of successfully reading data from PCM and thereby improving data reading efficiency.

[0006] An embodiment of the present disclosure provides a voltage control method for a PCM, which is applied to a host. The method includes: in response to a preset trigger event, predicting write-read interval description information of a target application performing a write-first-then-read data operation on the PCM within a future time period, where the target application is an application on the host that uses the PCM for data access; and sending the write-read interval description information to a storage controller in the PCM, so that the storage controller configures an initial voltage level and a corresponding target level switching strategy required for reading data from a storage unit in the PCM based on the write-read interval description information.

[0007] An embodiment of the present disclosure also provides a method for reading data from a PCM, which is applied to a storage controller in the PCM. The method includes: receiving write-read interval description information sent by a host, which is information indicating a target application performing a write-first-then-read data operation on the PCM in a future time period, wherein the target application is an application on the host that uses the PCM for data access; configuring an initial voltage level and a corresponding target level switching strategy required for reading data from a storage unit in the PCM according to the write-read interval description information; and upon receiving a read command from the target application, reading data from the storage unit of the PCM based on the initial voltage level and the corresponding target level switching strategy.

[0008] An embodiment of the present disclosure further provides a host, comprising: a memory and a processor; the memory is used to store a computer program, and the processor is coupled to the memory and is used to execute the computer program to implement the steps in the PCM voltage control method provided in the embodiment of the present disclosure.

[0009] An embodiment of the present disclosure further provides a phase change memory, comprising: a storage unit for storing data and a storage controller for controlling storage in the storage unit; the storage controller comprising: a processor and a memory, wherein the memory stores a firmware program for the phase change memory; and the processor is configured to execute the firmware program to implement the steps in the PCM data reading method.

[0010] The embodiment of the present disclosure further provides a memory controller, which is applied to a phase change memory and is used to control the phase change memory. The storage unit in the PCM performs storage control, the storage controller includes: a processor and a memory, the memory stores a firmware program of the phase change memory, and the processor is used to execute the firmware program to implement the steps in the data reading method of the PCM.

[0011] The present disclosure also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor implements the steps of the PCM voltage control method and / or the PCM data reading method provided in the embodiments of the present disclosure.

[0012] The present disclosure also provides a computer program product, including a computer program / instruction. When the computer program / instruction is executed by a processor, the processor implements the steps of the PCM voltage control method and the PCM data reading method provided in the present disclosure.

[0013] In this embodiment, the write-read interval description information when the application performs a write-first-then-read data operation on the PCM can be obtained. The initial voltage level and level switching strategy required for reading data from the storage unit of the PCM are determined based on the description information, and data is read from the PCM based on the initial voltage level and level switching strategy. Because the initial voltage level and level switching strategy take into account the write-read interval description information, and the write-read interval description information can reflect the voltage drift factor, not only the initial voltage level is determined, but also the level switching strategy corresponding to the initial voltage level is determined. This allows data to be read from the storage unit of the PCM based on the initial voltage level, and when the initial voltage level reading fails, a reasonable voltage level switching based on the level switching strategy is performed. This helps to increase the probability of successfully reading data from the storage unit of the PCM and improve the overall data reading efficiency. Illustrations

[0014] The drawings described herein are intended to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The illustrative embodiments of the present disclosure and their descriptions are intended to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0015] FIG1a is a system architecture diagram of a host system 100 provided by an exemplary embodiment of the present disclosure;

[0016] FIG1b is an interaction flow chart within the host system 100 according to an exemplary embodiment of the present disclosure;

[0017] FIG2 is a flow chart of a voltage control method for a phase change memory provided by another exemplary embodiment of the present disclosure;

[0018] FIG3 is a schematic flow chart of a method for reading data from a phase change memory provided by another exemplary embodiment of the present disclosure;

[0019] FIG4 is a schematic diagram of a flow chart in an actual scenario provided by another exemplary embodiment of the present disclosure;

[0020] FIG5 is a schematic structural diagram of a voltage control device of a phase change memory provided by another exemplary embodiment of the present disclosure;

[0021] FIG6 is a schematic structural diagram of a data reading device of a phase change memory provided by another exemplary embodiment of the present disclosure;

[0022] FIG7 is a schematic structural diagram of a host device provided by another exemplary embodiment of the present disclosure;

[0023] FIG8 is a schematic diagram of the structure of a PCM provided by another exemplary embodiment of the present disclosure.

[0024] To further clarify the objectives, technical solutions, and advantages of this disclosure, the technical solutions of this disclosure will be described clearly and completely below in conjunction with specific embodiments of the disclosure and the corresponding drawings. Obviously, the described embodiments represent only a portion of the embodiments of this disclosure, and are not exhaustive. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of this disclosure without inventive effort are intended to fall within the scope of protection of this disclosure.

[0025] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this disclosure are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data require The relevant laws, regulations, and standards of the relevant countries and regions must be complied with, and corresponding operation portals should be provided for users to choose to authorize or reject. Furthermore, the various models involved in this disclosure (including but not limited to language models and large models) comply with relevant laws and standards.

[0026] PCM consists of multiple memory cells, each storing a single piece of data, either a logical "0" or a logical "T." These cells are also called storage bits. In PCM, these cells are organized and managed in rows and columns. When reading data from a PCM, the cell to be read is identified and a corresponding read voltage is applied to that cell. However, in practical applications, PCM suffers from voltage drift. After data is written to a PCM cell, the voltage required to read the data increases as the data retention time increases. This can cause the originally applied read voltage to fail to successfully read the data from the PCM, reducing data read efficiency.

[0027] To address the above technical issues, the disclosed embodiments, based on the principle of voltage drift, obtain write-read interval description information when the target application (i.e., an application using PCM for data access) performs a write-first-then-read operation on the PCM. The write-read interval description information describes the interval between the data write operation and the corresponding data read operation. In other words, the write-read interval description information describes the time difference between the write time and the read time for any data. For example, if a target application writes data to the PCM at time T1 and reads the data from the PCM at time T2, the write / read interval between T1 and T2 is T2-T1. The write / read interval description information refers to information that can describe or reflect the write / read interval T2-T1 to a certain extent. Optionally, the write / read interval description information can be the write / read interval T2-T1 itself, or other information that can reflect the write / read interval T2-T1, such as the target application's average write / read interval, or the write / read interval range to which the write / read interval T2-T1 belongs. Different write / read interval ranges correspond to different write / read interval ranges. It should be noted that different applications may have different write / read intervals and different write / read interval description information depending on their type or applicable scenarios.

[0028] The initial voltage level and corresponding level switching strategy required for reading data from the PCM storage cells are determined based on the write / read interval description information. Data is then read from the PCM based on the initial voltage level and the corresponding level switching strategy. Because the initial voltage level and level switching strategy take into account the write / read interval description information, which can reflect voltage drift, and not only the initial voltage level but also the level switching strategy corresponding to the initial voltage level are determined, data can be read from the PCM storage cells based on the initial voltage level. If reading fails at the initial voltage level, a reasonable voltage level switching strategy can be performed based on the level switching strategy. This increases the probability of successfully reading data from the PCM storage cells, thereby improving overall data reading efficiency.

[0029] In the embodiments of the present disclosure, there are no limitations on the implementation of obtaining write / read interval description information when an application performs a write-first-then-read data operation on a PCM, nor on the implementation of determining the initial voltage level and corresponding level switching strategy required for reading data from a storage unit of the PCM based on the write / read interval description information. The embodiments of the present disclosure provide several implementations, in which different implementations may be used to determine the write / read interval description information, and different implementations may be used to determine the initial voltage level and corresponding level switching strategy required for reading data from a storage unit of the PCM based on the write / read interval description information.

[0030] Several implementations provided by the embodiments of the present disclosure are schematically described below in conjunction with a host system architecture using PCM as a storage medium.

[0031] FIG1a is a system architecture diagram of a host system 100 provided in an embodiment of the present disclosure. As shown in FIG1a, the host system 100 may include a host 10 and a phase-change memory 20. The phase-change memory 20 may be implemented as extended memory of the host 10 or as external memory of the host 10, without limitation. The host 10 and the phase-change memory 20 are interconnected. The phase-change memory 20 may be integrated into the host 10 or plugged into the host 10 in a removable manner, without limitation in this embodiment. Regardless of the interconnection method, the host 10 and the phase-change memory 20 may be interconnected using a bus, such as, but not limited to, a DDR (Double Data Rate Synchronous Dynamic Random Access) bus or a PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard).

[0032] Furthermore, when different buses are used for interconnection between the host 10 and the phase-change memory 20, the transmission protocols between the host 10 and the phase-change memory 20 may also vary. For example, when a DDR bus is used for interconnection, the DDR protocol can be used. The DDR protocol includes multiple generations, such as DDR1, DDR2, DDR3, DDR4, and DDR5. Furthermore, based on the topology of the DDR bus, the DDR protocol is further divided into a DDR protocol that supports a T-type topology (DDR-T) and a DDR protocol that supports a daisy-chain topology. The appropriate DDR protocol can be flexibly selected as needed, such as the DDR-T protocol. For another example, when a PCIE bus is used for interconnection, the CXL (Compute Express Link) protocol or the NVMe (Non-volatile Memory Express) protocol can be used. The CXL protocol is a cache coherent interconnect protocol for processors, memory expansion, and accelerators, enabling high-speed and efficient interconnection between the host 10 processor and the phase-change memory 20.

[0033] In this embodiment, at least one application can run on the host 10, and the phase-change memory 20 can provide storage services for one or more applications on the host. The host 10 can use the phase-change memory 20 to provide storage services for one or several applications, or it can flexibly and dynamically allocate the phase-change memory 20 to different applications based on application requirements. For ease of description, the application currently using the phase-change memory 20 to provide storage services is referred to as the target application. The target application can be fixed or dynamically changing. As shown in FIG. 1a , the host 10 may include a first memory 101 and a first CPU 102 (Central Processing Unit). The first CPU 102 is the CPU on the host 10. To distinguish it from the CPU in the phase-change memory 20, the CPU in the host 10 is referred to as the first CPU. The first memory 101 is a memory in the host 10, used to store various software codes such as various application programs and operating systems on the host 10. In Figure 1a, the program code of a target application stored in the first memory 101 is used as an example. The target application is at least one application that currently uses the phase change memory 20 for data access. The first CPU 102 serves as the control brain of the host 10 and is used to execute certain operations on the host 10, such as calculations, control, and data processing.

[0034] As shown in FIG1a , the phase-change memory 20 may include a memory controller 201 and a memory cell array 202. The memory cell array 202 includes multiple memory cells organized and managed in rows and columns. The memory controller 201 and the memory cell array 202 may be interconnected via an internal bus. As shown in FIG1a , the memory controller 201 includes a second CPU 2012, a second memory 2011, a read circuit 2016, and various related hardware registers. The second CPU refers to the CPU within the memory controller 201 and is responsible for executing operations such as calculations, control, and data processing within the memory controller 201. The second memory 2011 refers to the memory within the memory controller 201, primarily the internal memory of the memory controller 201, and is primarily used to store the firmware program for the phase-change memory 20. The firmware program can be understood as program code stored in the second memory 2011 for controlling the phase-change memory 20 and driving its operation. In the disclosed embodiments, whether for a CPU or memory, the terms "first" and "second" are used solely to distinguish different CPUs or memories and do not limit the functions, models, or order of the CPUs or memories. As shown in FIG1a , the registers in the memory controller 201 include at least a voltage level register 2014, a voltage strategy selection register 2013, a vector register, and a times register 2015. These registers are used to store parameters or data related to read control of the phase-change memory 20. For details, see the description of the subsequent method embodiments. These registers are connected to a read circuit 2016. Based on the parameters or data stored in these registers, the read circuit 2016 can read data from the memory cell array 202 and write back data related to the read and write operations to the relevant registers, such as writing various read failure counts to the times register 2015.

[0035] Based on the above architecture, several solutions provided by the embodiments of the present disclosure are briefly described.

[0036] In solution A, to obtain write / read interval description information, the memory controller 201 of the PCM 20 can record the write address and write time of each memory cell. During each read operation, the write time of the memory cell involved in the read operation is queried. Based on the current time and the write time, the data retention time is determined as the write / read interval description information. Furthermore, based on the data retention time, a suitable read voltage for the read operation is determined. This read voltage is provided to the read circuit 2016, which reads data from the corresponding memory cell in the memory cell array 202 based on the read voltage. This solution allows the use of a suitable read voltage for data read operations, which is beneficial for improving the success rate of data read from the PCM 20. The probability of reading data from storage units can improve overall data reading efficiency to a certain extent, as the number of erroneous rereads is reduced. However, recording information at the storage unit granularity and performing query operations at the read operation granularity pose significant challenges to the storage controller 201, both in terms of required storage space and computing resources.

[0037] In solution B, the host 10 is responsible for predicting and maintaining the write / read interval description information when the target application performs a write-first, read-later data operation on the PCM 20. Each time data needs to be read from the PCM, the host 10 provides a read instruction and the write / read interval description information to the storage controller 201 in the PCM 20. Based on the write / read interval description information, the storage controller 201 determines the initial voltage level and the corresponding level switching strategy required for reading data from the storage cell array 202. The storage controller 201 then reads data from the storage cell array 202 based on the initial voltage level and the corresponding level switching strategy. By maintaining the write / read interval description information when the target application performs a write-first, read-later data operation on the PCM 20, the host 10 can promptly update the write / read interval description information based on actual application conditions. This allows the storage controller 201 to provide more accurate write / read interval description information, helping the storage controller 201 more accurately determine the initial voltage level and the corresponding level switching strategy. This increases the probability of successfully reading data from the storage cells of the PCM 20. By reducing the number of erroneous rereads, the overall data reading efficiency can be improved to a certain extent. However, each time the storage controller 201 reads data, there will be a certain delay in determining the initial voltage level and the corresponding level switching strategy in real time. Therefore, this solution B is suitable for some application scenarios that do not have high requirements for data reading latency.

[0038] In solution C, the host 10 can predict the write-read interval description information of the target application when performing a write-first-then-read operation on the PCM 20 in a future time period, and send the write-read interval description information to the storage controller 201 in advance; the storage controller 201 determines the initial voltage level and the corresponding level switching strategy required for reading data based on the write-read interval description information, and then, when data needs to be read from the storage cell array 202 subsequently, it can read data from the PCM 20 based on the initial voltage level and the corresponding level switching strategy. In this approach, the host 10 predicts the write / read interval description information for a target application performing a data write-first-then-read operation on the PCM 20 in a future time period and pre-sends it to the storage controller 201. Without performing any data read / write operations, the storage controller 201 pre-configures the initial voltage level and level switching strategy. When subsequently reading data, data can be directly read based on the pre-configured initial voltage level and level switching strategy. This not only increases the probability of successfully reading data from the PCM 20's storage cells, but also improves the efficiency of each data read, thereby enhancing overall data read efficiency. Furthermore, Solution C is highly adaptable, applicable to both applications with low data read latency requirements and those with high data read latency requirements.

[0039] It should be noted that in the above-mentioned solutions B and C, the logic for the storage controller 201 to set the initial voltage level and the level switching strategy can be pre-set in the firmware program of the phase-change memory. The storage controller can execute the firmware program to set the initial voltage level and the level switching strategy according to the logic in solution B or solution C. The logic for the storage controller to set the initial voltage level and the level switching strategy can be changed or updated by upgrading the firmware program.

[0040] Of course, in Solution C, the write / read interval description information used when the target application performs a write-first-then-read operation on the PCM 20 may change. For example, if the application mode significantly changes or during special periods, the target application may need to switch from low-frequency data reads to frequent data writes and reads, or from high-frequency data reads to low-frequency data reads. The host 10 can sense the change in the write / read interval description information when the target application performs a write-first-then-read operation on the PCM 20, re-predict the latest write / read interval description information, and provide the latest write / read interval description information to the storage controller 201, allowing the storage controller 201 to reset the initial voltage level and level switching strategy. The following embodiments of the present disclosure will focus on Solution C, and the implementation process of Solution C will be described in detail in conjunction with the host system architecture shown in FIG1a and the interaction flow chart shown in FIG1b.

[0041] As shown in FIG. 1b, the process of the host 10 interacting with the storage controller to set the initial voltage level and the level switching strategy includes the following steps.

[0042] Step 11: The host 10 can respond to a preset trigger event and predict the target application's operation on the PCM 20 in the future. Describes the write-read interval when data is written first and then read.

[0043] Step 14: The host 10 sends the write-read interval description information to the storage controller in the PCM 20 based on the interconnection bus between the host 10 and the PCM 20.

[0044] Step 15: After receiving the write / read interval description information sent by the host 10, the storage controller configures the initial voltage level and the corresponding target level switching strategy required for reading data from the storage unit in the PCM 20 according to the write / read interval description information.

[0045] Step 16: The host 10 responds to the read command initiated by the target application and sends the read command to the storage controller based on the interconnection bus between the host 10 and the PCM 20.

[0046] Step 17: When receiving the read command from the target application, the storage controller reads data from the storage unit of the PCM based on the configured initial voltage level and the corresponding target level switching strategy.

[0047] Step 18: If the data is read successfully, the storage controller sends the read data to the host 10, so that the host 10 provides the data to the target application for processing.

[0048] In this way, because the initial voltage level and level switching strategy take into account the write / read interval description information, which reflects voltage drift, not only the initial voltage level but also the level switching strategy corresponding to that initial voltage level are determined, data can be read from the PCM storage cells based on the initial voltage level. This solution rationally configures the initial voltage level and corresponding voltage level adjustment strategy required for reading data from the PCM, increasing the probability of successfully reading data from the PCM storage cells and, consequently, improving overall data reading efficiency.

[0049] In the embodiments of the present disclosure, the prediction triggering event is not limited and can be flexibly set according to application requirements. The following examples illustrate this.

[0050] ①: Resource scheduling event assigning PCM20 to the target application, i.e., assigning PCM20 to the target application. The host 10 can autonomously detect the storage resources required by the target application. If it detects that the current storage space is insufficient to accommodate the required storage resources, it can expand the storage capacity for the target application. In this case, PCM20 can be assigned to the target application and the target application's write and read interval description information can be predicted. Alternatively, the target application can send a request to the host 10 for PCM20 usage based on its own storage resource usage. The host 10 can respond to this request, assign PCM20 to the target application, and trigger the prediction of the target application's write and read interval description information.

[0051] ②: The target application switches operating modes while using the PCM20. Switching operating modes while using the PCM20 may cause changes in the data write and read patterns, which in turn changes the write and read interval description information. In this case, the host 10 can predict the target application's write and read interval description information. For example, if the target application switches from a slow read and write mode (which can be understood as a power-saving mode) to a high-speed read and write mode while using the PCM20, the read and write frequencies in these two modes are different. In response to this preset trigger event, the host 10 can predict the target application's write and read interval description information.

[0052] ③: The target application uses PCM20 for a duration greater than the set duration threshold. Specifically, the target application writes and reads historical data generated by the PCM20 for a duration greater than the preset time interval threshold. This event is considered a preset trigger event if, over time, a large amount of written data is read again after a time interval exceeding the set time threshold.

[0053] In this way, by presetting a relatively rich set of trigger events, the host can timely and accurately predict the write and read interval description information of the target application.

[0054] In some optional embodiments, when the host 10 responds to a preset trigger event and predicts the write-read interval description information of the target application performing a write-first-then-read operation on the PCM in a future time period, it can be implemented based on the following implementation manner.

[0055] Implementation A: In response to a preset trigger event, the write-read interval description is predicted according to the application type of the target application. Information. The target application types may include video production, video playback, games, and navigation. For example, video production applications, such as short video publishing applications in short video scenarios and anchor-side applications in live broadcast scenarios, primarily upload videos for storage and are applications with a high write frequency and a low read frequency. Video playback applications, such as short video publishing applications in short video scenarios and anchor-side applications in live broadcast scenarios, primarily read videos for playback and are applications with a high read frequency and a low write frequency.

[0056] Since different application types have different data read / write modes, and there is a certain correspondence between the data read / write modes and the write / read intervals, the write / read interval description information corresponding to different application types will also be different. Based on this, the host 10 can more accurately determine the write / read interval description information of the target application based on the application type of the target application. Furthermore, the host 10 can pre-maintain a correspondence between the application type and the data read / write mode, determine the target data read / write mode based on the application type of the target application, and further determine the corresponding write / read interval description information based on the target data read / write mode.

[0057] Implementation method B: In response to a preset trigger event, write-read interval description information is predicted based on the application scenario of the target application. The application scenarios may include: data backup scenario, gaming scenario, and vehicle navigation scenario.

[0058] Taking a database as an example, in a data backup scenario, assuming PCM is used as persistent memory on the primary database, the PCM in the primary database primarily performs read operations, reading data from the PCM in the primary database and writing it to the backup database. In everyday applications, the primary database needs to provide both storage and query functions, so both writes and reads are performed, potentially in a full-disk sequential write-followed-by-read mode. This means that the corresponding write-read interval description information can vary depending on the application scenario. For another example, in gaming scenarios, user interaction with the application is frequent, and the target application requires immediacy. Therefore, the write-read interval can be relatively short when performing write-first-then-read operations on the PCM.

[0059] Since different application scenarios have different data read and write modes, and there is a certain correspondence between the data read and write modes and the write and read intervals, the write and read interval description information corresponding to different application scenarios will also be different. Based on this, the host 10 can more accurately determine the write and read interval description information of the target application based on the application scenario of the target application. Furthermore, the host 10 can pre-maintain the correspondence between the application scenario and the data read and write mode, determine the target data read and write mode based on the application scenario of the target application, and further determine the corresponding write and read interval description information based on the target data read and write mode.

[0060] Implementation C: In response to a preset trigger event, write-read interval description information is predicted based on the historical write-read operation information of the target application. The historical write-read operation information of the target application describes detailed information about the read and write operations of the target application within a preset historical time range. The detailed information may include: bandwidth consumed for reading data, bandwidth consumed for writing data, read time, write time, number of read operations, number of write operations, time intervals between read operations, time intervals between write operations, and so on. The historical time range can be any range, for example, 30 seconds, 1 minute, 30 minutes, or 1 hour. This historical read-write operation information can reflect the data read and write pattern of the target application within the historical time period. There is a certain correspondence between the data read and write pattern and the write-read interval. If the data read and write pattern of the target application is relatively stable, the data read and write pattern of the target application in a future time period can be predicted based on this historical read-write operation information. Furthermore, based on the data read and write pattern of the target application in the future time period, the write-read interval description information for the target application performing a write-first-then-read operation on the PCM 20 in the future time period can be determined.

[0061] It should be noted that the above implementation modes A to C can be implemented individually or in combination, and this embodiment does not limit them.

[0062] The above-mentioned Implementation C will be described in further detail below. When the host 10 responds to a preset trigger event and predicts the write-read interval description information based on the historical write-read operation information of the target application, it can be implemented based on the following Implementations C1 to C3.

[0063] Implementation method C1: respond to a preset trigger event, count the historical write operations of the target application within the first set time range The first bandwidth ratio in historical write and read operations is used. Write and read interval description information is predicted based on the first bandwidth ratio. For example, if the bandwidth of historical write operations of the target application within a first set time range is A (bps), and the bandwidth of historical write and read operations of the target application within the first set time range is B (bps), then the first bandwidth ratio is A / B. The host 10 may determine the write and read interval description information based on a preset correspondence between the first bandwidth ratio and the write and read interval description information, as well as the first bandwidth ratio. For example, the preset correspondence between the first bandwidth ratio and the write and read interval description information may include: 80% first bandwidth ratio = 50s write and read interval, 70% first bandwidth ratio = 40s write and read interval, and 60% first bandwidth ratio = 30s write and read interval, etc. If the calculated first bandwidth ratio is 70%, the write and read interval description information may be determined to be 40s write and read interval based on this correspondence.

[0064] Implementation C2: In response to a preset trigger event, a second bandwidth ratio of historical read operations of a target application within a first preset time range is calculated; and write-read interval description information is predicted based on the second bandwidth ratio. For example, if the bandwidth of historical read operations of the target application within the first preset time range is C (bps), and the bandwidth of historical write-read operations of the target application within the first preset time range is D (bps), then the second bandwidth ratio is C / D. The host 10 may determine the write-read interval description information based on a preset correspondence between the second bandwidth ratio and the write-read interval description information, as well as the second bandwidth ratio. For example, the preset correspondence between the second bandwidth ratio and the write-read interval description information may include: 20% second bandwidth ratio = 50s write-read interval, 30% second bandwidth ratio = 40s write-read interval, and 40% second bandwidth ratio = 30s write-read interval, etc. If the calculated second bandwidth ratio is 40%, the write-read interval description information may be determined as 30s write-read interval based on this correspondence.

[0065] In implementation C3, in response to a preset trigger event, the target application calculates the time interval between historical write operations and the first historical read operations on the same data within a second preset time range, and predicts write / read interval description information based on the time intervals. The host 10 may calculate the time interval between historical write operations and the first historical read operations on each data item within the second preset time range. For example, the time interval for data M1 may be T10, the time interval for data M2 may be T20, and the time interval for data M3 may be T30. Based on this, when predicting the write / read interval description information based on the time intervals, the host 10 may perform an averaging operation, a maximum value operation, a minimum value operation, or a weighted sum operation on multiple time intervals, and use the result as the write / read interval description information. This is not limited in this embodiment. The weights used by the host 10 in the weighted summation of multiple time intervals may be preconfigured or set based on the time of the historical write operations, with earlier times receiving smaller weights. For example, if the time of the historical write operation of data M1 is earlier than the time of the historical write operation of data M2, then the weight of the time interval of data M1 may be 1 / 2 greater than the weight of the time interval of data M2.

[0066] In the above manner, the host 10 can respond to a preset trigger event and more accurately predict the write-read interval description information when the target application performs a write-first-then-read operation on the PCM in a future time period.

[0067] In some optional embodiments, as shown in FIG1b , before the host 10 sends the write-read interval description information to the storage controller 201 in the PCM 20, the process further includes: Step 12: The host 10 sends a first mode command to the storage controller 201 in the PCM 20 based on the interconnection bus between the host 10 and the PCM 20; Step 13: The storage controller 201 may respond to the first mode command and set the voltage strategy selection register 2013 to the first gear management mode.

[0068] It should be noted that, in FIG1b , the above steps 12 and 13 are illustrated with dotted lines to indicate that these two steps are optional operations.

[0069] Specifically, the host 10 may send various mode commands to the storage controller 201 to control the storage controller 201 to switch between different gear management modes. This may be specifically implemented based on the following embodiments.

[0070] In the first embodiment, the host 10 may issue a first mode command to the storage controller 201. In response, the storage controller 201 may set the voltage policy selection register to the first gear management mode. The first gear management mode is a mode that uses write / read interval description information to configure the initial voltage gear and target gear switching strategy. Specifically, in this gear management mode, the host 10 can indirectly control the storage controller 201 to perform voltage control by sending the write / read interval description information to the storage controller 201. The first gear management module may be referred to as a firmware model (FM).

[0071] In a second embodiment, the host 10 may issue a second mode command to the storage controller 201. Accordingly, the storage controller 201 may respond to the second mode command by setting the voltage policy selection register 2013 to the second gear management mode. The second gear management mode is a mode that does not rely on write / read interval description information to configure the initial voltage gear and target gear switching policy. In other words, in this gear management mode, the host 10 cannot indirectly control the storage controller 201 by sending write / read interval description information to the storage controller 201 to perform voltage control. Instead, the storage controller 201 performs voltage control autonomously. The second gear management module may be referred to as a hardware model (HM).

[0072] In the third embodiment, the host 10 may also send a mode recovery command to the storage controller 201. Correspondingly, the storage controller 201 may respond to the mode recovery command to restore the second gear management mode configured by the power-on initialization of the PCM 20, as well as the default voltage gear in the second gear management mode and the corresponding default gear switching strategy.

[0073] In this way, the host 10 can flexibly control the storage controller 201 to switch between different gear management modes by sending commands to the PCM 20 .

[0074] In some optional embodiments, the PCM 20 may support multiple write / read intervals, with different write / read intervals corresponding to different range commands. Each write / read interval may correspond to a voltage range, with different write / read intervals corresponding to different voltage ranges. The number of write / read intervals supported by the PCM 20, as well as the range commands and voltage ranges corresponding to different write / read intervals, can be pre-set before the PCM 20 leaves the factory and written into the corresponding firmware of the PCM 20. Of course, the number of write / read intervals supported by the PCM 20, as well as the range commands and voltage ranges corresponding to different write / read intervals, can also be updated through firmware upgrades. The voltage range corresponding to each write / read interval may include multiple voltage ranges. For example, if the voltage range corresponding to a write / read interval is 1V-10V, the voltage range may include four voltage ranges, with voltages of 2V, 4V, 6V, and 8V, respectively. The voltage level in the embodiment of the present disclosure refers to the amplitude of each adjustment of the read voltage. For example, when the voltage level is 2V, it means that when the read voltage is adjusted according to the voltage level, the read voltage will be increased by 2V each time; other voltage levels are similar.

[0075] Based on this, when the host 10 sends the write / read interval description information to the storage controller in the PCM 20, it can determine a target write / read interval level compatible with the write / read interval description information from multiple write / read interval levels. Specifically, the host 10 can determine the target voltage level range for the write / read interval description information from the voltage level range corresponding to each write / read interval level, and use the write / read interval level corresponding to the target voltage level range as the target write / read interval level compatible with the write / read interval description information. After determining the target write / read interval level compatible with the write / read interval description information, the host 10 can send a target level command corresponding to the target write / read interval level to the storage controller. The target write / read interval level represents the write / read interval description information, and the target level command represents the target write / read interval level. Therefore, the target level command represents the write / read interval description information.

[0076] Correspondingly, when receiving the write / read interval description information from the host 10, the storage controller 201 may receive a target gear command issued by the host 10. Furthermore, the storage controller 201 may respond to the target gear command and configure the initial voltage gear and corresponding gear switching strategy required for reading data from the storage cells in the PCM 20 based on the target voltage gear range corresponding to the target write / read interval gear.

[0077] Specifically, the storage controller 201 configures the initial voltage level and the corresponding level switching strategy according to the target voltage level range corresponding to the target write / read interval level, which can be implemented in the following manner.

[0078] Method 1: The storage controller 201 may respond to the target voltage range command and determine an initial voltage range and a corresponding target voltage range switching strategy based on multiple voltage ranges corresponding to the target write / read interval range. The storage controller 201 may randomly select a voltage range from the multiple voltage ranges as the initial voltage range, or may select the largest or smallest voltage range from the multiple voltage ranges as the initial voltage range. Alternatively, the storage controller 201 may select a voltage range located in the middle or near the middle as the initial voltage range, although this embodiment is not limiting. After determining the initial voltage range, the storage controller 201 may generate a switching strategy between the initial voltage range and its adjacent voltage ranges. The switching strategy may include: switching to the immediately adjacent range first, then to a larger range; directly switching to the range immediately next to it; or: Directly switch to a larger gear; this embodiment does not impose any limitation.

[0079] After determining the initial voltage level and the corresponding target level switching strategy, the memory controller 201 may write the initial voltage level and the corresponding target level switching strategy into the voltage level register 2014 shown in FIG. 1a , and provide these to the read circuit 2016 responsible for reading data from the memory cells in the PCM. When reading data from a memory cell, the read circuit 2016 may read the initial voltage level and the target level switching strategy from the voltage level register 2014 and attempt to read data starting from the initial voltage level. If the read fails during the data reading process and the read failure meets the set level switching conditions, the level may be switched according to the target level switching strategy, and attempts to read data may continue at the switched voltage level.

[0080] Method 2: Each voltage range may be assigned a default voltage range, and each default voltage range may correspond to a range switching strategy. Based on this, the storage controller 201 may use the default voltage range within the target voltage range and the range switching strategy corresponding to the default voltage range as the initial voltage range and the target range switching strategy, respectively. The voltage range, the default voltage range within the voltage range, and the corresponding range switching strategy may be pre-set in the PCM firmware and dynamically updated through PCM firmware upgrades.

[0081] Specifically, in the second approach described above, a voltage range may include multiple first-level voltage ranges. Any first-level voltage range is the maximum value of any of the multiple voltage ranges obtained by dividing the voltage range, and is used to adjust the voltage of the storage cells in the PCM 20. The value of any first-level voltage range can be understood as the adjustment value used when adjusting the reference voltage of the storage cells in the PCM 20.

[0082] For example, the voltage range of 1V-20V may include: a first-level voltage level D1 (5V), a first-level voltage level D2 (10V), and a first-level voltage level D3 (15V). When the configured initial voltage level is the first-level voltage level D1 (5V), the storage controller 201 may superimpose a 5V voltage on the reference voltage (e.g., 2V) applied to the PCM 20, thereby adjusting the 2V reference voltage to 7V.

[0083] Furthermore, a primary voltage level may also include multiple secondary voltage levels. A secondary voltage level is smaller than the primary voltage level to which it belongs. A secondary voltage level is any voltage value within any of the multiple voltage ranges obtained by dividing the voltage level range. This arbitrary voltage value can be customized based on actual design requirements, as long as it is smaller than the primary voltage level to which it belongs. This is not a limitation in this embodiment. The value of any secondary voltage level can be understood as an adjustment value for adjusting the sum of the reference voltage of a storage cell in PCM 20 and the primary voltage level to which it belongs. Continuing with the previous example, the primary voltage level DI (5V) may include secondary voltage levels D11 (IV) and D12 (3V). Secondary voltage level D11 (IV) can be used to superimpose IV on 7V, thereby adjusting the sum of the reference voltage of a storage cell in PCM 20 and the primary voltage level to which it belongs (7V) to 8V.

[0084] Based on this, when the storage controller 201 uses the default voltage level in the target voltage level range and its corresponding level switching strategy as the initial voltage level and the target level switching strategy, respectively, the default first-level voltage level and the default second-level voltage level below the default first-level voltage level in the target voltage level range may be used as the initial voltage level; and the level switching strategy corresponding to the default first-level voltage level and the level switching strategy corresponding to the default second-level voltage level may be used as the target level switching strategy.

[0085] Through the first and second approaches, the storage controller 201 can more accurately configure the initial voltage level and the corresponding level switching strategy required when reading data from the storage unit in the PCM according to the write-read interval description information.

[0086] In some optional embodiments, when the storage controller 201 receives a read command from a target application, the storage controller 201 may switch the strategy based on the initial voltage level and the corresponding target level to read data from the storage unit of the PCM in the following manner.

[0087] Upon receiving a read command from a target application, the storage controller 201 controls the read circuit 2016 to read data from the PCM storage cells based on the initial voltage level. The storage controller 201 then interacts with registers on the PCM 20 to determine whether the number of read failures meets the policy switching condition.

[0088] During the data read process, the read circuit 2016 can write relevant count information into at least one of the first count register, the second count register, and the third count register. Accordingly, the storage controller 201 can obtain the count information written by the read circuit 2016 into at least one of the first count register, the second count register, and the third count register. The first count register records the total number of read operations, the second count register records the number of successful reads after N rereads, and the third count register records the number of successful reads after M rereads. N and M are positive integers, and N is less than M. In an optional embodiment, N=1 and M=2, but this is not limited to this. Furthermore, the storage controller 201 can determine whether the number of read failures meets a switching condition based on this count information.

[0089] When the number of read failures meets the switching condition, the storage controller 201 can switch a new initial voltage level from the target voltage level range according to the target level switching strategy, and control the read circuit 2016 to continue reading data from the storage unit of the PCM based on the new initial voltage level.

[0090] The following examples illustrate the switching conditions and target gear switching strategies under different switching conditions.

[0091] From a single read operation perspective, a single read of a certain data from a storage cell of PCM 20 may fail. In this case, the read circuit 2016 can re-read the data. Based on this, a switching condition can be that the number of read failures by the read circuit 2016 for a certain data is greater than a positive integer N (e.g., 1). That is, for a certain data, when a read failure occurs once, it can be determined that the number of read failures meets the switching condition, and the current initial voltage level (a secondary voltage level within a primary voltage level) is switched to a higher secondary voltage level within the target voltage level range.

[0092] Furthermore, when the number of read failures of the read circuit 2016 for a certain data is not less than a positive integer M (for example, 2), the current first-level voltage level in the target voltage level range may be switched to another first-level voltage level. That is, after the read circuit 2016 fails to read a certain data N times, it will continue to attempt to read. If the read still fails after M times, the current first-level voltage level may be switched to another first-level voltage level.

[0093] From the perspective of global read operations, the switching condition may include that the frequency of read failures within a set time period is higher than a preset frequency threshold. The storage controller 201 may count the frequency of read failures within the preset time period by reading the number information written to at least one of the first number register, the second number register, and the third number register by the reading circuit 2016, and determine whether the number of read failures within the preset time period meets the switching condition. If the switching condition is met, the current initial voltage level (a secondary voltage level under a primary voltage level) is switched to a higher secondary voltage level within the target voltage level range.

[0094] Furthermore, the switching condition may also include that the number of reread failures M times is greater than a set threshold value (for example, 5). If the switching condition is met, the storage controller 201 may switch the current initial voltage level (a certain first-level voltage) to a larger first-level voltage level from the target voltage level range when the number of read failures meets the switching condition.

[0095] Furthermore, the switching condition may also include the number of times multiple data items have been reread M times without success. For example, if five data items have failed to be reread M times (e.g., twice) in a row, and only succeeded after switching to a higher voltage level, the next higher voltage level may be selected.

[0096] In the above manner, the storage controller 201 can flexibly switch between the primary voltage level and the secondary voltage level within the target voltage level range according to the target level switching strategy when the number of read failures meets the switching condition, thereby more accurately controlling the read circuit 2016 based on the adjusted voltage level.

[0097] FIG2 is a flow chart of a voltage control method for a phase change memory PCM provided by another exemplary embodiment of the present disclosure. When the method is executed by a host computer 1, the method may include steps 201 and 202 as shown in FIG2.

[0098] Step 201: In response to a preset trigger event, predict the write-read interval description information of a target application when performing a write-first-then-read operation on a PCM in a future period of time, where the target application is an application on a host that uses the PCM for data access.

[0099] Step 202: Send the write / read interval description information to the storage controller in the PCM, so that the storage controller configures the initial voltage level and the corresponding target level switching strategy required for reading data from the storage unit in the PCM according to the write / read interval description information.

[0100] In this way, because the initial voltage level and level switching strategy take into account the write / read interval description information, which reflects voltage drift, not only the initial voltage level but also the level switching strategy corresponding to that initial voltage level are determined, data can be read from the PCM storage cells based on the initial voltage level. This solution rationally configures the initial voltage level and corresponding voltage level adjustment strategy required for reading data from the PCM, increasing the probability of successfully reading data from the PCM storage cells and, consequently, improving overall data reading efficiency.

[0101] Optionally, in response to a preset trigger event, predicting write-read interval description information of a target application performing a data write-then-read operation on a PCM in a future time period includes: in response to the preset trigger event, predicting the write-read interval description information according to an application type, an application scenario, and / or historical write-read operation information of the target application.

[0102] Optionally, in response to a preset trigger event, predicting write-read interval description information based on historical write and read operation information of the target application includes: in response to the preset trigger event, counting a first bandwidth ratio of historical write operations of the target application within a first set time range in the historical write and read operations; predicting the write-read interval description information based on the first bandwidth ratio; and / or, in response to the preset trigger event, counting a second bandwidth ratio of historical read operations of the target application within the first set time range in the historical write and read operations; predicting the write-read interval description information based on the second bandwidth ratio; and / or, in response to the preset trigger event, counting a time interval between a historical write operation and a first historical read operation of the target application for the same data within a second preset time range, and predicting the write-read interval description information based on the time interval.

[0103] Optionally, the preset trigger event includes: a resource scheduling event that allocates PCM to the target application; and / or an event that the target application switches the working mode during the use of PCM; and / or an event that the target application uses PCM for a time greater than a set time threshold.

[0104] Optionally, the PCM supports multiple write-read interval gears, different write-read interval gears correspond to different gear commands, and one write-read interval gear corresponds to a voltage gear range; the write-read interval description information is sent to the storage controller in the PCM, so that the storage controller configures the initial voltage gear required to read data from the storage unit in the PCM and the corresponding target gear switching strategy according to the write-read interval description information, including: determining a target write-read interval gear that is compatible with the write-read interval description information from multiple write-read interval gears; and sending a target gear command corresponding to the target write-read interval gear to the storage controller, so that the storage controller configures the initial voltage gear and the corresponding target gear switching strategy according to the voltage gear range corresponding to the target write-read interval gear.

[0105] Optionally, before sending the write-read interval description information to the storage controller in the PCM, the method further includes: sending a first mode command to the storage controller to enable the storage controller to operate in a first gear management mode, where the first gear management mode refers to a mode for configuring an initial voltage gear and a target gear switching strategy based on the write-read interval description information.

[0106] Optionally, the method further includes: issuing a second mode command to the storage controller to enable the storage controller to operate in a second gear management mode, where the second gear management mode refers to a mode that does not rely on write-read interval description information to configure the initial voltage gear and the target gear switching strategy; or issuing a mode recovery command to the storage controller to enable the storage controller to restore the second gear management mode configured for PCM power-on initialization, as well as the default voltage gear and the corresponding default gear switching strategy under the second gear management mode.

[0107] The detailed implementation and beneficial effects of each step in the method of this embodiment have been described in detail in the aforementioned embodiments and will not be elaborated on here.

[0108] FIG3 is a flow chart of a method for reading data from a phase change memory provided by another exemplary embodiment of the present disclosure. When executed by a memory controller in a PCM, the method may include steps 301 to 303 as shown in FIG3 .

[0109] Step 301: Receive the target application sent by the host and perform a data write-first and read-later operation on the PCM in the future period. The target application is an application on the host that uses PCM to access data.

[0110] Step 302: Configure the initial voltage level and the corresponding target level switching strategy required when reading data from the storage unit in the PCM according to the write-read interval description information.

[0111] Step 303: upon receiving a read command from the target application, data is read from the storage unit of the PCM based on the initial voltage level and the corresponding target level switching strategy.

[0112] In this way, because the initial voltage level and level switching strategy take into account the write / read interval description information, which reflects voltage drift, not only the initial voltage level but also the level switching strategy corresponding to that initial voltage level are determined, data can be read from the PCM storage cells based on the initial voltage level. This solution rationally configures the initial voltage level and corresponding voltage level adjustment strategy required for reading data from the PCM, increasing the probability of successfully reading data from the PCM storage cells and, consequently, improving overall data reading efficiency.

[0113] Optionally, the PCM supports multiple write and read interval gears, and different write and read interval gears correspond to different gear commands; receiving write and read interval description information sent by the host when the target application performs a data write-first-then-read operation on the PCM in a future time period, includes: receiving a target gear command sent by the host, the target gear command corresponds to a target write and read interval gear, and the target write and read interval gear is a write and read interval gear among the multiple write and read interval gears that is adapted to the write and read interval description information.

[0114] Optionally, one write-read interval gear corresponds to a voltage gear range, and the voltage gear range includes multiple voltage gears. Then, according to the write-read interval description information, an initial voltage gear and a corresponding gear switching strategy required for reading data from a storage unit in the PCM are configured, including: determining an initial voltage gear and a corresponding target gear switching strategy based on multiple voltage gears in a target voltage gear range corresponding to a target write-read interval gear; and writing the initial voltage gear and the corresponding target gear switching strategy into a voltage gear register to provide them to a read circuit responsible for reading data from a storage unit in the PCM.

[0115] Optionally, a default voltage range is set in a voltage range, and the default voltage range corresponds to a range switching strategy; configuring the initial voltage range and the corresponding range switching strategy according to multiple voltage ranges in the target voltage range corresponding to the target write / read interval range includes: using the default voltage range in the target voltage range and the corresponding range switching strategy as the initial voltage range and the target range switching strategy, respectively.

[0116] Optionally, a voltage gear range includes multiple first-level voltage gears, a first-level voltage gear includes multiple second-level voltage gears, and the second-level voltage gear is smaller than the first-level voltage gear to which it belongs; the default voltage gear in the target voltage gear range and its corresponding gear switching strategy are used as the initial voltage gear and the target gear switching strategy, respectively, including: using the default first-level voltage gear in the target voltage gear range and the default second-level voltage gear below the default first-level voltage gear as the initial voltage gear; using the gear switching strategy corresponding to the default first-level voltage gear and the gear switching strategy corresponding to the default second-level voltage gear as the target gear switching strategy.

[0117] Optionally, upon receiving a read command from a target application, reading data from a storage unit of the PCM based on the initial voltage level and a corresponding target level switching strategy includes: upon receiving a read command from the target application, controlling a read circuit to read data from the storage unit of the PCM based on the initial voltage level; and, when the number of read failures meets a switching condition, switching to a new initial voltage level from a target voltage level range according to the target level switching strategy, and controlling the read circuit to continue reading data from the storage unit of the PCM based on the new initial voltage level.

[0118] Optionally, the method further includes: obtaining number information written by the reading circuit in a first number register, a second number register and / or a third number register; judging, based on the number information, whether the number of read failures satisfies a switching condition; wherein, the number of read operations recorded in the first number register, the number of successful reads after rereading N times recorded in the second number register, and the number of successful reads after rereading M times recorded in the third number register; N and M are positive integers, and N is less than M.

[0119] Optionally, before receiving the write-read interval description information sent by the host, the process further includes: receiving the first A mode command is sent, and the voltage strategy selection register is set to the first gear management mode. The first gear management mode refers to a mode for configuring the initial voltage gear and the target gear switching strategy based on the write-read interval description information.

[0120] Optionally, the method further includes: receiving a second mode command sent by the host, and setting the voltage strategy selection register to the second gear management mode, where the second gear management mode refers to a mode that does not rely on write-read interval description information to configure the initial voltage gear and target gear switching strategy; or receiving a mode recovery command sent by the host, and setting the voltage strategy selection register to the second gear management mode, and setting the voltage gear register to the default voltage gear and the corresponding default gear switching strategy under the second gear management mode.

[0121] The detailed implementation and beneficial effects of each step in the method of this embodiment have been described in detail in the aforementioned embodiments and will not be elaborated on here.

[0122] The voltage control and data reading method of the present disclosure will be further described below from a host example and a PCM example in combination with actual application scenarios.

[0123] The host instance can control the storage controller to enter different modes by issuing the following commands to the storage controller.

[0124] L1 command (i.e., the first mode command mentioned above): This command switches the host firmware control strategy to the controller logic control strategy, that is, the firmware switching strategy becomes invalid, and the storage controller performs voltage control based on the interval description information.

[0125] L2 command (i.e., the second mode command mentioned above): This command switches the controller logic control strategy to the host firmware control strategy, that is, the storage controller no longer performs voltage control based on the interval description information.

[0126] L0 command (also referred to as the mode restore command): When the storage controller receives this command, all adjustment commands previously issued by the host to the storage controller are invalid. The storage controller selects the gear strategy according to the power-on initialization configuration. Specifically, the storage controller restores the second gear management mode, the default voltage level, and the corresponding default gear switching strategy in the second gear management mode configured during power-on initialization.

[0127] In addition, in this embodiment, the gears can be divided into multiple different types according to the write and read interval description information. Different types of gears can correspond to different commands, such as the following commands.

[0128] L3 commands correspond to the write-read cold mode. This mode is suitable for read-after-write scenarios with a latency of 100 seconds or more. This mode can be proactively switched to when data is mostly read with little write activity, or when write bandwidth usage has been reduced to a very low level for a long period of time. This mode is typically beneficial in long-term stability testing or post-production scenarios with low load. The write-read hot mode is suitable for read-after-write scenarios with a latency of 300ms or less.

[0129] L4 command: Corresponding to the write-read hot gear, this gear is suitable for write-after-read scenarios with a speed of 300ms or less. When data scenarios are mostly write-intensive or when write bandwidth usage is at a very high level for a long time, it can be considered to be actively switched to this scenario. It is usually more advantageous in stress testing scenarios or performance competition scenarios.

[0130] L5 command: corresponds to the write-read temperature range, which is suitable for write-read scenarios with a 300ms-100s level. When the data scenario has a regular sequential write and read scenario, the software can determine whether the write-read interval is within this range based on calculations. If so, this range can be set.

[0131] The three gears corresponding to the above L3-L4 command are merely examples of the write-read interval gears mentioned above. In addition, the write-read intervals and application scenarios corresponding to the three gears are merely examples and are not limited thereto.

[0132] The following will explain the process of the host instance determining the gear from the perspective of the host instance: In the default state of the host instance, no operation or cmd (Command Prompt) command is required. In the subsequent process, the host can send corresponding commands to the storage controller according to the gear adjustment requirements. For example, if it is necessary to return to the firmware default configuration, the host can send the target gear command cmd L0 to the storage controller to adjust the control logic of the storage controller to L0. If it is necessary to switch to the L1 policy, the host can send the target gear command cmd L1 to the storage controller to adjust the control logic of the storage controller to LL. If it is necessary to switch to the L2 policy, the host can send the target gear command cmd L1 to the storage controller to adjust the control logic of the storage controller to LL. The host issues a target gear command (cmd L2) to adjust the storage controller's control logic to L2. If the write bandwidth usage falls below 5% of the rated bandwidth within 10 minutes, the host can issue a target gear command (cmd L3) to the storage controller to adjust the storage controller's control logic to L3. If the write bandwidth usage rises above 60% of the rated bandwidth within 10 minutes, the host can issue a target gear command (cmd L4) to adjust the storage controller's control logic to L4. If the read interval after a full-disk sequential write is 300ms to 100s, the host can issue a target gear command (cmd L5) to adjust the storage controller's control logic to L5. If the read interval after a full-disk sequential write is less than 300ms, the host can issue a target gear command (cmd L4) to adjust the storage controller's control logic to L5. If all disks are written sequentially and then read after a delay of more than 100 seconds, the host can send a target gear command cmd L3 to the storage controller to adjust the storage controller's control logic to L3.

[0133] The following will be combined with Figure 4 to illustrate the storage controller's voltage level processing logic from the perspective of a storage controller example. In the following embodiment, the PCM supports two levels of voltage levels. The first-level voltage level includes five levels, namely Va, Vb, Vc, Vd, and Ve. Each first-level voltage level includes three second-level voltage levels, which are indicated by subscripts x, y, and z below the first-level voltage level. Taking the first-level voltage level Vb as an example, it includes second-level voltage levels Vbx, Vby, and Vbz, and the others are similar.

[0134] ① The storage controller can power on and check endurance information, selecting any primary voltage level (Vb) from multiple primary voltage levels (Va, Vb, Vc, Vd, Ve). During operation, if the endurance indicator exceeds the switching threshold specified by the media management policy, the primary voltage level (Vb) can be switched to the primary voltage level (Vd). This switching method is merely an example, primarily indicating that other voltage levels can be switched. ② Based on the media management policy, the default secondary voltage level (Vbx) is selected from the secondary voltage levels (Vbx, Vby, Vbz) associated with the default primary voltage level (Vb).

[0135] ③ When the storage controller receives the host command "cmd L*," it can update the firmware policy or switch to the primary voltage range based on the value of *. Specifically, the "*" in the command "cmd L*" can be any number from 1 to 5. The command differs depending on the number * represents. For example, when "*" is 1, the command "cmd Ll" is the first-mode command, which sets the read mode to the first-range management mode (firmware mode, FM). Before the range switching policy takes effect in FM mode, the media management policy uses the range switching policy defined in HW mode. After the range switching policy takes effect in FM mode, the media management policy uses the range switching policy defined in FM mode. The range switching policy defines the switching methods between secondary voltage ranges, from secondary voltage range to primary voltage range, and between primary voltage ranges.

[0136] ④ For a single read operation, when a read fails and a reread occurs, the storage controller can switch the current secondary voltage gear to a subsequent secondary voltage gear according to the gear switching strategy defined in the media management strategy, for example, from Vbx to Vby and then to Vbz.

[0137] ⑤ If the read fails twice, switch to the first-level voltage gear and try again according to the media management strategy; if this happens more than 5 times, update the first-level voltage gear to be used subsequently.

[0138] ⑥ When the reread probability is higher than the preset threshold, the current secondary voltage level can be switched to the subsequent default secondary voltage level according to the media management strategy, or the subsequent primary voltage level can be updated.

[0139] ⑦Logic voltage gear adaptive function switch. When turned on (receiving host cmd L1 or L2), the logic determines the subsequent default gear based on the last successful gear, and the firmware gear configuration register is closed at this time; when turned off, the logic no longer actively updates the gear, but reads the firmware gear configuration register to determine the subsequent voltage gear.

[0140] The registers in the PCM include: ① Voltage level register reg_VreadLevel, which is readable and writable by the firmware and is used by the firmware to control the current system voltage level. ② Voltage strategy selection register reg_VreadHw, which is readable and writable by the firmware and is used to select between autonomous voltage control and firmware-controlled voltage control during firmware initialization. ③ Read count register group, which includes the following three registers: reg_ReadCount (the first count register mentioned above), reg_ReadRetry1Count (the second count register mentioned above), and reg_ReadRetry2Count (the third count register mentioned above). These registers are readable and writable by the firmware and are used to record the total number of reads, the number of successful rereads (one time), and the number of successful rereads (two times). After reading, the firmware can choose to actively clear these registers.

[0141] For a write operation, data can be written directly to the memory cell array. Optionally, to facilitate subsequent read operations, it is also possible to detect whether the read mode is the FW mode. If so, relevant registers are set according to the FW mode. If not, relevant registers are set according to the HW mode to facilitate subsequent data reading.

[0142] In this embodiment, write-read interval description information for an application performing a write-first-then-read data operation on a PCM can be obtained. Based on this description information, the initial voltage level and level switching strategy required for reading data from the PCM's storage cells are determined. Data is then read from the PCM based on the initial voltage level and level switching strategy. Because the initial voltage level and level switching strategy take into account the write-read interval description information, which can reflect voltage drift, not only the initial voltage level but also the level switching strategy corresponding to the initial voltage level are determined. This allows data to be read from the PCM's storage cells based on the initial voltage level. If a read fails at the initial voltage level, a voltage level switch is performed based on the level switching strategy. This improves the probability of successfully reading data from the PCM's storage cells and overall data reading efficiency.

[0143] It should be noted that the execution entity of each step of the method provided in the above embodiment may be the same device, or the method may be executed by different devices. For example, the execution entity of steps 301 to 303 may be device A; for another example, the execution entity of steps 301 and 302 may be device A, and the execution entity of step 303 may be device B; and so on.

[0144] Furthermore, some of the processes described in the above embodiments and accompanying drawings include multiple operations that appear in a specific order. However, it should be understood that these operations may be executed in a different order than the order in which they appear herein or in parallel. Operation sequence numbers, such as 301 and 302, are merely used to distinguish between different operations and do not represent any specific execution order. Furthermore, these processes may include more or fewer operations, and these operations may be executed sequentially or in parallel. It should be noted that terms such as "first" and "second" are used herein to distinguish between different messages, devices, modules, and the like, and do not represent a sequential order or limit "first" and "second" to different types.

[0145] Figure 5 is a schematic diagram of the structure of a voltage control device for a phase change memory provided by another exemplary embodiment of the present disclosure. As shown in Figure 5, the device includes a prediction module 501, configured to, in response to a preset trigger event, predict write / read interval description information for a target application performing a write-first-then-read data operation on a PCM within a future time period. The target application is an application on the host that uses the PCM for data access. A delivery module 502, configured to deliver the write / read interval description information to a storage controller in the PCM, so that the storage controller configures the initial voltage level and corresponding target level switching strategy required for reading data from storage cells in the PCM based on the write / read interval description information.

[0146] Optionally, when the prediction module 501 responds to a preset trigger event and predicts the write-read interval description information when the target application performs a data write-then-read operation on the PCM in a future time period, it is configured to: respond to the preset trigger event and predict the write-read interval description information according to the application type, application scenario and / or historical write-read operation information of the target application.

[0147] Optionally, when the prediction module 501 predicts the write-read interval description information based on historical write and read operation information of the target application in response to a preset trigger event, the prediction module 501 is specifically configured to: in response to the preset trigger event, calculate a first bandwidth ratio of historical write operations of the target application in the historical write and read operations within a first preset time range; predict the write-read interval description information based on the first bandwidth ratio; and / or, in response to the preset trigger event, calculate a second bandwidth ratio of historical read operations of the target application in the historical write and read operations within the first preset time range; predict the write-read interval description information based on the second bandwidth ratio; and / or, in response to the preset trigger event, calculate a time interval between historical write operations and first historical read operations of the target application for the same data within a second preset time range, and predict the write-read interval description information based on the time interval.

[0148] Optionally, the preset trigger event includes: a resource scheduling event that allocates PCM to the target application; and / or an event that the target application switches the working mode during the use of PCM; and / or an event that the target application uses PCM for a time greater than a set time threshold.

[0149] Optionally, the PCM supports multiple write and read interval gears, and different write and read interval gears correspond to different gear commands. One write-read interval gear corresponds to one voltage gear range; the sending module 502 sends the write-read interval description information to the storage controller in the PCM, so that the storage controller configures the initial voltage gear required to read data from the storage unit in the PCM and the corresponding target gear switching strategy according to the write-read interval description information. Specifically, it is used to: determine the target write-read interval gear that is compatible with the write-read interval description information from multiple write-read interval gears; send the target gear command corresponding to the target write-read interval gear to the storage controller, so that the storage controller configures the initial voltage gear and the corresponding target gear switching strategy according to the voltage gear range corresponding to the target write-read interval gear.

[0150] Optionally, before sending the write-read interval description information to the storage controller in the PCM, the sending module 502 is further used to: send a first mode command to the storage controller to enable the storage controller to operate in a first gear management mode, where the first gear management mode refers to a mode that configures an initial voltage gear and a target gear switching strategy based on the write-read interval description information.

[0151] Optionally, the sending module 502 is further used to: send a second mode command to the storage controller to enable the storage controller to operate in the second gear management mode, where the second gear management mode refers to a mode that does not rely on write-read interval description information to configure the initial voltage gear and target gear switching strategy; or send a mode recovery command to the storage controller to enable the storage controller to restore the second gear management mode configured during PCM power-on initialization, as well as the default voltage gear and the corresponding default gear switching strategy under the second gear management mode.

[0152] In this embodiment, write-read interval description information for an application performing a write-first-then-read data operation on a PCM can be obtained. Based on this description information, the initial voltage level and level switching strategy required for reading data from the PCM's storage cells are determined. Data is then read from the PCM based on the initial voltage level and level switching strategy. Because the initial voltage level and level switching strategy take into account the write-read interval description information, which can reflect voltage drift, not only the initial voltage level but also the level switching strategy corresponding to the initial voltage level are determined. This allows data to be read from the PCM's storage cells based on the initial voltage level. If a read fails at the initial voltage level, a voltage level switch is performed based on the level switching strategy. This improves the probability of successfully reading data from the PCM's storage cells and overall data reading efficiency.

[0153] Figure 6 is a schematic diagram of the structure of a data reading device for a phase-change memory provided by another exemplary embodiment of the present disclosure. As shown in Figure 6, the device includes: a receiving module 601, configured to receive, from a host, a description of the write-read interval for a target application performing a write-first-then-read operation on a PCM within a future time period; the target application being an application on the host that uses the PCM for data access; a configuration module 602, configured to configure, based on the write-read interval description, the initial voltage level and the corresponding target level switching strategy required for reading data from a storage cell in the PCM; and a reading module 603, configured to, upon receiving a read command from the target application, read data from the storage cell in the PCM based on the initial voltage level and the corresponding target level switching strategy.

[0154] Optionally, the PCM supports multiple write-read interval gears, and different write-read interval gears correspond to different gear commands; when the receiving module 601 receives the write-read interval description information sent by the host when the target application performs a data write-first-then-read operation on the PCM in a future time period, it is specifically used to: receive the target gear command sent by the host, the target gear command corresponds to the target write-read interval gear, and the target write-read interval gear is a write-read interval gear among the multiple write-read interval gears that is adapted to the write-read interval description information.

[0155] Optionally, one write-read interval gear corresponds to a voltage gear range, and the voltage gear range includes multiple voltage gears. Then, when configuring the initial voltage gear and the corresponding gear switching strategy required for reading data from the storage unit in the PCM according to the write-read interval description information, the configuration module 602 is specifically used to: determine the initial voltage gear and the corresponding target gear switching strategy based on the multiple voltage gears in the target voltage gear range corresponding to the target write-read interval gear; and write the initial voltage gear and the corresponding target gear switching strategy into the voltage gear register to provide them to the read circuit responsible for reading data from the storage unit in the PCM.

[0156] Optionally, a default voltage gear is set in a voltage gear range, and the default voltage gear corresponds to a gear switching strategy; the configuration module 602 is configured according to the target write and read interval gear corresponding to the target voltage gear range, the initial voltage gear and the corresponding gear switching strategy, specifically for: The default voltage gear and its corresponding gear switching strategy in are used as the initial voltage gear and target gear switching strategy respectively.

[0157] Optionally, a voltage gear range includes multiple first-level voltage gears, a first-level voltage gear includes multiple second-level voltage gears, and the second-level voltage gear is smaller than the first-level voltage gear to which it belongs; when the configuration module 602 uses the default voltage gear in the target voltage gear range and its corresponding gear switching strategy as the initial voltage gear and the target gear switching strategy, respectively, it is specifically used to: use the default first-level voltage gear in the target voltage gear range and the default second-level voltage gear below the default first-level voltage gear as the initial voltage gear; use the gear switching strategy corresponding to the default first-level voltage gear and the gear switching strategy corresponding to the default second-level voltage gear as the target gear switching strategy.

[0158] Optionally, when receiving a read command from a target application, the read module 603 reads data from the storage unit of the PCM based on the initial voltage level and the corresponding target level switching strategy. Specifically, the read module 603 is used to: control the read circuit to read data from the storage unit of the PCM based on the initial voltage level when receiving a read command from the target application; and, when the number of read failures meets the switching condition, switch to a new initial voltage level from the target voltage level range according to the target level switching strategy, and control the read circuit to continue reading data from the storage unit of the PCM based on the new initial voltage level.

[0159] Optionally, the reading module 603 is further used to: obtain the number of times written by the reading circuit in the first number register, the second number register and / or the third number register; and determine whether the number of read failures meets the switching condition based on the number information; wherein, the number of read operations recorded in the first number register, the number of successful reads after rereading N times recorded in the second number register, and the number of successful reads after rereading M times recorded in the third number register; N and M are positive integers, and N is less than M.

[0160] Optionally, before receiving the write-read interval description information sent by the host, the receiving module 601 is further configured to: receive a first mode command sent by the host, and set the voltage strategy selection register to the first gear management mode, where the first gear management mode refers to a mode for configuring the initial voltage gear and target gear switching strategy based on the write-read interval description information.

[0161] Optionally, the receiving module 601 is further configured to: receive a second mode command sent by the host, and set the voltage policy selection register to the second gear management mode, where the second gear management mode refers to a mode that does not rely on write-read interval description information to configure the initial voltage gear and the target gear switching strategy; or receive a mode recovery command sent by the host, and set the voltage policy selection register to the second gear management mode, and set the voltage policy selection register to the default voltage gear and the corresponding default gear switching strategy under the second gear management mode.

[0162] In this embodiment, write-read interval description information for an application performing a write-first-then-read data operation on a PCM can be obtained. Based on this description information, the initial voltage level and level switching strategy required for reading data from the PCM's storage cells are determined. Data is then read from the PCM based on the initial voltage level and level switching strategy. Because the initial voltage level and level switching strategy take into account the write-read interval description information, which can reflect voltage drift, not only the initial voltage level but also the level switching strategy corresponding to the initial voltage level are determined. This allows data to be read from the PCM's storage cells based on the initial voltage level. If a read fails at the initial voltage level, a voltage level switch is performed based on the level switching strategy. This improves the probability of successfully reading data from the PCM's storage cells and overall data reading efficiency.

[0163] The above describes the internal functions and structure of the voltage control device of the phase change memory. As shown in FIG7 , in practice, the voltage control device of the phase change memory can be implemented as a host device, which includes: a memory 701, a processor 702, and a communication component 703.

[0164] The memory 701 is used to store computer programs and can be configured to store various other data to support operations on the host device. Examples of such data include instructions for any application or method operating on the host device, contact data, phone book data, messages, images, videos, etc.

[0165] The memory 701 may be implemented by any type of volatile or non-volatile storage device or a combination thereof. Such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0166] A processor 702 is coupled to the memory 701 and is configured to execute a computer program in the memory 701, so as to: predict, in response to a preset trigger event, write-read interval description information of a target application when performing a write-first-then-read operation on a PCM in a future time period, where the target application is an application on the host that uses the PCM for data access; and send the write-read interval description information to a storage controller in the PCM, so that the storage controller configures an initial voltage level and a corresponding target level switching strategy required for reading data from a storage unit in the PCM according to the write-read interval description information.

[0167] Optionally, when the processor 702 predicts, in response to a preset trigger event, write-read interval description information of a target application performing a write-first-then-read operation on the PCM in a future time period, the processor 702 is configured to: predict, in response to the preset trigger event, the write-read interval description information according to an application type, an application scenario, and / or historical write-read operation information of the target application.

[0168] Optionally, when the processor 702 responds to a preset trigger event and predicts the write-read interval description information based on historical write and read operation information of the target application, the processor 702 is specifically configured to: in response to the preset trigger event, calculate a first bandwidth ratio of historical write operations of the target application in the historical write and read operations within a first preset time range; predict the write-read interval description information based on the first bandwidth ratio; and / or, in response to the preset trigger event, calculate a second bandwidth ratio of historical read operations of the target application in the historical write and read operations within the first preset time range; predict the write-read interval description information based on the second bandwidth ratio; and / or, in response to the preset trigger event, calculate a time interval between a historical write operation and a first historical read operation of the target application for the same data within a second preset time range, and predict the write-read interval description information based on the time interval.

[0169] Optionally, the preset trigger event includes: a resource scheduling event that allocates PCM to the target application; and / or an event that the target application switches the working mode during the use of PCM; and / or an event that the target application uses PCM for a time greater than a set time threshold.

[0170] Optionally, the PCM supports multiple write-read interval gears, different write-read interval gears correspond to different gear commands, and one write-read interval gear corresponds to a voltage gear range; the processor 702 sends the write-read interval description information to the storage controller in the PCM, so that the storage controller configures the initial voltage gear required to read data from the storage unit in the PCM and the corresponding target gear switching strategy according to the write-read interval description information, specifically for: determining a target write-read interval gear that is compatible with the write-read interval description information from multiple write-read interval gears; and sending a target gear command corresponding to the target write-read interval gear to the storage controller, so that the storage controller configures the initial voltage gear and the corresponding target gear switching strategy according to the voltage gear range corresponding to the target write-read interval gear.

[0171] Optionally, before sending the write-read interval description information to the storage controller in the PCM, the processor 702 is further configured to: send a first mode command to the storage controller to enable the storage controller to operate in a first gear management mode, where the first gear management mode refers to a mode that configures an initial voltage gear and a target gear switching strategy based on the write-read interval description information.

[0172] Optionally, the processor 702 is further used to: issue a second mode command to the storage controller to enable the storage controller to operate in the second gear management mode, where the second gear management mode refers to a mode that does not rely on write-read interval description information to configure the initial voltage gear and the target gear switching strategy; or issue a mode recovery command to the storage controller to enable the storage controller to restore the second gear management mode configured during PCM power-on initialization, as well as the default voltage gear and the corresponding default gear switching strategy in the second gear management mode.

[0173] Furthermore, as shown in FIG7 , the host device also includes other components such as a display 704 and a power supply component 705. FIG7 only schematically shows some components, which does not mean that the host device only includes the components shown in FIG7 . In addition, the components in the dotted box in FIG7 are optional components, not mandatory components, and the specific components may depend on the product form of the host device. The host device of this embodiment can be implemented as a terminal device such as a desktop computer, a laptop computer, a smart phone or an IOT device, or a server-side device such as a conventional server, a cloud server or a server array. If the host device of this embodiment is implemented as Currently, terminal devices such as desktop computers, laptops, and smart phones may include the components in the dotted box in Figure 7; if the host device of this embodiment is implemented as a server device such as a conventional server, cloud server, or server array, it may not include the components in the dotted box in Figure 7.

[0174] In this embodiment, write-read interval description information for an application performing a write-first-then-read data operation on a PCM can be obtained. Based on this description information, the initial voltage level and level switching strategy required for reading data from the PCM's storage cells are determined. Data is then read from the PCM based on the initial voltage level and level switching strategy. Because the initial voltage level and level switching strategy take into account the write-read interval description information, which can reflect voltage drift, not only the initial voltage level but also the level switching strategy corresponding to the initial voltage level are determined. This allows data to be read from the PCM's storage cells based on the initial voltage level. If a read fails at the initial voltage level, a voltage level switch is performed based on the level switching strategy. This improves the probability of successfully reading data from the PCM's storage cells and overall data reading efficiency.

[0175] The above describes the internal functions and structure of a data reading device for a phase change memory (PCM). As shown in FIG8 , in practice, the data reading device for a phase change memory (PCM) can be implemented as a PCM, comprising: a storage unit 801 for storing data and a storage controller 802 for performing storage control on the storage unit; the storage controller 802 comprises: a processor 8021 and a memory 8022, wherein the memory stores a firmware program for the phase change memory; and the processor is configured to execute the firmware program to implement the steps of the data reading method for the phase change memory (PCM).

[0176] The memory 8022 is used to store computer programs and can be configured to store various other data to support operations on the computing platform. Examples of such data include instructions for any application or method operating on the computing platform, contact data, phone book data, messages, images, videos, etc.

[0177] The processor 8021 and the memory 8022 can be implemented by any type of volatile or non-volatile memory device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EPROM), or a combination thereof. (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), Magnetic Memory, Flash Memory, Magnetic or Optical Disk.

[0178] The processor 8021 is coupled to the memory 8022 and is used to execute a computer program in the memory 8022, so as to: receive write-read interval description information sent by a host when a target application performs a write-first-then-read operation on the PCM in a future time period, where the target application is an application on the host that uses the PCM to access data; configure an initial voltage level and a corresponding target level switching strategy required for reading data from a storage unit in the PCM according to the write-read interval description information; and upon receiving a read command from the target application, read data from the storage unit of the PCM based on the initial voltage level and the corresponding target level switching strategy.

[0179] Optionally, the PCM supports multiple write and read interval gears, and different write and read interval gears correspond to different gear commands; when the processor 8021 receives the write and read interval description information sent by the host, which is for a target application to perform a data write-first-then-read operation on the PCM in a future time period, it is specifically used to: receive a target gear command sent by the host, where the target gear command corresponds to a target write and read interval gear, and the target write and read interval gear is a write and read interval gear among the multiple write and read interval gears that is adapted to the write and read interval description information.

[0180] Optionally, one write-read interval gear corresponds to one voltage gear range, and the voltage gear range includes multiple voltage gears. Then, when the processor 8021 configures the initial voltage gear and the corresponding gear switching strategy required when reading data from the storage unit in the PCM according to the write-read interval description information, it is specifically used to: determine the initial voltage gear and the corresponding target gear switching strategy based on the multiple voltage gears in the target voltage gear range corresponding to the target write-read interval gear; and write the initial voltage gear and the corresponding target gear switching strategy into the voltage gear register to provide them to the read circuit responsible for reading data from the storage unit in the PCM.

[0181] Optionally, a default voltage gear is set in a voltage gear range, and the default voltage gear corresponds to a gear switching strategy; the processor 8021 selects a plurality of voltages in the target voltage gear range corresponding to the target write / read interval gear. Gear, when configuring the initial voltage gear and the corresponding gear switching strategy, is specifically used to: use the default voltage gear and its corresponding gear switching strategy in the target voltage gear range as the initial voltage gear and the target gear switching strategy respectively.

[0182] Optionally, a voltage gear range includes multiple first-level voltage gears, a first-level voltage gear includes multiple second-level voltage gears, and the second-level voltage gear is smaller than the first-level voltage gear to which it belongs; when the processor 8021 uses the default voltage gear in the target voltage gear range and its corresponding gear switching strategy as the initial voltage gear and the target gear switching strategy, respectively, it is specifically used to: use the default first-level voltage gear in the target voltage gear range and the default second-level voltage gear below the default first-level voltage gear as the initial voltage gear; use the gear switching strategy corresponding to the default first-level voltage gear and the gear switching strategy corresponding to the default second-level voltage gear as the target gear switching strategy.

[0183] Optionally, when the processor 8021 receives a read command from the target application, based on the initial voltage level and the corresponding target level switching strategy, when reading data from the storage unit of the PCM, it is specifically used to: when receiving the read command from the target application, control the read circuit to read data from the storage unit of the PCM based on the initial voltage level; and, when the number of read failures meets the switching condition, switch to a new initial voltage level from the target voltage level range according to the target level switching strategy, and control the read circuit to continue reading data from the storage unit of the PCM based on the new initial voltage level.

[0184] Optionally, the processor 8021 is further configured to: obtain number information written by the read circuit in a first number register, a second number register, and / or a third number register; and determine, based on the number information, whether the number of read failures satisfies a switching condition; wherein, the first number register records the number of read operations, the second number register records the number of successful rereads after N times, and the third number register records the number of successful rereads after M times; N and M are positive integers, and N is less than M.

[0185] Optionally, before receiving the write-read interval description information sent by the host, the processor 8021 is further configured to: receive a first mode command sent by the host, and set the voltage strategy selection register to a first gear management mode, where the first gear management mode refers to a mode for configuring an initial voltage gear and a target gear switching strategy based on the write-read interval description information.

[0186] Optionally, the processor 8021 is further configured to: receive a second mode command sent by the host, and set the voltage policy selection register to a second gear management mode, where the second gear management mode refers to a mode that does not rely on write-read interval description information to configure an initial voltage gear and a target gear switching strategy; or receive a mode recovery command sent by the host, and set the voltage policy selection register to the second gear management mode, and set the voltage policy selection register to a default voltage gear and a corresponding default gear switching strategy under the second gear management mode.

[0187] Furthermore, as shown in FIG8 , the PCM also includes other components, such as a power supply assembly 804. FIG8 only schematically illustrates some components and does not mean that the host only includes the components shown in FIG8 . Furthermore, the components within the dashed boxes in FIG8 are optional, not mandatory, components, and may depend on the product form factor of the working node. The working node of this embodiment can be implemented as a terminal device such as a desktop computer, laptop computer, smartphone, or IoT device, or as a server-side device such as a conventional server, cloud server, or server array. If the working node of this embodiment is implemented as a terminal device such as a desktop computer, laptop computer, or smartphone, it may include the components within the dashed boxes in FIG8 . If the working node of this embodiment is implemented as a server-side device such as a conventional server, cloud server, or server array, it may not include the components within the dashed boxes in FIG8 .

[0188] In this embodiment, write-read interval description information can be obtained when an application performs a write-first-then-read data operation on a PCM. Based on this description information, the initial voltage level and level switching strategy required for reading data from the PCM's storage cells are determined. Data is then read from the PCM based on the initial voltage level and level switching strategy. Because the initial voltage level and level switching strategy take into account the write-read interval description information, which can reflect voltage drift factors, not only the initial voltage level is determined, but also the level switching strategy corresponding to the initial voltage level is determined. This allows data to be read from the PCM's storage cells based on the initial voltage level. If reading fails at the initial voltage level, a reasonable voltage level switching strategy is implemented based on the level switching strategy. This helps increase the probability of successfully reading data from the PCM's storage cells and improves overall efficiency. The data reading efficiency of the body.

[0189] An embodiment of the present disclosure further provides a storage controller, applied to a phase change memory, for controlling storage in storage units of the phase change memory. The storage controller includes a processor and a memory, wherein the memory stores a firmware program for the phase change memory, and the processor is configured to execute the firmware program to implement the steps in the data reading method for the phase change memory (PCM).

[0190] Accordingly, an embodiment of the present disclosure further provides a computer-readable storage medium storing a computer program. When the computer program is executed, the steps that can be performed by the host and / or PCM in the above method embodiment can be implemented.

[0191] An embodiment of the present disclosure further provides a computer program product, including: a computer program / instruction, which, when executed by a processor, enables the processor to implement the steps of the data reading method and / or voltage control method of a phase change memory.

[0192] The above-mentioned memory can be implemented by any type of volatile or non-volatile memory device or a combination thereof, such as static random-access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0193] The communication component is configured to facilitate wired or wireless communication between the device containing the communication component and other devices. The device containing the communication component can access wireless networks based on communication standards, such as WiFi, 2G, 3G, and 4G / LTE. 5G and other mobile communication networks, or a combination thereof. In one exemplary embodiment, the communication component receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0194] The display includes a screen, which may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, it may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensors can not only detect the boundaries of a touch or slide action, but also the duration and pressure associated with the touch or slide action.

[0195] The power supply assembly provides power to various components of the device in which the power supply assembly is located. The power supply assembly may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which the power supply assembly is located.

[0196] The audio component can be configured to output and / or input audio signals. For example, the audio component includes a microphone (MIC). When the device containing the audio component is in an operating mode, such as call mode, recording mode, or voice recognition mode, the microphone is configured to receive external audio signals. The received audio signals can be further stored in a memory or transmitted via a communication component. In some embodiments, the audio component also includes a speaker for outputting audio signals.

[0197] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to magnetic disk storage, compact disc read-only memory (CD-ROM), optical storage, etc.) containing computer-usable program code.

[0198] The present disclosure is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each process flow and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, such that the instructions, when executed by the processor of the computer or other programmable data processing device, produce means for implementing the functions specified in one or more processes in the flowcharts and / or one or more blocks in the block diagrams.

[0199] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0200] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0201] In a typical configuration, a computing device includes one or more processors (Central Processing Unit, CPU), input / output interfaces, network interfaces, and memory.

[0202] Memory may include non-permanent storage in a computer-readable medium, in the form of random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0203] Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can be implemented using any method or technology to store information. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change random access memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmitting medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media, such as modulated data signals and carrier waves.

[0204] It should also be noted that the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, product, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, product, or apparatus. In the absence of further limitations, the phrase "comprising a..." does not preclude the presence of additional identical elements in the process, method, product, or apparatus comprising the elements.

[0205] The above are merely examples of the present disclosure and are not intended to limit the present disclosure. Persons skilled in the art will readily appreciate that various modifications and variations are possible with the present disclosure. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present disclosure are intended to be encompassed by the claims of the present disclosure.

Claims

24 Claims 1. A voltage control method for a phase change memory (PCM), applied to a host, comprising: In response to a preset trigger event, predict write-read interval description information of a target application when performing a write-first-then-read operation on a PCM in a future time period, where the target application is an application on the host that uses the PCM for data access; and send the write-read interval description information to a storage controller in the PCM, so that the storage controller configures an initial voltage level and a corresponding target level switching strategy required for reading data from a storage unit in the PCM according to the write-read interval description information.

2. The method according to claim 1, wherein: Responding to a preset trigger event, predicting write-read interval description information of a target application when performing a write-first-then-read operation on a PCM in a future time period, including: responding to the preset trigger event, predicting the write-read interval description information based on an application type, application scenario, and / or historical write-read operation information of the target application.

3. The method according to claim 2, wherein: Responding to a preset trigger event and predicting the write-read interval description information based on historical write and read operation information of the target application, including: in response to the preset trigger event, counting a first bandwidth ratio of historical write operations of the target application within a first preset time range in historical write and read operations; predicting the write-read interval description information based on the first bandwidth ratio; and / or in response to the preset trigger event, counting a second bandwidth ratio of historical read operations of the target application within the first preset time range in historical write and read operations; predicting the write-read interval description information based on the second bandwidth ratio; and / or in response to the preset trigger event, counting a time interval between a historical write operation and a first historical read operation of the target application for the same data within a second preset time range, and predicting the write-read interval description information based on the time interval.

4. The method according to claim 1, wherein: The preset trigger event includes: a resource scheduling event that allocates the PCM to the target application; and / or an event that the target application switches the working mode during the use of the PCM; and / or an event that the target application uses the PCM for a time greater than a set duration threshold.

5. The method according to any one of claims 1 to 4, wherein: The PCM supports multiple write-read interval gears, different write-read interval gears correspond to different gear commands, and one write-read interval gear corresponds to a voltage gear range; the write-read interval description information is sent to the storage controller in the PCM, so that the storage controller configures the initial voltage gear required to read data from the storage unit in the PCM and the corresponding target gear switching strategy according to the write-read interval description information, including: determining a target write-read interval gear that is compatible with the write-read interval description information from the multiple write-read interval gears; sending a target gear command corresponding to the target write-read interval gear to the storage controller, so that the storage controller configures the initial voltage gear and the corresponding target gear switching strategy according to the voltage gear range corresponding to the target write-read interval gear.

6. The method according to any one of claims 1 to 4, wherein: Before sending the write-read interval description information to the storage controller in the PCM, the method further includes: sending a first mode command to the storage controller to enable the storage controller to operate in a first gear management mode, where the first gear management mode refers to a mode for configuring an initial voltage gear and a target gear switching strategy based on the write-read interval description information.

7. The method according to claim 6, further comprising: issuing a second mode command to the storage controller to enable the storage controller to operate in a second gear management mode, wherein the second gear management mode is a mode in which the initial voltage gear and the target gear switching strategy are configured without relying on the write / read interval description information; or A mode recovery command is issued to the storage controller to enable the storage controller to restore the second gear management mode configured by the PCM power-on initialization, the default voltage gear in the second gear management mode, and the corresponding default gear switching strategy.

8. A method for reading data from a phase change memory (PCM), applied to a memory controller in the PCM, the method comprising: Receive write-read interval description information sent by a host, which is information for a target application that performs a write-first-then-read operation on a PCM in a future time period, where the target application is an application on the host that uses the PCM to access data; configure an initial voltage level and a corresponding target level switching strategy required for reading data from a storage unit in the PCM according to the write-read interval description information; and upon receiving a read command from the target application, read data from the storage unit of the PCM based on the initial voltage level and the corresponding target level switching strategy.

9. The method according to claim 8, wherein: The PCM supports multiple write and read interval gears, and different write and read interval gears correspond to different gear commands; Receiving write-read interval description information sent by a host when a target application performs a write-first-read-later-data operation on a PCM in a future time period, including: receiving a target gear command sent by the host, the target gear command corresponding to a target write-read interval gear, and the target write-read interval gear being a write-read interval gear among the multiple write-read interval gears that is adapted to the write-read interval description information.

10. The method according to claim 9, wherein: One write-read interval gear corresponds to a voltage gear range, and the voltage gear range includes multiple voltage gears. Then, based on the write-read interval description information, the initial voltage gear and the corresponding gear switching strategy required for reading data from the storage unit in the PCM are configured, including: determining the initial voltage gear and the corresponding target gear switching strategy based on the multiple voltage gears in the target voltage gear range corresponding to the target write-read interval gear; and writing the initial voltage gear and the corresponding target gear switching strategy into a voltage gear register to provide them to the read circuit responsible for reading data from the storage unit in the PCM.

11. The method according to claim 10, wherein: A default voltage level is set in a voltage level range, and the default voltage level corresponds to a level switching strategy; an initial voltage level and a corresponding level switching strategy are configured according to multiple voltage levels in a target voltage level range corresponding to the target write / read interval level, including: using the default voltage level in the target voltage level range and its corresponding level switching strategy as the initial voltage level and the target level switching strategy, respectively.

12. The method according to claim 11, wherein: A voltage gear range includes multiple first-level voltage gears, a first-level voltage gear includes multiple second-level voltage gears, and the second-level voltage gear is smaller than the first-level voltage gear to which it belongs; the default voltage gear in the target voltage gear range and its corresponding gear switching strategy are respectively used as the initial voltage gear and the target gear switching strategy, including: the default first-level voltage gear in the target voltage gear range and the default second-level voltage gear below the default first-level voltage gear are used as the initial voltage gear; the gear switching strategy corresponding to the default first-level voltage gear and the gear switching strategy corresponding to the default second-level voltage gear are used as the target gear switching strategy.

13. The method according to any one of claims 10 to 12, wherein: When receiving a read command from the target application, reading data from the storage unit of the PCM based on the initial voltage level and the corresponding target level switching strategy, comprising: when receiving a read command from the target application, controlling the read circuit to read data from the storage unit of the PCM based on the initial voltage level; and when the number of read failures meets a switching condition, switching data from the storage unit of the target application according to the target level switching strategy. A new initial voltage level is switched in the voltage level range, and the reading circuit is controlled to continue reading data from the storage unit of the PCM based on the new initial voltage level.

14. The method according to claim 13, further comprising: Acquire the number of times information written by the reading circuit into the first number register, the second number register and / or the third number register; According to the number information, determining whether the number of read failures meets the switching condition; The first number register records the number of read operations, the second number register records the number of successful reads after N rereads, and the third number register records the number of successful reads after M rereads; N and M are positive integers, and N is less than M.

15. A host, comprising: A memory and a processor; wherein the memory is used to store a computer program, and the processor is coupled to the memory and is used to execute the computer program to implement the steps in the method according to any one of claims 1 to 7.

16. A phase change memory, comprising: A storage unit for storing data and a storage controller for performing storage control on the storage unit; wherein the storage controller comprises: a processor and a memory, the memory storing a firmware program of the phase change memory, and the processor executing the firmware program to implement the steps of the method according to any one of claims 8 to 14.

17. A computer-readable storage medium storing a computer program, wherein: When the computer program is executed by a processor, the processor is caused to implement the steps of the method according to any one of claims 1 to 7 and claims 8 to 14.

18. A computer program product comprising: A computer program / instruction, wherein when the computer program / instruction is executed by a processor, the processor is caused to implement the steps of the method according to any one of claims 1 to 7 and claims 8 to 14.

Images