Memory device, memory system, memory controller, and operation method

Abstract

Embodiments of the present application provide a memory device, a memory system, a memory controller, and an operation method. The memory device comprises: storage units each having multiple storage bits, wherein a preset number of storage units form a codeword, and the multiple storage bits respectively correspond to multiple pages, at least some pages correspond to multiple levels, the multiple levels include a first level and a second level, and a read voltage of the second level is less than that of the first level; and a peripheral circuit of the memory device, configured to: acquire a predicted valley voltage of the first level on the basis of a corresponding first result under a target read voltage of the first level, wherein the first result comprises the number of flipped bits of at least one codeword in two read results; acquire a predicted valley voltage of the second level on the basis of the predicted valley voltage of the first level; and use the predicted valley voltage of the first level and the predicted valley voltage of the second level to perform a first read operation on the at least one codeword.

Description

Memory device, memory system, memory controller and operation method Technical Field

[0001] The present application relates to, but is not limited to, a memory device, a memory system, a memory controller, and an operating method. Background Art

[0002] With the advancement of technology, the integrated circuit industry has seen a growing market. Within this industry, the processes and technologies for non-volatile memory devices have seen rapid advancements in recent years, with NAND memory being particularly widely used. NAND memory achieves data storage by capturing and storing charge within the gate dielectric layer of its memory cells. However, over time, the charge stored in the memory cells changes with age, repeated read operations, and temperature fluctuations, affecting the accuracy of data read from the cells.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present application provides a memory device, which includes: a memory cell array, including memory cells with a plurality of storage bits, a preset number of memory cells forming a codeword, and multiple storage bits corresponding to multiple pages respectively; at least some pages corresponding to multiple stages, the multiple stages including a first stage and a second stage, and a read voltage of the second stage being less than a read voltage of the first stage; a peripheral circuit coupled to the memory cell array and configured to: obtain a predicted valley voltage of the first stage based on a first result corresponding to a target read voltage of the first stage; the first result includes the number of bits flipped in two read results of at least one codeword at the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; obtain a predicted valley voltage of the second stage based on the predicted valley voltage of the first stage; and perform a first read operation on at least one codeword using the predicted valley voltage of the first stage and the predicted valley voltage of the second stage.

[0005] In a second aspect, an embodiment of the present application provides a memory system, comprising: one or more memory devices as provided in the first aspect; and a memory controller coupled to and controlling the memory devices.

[0006] In a third aspect, an embodiment of the present application provides a memory controller coupled to at least one memory device, the memory device including a storage unit having multiple storage bits, a preset number of storage units forming a codeword; multiple storage bits correspond to multiple pages respectively; at least some pages correspond to multiple stages, the multiple stages include a first stage and a second stage, and the read voltage of the second stage is less than the read voltage of the first stage; the memory controller includes: a control unit, configured to: obtain a predicted valley voltage of the first stage according to a first result corresponding to a target read voltage of the first stage; the first result includes the number of bits flipped in two read results of at least one codeword under the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; obtain the predicted valley voltage of the second stage according to the predicted valley voltage of the first stage; and use the predicted valley voltage of the first stage and the predicted valley voltage of the second stage to control the memory device to perform a first read operation, and perform a first error correction decoding on the first read result of the first read operation.

[0007] In a fourth aspect, an embodiment of the present application provides an operating method for a memory device, the operating method comprising: obtaining a predicted valley voltage of the first stage according to a first result corresponding to a target read voltage of the first stage; the first result includes the number of bits flipped in two read results of at least one codeword at the first read voltage and the second voltage; a preset number of storage cells in the memory device form a codeword; the difference between the first read voltage and the second read voltage is less than a preset voltage; the number of storage bits of the storage cell is multiple bits, and the multiple storage bits correspond to multiple pages respectively; at least part of the pages correspond to multiple stages, the multiple stages include a first stage and a second stage, and the read voltage of the second stage is less than the read voltage of the first stage; obtaining a predicted valley voltage of the second stage according to the predicted valley voltage of the first stage; and performing a first read operation on at least one codeword using the predicted valley voltage of the first stage and the predicted valley voltage of the second stage.

[0008] In a fifth aspect, an embodiment of the present application provides an operating method for a memory system, the operating method comprising: a memory controller in the memory system sends a first instruction, the first instruction instructing to obtain information representing a target valley voltage of multiple levels; a memory device in the memory system receives the first instruction, obtains information representing a predicted valley voltage of multiple levels according to the operating method of the memory device provided in the fourth aspect, and sends the information representing the predicted valley voltage of multiple levels to the memory controller; the memory controller uses the information representing the predicted valley voltage of multiple levels to control the memory device to perform a first read operation, and performs a first error correction decoding operation on a first read result of the first read operation.

[0009] In a sixth aspect, an embodiment of the present application provides an operating method for a memory controller, the operating method comprising: obtaining a predicted valley voltage of the first stage according to a first result corresponding to a target read voltage of the first stage; the first result comprises the number of bits flipped in two read results at the first read voltage and the second read voltage of at least one codeword; a preset number of storage cells in at least one memory device coupled to the memory controller form a codeword; the difference between the first read voltage and the second read voltage is less than a preset voltage; the number of storage bits of the storage cell is multiple bits, and the multiple storage bits correspond to multiple pages respectively; at least part of the pages correspond to multiple stages, and the multiple stages include a first stage and a second stage, and the read voltage of the second stage is less than the read voltage of the first stage; obtaining a predicted valley voltage of the second stage according to the predicted valley voltage of the first stage; and controlling the memory device to perform a first read operation using the predicted valley voltage of the first stage and the predicted valley voltage of the second stage, and performing a first error correction decoding on the first read result of the first read operation.

[0010] In the seventh aspect, an embodiment of the present application provides a storage medium having executable instructions stored thereon, which, when executed by a processor, implement the steps of any one of the operating methods provided in the fourth aspect, the fifth aspect, and the sixth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0012] FIG1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present application;

[0013] FIG2A is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present application;

[0014] FIG2B is a schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present application;

[0015] FIG3 is a schematic diagram of an exemplary memory including peripheral circuits according to an embodiment of the present application;

[0016] FIG4 is a cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present application;

[0017] FIG5 is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuits according to an embodiment of the present application;

[0018] FIG6 is a schematic diagram of an exemplary read operation flow of a memory system provided by the present application;

[0019] FIG7 is a schematic diagram illustrating a flowchart of an implementation of an operation method performed by a peripheral circuit of a memory device according to an embodiment of the present application;

[0020] FIG8A is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including two memory bits provided in one embodiment of the present application;

[0021] FIG8B is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including three memory bits provided in one embodiment of the present application;

[0022] FIG8C is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including four memory bits provided in one embodiment of the present application;

[0023] FIG9A is a schematic diagram of a method for confirming predicted valley voltage / target valley voltage of the first and second stages corresponding to the lower page shown in FIG8B , provided by an embodiment of the present application;

[0024] 9B is a schematic diagram of a method for confirming predicted valley voltages / target valley voltages of the first and second stages corresponding to the middle page shown in FIG8B , provided by an embodiment of the present application;

[0025] FIG9C is a schematic diagram of a method for confirming the predicted valley voltage / target valley voltage of the first and second stages corresponding to the upper page shown in FIG8B , provided by an embodiment of the present application;

[0026] FIG9D is an enlarged schematic diagram of the rectangular dotted line area in FIG9A ;

[0027] FIG9E is an enlarged schematic diagram of the rectangular dotted line area in FIG9B ;

[0028] FIG9F is an enlarged schematic diagram of the rectangular dotted line area in FIG9C ;

[0029] FIG10A is a schematic diagram of the distribution of near-valley points and near-valley thresholds provided in one embodiment of the present application;

[0030] FIG10B is a schematic diagram of statistics showing an upward trend when a second adjustment is made to the left, provided by an embodiment of the present application;

[0031] FIG10C is a schematic diagram of statistics showing an upward trend when a second adjustment is made to the right, provided by an embodiment of the present application;

[0032] FIG10D is a schematic diagram of a method for confirming the seventh-level read voltage corresponding to the upper page shown in FIG9C according to an embodiment of the present application;

[0033] FIG11 is a schematic diagram of an exemplary structure of a memory system provided in one embodiment of the present application;

[0034] FIG12 is a block diagram of a memory system provided by an embodiment of the present application;

[0035] FIG13 is a flowchart of an operating method that a memory system is configured to perform according to an embodiment of the present application;

[0036] FIG14 is a flowchart of a method for operating a memory device according to an embodiment of the present application;

[0037] FIG15 is a second flowchart of a method for operating a memory device according to an embodiment of the present application;

[0038] FIG16 is a timing diagram of an exemplary start-up single-level read mode operation provided by the present application;

[0039] FIG17 is a timing diagram of predicting valley voltage / target valley voltage and executing a read operation according to an embodiment of the present application;

[0040] FIG18 is a schematic diagram of the composition structure of a storage medium provided in an embodiment of the present application;

[0041] FIG19A is a block-level iteration count of all pages in a memory cell array of a first exemplary memory system / memory device provided by an embodiment of the present application, using the memory system / memory device provided by an embodiment of the present application;

[0042] 19B is a block-level iteration count of all pages in a memory cell array of a second exemplary memory system / memory device provided by an embodiment of the present application, using the memory system / memory device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0043] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0044] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0045] In addition, the accompanying drawings are merely schematic illustrations of the present application and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the blocks shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0046] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all steps. For example, some steps may be decomposed, while some steps may be combined or partially combined, so the actual execution order may change according to actual circumstances.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] The memory device in the embodiments of the present application includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is used as an example for description.

[0049] FIG1 shows a block diagram of an exemplary system 100 with a memory device according to some aspects of the present application. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG1 , system 100 can include a host 108 and a memory system 102, and memory system 102 has one or more memory devices 104 and a memory controller 2. Host 108 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host 108 can be configured to send data to or receive data from memory device 104.

[0050] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0051] In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment Solid State Disk (SSD) or embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0052] The memory controller 106 may be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 may also be configured to process error correction codes for data read from or written to the memory device 104.

[0053] The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0054] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). In other words, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0055] 2A , the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 may also include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG. 1 ).

[0056] 2B , the memory controller 106 and the plurality of memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 in FIG. 1 ). In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0057] In some embodiments, each memory block may be coupled to a plurality of word lines, and a plurality of memory cells coupled to each word line constitute a physical page.

[0058] FIG3 illustrates a schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry according to some aspects of the present disclosure. Memory device 300 may be an example of memory device 104 in FIG1 . Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to memory cell array 301. For illustration, memory cell array 301 is described as a three-dimensional NAND-type memory cell array, wherein memory cells 306 are NAND-type memory cells provided in an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating-gate memory cell including a floating-gate transistor, or a charge-trapping memory cell including a charge-trapping transistor.

[0059] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible storage states and can therefore store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) that can store more than one bit of data in more than four storage states. For example, an MLC can store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell (TLC)), four bits per cell (also referred to as a quad-level cell (QLC)), five bits per cell (also referred to as a penta-level cell (PLC)), or more than five bits per cell. Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0060] It should be noted that the storage state mentioned here is the storage state of the storage unit mentioned in this application. Different storage cells have different numbers of storage states. For example, an SLC type storage cell has 2 storage states (that is, two memory states), wherein these 2 storage states include: a programming state and an erased state. For another example, an MLC type storage cell has 4 storage states, wherein these 4 storage states include: an erased state and three programming states. For another example, a TLC type storage cell has 8 storage states, wherein these 8 storage states include: one erased state and seven programming states. In some embodiments, a QLC type storage cell has 16 storage states, wherein these 16 storage states include: one erased state and fifteen programming states.

[0061] As shown in FIG3 , each memory string 308 may include a lower select transistor (BSG) 310 (also known as a source-side select transistor) at its source terminal and an upper select transistor (TSG) 312 (also known as a drain-side select transistor) at its drain terminal. The BSG 310 and the TSG 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0V) to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0V) to a corresponding BSG 310 via one or more BSG lines 315.

[0062] As shown in FIG3 , a memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and to unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0063] 3 , each memory cell 306 in the plurality of memory cells is coupled to a corresponding word line 318 , and each memory string 308 is coupled to a corresponding bit line 316 via a corresponding select transistor (eg, top select transistor (TSG) 312 ).

[0064] FIG4 illustrates a cross-sectional schematic diagram of an exemplary memory cell array 301 including a NAND memory string 308 according to some aspects of the present disclosure. As shown in FIG4 , the NAND memory cell array 301 may include a stacked structure 410 comprising a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a channel structure vertically extending through the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure is coupled to the plurality of gate layers in the stacked structure 410 to form the memory string 308. The gate layers 411 and the insulating layers 412 may be alternately stacked, with two adjacent gate layers 411 separated by an insulating layer 412.

[0065] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0066] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0067] In some embodiments, memory string 308 includes a channel structure extending vertically through stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel includes silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0068] Referring back to FIG3 , the peripheral circuit 302 can be coupled to the memory cell array 301 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 can include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG5 shows some exemplary peripheral circuits, including a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuits not shown in FIG. 5 may also be included.

[0069] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store program data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more memory strings 308 by applying a bit line voltage obtained from the voltage generator 510.

[0070] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and select / deselect memory blocks 304 of the memory cell array 301 and select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages obtained from a voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by control logic 512 and obtain word line voltages (e.g., read voltage, program voltage, pass voltage, channel boosting voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0071] The control logic 512 can be coupled to each of the other parts in the peripheral circuit described above and is configured to control the operation of each of the other parts in the peripheral circuit. The register 514 can be coupled to the control logic 512 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0072] The basic principle of 3D NAND memory is that data is written by injecting a certain amount of charge into a memory cell, via carriers (electrons or holes) across a charge barrier. The stored data can then be read based on the threshold voltage at which the memory cell turns on. Therefore, to ensure accurate data is read, a robust and efficient error correction algorithm is typically employed during data reading.

[0073] However, as the charge stored in a memory cell changes over time due to age, repeated read operations, and temperature fluctuations, this can affect the accuracy of data reads. When the threshold voltage shifts significantly upward or downward, the likelihood of read errors is high when reading the data from the memory cell using the original read voltage. Furthermore, when the read error rate exceeds the error correction capability, data read failures can occur.

[0074] FIG6 is a schematic diagram illustrating an exemplary read operation flow for a memory system. As shown in FIG6 , when a memory controller controls a memory device to perform a read operation, it first performs a default read operation (FW default read) on the memory cell at the corresponding physical address. If the default read operation fails, a reread operation (Read retry) is performed. If the reread operation fails, a soft decode operation is performed. If the soft decode operation fails, a Redundant Array of Independent Disks (RAID) operation is performed. If the RAID operation fails, the read operation ceases and the read fails due to uncorrectable errors. The memory controller then sends a Read Fail signal to the host 108. The reread operation and the default read operation can be applied to hard decode.

[0075] In some embodiments, a reread operation can typically be performed by querying a retry table provided by the manufacturer. The reread operation is essentially an error correction mechanism. The reread table provides a reference voltage for reading data. By querying the reread table, each storage cell is read again at a read voltage that deviates from the normal threshold voltage and corrects the error in conjunction with an error correction algorithm in an attempt to correctly read the data. If the read error data is corrected, the reread table query stops. If the read error data cannot be corrected, the reread table query continues until the entire reread table is traversed.

[0076] The aforementioned reread operation method requires querying the reread table line by line, which inevitably increases the number of trial and error cycles and is time-consuming. Furthermore, the reread table provided by the manufacturer is only a reference value for specific environments. Real-world usage scenarios vary greatly, so the manufacturer's reread table does not cover many scenarios. Consequently, even after traversing the reread table, data may not be corrected, resulting in a significant waste of command processing time. In short, rereading by repeatedly polling the reread table is time-consuming, affecting the response time of subsequent commands and, consequently, device performance.

[0077] Based on one or more of the above-mentioned problems, in a first aspect, embodiments of the present application provide a memory device. As shown in FIG7 , the memory device includes: a memory cell array including memory cells having a plurality of storage bits, wherein a predetermined number of memory cells form a codeword, and the plurality of storage bits correspond to a plurality of pages; at least some of the pages correspond to a plurality of stages, wherein the plurality of stages include a first stage and a second stage, wherein a read voltage of the second stage is less than a read voltage of the first stage; and a peripheral circuit coupled to the memory cell array and configured to perform the following steps:

[0078] Step S10: Obtaining a predicted valley voltage for the first stage based on a first result corresponding to a target read voltage for the first stage; the first result includes the number of bits flipped in at least one codeword read at the first read voltage and at the second read voltage; and the difference between the first read voltage and the second read voltage is less than a preset voltage.

[0079] Step S20: obtaining a second-order predicted valley voltage according to the first-order predicted valley voltage;

[0080] Step S30 : performing a first read operation on at least one codeword using the predicted valley voltage of the first order and the predicted valley voltage of the second order.

[0081] Here, the structure of the memory device is referred to above FIG3 and will not be described in detail here.

[0082] In some embodiments, a memory device includes a memory cell array, the memory cell array includes a plurality of memory cells, and a preset number of memory cells form a code word (CW).

[0083] In some embodiments, the number of storage cells included in a codeword is the same as the number of storage cells included in one encoding or decoding when performing error correction encoding or decoding. In some specific embodiments, the number of storage cells included in a codeword may be less than or equal to the number of storage cells coupled to a physical page, such as the number of storage cells included in a codeword is 1 / 4 of the number of storage cells coupled to a physical page. In some specific embodiments, a codeword may include a number ranging from 2 4 to 2 12 For example, a code word may include 2 4 , 2 8 or 2 12 storage units.

[0084] In general, different memory systems may choose codewords of different sizes to meet their performance, reliability, and storage requirements.

[0085] Memory cells in different types of memory devices (eg, MLC, TLC, or QLC) can store different numbers of bits.

[0086] It should be noted that in practice, codewords will have some additional reserved space for management and error correction, so the number of storage units actually required may slightly exceed the above calculation result.

[0087] It is understandable that a codeword may include multiple storage units, and the number of storage units included in a codeword may be adjusted according to actual conditions.

[0088] In some embodiments, during the reading of the memory device, a read operation reads out the data of a physical page. When the number of storage cells contained in a codeword may be less than the number of storage cells coupled to a physical page, the codeword is a unit that can be executed to obtain the first result, but multiple codewords are not actually excluded. In other words, the first result corresponding to at least one codeword under the current read voltage can be obtained here. For example, a physical page may include 4 codewords, and the page buffer hardware operation can count the fail bit count (FBC) of each of the 4 codewords at one time, and then add the FBC of the four codewords to obtain the FBC of a physical page, and the subsequent calculation uses the added value. It can be understood that the first result here can be based on the data of a physical page, and a physical page can include multiple codewords.

[0089] In some embodiments, the memory cell array includes memory cells with a storage bit number of P bits, the P storage bits correspond to P pages respectively, and the P-bit memory cells read their P-bit storage data through a Q-level read voltage; P and Q are both integers greater than 1, and Q=2 P -1.

[0090] For example, when the number of storage bits of a memory cell includes two bits, the corresponding storage states include states 0 to 4. Referring to FIG8A , the four states are state 0 (also called the erased state) E, state 1 (also called the first storage state) P1, state 2 (also called the second storage state) P2, and state 3 (also called the third storage state) P3. The binary data corresponding to these four states are 11, 10, 00, and 01, respectively. Accordingly, the memory device includes two pages, namely, a lower page (LP) and an upper page (UP).

[0091] Taking the memory cell shown in FIG8A as an example, the two-bit memory cell reads its two-bit four-state storage data through three levels of read voltage (the first level read voltage L1, the second level read voltage L2 and the third level read voltage L3 shown in FIG8A).

[0092] For example, one page corresponds to multiple read voltages, and the other page corresponds to a single read voltage. As shown in FIG8A , the binary data corresponding to the lower page is 1001, and reading the lower page requires the corresponding first read voltage L1 and third read voltage L3. The binary data corresponding to the upper page is 1100, and reading the upper page requires the corresponding second read voltage L2.

[0093] For example, when the number of storage bits of a memory cell includes three bits, the corresponding storage states include states 0 to 7. Referring to FIG8B , the eight states are state 0 (also called the erased state) E, state 1 (also called the first storage state) P1, state 2 (also called the second storage state) P2, ... state 7 (also called the seventh storage state) P7. The binary data corresponding to the eight states are 111, 110, 100, 000, 010, 011, 001, and 101, respectively. Accordingly, the memory device includes three pages: a lower page, a middle page (MP), and an upper page.

[0094] Taking the memory cell shown in FIG8B as an example, the three-bit memory cell reads its three-bit eight-state storage data through seven levels of read voltages (the first-level read voltage L1, the second-level read voltage L2, the third-level read voltage L3, the fourth-level read voltage L4, the fifth-level read voltage L5, the sixth-level read voltage L6, and the seventh-level read voltage L7 shown in FIG8B ).

[0095] For example, each page corresponds to multiple read voltage levels. As shown in FIG8B , the binary data corresponding to the lower page are 10000111, and reading the lower page requires corresponding to the first read voltage L1 and the fifth read voltage L5. The binary data corresponding to the middle page are 11001100, and reading the middle page requires corresponding to the second read voltage L2, the fourth read voltage L4, and the sixth read voltage L6. The binary data corresponding to the upper page are 11100001, and reading the upper page requires corresponding to the third read voltage L3 and the seventh read voltage L7.

[0096] Exemplarily, when the number of storage bits of a memory cell includes four bits, the corresponding storage states include the 0th state to the 15th state. Referring to FIG8C , the 16 states are the 0th state (also called the erased state) E, the 1st state (also called the 1st storage state) P1, the 2nd state (also called the 2nd storage state) P2…the 15th state (also called the 15th storage state) P15, and the binary data corresponding to the 16 states are 1111, 0111, 0110….1110. Accordingly, the memory device includes four pages, namely, a lower page, a middle page, an upper page, and an extra page (XP). Here, the four storage bits corresponding to the 16 states are stored in the lower page, the middle page, the upper page, and the extra page, respectively.

[0097] Taking the memory cell shown in Figure 8C as an example, the four-bit memory cell reads its four-bit sixteen-state storage data through 15 levels of read voltages (the first level read voltage L1, the second level read voltage L2, the third level read voltage L3, the fourth level read voltage L4, the fifth level read voltage L5, the sixth level read voltage L6, the seventh level read voltage L7, the eighth level read voltage L8, the ninth level read voltage L9, the tenth level read voltage L10, the eleventh level read voltage L11, the twelfth level read voltage L12, the thirteenth level read voltage L13, the fourteenth level read voltage L14, and the fifteenth level read voltage L15 shown in Figure 8C).

[0098] Exemplarily, each page corresponds to multiple read voltage levels. As shown in FIG8C , the binary data corresponding to the lower page are 1100000011111100. Reading the lower page requires corresponding read voltages L2, L8, and L14. The binary data corresponding to the middle page are 1110000110000111. Reading the middle page requires corresponding read voltages L3, L7, L9, and L13. The binary data corresponding to the upper page are 1111100000110001. Reading the upper page requires corresponding read voltages L5, L10, L12, and L15. The binary data corresponding to the extra pages are 1000110000011111. Reading the extra pages requires corresponding first-level read voltage L1, fourth-level read voltage L4, sixth-level read voltage L6 and eleventh-level read voltage L11.

[0099] The lower page is usually closest to the source / drain, so each level of the read voltage corresponding to the lower page is determined first, with the fastest access speed and shortest response time, which can ensure balanced performance and durability during data access.

[0100] It should be noted that the method of preferentially determining each level of read voltage corresponding to the next page is only an example and is not used to limit the order of determining each level of read voltage in the multi-level read voltage corresponding to at least part of the pages in the embodiment of the present application.

[0101] In some embodiments, at least some pages correspond to multi-level read voltages, the multi-level read voltages including a first-level read voltage and a second-level read voltage, wherein the second-level read voltage is lower than the first-level read voltage. For example, the first-level read voltage can be understood as the highest read voltage among the multi-level read voltages for each page, and the second-level read voltage can be understood as other read voltages lower than the highest read voltage among the multi-level read voltages for each page.

[0102] It should be noted that the first and second levels are used to distinguish between a high-level read voltage and a low-level read voltage among the multiple-level read voltages corresponding to at least a portion of the page, with the low-level read voltage being lower than the high-level read voltage. For a memory cell containing multiple storage bits, a page corresponding to one storage bit may include one or more levels, and one level may include one or more levels.

[0103] For example, referring to FIG8A , a memory device includes a lower page and an upper page, wherein the lower page corresponds to multiple levels, the multiple levels of the lower page include a first level and a third level, and the first level read voltage L1 is less than the third level read voltage L3. Here, the third level read voltage L3 corresponds to the read voltage of the first level of the lower page (the upper level read voltage of the lower page), and the first level read voltage L1 corresponds to the read voltage of the second level of the lower page (the lower level read voltage of the lower page).

[0104] For example, referring to FIG8B , a memory device includes a lower page, a middle page, and an upper page, wherein each page corresponds to multiple levels. The multiple levels of the lower page include a first level and a fifth level, where a first level read voltage L1 is less than a fifth level read voltage L5. The multiple levels of the middle page include a second level, a fourth level, and a sixth level, where a second level read voltage L2 and a fourth level read voltage L4 are both less than a sixth level read voltage L6. The multiple levels of the upper page include a third level and a seventh level, where a third level read voltage L3 is less than a seventh level read voltage L7. Here, the fifth level read voltage L5, the sixth level read voltage L6, and the seventh level read voltage L7 correspond to the first level read voltages of the lower, middle, and upper pages, respectively, and the first level read voltage L1, the second level read voltage L2, the fourth level read voltage L4, and the third level read voltage L3 correspond to the second level read voltages of the lower, middle, and upper pages, respectively.

[0105] Exemplarily, referring to Figure 8C, the memory device includes a lower page, a middle page, an upper page and an additional page, wherein each page corresponds to multiple levels, the multiple levels of the lower page include the second level, the eighth level and the fourteenth level, the second level read voltage L2 and the eighth level read voltage L8 are both less than the fourteenth level read voltage L14, the multiple levels of the middle page include the third level, the seventh level, the ninth level and the thirteenth level, the third level read voltage L3, the seventh level read voltage L7 and the ninth level read voltage L9 are all less than the thirteenth level read voltage L13, the multiple levels of the upper page include the fifth level, the tenth level, the twelfth level and the fifteenth level, the fifth level read voltage L5, the tenth level read voltage L10 and the twelfth level read voltage L12 are less than the fifteenth level read voltage L15, the multiple levels of the additional page include the first level, the fourth level, the sixth level and the eleventh level, the first level read voltage L1, the fourth level read voltage L4 and the sixth level read voltage L6 are less than the eleventh level read voltage L11. Here, the fourteenth-level read voltage L14, the thirteenth-level read voltage L13, the fifteenth-level read voltage L15 and the eleventh-level read voltage L11 correspond to the first-level read voltages of the lower page, middle page, upper page and extra page respectively, the second-level read voltage L2 and the eighth-level read voltage L8 correspond to the second-level read voltage of the lower page, the third-level read voltage L3, the seventh-level read voltage L7 and the ninth-level read voltage L9 correspond to the second-level read voltage of the middle page, the fifth-level read voltage L5, the tenth-level read voltage L10 and the twelfth-level read voltage L12 correspond to the second-level read voltage of the upper page, the first-level read voltage L1, the fourth-level read voltage L4 and the sixth-level read voltage L6 correspond to the second-level read voltage of the extra page.

[0106] It should be noted that the difference between the first read voltage and the second read voltage can be less than a preset voltage. In some specific embodiments, the second read voltage is greater than the first read voltage, and the difference between the first read voltage and the second read voltage is set to a range of 5mV to 20mV, and can be 5mV, 10mV, 15mV, or 20mV, for example. In other specific embodiments, the second read voltage is less than the first read voltage, and the difference between the first read voltage and the second read voltage is set to a range of -5mV to -20mV, and can be -5mV, -10mV, -15mV, or -20mV, for example.

[0107] It should be noted that the first read voltage and the second read voltage are contextually related, that is, the second read voltage is obtained after the third adjustment is performed on the first read voltage. Based on this, the voltage difference between the first read voltage and the second read voltage is the step size of the third adjustment. The fact that the difference between the first read voltage and the second read voltage is less than the preset voltage can be understood as the first read voltage and the second read voltage having a smaller voltage difference. The preset voltage is related to the step size of the third adjustment and can be a voltage slightly larger than the step size of the third adjustment. In some specific embodiments, the preset voltage is set in a range of 6mV to 21mV. Exemplarily, the preset voltage can be 6mV, 11mV, 16mV, or 21mV. In other specific embodiments, the preset voltage is set in a range of -6mV to -21mV. Exemplarily, the preset voltage can be -6mV, -11mV, -16mV, or -21mV.

[0108] It should be noted that the first read voltage and the second read voltage are both general terms. The target read voltage and the read voltage after the first and second adjustments to the target read voltage may all be referred to as the first read voltage, and the read voltage obtained after the third adjustment to the first read voltage may all be referred to as the second read voltage. In other words, the first read voltage is a general term and can be understood as the target read voltage or the target adjusted read voltage (the voltage obtained after the first or second adjustment to the target read voltage with a target step size; wherein the target step size can be set to a range of 20mV to 40mV, and illustratively, the step size of the second adjustment can be 20mV, 30mV, or 40mV; the target step size can also be set to a range of 50mV to 150mV, and illustratively, the step size of the first adjustment can be 50mV, 60mV, 70mV, 80mV, 100mV, 120mV, or 150mV).

[0109] In each embodiment of the present application, the first result corresponding to a specific voltage can be understood as: the specific voltage is subjected to a third adjustment, that is, the specific voltage and the specific voltage after the third adjustment have a first voltage difference △V1, and the number of bits flipped in the two reading results of a preset number of storage cells at the specific voltage and the specific voltage after the third adjustment can be used as the first result corresponding to the specific voltage, wherein the preset number of storage cells can form at least one codeword.

[0110] For example, the first result corresponding to the first read voltage can be understood as follows: the first read voltage is adjusted by the third adjustment, i.e., the first read voltage and the second read voltage have a first voltage difference ΔV1, and the number of bits flipped in the two read results of the preset number of memory cells at the first read voltage and the second read voltage can be used as the first result corresponding to the first read voltage. The first read voltage can be the target read voltage of the first stage (V0 shown in FIG9D ), and the second read voltage can be the read voltage after the first read voltage is adjusted by the third adjustment (V1 shown in FIG9D ). Alternatively, the first read voltage can be the target adjusted read voltage of the first stage (V2 shown in FIG9D ), and the second read voltage can be the read voltage after the target adjusted read voltage is adjusted by the third adjustment (V3 shown in FIG9D ).

[0111] In various embodiments of the present application, the target valley voltage can be obtained as follows: based on whether a first result corresponding to a specific voltage satisfies a preset condition, a specific voltage is determined to be the target valley voltage. For example, based on whether the first result corresponding to the read voltage of the first stage is less than or equal to a second preset value, the read voltage of the first stage is determined to be the target valley voltage of the first stage; wherein the second preset value is set in the range of 5 to 30, and more specifically, the second preset value can be 5, 10, 15, 20, 25, or 30.

[0112] In each embodiment of the present application, the acquisition of the predicted valley voltage can be understood as follows: the predicted valley voltage is acquired according to a specific voltage and a first mapping function. For example, the predicted valley voltage of the second order is obtained according to the predicted valley voltage of the first order / the target valley voltage of the first order and the first mapping function, and the first mapping function is used to characterize the relationship between the predicted valley voltage of the first order / the target valley voltage of the first order and the predicted valley voltage of the second order. The acquisition of the predicted valley voltage can also be understood as follows: the predicted valley voltage is acquired according to the first result corresponding to a specific voltage, the order of a specific voltage, and the second mapping function. For example, the predicted valley voltage of the first order is acquired according to the first result corresponding to the target read voltage of the first order, the order of the first order, and the second mapping function; wherein the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage, the order of each order, and the predicted valley voltage.

[0113] In various embodiments of the present application, obtaining an adjusted voltage (e.g., an adjusted read voltage / an adjusted target read voltage) can be understood as follows: a voltage obtained by adjusting a specific voltage according to a target step size. For example, a first adjustment is performed on the target read voltage multiple times with a first step size, and the target read voltages after the first adjustment are obtained multiple times, or a second adjustment is performed on the target read voltage multiple times with a second step size, and the target read voltages after the second adjustment are obtained multiple times; wherein the first step size value range is set to 50mV to 150mV, and the first step size value can be 50mV, 60mV, 70mV, 80mV, 100mV, 120mV, or 150mV, and the second step size value range is set to 20mV to 40mV, and the second step size value can be 20mV, 30mV, or 40mV.

[0114] In some embodiments, before obtaining a first result corresponding to at least one codeword at a first-level target read voltage, the read mode of the memory device is set to a single-level read mode (SLR); the single-level read mode includes reading at least one bit of data stored in a memory cell using a first-level read voltage. In some specific embodiments, the memory device is configured to enter the single-level read mode in response to a mode setting command, and to obtain a first result corresponding to at least one codeword at the first-level target read voltage in the single-level read mode.

[0115] In some embodiments, the peripheral circuit is configured to: obtain a predicted valley voltage of the first stage based on a first result corresponding to a target read voltage of the first stage; obtain a predicted valley voltage of the second stage based on the predicted valley voltage of the first stage; and perform a first read operation on at least one codeword using the predicted valley voltage of the first stage and the predicted valley voltage of the second stage.

[0116] It should be noted that the predicted valley voltage can be used directly as a target valley voltage to perform a read operation on the data to be read, or can be obtained after further processing. The specific method of obtaining the predicted valley voltage will be further described below.

[0117] Here and below, a memory cell array including a memory cell with a storage bit number of 3 bits is used as an example for detailed description, but this is not intended to limit the various embodiments of the present application. Specifically, as shown in Figures 9A, 9B, 9C, 9D, 9E, and 9F, the storage bit number of the memory cell of at least one codeword is 3 bits, corresponding to the lower page, the middle page, and the upper page, respectively; wherein each page corresponds to multiple levels, the multiple levels of the lower page include the first level and the fifth level, the first level read voltage L1 is less than the fifth level read voltage L5, the multiple levels of the middle page include the second level, the fourth level, and the sixth level, the second level read voltage L2 and the fourth level read voltage L4 are both less than the sixth level read voltage L6, and the multiple levels of the upper page include the third level and the seventh level, the third level read voltage L3 is less than the seventh level read voltage L7. Here, the fifth-level read voltage L5, the sixth-level read voltage L6 and the seventh-level read voltage L7 correspond to the first-level read voltages of the lower page, the middle page and the upper page respectively, the first-level read voltage L1 corresponds to the second-level read voltage of the lower page, the second-level read voltage L2 and the fourth-level read voltage L4 correspond to the second-level read voltage of the middle page, and the third-level read voltage L3 corresponds to the second-level read voltage of the upper page.

[0118] Exemplarily, as shown in Figures 9A and 9D, the peripheral circuit is configured to: obtain the predicted valley voltage of the fifth level (V2 shown in Figures 9A and 9D) based on the first result Y1 corresponding to the target read voltage of the fifth level (V0 shown in Figures 9A and 9D); obtain the predicted valley voltage of the first level (V4 shown in Figure 9A) based on the predicted valley voltage of the fifth level; and perform a first read operation on the lower page of at least one codeword using the predicted valley voltage of the fifth level and the predicted valley voltage of the first level.

[0119] As shown in Figures 9B and 9E, the peripheral circuit is configured to: obtain the predicted valley voltage of the sixth level (V2 shown in Figures 9B and 9E) based on the first result Y1 corresponding to the target read voltage of the sixth level (V0 shown in Figures 9B and 9E); obtain the predicted valley voltage of the fourth level (V4 shown in Figure 9B) and the predicted valley voltage of the second level (V5 shown in Figure 9B) based on the predicted valley voltage of the sixth level; and perform a first read operation on the middle page of at least one codeword using the predicted valley voltage of the sixth level, the predicted valley voltage of the second level, and the predicted valley voltage of the fourth level.

[0120] As shown in Figures 9C and 9F, the peripheral circuit is configured to: obtain the predicted valley voltage of the seventh level (V2 shown in Figures 9C and 9F) based on the first result Y1 corresponding to the target read voltage of the seventh level (V0 shown in Figures 9C and 9F); obtain the predicted valley voltage of the third level (V4 shown in Figure 9C) based on the predicted valley voltage of the seventh level; and perform a first read operation on the upper page of at least one codeword using the predicted valley voltage of the seventh level and the predicted valley voltage of the third level.

[0121] In other embodiments, the peripheral circuit is further configured to obtain the predicted valley voltage of the sixth level of the middle page (V2 shown in Figures 9B and 9E) and / or the predicted valley voltage of the fifth level of the upper page (V2 shown in Figures 9A and 9D) based on the predicted valley voltage of the seventh level (V2 shown in Figures 9C and 9F).

[0122] In some specific embodiments, the peripheral circuit is further configured to: obtain the predicted valley voltage of the sixth level of the middle page (V2 shown in Figures 9B and 9E) and the predicted valley voltage of the fifth level of the upper page (V2 shown in Figures 9A and 9D) based on the predicted valley voltage of the seventh level (V2 shown in Figures 9C and 9F), obtain the first-level read voltages of the lower page, middle page, and upper page, and obtain the second-level read voltages of the lower page, middle page, and upper page based on the first-level read voltages of the lower page, middle page, and upper page, respectively; wherein the obtained first-level read voltages and second-level read voltages can be used to perform a first read operation on the lower page, middle page, and upper page of at least one codeword, respectively.

[0123] In some embodiments, the peripheral circuit is configured to: use the predicted valley voltage of the first stage and the predicted valley voltage of the second stage as the initial target read voltage; obtain a first result corresponding to the initial target read voltage; determine that the initial target read voltage is the target valley voltage based on the first result corresponding to the initial target read voltage meeting a preset condition; and perform a second read operation on at least one codeword based on the target valley voltage.

[0124] In some specific embodiments, the preset condition can be that the first result corresponding to the initial target read voltage is less than or equal to a second preset value; the second preset value serves as a judgment threshold for the target valley voltage, that is, when the first result is less than or equal to the second preset value, it indicates that when the read voltage corresponding to the first result is used as the target valley voltage, the error rate of the read result is low and the reliability is high. Here, the size of the second preset value is related to the type and storage density of the memory device. The second preset value can be an empirical value; it can also be a default value configured when the memory device is shipped, which is obtained through a large number of simulation experiments before the memory device is shipped. Exemplarily, the second preset value is set in the range of 5 to 30. More specifically, the second preset value can be 5, 10, 15, 20, 25, or 30.

[0125] For example, as shown in FIG9A and FIG9D , the peripheral circuit is configured to: use the predicted valley voltage of the fifth stage (V2 shown in FIG9A and FIG9D ) as the initial target read voltage of the fifth stage, obtain a first result Y2 corresponding to the initial target read voltage of the fifth stage; and determine the initial target read voltage of the fifth stage as the fifth-stage read voltage L5 based on the first result Y2 corresponding to the initial target read voltage of the fifth stage being less than or equal to the second preset value. A similar method is used to determine the fifth-stage read voltage L5 to determine the first-stage read voltage L1.

[0126] For example, as shown in FIG9B and FIG9E , the peripheral circuit is configured to: use the predicted valley voltage of the sixth stage (V2 shown in FIG9B and FIG9E ) as the initial target read voltage of the sixth stage, obtain a first result Y2 corresponding to the initial target read voltage of the sixth stage; and determine the initial target read voltage of the sixth stage as the sixth-stage read voltage L6 based on the first result Y2 corresponding to the initial target read voltage of the sixth stage being less than or equal to the second preset value. A similar method is used to determine the sixth-stage read voltage L6 to determine the fourth-stage read voltage L4 and the second-stage read voltage L2.

[0127] For example, as shown in FIG9C and FIG9F , the peripheral circuit is configured to: use the predicted valley voltage of the seventh stage (V2 shown in FIG9C and FIG9F ) as the initial target read voltage of the seventh stage, obtain a first result Y2 corresponding to the initial target read voltage of the seventh stage; and determine the initial target read voltage of the seventh stage as the seventh-stage read voltage L7 based on the first result Y2 corresponding to the initial target read voltage of the seventh stage being less than or equal to the second preset value. A similar method is used to determine the seventh-stage read voltage L7 to determine the third-stage read voltage L3.

[0128] A second read operation is performed on the lower page of at least one codeword based on determining the fifth-level read voltage L5 and determining the first-level read voltage L1, a second read operation is performed on the middle page of at least one codeword based on determining the sixth-level read voltage L6, determining the fourth-level read voltage L4 and the second-level read voltage L2, and a second read operation is performed on the upper page of at least one codeword based on determining the seventh-level read voltage L7 and determining the third-level read voltage L3.

[0129] In some embodiments, the peripheral circuit is configured to: use the predicted valley voltage of the first stage and the predicted valley voltage of the second stage as the initial target read voltage; adjust the initial target read voltage at least once, and obtain a first result corresponding to the adjusted target read voltage after each adjustment; determine that the adjusted target read voltage is the target valley voltage based on whether the first result corresponding to the adjusted target read voltage meets a preset condition; and perform a second read operation on at least one codeword based on the target valley voltage.

[0130] In some specific embodiments, at least one adjustment can be a first adjustment; the first adjustment can be understood as a larger adjustment, with the first adjustment amplitude being greater than the second adjustment amplitude. In some specific embodiments, the step size of the first adjustment is set to range from 50mV to 150mV. Exemplarily, the first adjustment step size can be 50mV, 60mV, 70mV, 80mV, 100mV, 120mV, or 150mV. Exemplarily, as shown in Figures 9A and 9D, a first adjustment is performed on the predicted valley voltage V2 of the fifth stage to obtain an adjusted target read voltage V22 of the fifth stage. A second voltage difference ΔV2 exists between the predicted valley voltage V2 of the fifth stage and the adjusted target read voltage V22 of the fifth stage. The magnitude of the second voltage difference ΔV2 is the step size of the first adjustment. The step size of the first adjustment is greater than the step size of the third adjustment, i.e., the second voltage difference ΔV2 is greater than the first voltage difference ΔV1.

[0131] For example, as shown in Figures 9A and 9D , the peripheral circuit is configured to: use the predicted valley voltage of the fifth stage (V2 shown in Figure 9D ) as the initial target read voltage of the fifth stage, adjust the predicted valley voltage of the fifth stage at least once, and obtain a first result Y3 corresponding to the adjusted target read voltage (V22 shown in Figure 9D ) after each adjustment; and determine the initial target read voltage of the fifth stage as the fifth-stage read voltage L5 based on the first result corresponding to the adjusted target read voltage being less than or equal to a second preset value. A similar method is used to determine the fifth-stage read voltage L5 for determining the first-stage read voltage L1. As shown in Figures 9B and 9E , and Figures 9C and 9F , a similar method is used to determine the fifth-stage read voltage L5 for determining the sixth-stage read voltage L6, the fourth-stage read voltage L4, and the second-stage read voltage L2, and the seventh-stage read voltage L7 and the third-stage read voltage L3.

[0132] A second read operation is performed on the lower page of at least one codeword based on the determined fifth-level read voltage L5 and the determined first-level read voltage L1, a second read operation is performed on the middle page of at least one codeword based on the determined sixth-level read voltage L6, the determined fourth-level read voltage L4 and the determined second-level read voltage L2, and a second read operation is performed on the upper page of at least one codeword based on the determined seventh-level read voltage L7 and the determined third-level read voltage L3.

[0133] In some embodiments, the peripheral circuit is configured to: use the predicted valley voltage of the first stage as the initial target read voltage to obtain a first result corresponding to the initial target read voltage; determine that the initial read voltage is the target valley voltage based on the first result corresponding to the initial read voltage satisfying a preset condition; and perform a second read operation on at least one codeword based on the determined first-stage target valley voltage and the predicted valley voltage of the second stage.

[0134] For example, as shown in Figures 9A and 9D , the peripheral circuit is configured to: use the predicted valley voltage of the fifth stage (V2 shown in Figures 9A and 9D ) as the initial target read voltage of the fifth stage, obtain a first result Y2 corresponding to the initial target read voltage of the fifth stage; and determine the initial target read voltage of the fifth stage as the fifth-stage read voltage L5 based on the first result Y2 corresponding to the initial target read voltage of the fifth stage being less than or equal to a second preset value. As shown in Figures 9B and 9E , and Figures 9C and 9F , the sixth-stage read voltage L6 and the seventh-stage read voltage L7 are determined in a manner similar to that used to determine the fifth-stage read voltage L5.

[0135] A second read operation is performed on the lower page of at least one codeword based on the determined fifth-level read voltage L5 and the predicted valley voltage of the first level (V4 shown in FIG9A ); a second read operation is performed on the middle page of at least one codeword based on the determined sixth-level read voltage L6, the predicted valley voltage of the fourth level (V4 shown in FIG9B ), and the predicted valley voltage of the second level (V5 shown in FIG9B ); and a second read operation is performed on the upper page of at least one codeword based on the determined seventh-level read voltage L7 and the predicted valley voltage of the third level (V4 shown in FIG9C ).

[0136] In some embodiments, the peripheral circuit is configured to: use the predicted valley voltage of the first stage as the initial target read voltage, adjust the initial target read voltage at least once, and obtain a first result corresponding to the adjusted target read voltage after each adjustment; determine the target valley voltage based on whether the first result corresponding to the adjusted target read voltage meets a preset condition; obtain the predicted valley voltage of the second stage based on the determined target valley voltage of the first stage; and perform a second read operation on at least one codeword based on the determined target valley voltage of the first stage and the predicted valley voltage of the second stage.

[0137] For example, as shown in Figures 9A and 9D , the peripheral circuit is configured to: use the predicted valley voltage of the fifth stage (V2 shown in Figures 9A and 9D ) as the initial target read voltage of the fifth stage, adjust the predicted valley voltage of the fifth stage at least once, and obtain a first result Y3 corresponding to the adjusted target read voltage (V22 shown in Figures 9A and 9D ) after each adjustment; and determine the initial target read voltage of the fifth stage as the fifth-stage read voltage L5 based on the first result corresponding to the adjusted target read voltage being less than or equal to a second preset value. As shown in Figures 9B and 9E , and Figures 9C and 9F , the sixth-stage read voltage L6 and the seventh-stage read voltage L7 are determined in a manner similar to that used to determine the fifth-stage read voltage L5.

[0138] A second read operation is performed on the lower page of at least one codeword based on the determination of the fifth-level read voltage L5 and the predicted valley voltage of the first level (V4 shown in Figure 9A), a second read operation is performed on the middle page of at least one codeword based on the determination of the sixth-level read voltage L6, the predicted valley voltage of the fourth level (V4 shown in Figure 9B) and the predicted valley voltage of the second level (V5 shown in Figure 9B), and a second read operation is performed on the upper page of at least one codeword based on the determination of the seventh-level read voltage L7 and the predicted valley voltage of the third level (V4 shown in Figure 9C).

[0139] In some embodiments, each page of the multiple pages includes multiple second stages; the peripheral circuit is configured to: obtain the predicted valley voltage of the second stage with the largest read voltage among the multiple second stages of each page based on the predicted valley voltage of the first stage / the target valley voltage of the first stage; and sequentially obtain the predicted valley voltage of the second stage with the larger read voltage among the multiple second stages of each page based on the predicted valley voltage of the second stage with the larger read voltage, until the predicted valley voltage of each second stage of each page is obtained.

[0140] For example, as shown in FIG9B , the middle page includes a first stage (i.e., the sixth stage) and multiple second stages (i.e., the fourth and second stages); the peripheral circuit is configured to: obtain the predicted valley voltage of the fourth stage of the middle page based on the predicted valley voltage of the sixth stage of the middle page / determine the target valley voltage of the sixth stage, and obtain the predicted valley voltage of the second stage of the middle page based on the predicted valley voltage of the fourth stage of the middle page. As shown in FIG9A , the predicted valley voltage of the first stage of the lower page is obtained based on the predicted valley voltage of the fifth stage of the lower page / determine the target valley voltage of the fifth stage. As shown in FIG9C , the predicted valley voltage of the third stage of the upper page is obtained based on the predicted valley voltage of the seventh stage of the upper page / determine the target valley voltage of the seventh stage.

[0141] In some embodiments, in the scenario of a QLC type memory cell, the number of storage bits of the memory cell includes four bits, and the corresponding storage states include the 0th state to the 15th state. The four storage bits corresponding to the 16 states are respectively stored in the lower page, the middle page, the upper page, and the extra page. The lower page includes a first level (i.e., the fourteenth level) and multiple second levels (i.e., the eighth level and the second level); the middle page includes a first level (i.e., the thirteenth level) and multiple second levels (i.e., the ninth level, the seventh level, and the third level); the upper page includes a first level (i.e., the fifteenth level) and multiple second levels (i.e., the twelfth level, the tenth level, and the fifth level); and the extra page includes a first level (i.e., the eleventh level) and multiple second levels (i.e., the sixth level, the fourth level, and the first level).

[0142] In some embodiments, the peripheral circuit is configured to: obtain the predicted valley voltage of the eighth level of the lower page according to the predicted valley voltage of the fourteenth level / determine the target valley voltage of the fourteenth level, obtain the predicted valley voltage of the second level of the lower page according to the predicted valley voltage of the eighth level of the lower page; obtain the predicted valley voltage of the ninth level of the middle page according to the predicted valley voltage of the thirteenth level / determine the target valley voltage of the thirteenth level, obtain the predicted valley voltage of the seventh level of the middle page according to the predicted valley voltage of the ninth level of the middle page, obtain the predicted valley voltage of the third level of the middle page according to the predicted valley voltage of the seventh level of the middle page; obtain the predicted valley voltage of the fifteenth level of the upper page according to the predicted valley voltage of the fifteenth level of the upper page Predicting the valley voltage / determining the target valley voltage of the fifteenth level, obtaining the predicted valley voltage of the twelfth level of the previous page, obtaining the predicted valley voltage of the tenth level of the previous page based on the predicted valley voltage of the twelfth level of the previous page, and obtaining the predicted valley voltage of the fifth level of the previous page based on the predicted valley voltage of the tenth level of the previous page; obtaining the predicted valley voltage of the sixth level of the additional page based on the predicted valley voltage of the eleventh level of the additional page, obtaining the predicted valley voltage of the fourth level of the additional page based on the predicted valley voltage of the sixth level of the additional page, and obtaining the predicted valley voltage of the first level of the additional page based on the predicted valley voltage of the fourth level of the additional page. In this way, 15 voltages required for reading a QLC type memory cell are obtained, for example, the 15 voltages are the 15 predicted valley voltages, or a portion of the 15 voltages are the target valley voltages and the other portion are the predicted valley voltages obtained based on the target valley voltages.

[0143] In some embodiments, the peripheral circuit is configured to obtain the predicted valley voltage of the second order based on the predicted valley voltage of the first order / the target valley voltage of the first order and a first mapping function, and the first mapping function is used to characterize the relationship between the predicted valley voltage of the first order / the target valley voltage of the first order and the predicted valley voltage of the second order.

[0144] In some specific embodiments, the second-order predicted valley voltage may refer to a predicted read voltage predicted based on the first-order predicted valley voltage / the first-order target valley voltage and a usage scenario of the memory device (e.g., a data retention scenario or a read disturb scenario). The second-order predicted valley voltage is obtained by querying a preset mapping table based on the first-order predicted valley voltage / the first-order target valley voltage. The preset mapping table stores empirical values ​​of the second-order predicted valley voltage corresponding to the first-order predicted valley voltage / the first-order target valley voltage. These empirical values ​​are obtained through a large number of simulation experiments.

[0145] In some specific embodiments, the first mapping function is used to characterize the relationship between the difference between the predicted valley voltage of the first stage / the target valley voltage of the first stage relative to the target read voltage of the first stage and the predicted valley voltage of the second stage, and the relationship between the usage scenario of the memory device and the predicted valley voltage of the second stage.

[0146] Exemplarily, in a data retention scenario, when the difference between the predicted valley voltage of the first stage / the target valley voltage of the first stage and the target read voltage of the first stage exceeds a threshold value, according to the characteristics of the memory device, it can be considered that the threshold voltage VT of the storage cell of the memory device is in a relatively strong left-shifted state, and according to the predicted valley voltage of the first stage / the target valley voltage of the first stage and the difference between the predicted valley voltage of the first stage / the target valley voltage of the first stage and the target read voltage, the predicted valley voltage of the second stage can be adjusted based on the first mapping function, wherein, relative to the target read voltage of the second stage, the predicted valley voltage of the second stage is in a relatively strong left-shifted state.

[0147] For example, in a read operation interference scenario, when the difference between the predicted valley voltage of the first stage / the target valley voltage of the first stage and the target read voltage exceeds a threshold value, according to the characteristics of the memory device, it can be given priority to consider that the threshold voltage VT of the storage cell of the memory device is in a stronger right-shifted state, and the predicted valley voltage of the second stage can be adjusted based on the first mapping function according to the predicted valley voltage of the first stage / the target valley voltage of the first stage and the difference between the predicted valley voltage of the first stage / the target valley voltage of the first stage and the target read voltage.

[0148] In some embodiments, the peripheral circuit is configured to: during at least one adjustment of the initial target read voltage, use the initial target read voltage as a reference value; starting from the reference value, adjust in two opposite directions with a step size smaller than a first preset step size; during the adjustment in each direction, perform a statistical analysis showing an upward trend based on the first result corresponding to the read voltage after the next adjustment being greater than the first result corresponding to the read voltage after the previous adjustment, and determine the first voltage boundary and the second voltage boundary using a total statistical number greater than or equal to a preset number; during the adjustment in two directions, if the first result corresponding to the target read voltage after one adjustment is lower than the first threshold, or the smallest first result among the multiple first results corresponding to the target read voltage after multiple adjustments is used as the reference value, and when the number of the remaining multiple first results whose difference from the reference value is smaller than the second threshold is greater than a preset number, stop the adjustment and use the target read voltage corresponding to the smallest first result among the multiple first results as the target valley voltage.

[0149] In some embodiments, the peripheral circuit is configured as follows: during the adjustment process in two directions, the adjusted target read voltages corresponding to the total statistical number of times equal to the preset number are used as the first voltage boundary and the second voltage boundary respectively; during the adjustment process in two directions, if the first voltage boundary and the second voltage boundary have been determined, the target read voltage adjusted for the last time is the average value of the first voltage boundary and the second voltage boundary; the read voltage corresponding to the smallest first result among the multiple first results corresponding to all the adjusted target read voltages is used as the target valley voltage.

[0150] In some embodiments, the peripheral circuit is configured as follows: in the process of performing M first adjustments on the near-valley point voltage with a first step length, starting from the near-valley point voltage, adjusting in a first direction with a first step length until a first result corresponding to the target read voltage after adjustment in the first direction is greater than a near-valley threshold; starting from the near-valley point voltage, adjusting in a second direction opposite to the first direction with a first step length until a first result corresponding to the target read voltage after adjustment in the second direction is greater than the near-valley threshold.

[0151] Here, the first adjustment needs to be performed in two directions: the first direction can be the left direction (or negative direction), and the second direction can be the right direction (or positive direction); or the first direction can be the right direction (or positive direction), and the second direction can be the left direction (or negative direction). During the process of performing the M first adjustments, the order of adjusting the first direction and the second direction can be adjusted according to actual needs.

[0152] In other embodiments, the first adjustment may also be performed in one direction. It should be noted that, for an application scenario, if the direction of the threshold voltage shift can be inferred, the first adjustment may be performed in only one direction. For example, for an application scenario determined to be data retention, it can be inferred that the threshold voltage distribution of the memory cell is shifted to the left, and the first adjustment may be performed only in the left direction (or negative direction).

[0153] For example, as shown in Figure 10A , the first result corresponding to the initial target read voltage is the first FBC. The near-valley threshold is obtained based on this first FBC and the first mapping function. The near-valley point fnvp is found based on this first FBC and the second mapping function (one or more iterations). Starting from the near-valley point, adjustments are made in the left and right directions (or forward directions) with a first step length until the first results corresponding to the adjusted read voltages in both directions are greater than the near-valley threshold.

[0154] In some embodiments, the peripheral circuit is configured as follows: in the process of performing N second adjustments to the inflection point voltage with a second step size, starting from the inflection point voltage, adjusting in two opposite directions with a second step size respectively; in the process of adjusting in each direction, when the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, a statistical analysis showing an upward trend is performed, and the first boundary voltage and the second boundary voltage are determined based on the total statistical number being greater than or equal to a preset number; in the process of adjusting in two directions, if the first result corresponding to the target read voltage after one adjustment is lower than a preset threshold, or the smallest first result among the multiple first results corresponding to the target read voltage after multiple adjustments is used as a reference value, when the number of the remaining multiple first results whose differences from the reference value are less than the preset difference is greater than a preset number, the adjustment is stopped and the adjusted target read voltage corresponding to the smallest first result among the multiple first results is used as the target valley voltage.

[0155] Here, the target read voltage after the last adjustment and the target read voltage after the next adjustment are both general concepts, which are the adjustment with an earlier adjustment time and the adjustment with a later adjustment time in any two adjacent second adjustments.

[0156] Here, the preset number represents the degree to which the inflection point is raised. The preset number can be adjusted according to actual conditions. In some embodiments, the preset number is 3-7 times. Exemplarily, the preset number can be 3, 5 or 7 times.

[0157] During the adjustment process in each direction, if the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, it indicates that the first result corresponding to the target read voltage after the next adjustment is on an upward trend compared to the first result corresponding to the target read voltage after the previous adjustment, and a statistical analysis of the upward trend is performed. If the first result corresponding to the target read voltage after the next adjustment is less than or equal to the first result corresponding to the target read voltage after the previous adjustment, it indicates that the first result corresponding to the target read voltage after the next adjustment is on a downward or unchanged trend compared to the first result corresponding to the target read voltage after the previous adjustment, and a statistical analysis of the upward trend is not performed. In other words, the data of the statistical analysis of the upward trend remains unchanged during this statistical analysis.

[0158] Here, the preset threshold value is used to characterize the maximum value in the range of predicted effective target valley voltage. The preset threshold value can be determined based on the first result under the initial target read voltage. It is understandable that when performing a read operation, the further the threshold voltage of the memory cell shifts from the threshold voltage during writing, the larger the first result read using the initial target read voltage will generally be. Based on this, the specific value of the first result under the initial target read voltage can be used to confirm the preset threshold value. The preset threshold value is used to characterize the change (increase) in the target valley voltage caused by the shift in the threshold voltage of the memory cell.

[0159] It should be noted that although the preset threshold and the aforementioned near-valley threshold are both obtained based on the first result corresponding to the initial target reading voltage, there are differences between the two. When the first result is less than the near-valley threshold, it means that more precise adjustments or searches can be carried out next; when the first result is less than the preset threshold, it means that you can consider stopping the adjustment or search and directly determine the target valley voltage.

[0160] In some embodiments, when the first result is less than a preset threshold, it indicates that the adjusted target read voltage corresponding to the first result can be used as the target valley voltage.

[0161] In some embodiments, the smallest first result among the plurality of first results corresponding to the target read voltage after N times of second adjustment is used as a reference value. If the number of the remaining plurality of first results whose difference from the reference value is less than a preset difference is greater than a preset number, the search is stopped and the adjusted target read voltage corresponding to the smallest first result among the plurality of first results is used as the target valley voltage. Here, the preset difference and the preset number can be set together based on actual conditions. Generally, a slightly larger preset difference is set, and a relatively larger preset number is also set; generally, a slightly smaller preset difference is set, and a relatively smaller preset number is also set.

[0162] In some embodiments, the peripheral circuit is configured as follows: during the process of performing N second adjustments to the inflection point voltage with a second step size, starting from the inflection point voltage, adjusting in the first direction with a second step size until the total statistical number of times the upward trend is present during the adjustment process in the first direction is equal to a preset number; starting from the inflection point voltage, adjusting in a second direction opposite to the first direction with a second step size until the total statistical number of times the upward trend is present during the adjustment process in the second direction is equal to a preset number.

[0163] Here, the second adjustment needs to be performed in two directions: the first direction can be the left direction (or negative direction), and the second direction can be the right direction (or positive direction); or the first direction can be the right direction (or positive direction), and the second direction can be the left direction (or negative direction). During the process of performing the first adjustment M times, the order of adjusting the first direction and the second direction can be adjusted according to actual needs.

[0164] Here, when the total statistical number of times of the upward trend in the adjustment process toward the first direction / the second direction is equal to a preset number, the second adjustment is stopped.

[0165] In some embodiments, the peripheral circuit is configured to: use the adjusted target read voltage corresponding to the total statistical number of times the upward trend is equal to the preset number during the adjustment in the first direction as the first boundary voltage, and use the adjusted target read voltage corresponding to the total statistical number of times the upward trend is equal to the preset number during the adjustment in the second direction as the second boundary voltage; in the process of adjusting in both directions, if the first boundary voltage and the second boundary voltage have been determined, obtain the first result corresponding to the last adjusted read voltage, and the last adjusted read voltage is the average of the first boundary voltage and the second boundary voltage; and use the read voltage corresponding to the smallest first result among the multiple first results corresponding to all the adjusted read voltages as the target valley voltage.

[0166] Here, the boundary corresponding to the first boundary voltage may be the left boundary, and the boundary corresponding to the second boundary voltage may be the right boundary; or, the boundary corresponding to the first boundary voltage may be the right boundary, and the boundary corresponding to the second boundary voltage may be the left boundary.

[0167] For example, as shown in Figure 10B , after M first adjustments, the point corresponding to the smallest first result among the M first results corresponding to the M first adjustments is determined as the inflection point vtp. Starting from the inflection point vtp, adjustments are made in a second step size toward the left. When the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, an upward trend count is performed. In Figure 10B , both leftward second adjustments show an upward trend, and the total upward trend count is 2. Thereafter, according to the preset number of times, if the preset number has been reached, a second adjustment can be started in a second step size toward the right; if the preset number has not been reached, the second adjustment can continue in a leftward second step size until the preset number is reached.

[0168] For example, as shown in FIG10C , starting from the inflection point vtp, adjustments are made in a second step size toward the right. When the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, an upward trend count is performed. In FIG10C , of the three second adjustments toward the right, the first adjustment shows a downward trend, and the total statistical value of the upward trend is 0. The next two adjustments both show an upward trend, and the total statistical value of the upward trend is 2. Thereafter, according to the preset number of times, if the preset number of times has been reached, the second adjustment can be stopped; if the preset number of times has not been reached, the adjustment can continue toward the right until the preset number of times has been reached, and the second adjustment can be stopped.

[0169] FIG10D is a schematic diagram of a method for determining the seventh-level read voltage corresponding to the upper page shown in FIG9C , provided by an embodiment of the present application. As shown in FIG10D , in some embodiments, the peripheral circuit is configured to: perform multiple first adjustments on the target read voltage with a first step length, and obtain first results corresponding to the target read voltage after the multiple first adjustments; determine an inflection point value based on the obtained first results corresponding to the read voltage after the multiple first adjustments, with the target read voltage corresponding to the inflection point value being the inflection point voltage; perform multiple second adjustments on the inflection point voltage with a second step length, and obtain first results corresponding to the target read voltage after the multiple second adjustments; the second step length is smaller than the first step length; and determine the target valley voltage using the obtained first results corresponding to the target read voltage after the multiple second adjustments.

[0170] In some specific embodiments, as shown in FIG. 10D , taking the target read voltage of the seventh stage as an example, the peripheral circuit is configured to obtain the knee voltage V4 through the following steps:

[0171] After obtaining the first result Y1 corresponding to the target read voltage V0, the target read voltage is adjusted for the first time using the first step length value (positive value) with the target read voltage V0 as a reference to obtain the first result Y1-2, and the target read voltage is adjusted for the second time using the first step length value (negative value) to obtain the first result Y1-3;

[0172] According to the first result Y1-2 being greater than the first result Y1 and the first result Y1-3 being less than the first result Y1-1, determining to use the first step length value (negative value) to adjust the target read voltage multiple times to obtain first results after the multiple adjustments (for example, first results Y1-4, Y1-5, Y1-6, Y1-7, or first results Y1-4 to Y1-9, or first results Y1-4 to Y1-10);

[0173] Based on at least one rising trend, it is determined that the first adjustment of the target read voltage is stopped. Here, an rising trend can be understood as a first result Y1-(N+1) obtained by performing the Nth first adjustment on the target read voltage using the first step length value (negative value) is less than the first result Y1-(N+2) obtained by performing the (N+1)th first adjustment on the target read voltage using the first step length value (negative value), and it is determined as an rising trend. For example, the first result Y1-7 is greater than the first result Y1-6, the first result Y1-8 is greater than the first result Y1-7, the first result Y1-9 is greater than the first result Y1-8, or the first result Y1-10 is greater than the first result Y1-9, and all of these can be determined as an rising trend.

[0174] The minimum value among the first results corresponding to the read voltages obtained after multiple first adjustments is determined as the inflection point value, and the target read voltage corresponding to the inflection point value is the inflection point voltage; for example, the minimum value among the multiple first results is the first result Y1-6, the first result Y1-6 is the inflection point value Yt, and the target read voltage corresponding to the inflection point value Yt is the inflection point voltage V4.

[0175] As shown in Figure 10D, in some embodiments, the first result corresponding to the target read voltage after multiple first adjustments includes a first adjacent value and a second adjacent value adjacent to the inflection point value, and the peripheral circuit is configured to: based on the difference between the first adjacent value and the inflection point value being less than the difference between the second adjacent value and the inflection point value, narrow the range of the multiple second adjustments to between the target read voltage corresponding to the first adjacent value and the inflection point voltage; and take the average value of the read voltage corresponding to the first adjacent value and the inflection point voltage, and based on the first result corresponding to the average value being less than the first threshold, use the average value as the target valley voltage; based on the first result corresponding to the average value being greater than or equal to the first threshold, continue to perform a second adjustment between the read voltage corresponding to the first adjacent value and the inflection point voltage until the first result corresponding to the adjusted target read voltage is less than the first threshold.

[0176] In some specific embodiments, as shown in FIG10D , taking the target read voltage of the seventh stage as an example, the peripheral circuit is configured to: after obtaining the knee point value Yt and the knee point voltage V4, perform at least one second adjustment using the second step value based on the knee point voltage V4 to obtain an adjusted target read voltage. The detailed process of performing at least one second adjustment using the second step value can be understood by referring to the detailed process of performing at least one first adjustment using the first step value in the above embodiment, wherein the first step value is greater than the second step value, and will not be further described here.

[0177] Here, the absolute value of the first step length is greater than the absolute value of the second step length; illustratively, the second direction (or the right direction, or the positive direction) is adjusted, and the first step length value range is set to 50mV to 150mV, which can be 50mV, 60mV, 70mV, 80mV, 100mV, 120mV or 150mV, or, the first direction (or the left direction, or the negative direction) is adjusted, and the first step length value range is set to -50mV to -80mV, which can be -50mV, -60mV, -70mV, -80mV, -100mV, -120mV or -150mV. The second direction (or the right direction, or the positive direction) is adjusted, and the second step value range is set to 20mV to 40mV, which can be 20mV, 30mV, or 40mV. Alternatively, the first direction (or the left direction, or the negative direction) is adjusted, and the second step value range is set to -20mV to -50mV, which can be -20mV, -30mV, or -40mV.

[0178] In some specific embodiments, as shown in FIG10D , taking the target read voltage of the seventh level as an example, the peripheral circuit is configured as follows: based on the difference between the first adjacent value (first result Y1-7) and the inflection point value Yt (first result Y1-6) being less than the difference between the second adjacent value (first result Y1-5) and the inflection point value Yt, the range of multiple second adjustments is narrowed to between the target read voltage V3 corresponding to the first adjacent value (first result Y1-7) and the inflection point voltage V4; and taking the average value of the read voltage V3 and the inflection point voltage V4 corresponding to the first adjacent value, and based on the first result Yv corresponding to the average value being less than the first threshold, taking the average value as the target valley voltage V2, and determining the target valley voltage V2 as the read voltage L7 of the seventh level.

[0179] In some embodiments, the peripheral circuit is configured to obtain the predicted valley voltage of the first stage based on the first result corresponding to the target read voltage of the first stage, the order number of the first stage, and the second mapping function; the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage, the order number of each stage and the predicted valley voltage.

[0180] In some specific embodiments, the predicted valley voltage of the first stage may refer to a predicted read voltage predicted based on a first result corresponding to a target read voltage of the first stage and a usage scenario of the memory device. The predicted valley voltage of the first stage is obtained by querying a preset mapping table based on the first result (here, the first result corresponding to the target read voltage of the first stage). The preset mapping table stores empirical values ​​of the predicted valley voltage of the first stage corresponding to the first result, and these empirical values ​​are obtained through a large number of simulation experiments.

[0181] In some specific embodiments, the second mapping function is used to characterize the relationship between the difference between the first result corresponding to the target read voltage of the first stage and the first result threshold configured when the memory device leaves the factory and the predicted valley voltage of the first stage, the stage number of the predicted valley voltage of the first stage, and the relationship between the usage scenario of the memory device and the predicted valley voltage of the first stage.

[0182] Exemplarily, in a data retention scenario, when the first result corresponding to the target read voltage of the first stage exceeds a threshold value (e.g., 400), based on the characteristics of the memory device, it can be considered that the threshold voltage VT of the storage cell of the memory device is in a relatively strong left-shifted state. According to the first result corresponding to the target read voltage of the first stage, the predicted valley voltage of the first stage can be adjusted based on the second mapping function, wherein, relative to the target read voltage of the first stage, the predicted valley voltage of the first stage is in a relatively strong left-shifted state.

[0183] For example, in a read operation interference scenario, when the first result corresponding to the target read voltage of the first stage exceeds a threshold value (for example, 300), according to the characteristics of the memory device, it can be considered that the threshold voltage VT of the storage cell of the memory device is in a relatively strong left-shifted state. According to the first result corresponding to the target read voltage of the first stage, the predicted valley voltage of the first stage can be adjusted based on the second mapping function, wherein, relative to the target read voltage of the first stage, the predicted valley voltage of the first stage is in a relatively strong right-shifted state.

[0184] In some embodiments, the peripheral circuit is configured to: read the stored data of at least one codeword at a first read voltage to obtain a second result; read the stored data of at least one codeword at a second read voltage to obtain a third result; perform a logical operation on the second result and the third result to obtain a fourth result; and count the number of bits in the fourth result that represent the flipping of the third result compared to the second result to obtain the first result.

[0185] For example, as shown in FIG9D , data stored in the lower page of a storage cell in at least one codeword is read at a first read voltage (V0 shown in FIG9D ), and storage cells whose threshold voltage is less than the first read voltage are marked as bit 1, and storage cells whose threshold voltage is greater than the first read voltage are marked as bit 0, thereby obtaining a second result.

[0186] For example, as shown in FIG9D , data stored in the lower page of a storage cell in at least one codeword is read at a second read voltage (V1 shown in FIG9D ), and storage cells whose threshold voltage is less than the second read voltage are marked as bit 1, and storage cells whose threshold voltage is greater than the second read voltage are marked as bit 0, thereby obtaining a third result.

[0187] Exemplarily, the second result and the third result are subjected to an XOR operation to obtain a fourth result. It should be noted that the XOR operation is one of the basic logical operations. In binary, if two binary numbers at the same position are the same, the result is "0", and if two binary numbers at the same position are different, the result is "1" (i.e., the same is 0, and different is 1).

[0188] Exemplarily, a bit that is 1 in the fourth result indicates that the data read from a storage cell in at least one codeword at the first read voltage and at the second read voltage are different, and a bit that is 0 in the fourth result indicates that the data read from a storage cell in at least one codeword at the first read voltage and at the second read voltage are the same. In other words, the number of bits that are 1 in the fourth result indicates the number of bits of the at least one codeword that are flipped between the first read voltage and the second read voltage, and the number of bits that are 0 in the fourth result indicates the number of bits of the at least one codeword that are identical between the first read voltage and the second read voltage. Because a single-stage read mode is employed, i.e., both read operations read a single bit of data stored in the lower page of the storage cell in the at least one codeword, the number of bits that are 1 in the fourth result indicates the number of storage cells of the at least one codeword that are flipped between the first read voltage and the second read voltage, and this number is recorded as the first result corresponding to the first read voltage. For example, at least one codeword corresponds to a first result Y1 at the target read voltage of the first stage (V0 shown in Figure 9D), at least one codeword corresponds to a first result Y2 at the target adjusted read voltage of the first stage (V2 shown in Figure 9D), and at least one codeword corresponds to a first result Y3 at the adjusted target read voltage of the first stage (V22 shown in Figure 9D).

[0189] In some embodiments, the peripheral circuit includes: a first latch, a second latch, and a third latch; the first latch is configured to store the second result; the second latch is configured to store the third result; and the third latch is configured to store the fourth result.

[0190] Exemplarily, the stored data of at least one codeword read at a first read voltage (i.e., the second result) is stored in the first latch, the stored data of at least one codeword read at a second read voltage (i.e., the third result) is stored in the second latch, and the data after performing an XOR operation on the second result and the third result (i.e., the fourth result) is stored in the third latch.

[0191] On the first aspect, in each memory device provided by the embodiments of the present application, the first result (the size of the first result can be several bytes) is transmitted without transmitting at least one codeword (for example, the size of the codeword can be 4KB), and the amount of data transmitted is reduced; the process of obtaining the first result converges inside the memory device, does not occupy the space of, for example, a memory controller, and has a low degree of dependence on, for example, the memory controller; the process of obtaining the predicted valley voltage / target valley voltage based on the first result is completed in the memory device; the transmission time of the output port is reduced; and it is applicable to MLC, TLC or QLC type memory devices.

[0192] In a second aspect, an embodiment of the present application provides a memory system, as shown in Figures 11 and 12, the memory system 102 includes: one or more memory devices 104 as provided in the first aspect; and a memory controller 106, which is coupled to the memory device 104 and controls the memory device 104.

[0193] As shown in FIG11 , in some embodiments, a memory system 102 is coupled to a host, responding to host instructions and performing various feedback operations. Memory system 102 may include a memory controller 106 and a memory device 104. Memory controller 106 is configured to control memory device 104 to perform operations such as read, write, and erase. Memory controller 106 and memory device 104 may also be coupled in any suitable manner.

[0194] The memory controller 106 may include a host interface (I / F) 1061, a memory interface (I / F) 1062, a control unit 1063, a read-only memory (ROM) 1069, a random access memory (RAM) 1070, an error correction module 1064, a garbage collection module 1065, a wear leveling module 1066, a data buffer 1067, and a bus 1060. The host interface 1061 is a connection interface between the host 108 and the memory controller 106. The host interface 1061 allows the host and the memory controller to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1062 is a connection interface between the memory controller 106 and the memory device 104. The memory interface 1062 is used to implement data transmission between the memory controller 106 and the memory device 104. The control unit 1063 is used to control the memory system 106 as a whole. The specific steps executed by the memory controller described above are mainly executed and completed by the control unit 1063 here. In some specific embodiments, the control unit 1063 is, for example, a central processing unit (CPU), a microprocessor (MCU), etc. The ROM 1069 generally contains the firmware or firmware program code of the memory controller 106, which is used to initialize and operate the various components of the memory controller. The RAM 1070 is generally used to cache data. The error correction module 1064 can further include an encoding unit and a decoding unit; the encoding unit is used to encode the data to be stored to obtain check data, and the decoding unit is used to decode the check data to detect and correct possible erroneous data during data transmission.

[0195] The garbage collection module 1065 is used to read valid data from some storage blocks, rewrite it, and then mark these storage blocks as new backup storage blocks after the storage space of the memory device reaches a certain threshold. Garbage collection is generally implemented in three steps: selecting a source storage block with less valid data; finding valid data from the source storage block; and writing the valid data to the target storage block. At this point, all data in the source storage block becomes invalid data, and the source storage block is marked and can be used as a new backup storage block. The wear leveling module 1066 is used to maintain a balanced wear (number of erases) on each storage block in the memory system through data statistics and algorithms. Wear leveling is generally implemented in two steps: selecting a source storage block containing cold data; reading valid data from the source storage block and writing it to a storage block with a relatively high erase count. At this point, the valid data in the source storage block becomes invalid data and is marked. The buffer 1067 is used to cache data.

[0196] In some specific embodiments, the memory controller 106 is configured to control the memory device 104 to perform a first read operation on the at least one codeword.

[0197] In some specific embodiments, the memory device 104 includes a memory cell array, the memory cell array includes memory cells with multiple storage bits, the multiple storage bits correspond to multiple pages respectively; at least some of the pages correspond to multiple levels, the multiple levels include a first level and a second level, and the read voltage of the second level is less than the read voltage of the first level; the peripheral circuit of the memory device 104 is coupled to the memory cell array and configured to perform the following steps: obtaining a predicted valley voltage of the first level based on a first result corresponding to a target read voltage of the first level; the first result includes the number of bits flipped in two read results at the first read voltage and the second read voltage of at least one codeword formed by a preset number of memory cells; the difference between the first read voltage and the second read voltage is less than a preset voltage; obtaining a predicted valley voltage of the second level based on the predicted valley voltage of the first level; and performing a first read operation on at least one codeword using the predicted valley voltage of the first level and the predicted valley voltage of the second level.

[0198] In some specific embodiments, the peripheral circuit of the memory device 104 is configured to: use the predicted valley voltage of the first stage and the predicted valley voltage of the second stage as the initial target read voltage; obtain a first result corresponding to the initial target read voltage; determine that the initial target read voltage is the target valley voltage based on the first result corresponding to the initial target read voltage satisfying a preset condition; or, adjust the initial target read voltage at least once, and obtain the first result corresponding to the adjusted target read voltage after each adjustment; determine that the adjusted target read voltage is the target valley voltage based on the first result corresponding to the adjusted target read voltage satisfying a preset condition; and perform a second read operation on at least one codeword based on the target valley voltage.

[0199] In some specific embodiments, the peripheral circuit of the memory device 104 is configured to: use the predicted valley voltage of the first stage as the initial target read voltage, and obtain a first result corresponding to the initial target read voltage; determine that the initial read voltage is the target valley voltage based on the first result corresponding to the initial read voltage satisfying a preset condition; or, adjust the initial target read voltage at least once, and obtain the first result corresponding to the adjusted target read voltage after each adjustment; determine the target valley voltage based on the first result corresponding to the adjusted target read voltage satisfying the preset condition; obtain the predicted valley voltage of the second stage based on the determined target valley voltage of the first stage; and perform a second read operation on at least one codeword based on the determined target valley voltage of the first stage and the predicted valley voltage of the second stage.

[0200] In some specific embodiments, each of the multiple pages includes multiple second stages; the peripheral circuit of the memory device 104 is configured to: obtain the predicted valley voltage of the second stage with the largest read voltage among the multiple second stages of each page based on the predicted valley voltage of the first stage / the target valley voltage of the first stage; and sequentially obtain the predicted valley voltages of the second stages with smaller read voltages adjacent to the second stage with larger read voltage among the multiple second stages of each page, until the predicted valley voltage of each second stage of each page is obtained.

[0201] In some specific embodiments, the peripheral circuit of the memory device 104 is configured to obtain the predicted valley voltage of the second order based on the predicted valley voltage of the first order / the target valley voltage of the first order and a first mapping function, where the first mapping function is used to characterize the relationship between the predicted valley voltage of the first order / the target valley voltage of the first order and the predicted valley voltage of the second order.

[0202] In some specific embodiments, the peripheral circuit of the memory device 104 is configured to: during at least one adjustment of the initial target read voltage, use the initial target read voltage as a reference value; starting from the reference value, adjust in two opposite directions with a step size smaller than a first preset step size; during the adjustment in each direction, perform a statistical analysis showing an upward trend based on whether the first result corresponding to the read voltage after the next adjustment is greater than the first result corresponding to the read voltage after the previous adjustment, and determine the first voltage boundary and the second voltage boundary using a total statistical number greater than or equal to a preset number; during the adjustment in both directions, if the first result corresponding to the target read voltage after one adjustment is lower than the first threshold, or if the smallest first result among multiple first results corresponding to the target read voltage after multiple adjustments is used as the reference value, and when the number of the remaining multiple first results whose difference from the reference value is smaller than the second threshold is greater than a preset number, stop the adjustment and use the target read voltage corresponding to the smallest first result among the multiple first results as the target valley voltage.

[0203] In some specific embodiments, the peripheral circuit of the memory device 104 is configured as follows: during the adjustment process in two directions, the adjusted target read voltages corresponding to the total statistical number of times equal to the preset number are used as the first voltage boundary and the second voltage boundary respectively; during the adjustment process in two directions, if the first voltage boundary and the second voltage boundary have been determined, the target read voltage of the last adjustment is the average value of the first voltage boundary and the second voltage boundary; and the read voltage corresponding to the smallest first result among multiple first results corresponding to all the adjusted target read voltages is used as the target valley voltage.

[0204] In some specific embodiments, the peripheral circuit of the memory device 104 is configured to obtain a predicted valley voltage of the first stage based on a first result corresponding to a target read voltage of the first stage, the stage number of the first stage, and a second mapping function; the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage, the stage number of each stage, and the predicted valley voltage.

[0205] In some specific embodiments, the peripheral circuit of the memory device 104 is configured to: read the stored data of at least one codeword at a first read voltage to obtain a second result; read the stored data of at least one codeword at a second read voltage to obtain a third result; perform a logical operation on the second result and the third result to obtain a fourth result; and count the number of bits in the fourth result that represent the flipping of the third result compared to the second result to obtain the first result.

[0206] In some specific embodiments, the peripheral circuit of the memory device 104 is configured as: a first latch, a second latch, and a third latch; the first latch is configured to store the second result; the second latch is configured to store the third result; and the third latch is configured to store the fourth result.

[0207] In some embodiments, the memory controller 106 is configured to: send a first instruction, the first instruction instructing to obtain information representing the target valley voltage of multiple levels; the memory device 104 is configured to: receive the first instruction, obtain information representing the predicted valley voltage of multiple levels, and send the obtained information representing the predicted valley voltage of multiple levels to the memory controller; the memory controller 106 is also configured to: use the predicted valley voltage in the information representing the predicted valley voltage of multiple levels to control the memory device to perform a first read operation, and perform a first error correction decoding operation on the first read result of the first read operation.

[0208] In some specific embodiments, as shown in FIG12 , the memory controller 106 is configured to: send a first instruction, the first instruction instructing to obtain information representing the target valley voltage of multiple stages; the memory device 104 is configured to: receive the first instruction, obtain information representing the predicted valley voltage of multiple stages, and send the obtained information representing the predicted valley voltage of multiple stages to the memory controller.

[0209] In some specific embodiments, as shown in FIG12 and FIG13 , the memory device 104 is configured to receive a first instruction and obtain information representing predicted valley voltages of multiple levels, including performing the following steps:

[0210] Step S301, obtaining a first result corresponding to a first-stage target read voltage;

[0211] Step S302: Obtaining a predicted valley voltage for the first stage based on a first result corresponding to a target read voltage for the first stage; the first result includes the number of bits flipped in at least one codeword formed by a preset number of memory cells in two read results at the first read voltage and at the second read voltage; and the difference between the first read voltage and the second read voltage is less than a preset voltage.

[0212] Step S303: obtaining the second-order predicted valley voltage according to the first-order predicted valley voltage;

[0213] The memory controller 106 is further configured to perform the following steps:

[0214] Step S304 : Controlling the memory device to perform a first read operation on at least one codeword using the first-order predicted valley voltage and the second-order predicted valley voltage, and performing a first error correction decoding operation on a first read result of the first read operation.

[0215] For example, as shown in Figures 9A, 9B, and 9C, at least one codeword corresponds to a lower page, a middle page, and an upper page, wherein the multi-level of the lower page includes the first and fifth levels, the multi-level of the middle page includes the second, fourth, and sixth levels, and the multi-level of the upper page includes the third and seventh levels. The fifth, sixth, and seventh levels correspond to the predicted valley voltages of the first level of the lower page, middle page, and upper page, respectively, and the first, second, fourth, and third levels correspond to the predicted valley voltages of the second level of the lower page, middle page, and upper page, respectively.

[0216] For example, steps S301 to S304 can be performed on the lower page corresponding to at least one codeword to obtain the predicted valley voltage of the first stage and the predicted valley voltage of the second stage corresponding to the lower page. The predicted valley voltage of the first stage and the predicted valley voltage of the second stage are used to control the memory device to perform a first read operation on the lower page of the at least one codeword, and to perform a first error correction decoding operation on the first read result of the first read operation. Similarly, referring to the details of performing steps S301 to S304 on the lower page corresponding to at least one codeword, steps S301 to S304 can be performed on the middle page and upper page of at least one codeword, respectively. In this way, by performing steps S301 to S304 on the lower, middle, and upper pages corresponding to at least one codeword, the first read operation on the at least one codeword is completed, and the first error correction decoding operation is performed on the first read result of the first read operation.

[0217] In some embodiments, the memory controller 106 is configured to perform the following steps: output a first read result based on the success of the first error correction decoding; or, based on the failure of the first error correction decoding, send a second instruction, wherein the second instruction instructs to re-acquire information representing the target valley voltages of the multiple stages; the memory device 104 is configured to: receive the second instruction, redetermine the target valley voltages of the multiple stages, and send second information representing the redetermined target valley voltages to the memory controller; the memory controller 106 is further configured to: use the redetermined target valley voltages in the second information to control the memory device to perform a second read operation, and perform a second error correction decoding operation on a second read result of the second read operation.

[0218] In some specific embodiments, as shown in FIG12 , the memory controller 106 is configured to: send a second instruction, the second instruction instructing to reacquire information representing the target valley voltage of the multiple stages; the memory device 104 is configured to: receive the second instruction, re-determine the target valley voltage of the multiple stages, and send the second information representing the re-determined target valley voltage to the memory controller.

[0219] In some specific embodiments, as shown in FIG. 12 and FIG. 13 , the memory device 104 is configured to receive a second instruction and redetermine a target valley voltage of the multiple stages, including performing the following steps:

[0220] Step S306 , using the first-order predicted valley voltage and the second-order predicted valley voltage as initial target reading voltages;

[0221] Step S307 , adjusting the initial target read voltage at least once, and obtaining a first result corresponding to the adjusted target read voltage after each adjustment;

[0222] Step S308 , determining that the adjusted target read voltage is a target valley voltage based on whether the first result corresponding to the adjusted target read voltage satisfies a preset condition;

[0223] The memory controller 106 is further configured to perform the following steps:

[0224] Step S309 : controlling the memory device to perform a second read operation on the at least one codeword according to the target valley voltage, and performing a second error correction decoding operation on a second read result of the second read operation.

[0225] For example, steps S306 to S309 can be performed on the lower page corresponding to at least one codeword to obtain adjusted target read voltages for the first and second stages corresponding to the lower page. The adjusted target read voltages for the first and second stages are then used to control the memory device to perform a first read operation on the lower page of the at least one codeword, and a first error correction decoding operation is performed on the first read result of the first read operation. Similarly, referring to the details of performing steps S306 to S309 on the lower page corresponding to at least one codeword, steps S306 to S309 can be performed on the middle page and upper page of the at least one codeword, respectively. In this way, by performing steps S306 to S309 on the lower, middle, and upper pages corresponding to the at least one codeword, a second read operation is performed on the at least one codeword, and a second error correction decoding operation is performed on the second read result of the second read operation.

[0226] In some embodiments, as shown in Figures 12 and 13, the memory controller 106 is configured to perform the following steps: step S305, based on the success of the first error correction decoding, step S311, output the first read result; or, step S310, based on the success of the second error correction decoding, step S311, output the second read result.

[0227] In some embodiments, as shown in FIG. 12 and FIG. 13 , the memory controller 106 is configured to perform the following steps: Step S310 , based on the unsuccessful second error correction decoding, Step S312 , confirming that the error cannot be corrected.

[0228] In some embodiments, the memory controller 106 is configured to: send a mode setting command, the mode setting command instructing to set the read mode of the memory device to a single-level read mode; the single-level read mode includes reading at least one bit of storage data stored in the memory cell using a first-level read voltage; the memory device 104 is configured to: enter the single-level read mode in response to the mode setting command, and, in the single-level read mode, obtain a first result corresponding to at least one codeword at a first-level target read voltage.

[0229] In some embodiments, the error correction decoding operation includes a hard decoding or a soft decoding (hard / soft decoding) operation, and the error correction decoding operation includes a first error correction decoding operation or a second error correction decoding operation.

[0230] Secondly, in the memory system provided by the embodiment of the present application, the first result (the size of the first result can be several bytes) is transmitted without transmitting at least one codeword (for example, the size of the codeword can be 4KB), and the amount of data transmitted between the memory device and the memory controller is reduced; the process of obtaining the first result converges inside the memory device, does not occupy the space of the memory controller, and has a low degree of dependence on the memory controller; the process of obtaining the predicted valley voltage / target valley voltage based on the first result is completed in the memory device; the transmission time of the input and output ports of the memory device and / or the time of the error correction decoding operation of the memory controller are reduced, the iteration time of the error correction decoding algorithm of the memory controller is saved, and the error correction decoding speed is faster; it is suitable for MLC, TLC or QLC type memory systems.

[0231] In a third aspect, an embodiment of the present application provides a memory controller, which is coupled to at least one memory device, the memory device including a storage cell with a plurality of storage bits; the plurality of storage bits correspond to a plurality of pages respectively; at least some of the pages correspond to a plurality of stages, the plurality of stages include a first stage and a second stage, and the read voltage of the second stage is less than the read voltage of the first stage; the memory controller includes: a control unit, configured to: obtain a predicted valley voltage of the first stage according to a first result corresponding to a target read voltage of the first stage; the first result includes the number of bits flipped in two read results under the first read voltage and the second read voltage of at least one codeword formed by a preset number of storage cells; the difference between the first read voltage and the second read voltage is less than a preset voltage; the predicted valley voltage of the second stage is obtained according to the predicted valley voltage of the first stage; and use the predicted valley voltage of the first stage and the predicted valley voltage of the second stage to control the memory device to perform a first read operation, and perform a first error correction decoding on the first read result of the first read operation.

[0232] In some embodiments, the control unit is configured to: based on the failure of the first error correction decoding, use the predicted valley voltage of the first stage and the predicted valley voltage of the second stage as the initial target read voltage; obtain a first result corresponding to the initial target read voltage; determine that the initial target read voltage is the target valley voltage based on the first result corresponding to the initial target read voltage satisfying a preset condition; or, adjust the initial target read voltage at least once, and obtain the first result corresponding to the adjusted target read voltage after each adjustment; determine that the adjusted target read voltage is the target valley voltage based on the first result corresponding to the adjusted target read voltage satisfying the preset condition; control the memory device to perform a second read operation on at least one codeword based on the target valley voltage, and perform a second error correction decoding on the second read result of the second read operation.

[0233] In some embodiments, the control unit is configured to: based on the failure of the first error correction decoding, use the predicted valley voltage of the first stage as the initial target read voltage to obtain a first result of the initial target read voltage; based on the first result corresponding to the initial read voltage satisfying a preset condition, determine that the initial read voltage is the target valley voltage; or, adjust the initial target read voltage at least once, and obtain the first result corresponding to the adjusted target read voltage after each adjustment; determine the target valley voltage based on the first result corresponding to the adjusted target read voltage satisfying the preset condition; obtain the predicted valley voltage of the second stage based on the determined target valley voltage of the first stage; and control the memory device to perform a second read operation on at least one codeword based on the determined target valley voltage of the first stage and the predicted valley voltage of the second stage, and perform a second error correction decoding on the second read result of the second read operation.

[0234] In some embodiments, each page of the multiple pages includes multiple second stages; the control unit is configured to: obtain the predicted valley voltage of the second stage with the largest read voltage among the multiple second stages of each page based on the predicted valley voltage of the first stage / the target valley voltage of the first stage; and sequentially obtain the predicted valley voltage of the second stage with the larger read voltage among the multiple second stages of each page based on the predicted valley voltage of the second stage with the larger read voltage, until the predicted valley voltage of each second stage of each page is obtained.

[0235] In some embodiments, the control unit is configured to obtain the predicted valley voltage of the second order based on the predicted valley voltage of the first order / the target valley voltage of the first order and the first mapping function, and the first mapping function is used to characterize the relationship between the predicted valley voltage of the first order / the target valley voltage of the first order and the predicted valley voltage of the second order.

[0236] In some embodiments, the control unit is configured to: in the process of adjusting the initial target read voltage at least once, use the initial target read voltage as a reference value; starting from the reference value, adjust in two opposite directions with a step size smaller than a first preset step size, and in the process of adjusting in each direction, perform an upward trend statistics based on the first result corresponding to the read voltage after the next adjustment being greater than the first result corresponding to the read voltage after the previous adjustment, and determine the first voltage boundary and the second voltage boundary using the total number of statistics greater than or equal to a preset number; in the process of adjusting in two directions, if the first result corresponding to the target read voltage after one adjustment is lower than the first threshold, or the smallest first result among the multiple first results corresponding to the target read voltage after multiple adjustments is used as the reference value, when the number of the remaining multiple first results whose difference from the reference value is less than the second threshold is greater than the preset number, stop the adjustment and use the target read voltage corresponding to the smallest first result among the multiple first results as the target valley voltage.

[0237] In some embodiments, the control unit is configured as follows: during the adjustment process in two directions, the adjusted target read voltages corresponding to the total statistical number of times being equal to the preset number are respectively used as the first voltage boundary and the second voltage boundary; during the adjustment process in two directions, if the first voltage boundary and the second voltage boundary have been determined, the target read voltage adjusted for the last time is the average value of the first voltage boundary and the second voltage boundary; the read voltage corresponding to the smallest first result among the multiple first results corresponding to all the adjusted target read voltages is used as the target valley voltage.

[0238] In some embodiments, the control unit is configured to: control the memory device to output a corresponding read result based on the success of the first error correction decoding or the success of the second error correction decoding; and determine error correction failure based on the failure of the second error correction decoding.

[0239] In some embodiments, the control unit is configured to: obtain the predicted valley voltage of the first stage based on the first result corresponding to the target read voltage of the first stage, the order number of the first stage, and the second mapping function; the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage, the order number of each stage and the predicted valley voltage.

[0240] On the third aspect, in the memory controller provided in the embodiment of the present application, the first result (the size of the first result can be several bytes) is transmitted without transmitting at least one codeword (for example, the size of the codeword can be 4KB), and the amount of data transmitted between the memory device and the memory controller is reduced; the process of obtaining the first result converges inside the memory device, does not occupy the space of the memory controller, and has a low degree of dependence on the memory controller; compared with the memory device, the process of obtaining the predicted valley voltage / target valley voltage based on the first result in the memory controller is more efficient; the transmission time of the input and output ports of the memory device and / or the time of the error correction decoding operation of the memory controller are reduced, the iteration time of the error correction decoding algorithm of the memory controller is saved, and the error correction decoding speed is faster; it is suitable for MLC, TLC or QLC type memory systems.

[0241] In a fourth aspect, an embodiment of the present application provides an operating method for a memory device, the operating method comprising: obtaining a predicted valley voltage of the first stage according to a first result corresponding to a target read voltage of the first stage; the first result includes the number of bits flipped in two read results at the first read voltage and the second voltage of at least one codeword formed by a preset number of memory cells in the memory device; the difference between the first read voltage and the second read voltage is less than the preset voltage; the number of storage bits of the memory cell is multiple bits, and the multiple storage bits correspond to multiple pages respectively; at least some pages correspond to multiple stages, the multiple stages include a first stage and a second stage, and the read voltage of the second stage is less than the read voltage of the first stage; obtaining a predicted valley voltage of the second stage according to the predicted valley voltage of the first stage; and performing a first read operation on at least one codeword using the predicted valley voltage of the first stage and the predicted valley voltage of the second stage.

[0242] In some specific embodiments, the operating method includes: using the predicted valley voltage of the first stage and the predicted valley voltage of the second stage as the initial target read voltage; obtaining a first result corresponding to the initial target read voltage; determining that the initial target read voltage is the target valley voltage based on the first result corresponding to the initial target read voltage satisfying a preset condition; or, adjusting the initial target read voltage at least once, and obtaining the first result corresponding to the adjusted target read voltage after each adjustment; determining that the adjusted target read voltage is the target valley voltage based on the first result corresponding to the adjusted target read voltage satisfying the preset condition; and performing a second read operation on at least one codeword based on the target valley voltage.

[0243] In some specific embodiments, the operating method includes: taking the predicted valley voltage of the first stage as the initial target read voltage, obtaining a first result corresponding to the initial target read voltage; determining that the initial read voltage is the target valley voltage based on the first result corresponding to the initial read voltage satisfying a preset condition; or, adjusting the initial target read voltage at least once, and obtaining the first result corresponding to the adjusted target read voltage after each adjustment; determining the target valley voltage based on the first result corresponding to the adjusted target read voltage satisfying the preset condition; obtaining the predicted valley voltage of the second stage based on the determined target valley voltage of the first stage; and performing a second read operation on at least one codeword based on the determined target valley voltage of the first stage and the predicted valley voltage of the second stage.

[0244] In some specific embodiments, the operating method includes: obtaining the predicted valley voltage of the second stage with the largest read voltage among the multiple second stages of each page based on the predicted valley voltage of the first stage / the target valley voltage of the first stage; and sequentially obtaining the predicted valley voltages of the second stages with smaller read voltages adjacent to the second stage with larger read voltage among the multiple second stages of each page, until the predicted valley voltage of each second stage of each page is obtained; wherein each page in the multiple pages includes multiple second stages.

[0245] In some specific embodiments, the operating method includes: obtaining the predicted valley voltage of the second order based on the predicted valley voltage of the first order / the target valley voltage of the first order and a first mapping function, and the first mapping function is used to characterize the relationship between the predicted valley voltage of the first order / the target valley voltage of the first order and the predicted valley voltage of the second order.

[0246] In some specific embodiments, the operating method includes: in the process of adjusting the initial target read voltage at least once, using the initial target read voltage as a reference value; starting from the reference value, adjusting in two opposite directions with a step size smaller than a first preset step size, and in the process of adjusting in each direction, performing an upward trend statistics based on the first result corresponding to the read voltage after the next adjustment being greater than the first result corresponding to the read voltage after the previous adjustment, and determining the first voltage boundary and the second voltage boundary using a total statistical number greater than or equal to a preset number; in the process of adjusting in two directions, if the first result corresponding to the target read voltage after one adjustment is lower than the first threshold, or the smallest first result among multiple first results corresponding to the target read voltage after multiple adjustments is used as the reference value, when the number of the remaining multiple first results whose difference from the reference value is smaller than the second threshold is greater than the preset number, stopping the adjustment and using the target read voltage corresponding to the smallest first result among the multiple first results as the target valley voltage.

[0247] In some specific embodiments, the operating method includes: in the process of adjusting in two directions, the adjusted target read voltages corresponding to the total statistical number equal to the preset number are used as the first voltage boundary and the second voltage boundary respectively; in the process of adjusting in two directions, if the first voltage boundary and the second voltage boundary have been determined, the target read voltage adjusted for the last time is the average value of the first voltage boundary and the second voltage boundary; and the read voltage corresponding to the smallest first result among multiple first results corresponding to all adjusted target read voltages is used as the target valley voltage.

[0248] In some specific embodiments, the operating method includes: obtaining the predicted valley voltage of the first stage based on the first result corresponding to the target read voltage of the first stage, the order number of the first stage, and the second mapping function; the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage, the order number of each stage and the predicted valley voltage.

[0249] In some specific embodiments, the operating method includes: reading the stored data of at least one codeword at a first read voltage to obtain a second result; reading the stored data of at least one codeword at a second read voltage to obtain a third result; performing a logical operation on the second result and the third result to obtain a fourth result; and counting the number of bits in the fourth result that represent the flipping of the third result compared to the second result to obtain the first result.

[0250] In a fifth aspect, an embodiment of the present application provides an operating method for a memory system, the operating method comprising: a memory controller in the memory system sends a first instruction, the first instruction instructing to obtain information representing a target valley voltage of multiple stages; a memory device in the memory system receives the first instruction, obtains information representing a predicted valley voltage of multiple stages according to any one of the operating methods for a memory device provided in the fourth aspect, and sends the information representing the predicted valley voltage of multiple stages to the memory controller; the memory controller uses the information representing the predicted valley voltage of multiple stages to control the memory device to perform a first read operation, and performs a first error correction decoding operation on a first read result of the first read operation.

[0251] In some specific embodiments, a method for operating a memory device includes: obtaining a predicted valley voltage of the first stage based on a first result corresponding to a target read voltage of the first stage; the first result includes the number of bits flipped in two read results at the first read voltage and the second voltage of at least one codeword formed by a preset number of memory cells in the memory device; the difference between the first read voltage and the second read voltage is less than a preset voltage; the number of storage bits of the memory cell is multiple bits, and the multiple storage bits correspond to multiple pages respectively; at least some pages correspond to multiple stages, the multiple stages include a first stage and a second stage, and the read voltage of the second stage is less than the read voltage of the first stage; obtaining a predicted valley voltage of the second stage based on the predicted valley voltage of the first stage; and performing a first read operation on at least one codeword using the predicted valley voltage of the first stage and the predicted valley voltage of the second stage.

[0252] In a sixth aspect, an embodiment of the present application provides an operating method for a memory controller, the operating method comprising: obtaining a predicted valley voltage of the first stage according to a first result corresponding to a target read voltage of the first stage; the first result comprises the number of bits flipped in two read results under the first read voltage and the second read voltage of at least one codeword formed by a preset number of storage cells in at least one memory device coupled to the memory controller; the difference between the first read voltage and the second read voltage is less than the preset voltage; the number of storage bits of the storage cell is multiple bits, and the multiple storage bits correspond to multiple pages respectively; at least part of the pages correspond to multiple stages, and the multiple stages include a first stage and a second stage, and the read voltage of the second stage is less than the read voltage of the first stage; obtaining a predicted valley voltage of the second stage according to the predicted valley voltage of the first stage; and controlling the memory device to perform a first read operation using the predicted valley voltage of the first stage and the predicted valley voltage of the second stage, and performing a first error correction decoding on the first read result of the first read operation.

[0253] In some embodiments, the operating method includes: based on the failure of the first error correction decoding, using the predicted valley voltage of the first stage and the predicted valley voltage of the second stage as the initial target read voltage; obtaining a first result corresponding to the initial target read voltage; determining that the initial target read voltage is the target valley voltage based on the first result corresponding to the initial target read voltage satisfying a preset condition; or, adjusting the initial target read voltage at least once, and obtaining the first result corresponding to the adjusted target read voltage after each adjustment; determining that the adjusted target read voltage is the target valley voltage based on the first result corresponding to the adjusted target read voltage satisfying a preset condition; controlling the memory device to perform a second read operation on at least one codeword based on the target valley voltage, and performing a second error correction decoding on a second read result of the second read operation.

[0254] In some embodiments, the operating method includes: based on the failure of the first error correction decoding, using the predicted valley voltage of the first stage as the initial target read voltage, obtaining a first result of the initial target read voltage; determining that the initial read voltage is the target valley voltage based on the first result corresponding to the initial read voltage satisfying a preset condition; or, adjusting the initial target read voltage at least once, and obtaining the first result corresponding to the adjusted target read voltage after each adjustment; determining the target valley voltage based on the first result corresponding to the adjusted target read voltage satisfying the preset condition; obtaining the predicted valley voltage of the second stage based on the determined target valley voltage of the first stage; and controlling the memory device to perform a second read operation on at least one codeword based on the determined target valley voltage of the first stage and the predicted valley voltage of the second stage, and performing a second error correction decoding on the second read result of the second read operation.

[0255] In some embodiments, the operating method includes: obtaining the predicted valley voltage of the second stage with the largest read voltage among the multiple second stages of each page based on the predicted valley voltage of the first stage / the target valley voltage of the first stage; and sequentially obtaining the predicted valley voltage of the second stage with the larger read voltage among the multiple second stages of each page based on the predicted valley voltage of the second stage with the larger read voltage, until the predicted valley voltage of each second stage of each page is obtained; wherein each page in the multiple pages includes multiple second stages.

[0256] In some embodiments, the operating method includes: obtaining the predicted valley voltage of the second order based on the predicted valley voltage of the first order / the target valley voltage of the first order and a first mapping function, and the first mapping function is used to characterize the relationship between the predicted valley voltage of the first order / the target valley voltage of the first order and the predicted valley voltage of the second order.

[0257] In some embodiments, the operating method includes: in the process of adjusting the initial target read voltage at least once, using the initial target read voltage as a reference value; starting from the reference value, adjusting in two opposite directions with a step size smaller than a first preset step size, and in the process of adjusting in each direction, performing an upward trend statistics based on the first result corresponding to the read voltage after the next adjustment being greater than the first result corresponding to the read voltage after the previous adjustment, and determining the first voltage boundary and the second voltage boundary using the total number of statistics greater than or equal to a preset number; in the process of adjusting in two directions, if the first result corresponding to the target read voltage after one adjustment is lower than the first threshold, or the smallest first result among the multiple first results corresponding to the target read voltage after multiple adjustments is used as the reference value, when the number of the remaining multiple first results whose difference with the reference value is smaller than the second threshold is greater than the preset number, stopping the adjustment and using the target read voltage corresponding to the smallest first result among the multiple first results as the target valley voltage.

[0258] In some embodiments, the operating method includes: in the process of adjusting in two directions, the adjusted target read voltages corresponding to the total statistical number equal to the preset number are respectively used as the first voltage boundary and the second voltage boundary; in the process of adjusting in two directions, if the first voltage boundary and the second voltage boundary have been determined, the target read voltage adjusted for the last time is the average value of the first voltage boundary and the second voltage boundary; the read voltage corresponding to the smallest first result among multiple first results corresponding to all the adjusted target read voltages is used as the target valley voltage.

[0259] In some embodiments, the operating method includes: controlling the memory device to output a corresponding read result based on the success of the first error correction decoding or the success of the second error correction decoding; and determining error correction failure based on the failure of the second error correction decoding.

[0260] In some embodiments, the operating method includes: obtaining the predicted valley voltage of the first stage based on the first result corresponding to the target read voltage of the first stage, the order number of the first stage, and the second mapping function; the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage, the order number of each stage and the predicted valley voltage.

[0261] FIG14 is a flowchart of a method for operating a memory device according to an embodiment of the present application. The detailed process of determining the target valley voltage will be described in detail below with reference to FIG14. It should be noted that, herein and hereinafter, the target valley voltage refers to the voltage used to perform a read operation on the data to be read.

[0262] In step S101, the target valley voltage acquisition procedure is triggered, and the target valley voltage acquisition process is started. Next, step S102 is executed.

[0263] As previously mentioned, since the memory cell has multiple storage bits, the multiple storage bits correspond to multiple pages, and at least one page corresponds to multiple levels. When determining the target valley voltage, the target valley voltage for each level of the at least one level of read voltage corresponding to each of the multiple pages is determined sequentially. In step S103, one level is selected from the multiple levels corresponding to a page as the target level, and the target valley voltage corresponding to the target level read voltage is first determined. For example, using TLC as an example, the target valley voltages for the first level read voltage L1 and the fifth level read voltage L5 corresponding to the next page are first determined. Either L1 or L5 can be selected as the target level. After the target level is determined, step S103 is executed.

[0264] In step S103, the main task is to determine the type of the target level. Here, the target level can be divided into two categories, the first level (also called high level) and the second level (also called low level), wherein the read voltage of the first level is greater than the read voltage of the second level. For example, still taking the lower page of TLC as an example, L5 is the first level and L1 is the second level. If L1 is selected as the target level in step S103, the target level is the second level, that is, the low level; if L5 is selected as the target level in step S104, the target level is the first level, that is, the high level. According to the target level being the low level, execute step S104; according to the target level being the high level, execute step S106.

[0265] In step S104, a predicted valley voltage is obtained. Here, the predicted valley voltage is obtained by deriving the predicted valley voltage corresponding to the lower order based on the target valley voltage corresponding to the higher order and a related mapping function. Here and below, the related mapping function may be obtained by fitting a large number of experimental results before the memory device leaves the factory and stored in the memory device. Next, step S105 is executed.

[0266] In step S105, it is determined whether the two-step prediction is successful. Here, the so-called two-step prediction may include a first prediction and a second prediction. The first prediction is to obtain a high-order predicted valley voltage. Specifically, the high-order predicted valley voltage is obtained based on the first result corresponding to the target read voltage (default read voltage), the order of the high-order, and the fourth mapping function. The second prediction is to obtain a low-order predicted valley voltage. Specifically, the low-order predicted valley voltage is obtained based on the high-order predicted valley voltage, the order of the low-order, and the third mapping function. After the two-step prediction, the predicted valley voltage is not confirmed. Hard decoding is directly performed using the high-order predicted valley voltage and the low-order predicted valley voltage. If the hard decoding is successful, the two-step prediction is successful. At this time, the search for the target valley voltage is stopped and step S121 is executed. If the hard decoding fails, the two-step prediction fails. At this time, the point corresponding to the predicted valley voltage is used as the near-valley point for the subsequent iteration, and step S107 is continued.

[0267] It should be noted that if the hard decoding fails, it means that the two-step prediction is unsuccessful. At this time, it is necessary to determine the target valley voltage through searching or also called looping (or iteration). Therefore, when the two-step prediction is unsuccessful, the loop process will be entered. After the two-step prediction is unsuccessful, the search process can be directly executed from the beginning of the loop, that is, jump from step S105 to S107.

[0268] If the target level is high, a search or loop is performed to determine the target valley voltage for the high level. In step S106, a default read voltage is used as the target read voltage. Here, the target read voltage can serve as the initial value for subsequent searches or loops. In some implementations, the default read voltage can be the read voltage when the threshold voltage of the memory cell has not shifted, such as the read voltage corresponding to a write operation, in which case the corresponding offset value is 0 DAC. Step S107 is executed after step S106.

[0269] It should be noted that here and below, the conversion relationship between DAC and the aforementioned mv is 1DAC=10mv.

[0270] In step S107, the target valley voltage is determined by searching or looping. After step S107, step S108 is executed.

[0271] For the first execution loop, in step S108, a first result at the target read voltage is obtained. It is understood that for subsequent execution loops, in step S108, a first result at an adjusted target read voltage is obtained. After step S108, step S109 is executed.

[0272] In step S109, a first threshold value TH1 is determined or adjusted based on the first result at the target read voltage. It is understood that, during a read operation, the further the threshold voltage of a memory cell deviates from the threshold voltage during a write operation, the larger the first result read using the target read voltage will generally be. Based on this, the specific value of the first result at the default read voltage can be used to determine the first threshold value TH1. The first threshold value TH1 is used to characterize the change (increase) in the target valley voltage caused by the memory cell threshold voltage deviation. Step S110 is executed after step S109.

[0273] It should be noted that step S109 is mainly for the first execution of the loop process, and can be skipped for subsequent execution of the loop process.

[0274] In step S110, a predicted valley voltage is obtained and a determination is made as to whether the predicted valley voltage is less than the aforementioned first threshold TH1. Based on the first result corresponding to the previously adjusted target read voltage and a related mapping function (such as the aforementioned second mapping function), a predicted valley voltage after the next adjustment is obtained and the obtained predicted valley voltage is compared with the first threshold TH1. If the determination result in step S110 is negative, it indicates that the predicted valley voltage obtained at this time is greater than or equal to the first threshold TH1. The loop continues with step S108, adjusting the target read voltage and re-obtaining the predicted valley voltage. Each time the predicted valley voltage is re-obtained, a comparison is performed against the first threshold TH1 until the obtained predicted read voltage is less than the first threshold TH1. In other words, the prediction is iterated using the aforementioned prediction formula or related mapping function until the obtained predicted read voltage is less than the first threshold TH1. If the determination result in step S110 is positive, it indicates that the predicted valley voltage obtained at this time is less than the first threshold TH1, and the process proceeds to the next step S111.

[0275] In step S111, an inflection point is found. Here, the target read voltage after each adjustment is used as the horizontal coordinate, and the first result corresponding to the corresponding adjusted target read voltage is used as the vertical coordinate, and the horizontal and vertical coordinates will form a point. The inflection point can be understood as a point relatively close to the bottom of the valley. In some embodiments, it is possible to start from the near-valley point with a coarser step size (first step size), and search to the left and right boundaries respectively until the left and right boundaries are reached, and the point corresponding to the minimum first result in the search process is used as the inflection point. Here, the inflection point is a point that is closer to the bottom of the valley than the near-valley point. The point that is less than the first threshold in the aforementioned step can be used as the near-valley point. For example, the near-valley point can be the point that is less than the first threshold that appears for the first time in the aforementioned step. The first step size can be a larger step size. In some embodiments, the first step size can be 5DAC-15DAC. Exemplarily, the first step size can be 5DAC, 10DAC or 15DAC. Step S112 is performed after step S111.

[0276] In step S112, it is determined whether an inflection point has been found. If no inflection point has been found, the search continues, and step S111 is continued until an inflection point is found. After the inflection point is found, step S113 is executed.

[0277] In step S113 and step S114, the search can be performed starting from the near-valley point with a finer step size (second step size) to the left boundary and the right boundary respectively until the left boundary and the right boundary are reached or the statistics of the upward trend exceed the preset number of times. Here, when the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, a statistics of the upward trend is performed. In some embodiments, the preset number of times is 3-7 times. Exemplarily, the preset number of times can be 3, 5 or 7 times. It should be noted that the positions of step S113 and step S114 can be interchanged. The second step size can be a smaller step size. In some embodiments, the second step size can be 2DAC-4DAC. Exemplarily, the second step size can be 2DAC, 3DAC or 4DAC.

[0278] When the searches in step S113 and step S114 satisfy the aforementioned conditions (reaching the boundary or the statistics showing an upward trend exceed the preset number of times), step S115 is executed.

[0279] In step S115, the adjusted target read voltage corresponding to the minimum first result is used as the target valley voltage. After step S115, step S116 is executed.

[0280] In step S116, it is determined whether the target valley voltage is valid. The method for determining whether the target valley voltage is valid may be to read data using the target valley voltage and decode the read data via the memory controller. Successful decoding indicates whether the target valley voltage is valid. If the result of step S116 is yes, step S121 is executed; if the result of step S116 is no, step S117 is executed.

[0281] In step S117, it is determined whether the loop has ended. If the determination result of step S117 is yes, step S119 is executed; if the determination result of step S117 is no, step S118 is executed.

[0282] In step S118, the process enters the next loop and continues searching. Step S118 jumps to step S107.

[0283] In step S119, it is determined whether the target order is a high order. If the determination result of step S119 is yes, step S120 is executed; if the determination result of step S119 is no, step S121 is executed.

[0284] In step S120, the predicted valley voltage of the low-order is obtained based on the target valley voltage of the high-order. Here, the predicted valley voltage of the low-order can be obtained by using the target valley voltage of the high-order, the order of the low-order, and a related mapping function (such as the third mapping function described above). Step S121 is executed after step S120.

[0285] In step S121, it is determined whether the corresponding target valley voltages for all the read voltage levels included in the page have been determined. If the determination result in step S121 is yes, it means that the target valley voltages for all the read voltage levels included in the page have been determined, and step S123 can be executed. If the determination result in step S121 is no, it means that the target valley voltages for all the read voltage levels included in the page have not yet been determined, and step S122 can be executed.

[0286] In step S122, for the steps for which the target valley voltage has not been determined, the target valley voltage of each step is determined in sequence. Step S122 jumps to step S102.

[0287] In step S123 , the process of obtaining the target valley voltage is terminated. It should be noted that after step S123 , the target valley voltages corresponding to the read voltages of all steps of the next page can be determined.

[0288] FIG15 is a second flowchart of the operating method of the memory device provided in one embodiment of the present application. The detailed process of determining the target valley voltage will be described in detail below with reference to FIG15.

[0289] In step S201, the target valley voltage acquisition procedure is triggered, and the target valley voltage acquisition process is started. Next, step S202 is executed.

[0290] In step S202, in some embodiments, the read mode of the memory device is set to a single-level read mode, where the single-level read mode includes reading at least one bit of data stored in the memory cell using a single-level read voltage.

[0291] As previously mentioned, since the memory cell has multiple storage bits, the multiple storage bits correspond to multiple pages, and at least one page corresponds to multiple levels. When determining the target valley voltage, the target valley voltage of each level of the at least one level of read voltage corresponding to each page in the multiple pages is determined in sequence. In step S203, one level is selected from the multiple levels corresponding to a page as the target level, and the target valley voltage corresponding to the target level read voltage is first determined. For example, taking TLC as an example, the target valley voltages of the first level read voltage L1 and the fifth level read voltage L5 corresponding to the next page are first determined. Either L1 or L5 can be selected as the target level. After the target level is determined, step S204 is executed.

[0292] In step S204, the main task is to determine the type of the target order. Here, the target order can be divided into two categories, the first order (also called high order) and the second order (also called low order), wherein the read voltage of the first order is greater than the read voltage of the second order. For example, still taking the lower page of TLC as an example, L5 is the first order and L1 is the second order. If L1 is selected as the target order in step S203, the target order is the second order, that is, the low order; if L5 is selected as the target order in step S204, the target order is the first order, that is, the high order. According to the target order being the low order, execute step S205; according to the target order being the high order, execute step S207.

[0293] In step S205, a predicted valley voltage is obtained. Here, the predicted valley voltage is obtained by deriving the predicted valley voltage corresponding to the lower order based on the target valley voltage corresponding to the higher order and a related mapping function. Here and below, the related mapping function may be obtained by fitting a large number of experimental results before the memory device leaves the factory and stored in the memory device. Next, step S206 is executed.

[0294] In step S206, it is determined whether the two-step prediction is successful. Here, the so-called two-step prediction may include a first prediction and a second prediction. The first prediction is to obtain a high-order predicted valley voltage. Specifically, the high-order predicted valley voltage is obtained based on the first result corresponding to the target read voltage (default read voltage), the order of the high-order, and the fourth mapping function. The second prediction is to obtain a low-order predicted valley voltage. Specifically, the low-order predicted valley voltage is obtained based on the high-order predicted valley voltage, the order of the low-order, and the third mapping function. After the two-step prediction, the predicted valley voltage is not confirmed. Hard decoding is directly performed using the high-order predicted valley voltage and the low-order predicted valley voltage. If the hard decoding is successful, the two-step prediction is successful. At this time, the search for the target valley voltage is stopped and step S245 is executed. If the hard decoding fails, the two-step prediction fails. At this time, the point corresponding to the predicted valley voltage is used as the near-valley point for the subsequent iteration, and step S220 is continued. Step S220 will be described in detail in the subsequent description.

[0295] It should be noted that if the hard decoding fails, it means that the two-step prediction is unsuccessful. At this time, it is necessary to determine the target valley voltage through searching or also called looping (or iteration). Therefore, when the two-step prediction is unsuccessful, the loop process will be entered. After the two-step prediction is unsuccessful, the search process can be directly executed from the beginning of the loop, that is, jumping from step S206 to S208; or the point corresponding to the predicted valley voltage can be directly used as the near-valley point of the subsequent iteration, that is, jumping from step S206 (S219) to S220.

[0296] If the target level is high, a search or loop is performed to determine the target valley voltage for the high level. In step S207, a default read voltage is used as the target read voltage. Here, the target read voltage can serve as the initial value for subsequent searches or loops. In some implementations, the default read voltage can be the read voltage when the threshold voltage of the memory cell has not shifted, such as the read voltage corresponding to a write operation, in which case the corresponding offset value is 0 DAC. Step S208 is executed after step S207.

[0297] In step S208, the target valley voltage is determined by searching or looping. After step S208, step S209 is executed.

[0298] During the first execution of the loop, step S209 is to obtain the first result at the target read voltage. It is understood that during subsequent execution of the loop, step S209 is to obtain the first result at the adjusted target read voltage. Step S210 is executed after step S209.

[0299] In step S210, various parameters are determined or adjusted based on the first result under the target read voltage. Here, the various parameters may include at least a first threshold, a first boundary voltage (the position corresponding to the first boundary voltage is also called the left boundary) and a second boundary voltage (the position corresponding to the second boundary voltage is also called the right boundary). It is understandable that when performing a read operation, the further the threshold voltage of the memory cell shifts from the threshold voltage during writing, the larger the first result read using the target read voltage will generally be. Based on this, the specific value of the first result under the default read voltage can be used to confirm the first threshold value. The first threshold value is used to characterize the change (elevation) in the target valley voltage caused by the shift of the threshold voltage of the memory cell. Here, the initial first boundary voltage and the initial second boundary voltage can be set based on empirical values, such as initially setting an initial first boundary voltage and an initial second boundary voltage with a relatively large range. Then, based on the first result under the target read voltage, the initial first boundary voltage and the initial second boundary voltage are adjusted, such as narrowing the range of the first boundary voltage and the second boundary voltage to obtain the first boundary voltage and the second boundary voltage. Step S211 is performed after step S10.

[0300] It should be noted that step S210 is mainly for the first execution cycle process, and can be skipped for subsequent execution cycles.

[0301] During the first execution of the loop, step S211 determines whether the first result at the target read voltage is less than the first threshold. It is understood that during subsequent executions of the loop, step S211 determines whether the first result at the adjusted target read voltage is less than the first threshold. If the determination result in step S211 is yes, it can be assumed that the first result corresponding to the adjusted target read voltage basically meets the requirements for read data decoding. The process then jumps to step S242, terminating the loop and outputting the corresponding target valley voltage. If the determination result in step S211 is no, the loop continues to step S212.

[0302] In step S212, it is determined whether the target memory block is a partially written memory block. Here, the target memory block is the memory block where at least one codeword to be read is located. A partially written memory block includes a memory block that has both a programmed state and an erased state. If the result of step S212 is yes, step S213 is executed; if the result of step S212 is no, step S214 is executed.

[0303] It should be noted that step S212 is mainly for the first execution of the loop process, and for subsequent execution of the loop process, this step can be skipped. After skipping this step, step S214 is continued.

[0304] In step S213, considering that the offset of the threshold voltage of the storage cell in the underfilled storage block is more complex than the offset of the threshold voltage of the storage cell in the filled storage block (the filled storage block can be understood as a storage block with the same application scenario as the underfilled storage block and a write time difference less than a preset time length), the offset of the threshold voltage of the storage cell in the underfilled storage block is also related to the position of the first blank physical page in the underfilled storage block (the first blank physical page can be understood as the physical page in which the first data state appearing in the underfilled storage block is all erased according to the programming order) and the position of the physical page to be read (the physical page where the at least one codeword to be read is located). Based on this, the predicted valley voltage can be obtained based on the first offset corresponding to the filled storage block, the second offset corresponding to the position of the first blank physical page in the underfilled storage block, and the third offset corresponding to the position of the physical page to be read, and then the process proceeds to step S214. It is understandable that the obtained predicted valley voltage is more targeted than blindly adjusting the target read voltage, and can shorten the search time to a certain extent and determine the target valley voltage more quickly.

[0305] In step S214, determine whether a near-valley point is found. Here, the target read voltage after each adjustment is used as the horizontal coordinate, and the first result corresponding to the corresponding adjusted target read voltage is used as the vertical coordinate, and the horizontal and vertical coordinates will form a point. In the process of adjusting the target read voltage multiple times, the point corresponding to the multiple first results corresponding to the multiple adjusted target read voltages that is first less than the near-valley threshold can be used as the near-valley point. The near-valley threshold is used to characterize the maximum value of the first result corresponding to the target valley bottom voltage. It should be noted that there is a difference between the near-valley threshold and the aforementioned first threshold. When the first result is less than the near-valley threshold, it means that a more refined search can be carried out next; when the first result is less than the first threshold, it means that the search can be stopped next. When the judgment result of step S214 is yes, execute step S219; when the judgment result of step S214 is no, execute step S215.

[0306] If no near-valley point is found in step S215, the process proceeds to step S215, where the predicted read voltage after the next adjustment is obtained based on the first result corresponding to the target read voltage after the previous adjustment and the related mapping function (such as the aforementioned second mapping function). That is, the prediction is iterated using the aforementioned prediction formula or mapping function. After step S215, step S216 is executed.

[0307] In step S216, a determination is made as to whether the next adjusted predicted read voltage hits a boundary. The boundary here can be either the left boundary or the right boundary, and hitting the boundary can be understood as being exactly on the boundary or crossing the boundary. If the determination result in step S216 is yes, step S217 is executed; if the determination result in step S216 is no, step S218 is executed.

[0308] In step S217, the adjustment direction is changed. There are two adjustment directions for adjusting the target read voltage: positive (rightward) and negative (leftward). Adjusting the offset direction can be understood as: previously adjusting to the right, then adjusting to the left after hitting the right boundary; or previously adjusting to the left, then adjusting to the right after hitting the left boundary. After step S217, step S218 is executed.

[0309] In step S218, the first result of the adjusted target read voltage is obtained. After step S218, step S214 is executed. That is, after each target voltage adjustment and the corresponding first result is obtained, a determination is made as to whether the latest adjustment point is a near-valley point. One or more adjustments are performed until a near-valley point is found.

[0310] It should be noted that if the next cycle is entered after the step of finding the near valley point because the subsequent conditions are not met, steps S215 to S218 can be skipped.

[0311] In step S219, you can refer to the description in step S206. When the two-step prediction is unsuccessful, the loop process will be entered. After the two-step prediction is unsuccessful, the point corresponding to the predicted valley bottom voltage can be directly used as the near-valley point of the subsequent iteration, that is, jump from step S219 to S220.

[0312] In step S220, it is determined whether the predicted valley voltage at the current point (the latest adjusted target read voltage) is valid. In some embodiments, the predicted valley voltage can be determined to be valid by the first result corresponding to the latest adjusted target read voltage being less than the first threshold. It should be noted that although in step S211, when the first result under the (adjusted) target read voltage is not less than the first threshold, S212 and subsequent steps are entered, but before the judgment result of step S214 is yes, the target read voltage is adjusted at least once, so the new adjusted target read voltage may be less than the first threshold at this time. When the judgment result of step S220 is yes, step S224 is executed; when the judgment result of step S220 is no, step S221 is executed.

[0313] In step S221, a determination is made as to whether the first result fbc of the current point is greater than the fbc of the previous point. After finding the near-valley point, a rough search for an inflection point begins to the left. Generally, the magnitude of fbc decreases and then increases. When the first result fbc of the current point is greater than the fbc of the previous point, this indicates that fbc will increase further during the subsequent leftward adjustment, and the previous point was a relatively small point. In this case, the previous point is set as the inflection point. In some embodiments, the step size used for the rough search can be a larger step size, for example, 5DAC-15DAC, or more specifically, 5DAC, 10DAC, or 15DAC. Based on this, if the determination result of step S221 is yes, step S223 is executed; if the determination result of step S221 is no, step S222 is executed.

[0314] In step S222, a rough search is performed to the left starting from the point near the valley, and each search is compared with the fbc of the previous search until a point is found where the value stops decreasing and starts increasing. Once this point is found, step S222 is completed and the process goes to step S223.

[0315] In step S223, the previous point (i.e., the point where the decrease stops and the increase begins) is set as the inflection point, and a fine search is performed to the right starting from the inflection point. In some embodiments, the step size used in the fine search can be a smaller step size, for example, 1DAC-4DAC, more specifically, 2DAC or 3DAC. After step S223, step S225 is executed.

[0316] In step S224, the current point is set as the inflection point, and a fine search is started from the inflection point to the right. In some embodiments, the step size used in the fine search can refer to step S223. After step S224, step S225 is executed.

[0317] In step S225 , it is determined whether the target read voltage is adjusted to the left. If the determination result of step S225 is yes, step S229 is executed; if the determination result of step S225 is no, step S226 is executed.

[0318] In step S226, the target read voltage is adjusted rightward. During the adjustment, a determination is made as to whether the right boundary is hit or whether the rise count (also known as an upward trend count, where an upward trend count is performed when the first result corresponding to the next adjusted target read voltage is greater than the first result corresponding to the previous adjusted target read voltage) exceeds a preset number TH2. In some embodiments, the preset number is 3-7 times, and illustratively, the preset number can be 3, 5, or 7 times. If the determination in step S226 is yes, step S228 is executed; if the determination in step S226 is no, step S227 is executed.

[0319] In step S227, if the right boundary is not hit or the lift count does not exceed the preset number TH2, the search continues to the right boundary, and a judgment is made after each search until the right boundary is hit or the lift count exceeds the preset number TH2. In other words, when step S227 is completed, jump to step S228.

[0320] In step S228 , the target read voltage starts to be adjusted leftward.

[0321] In step S229, while adjusting the target read voltage to the left, it is determined whether the left boundary or lift count is hit. The lift count here can be understood with reference to the aforementioned step S226. The thresholds for the left and right lift counts are generally set to the same value. If the judgment result of step S229 is yes, step S231 is executed; if the judgment result of step S229 is no, step S230 is executed.

[0322] In step S230, if the left boundary is not hit or the lift count does not exceed the preset number TH2, the search continues to the left boundary, and a judgment is made after each search until the left boundary is hit or the lift count exceeds the preset number TH2. That is, when step S230 is completed, jump to step S231.

[0323] In step S231, a determination is made as to whether the most recent first result is the minimum. Here, the most recent first result refers to whether the first result at the adjusted target read voltage after the last target read voltage adjustment is the minimum. At this point, it is necessary to traverse all search points in at least this loop to find the adjusted target read voltage corresponding to the point with the minimum first result. If the determination result in step S231 is yes, step S233 is executed; if the determination result in step S231 is no, step S232 is executed.

[0324] In step S232, the latest first result is updated using the found minimum first result. Step S233 is executed after step S232.

[0325] In step S233, a determination is made as to whether the near-valley count exceeds a preset number TH3. Here, the smallest first result among the multiple first results corresponding to the target read voltage after multiple adjustments is used as a reference value. If the number of remaining first results whose difference from the reference value is less than a second threshold (equivalent to the preset difference) is greater than a preset number, the search is stopped and the target read voltage corresponding to the smallest first result among the multiple first results is used as the target valley voltage. In some embodiments, the second threshold (equivalent to the preset difference) and the preset number can be set together based on actual conditions. Generally, a slightly larger second threshold (equivalent to the preset difference) results in a relatively larger preset number; and a slightly smaller second threshold (equivalent to the preset difference) results in a relatively smaller preset number. If the determination result in step S233 is yes, the search is stopped and step S237 is executed. If the determination result in step S233 is no, the process proceeds to the next determination step, step S234.

[0326] In step S234, a determination is made as to whether the repeated valley count exceeds a preset count TH4. Here, during multiple adjustments to the target read voltage, different adjustment methods may be employed. If the target read voltages corresponding to the different adjustment methods exceeding the preset count are the same, and the first result corresponding to the same target read voltage is the minimum value among all first results, the same target read voltage is used as the target valley voltage. In some embodiments, the preset count is 2-4, and illustratively, the preset number of times may be 2, 3, or 4. If the determination result in step S234 is yes, the search is terminated and step S237 is executed. If the determination result in step S234 is no, the search proceeds to the next determination and step S235 is executed.

[0327] It should be noted that step S233 and step S234 belong to different judgment methods and their positions can be interchanged. In other words, the repeated valley count can be judged first, and then the approximate estimate can be judged when the repeated valley count does not meet the conditions. It is understandable that other judgments can also be performed here to determine whether the loop has ended.

[0328] In step S235, it is determined whether the loop has ended. If the determination result of step S235 is yes, step S237 is executed; if the determination result of step S235 is no, step S236 is executed.

[0329] In step S236, the process enters the next loop and continues searching. Step S236 jumps to step S209.

[0330] In step S237, the target step search is completed, and the adjusted target read voltage corresponding to the minimum first result is used as the target valley voltage. After step S237, step S238 is executed.

[0331] In step S238, it is determined whether the target order is a high order. If the determination result of step S238 is yes, step S239 is executed; if the determination result of step S238 is no, step S240 is executed.

[0332] In step S239, the predicted valley voltage of the low order is obtained based on the target valley voltage of the high order. Here, the predicted valley voltage of the low order can be obtained by using the target valley voltage of the high order, the order of the low order, and a related mapping function (such as the fourth mapping function described above). Step S240 is executed after step S239.

[0333] In step S240, it is determined whether the corresponding target valley voltages have been determined for all the read voltage levels included in the page. If the determination result in step S240 is yes, it means that the target valley voltages corresponding to all the read voltage levels included in the page have been determined, and step S242 can be executed. If the determination result in step S240 is no, it means that the target valley voltages corresponding to all the read voltage levels included in the page have not yet been determined, and step S241 can be executed.

[0334] In step S241, for the steps for which the target valley voltage has not been determined, the target valley voltage of each step is determined in sequence. Step S236 jumps to step S202.

[0335] In step S242 , the process of obtaining the target valley voltage is terminated. It should be noted that after step S242 , the target valley voltages corresponding to the read voltages of all steps of the next page can be determined.

[0336] It should be noted that the method disclosed in the embodiments of the present application can solve many problems existing in the reread operation, but it is not used to limit the application scenarios in the embodiments of the present application. The method disclosed in the embodiments of the present application is also applicable to conventional read operations.

[0337] Figure 16 is an exemplary timing diagram for starting a single-stage read mode operation provided by the present application. DQx can be represented as a data bus signal, and Cycle Type can further represent the type of the data bus signal.

[0338] As shown in FIG16 , the set function command may include, for example, a sub-command (e.g., EFh). Exemplarily, the memory device starts the single-level read mode upon receiving a sub-command EFh. In the single-level read mode, the memory device transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received sub-commands 00h and 30h. During the read time, the data DATA (e.g., Dn) corresponding to the page of the received address may be cached in the page buffer first, and then the data DATA may be read on demand. It should be noted that, in the above embodiment, when performing a reread operation, the data corresponding to a physical page (e.g., Dn) needs to be frequently transmitted (Din / Dout) between the memory device and the memory controller, and the transmission of the data takes a long time.

[0339] FIG17 is a timing diagram for determining a target valley voltage and performing a read operation according to an embodiment of the present application. As shown in FIG17 , a read command may include, for example, two sub-commands (e.g., 00h and 30h). Exemplarily, the memory device transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received sub-commands 00h and 30h. After the memory device receives the sub-command 30h, within the read time, the corresponding data DATA (e.g., Dn) in the page of the received address may be cached in the page buffer, and then the data DATA may be read on demand. In an exemplary embodiment, the memory device 104 transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received sub-commands 00h and 30h. After receiving subcommand 30h, memory device 104 receives subcommands EFh and xxh of the first / second instructions. Under the direction of the first / second instructions, memory device 104 obtains a first result corresponding to the codeword at the corresponding read voltage and sends the obtained first result to the memory controller. The memory controller determines a target valley voltage based on the multiple first results corresponding to the multiple different read voltages received from the memory device and performs a read operation on the data stored in the memory device based on the target valley voltage.

[0340] As shown in FIG17 , in some embodiments, the first instruction / second instruction includes subcommands 05 / 06h and E0h. During the process of determining the target valley voltage, subcommands 05 / 06h and E0h are executed at most twice. In an exemplary embodiment, each subcommand 05 / 06h and E0h means that a read operation is performed on at least one codeword of the control memory device, and an error correction decoding operation is performed on the result of the read operation. During the process of determining the target valley voltage, a read operation is performed at most twice, and thus, only two error correction decoding operations are performed at most. The minimum number of iterations (at most two) is required to decode at least one codeword, significantly improving decoding efficiency.

[0341] In some specific embodiments, the memory controller 106 is configured to: send a first instruction, the first instruction including sub-commands 05 / 06h and E0h, instructing the memory device to perform a first read operation; the memory device 104 is configured to: receive the first instruction, perform the first read operation based on the predicted valley voltage in the information representing the multi-level predicted valley voltage; and send the obtained information representing the first read result of the first read operation to the memory controller; the memory controller 106 is further configured to: perform a second error correction decoding operation on the first read result of the first read operation.

[0342] In some specific embodiments, the memory controller 106 is configured to: output a first read result based on the success of the first error correction decoding; or, based on the failure of the first error correction decoding, send a second instruction, the second instruction including subcommands 05 / 06h and E0h, instructing the memory device to perform a second read operation; the memory device 104 is configured to: receive the second instruction, perform a second read operation using the predicted valley voltage in the re-acquired information representing the predicted valley voltages of the multiple levels; and send the acquired information representing the second read result of the second read operation to the memory controller; and the memory controller 106 is further configured to: perform a second error correction decoding operation on the second read result of the second read operation. It should be noted that the second instruction provided in the embodiments of the present application is merely an example and should not unduly limit the scope of protection of the present application. In some embodiments, the data size of the first result is less than a preset data size threshold, for example, the data size of the first result ranges from 1 byte to 4 bytes. Therefore, in the process of determining the target valley voltage, the amount of data transmitted between the memory device and the memory controller is small and the speed is fast, which is conducive to improving the overall speed of the read operation.

[0343] Referring to Figure 18, Figure 18 is a schematic diagram of the composition structure of a storage medium provided in an embodiment of the present application. In a seventh aspect, an embodiment of the present application provides a storage medium, as shown in Figure 18, on which executable instructions are stored. When the executable instructions are executed by a processor, the steps of any of the operating methods provided in the fourth, fifth, and sixth aspects are implemented.

[0344] In some specific embodiments, the storage medium can be a memory such as Ferromagnetic Random Access Memory (FRAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Flash Memory, magnetic surface storage, an optical disc, or a Compact Disc Read-Only Memory (CD-ROM); it can also be various devices including one or any combination of the above memory devices.

[0345] In some embodiments, executable instructions may be in the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0346] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinating files (e.g., files storing one or more modules, subroutines, or code portions).

[0347] As an example, executable instructions may be deployed to be executed on one electronic device, or on multiple electronic devices located at one site, or on multiple electronic devices distributed across multiple sites and interconnected by a communication network.

[0348] In some specific embodiments, referring to Figure 18, Figure 18 is a schematic diagram of the composition structure of a storage medium provided in an embodiment of the present application; wherein, the storage medium includes a first storage medium corresponding to the memory device 104, a second storage medium corresponding to the memory controller 104, and a third storage medium corresponding to the memory system 102; when the executable instruction is executed by the memory device, the first storage medium can be used to implement the steps of the operating method of the memory device in the above embodiment of the present application; when the executable instruction is executed by the memory controller, the second storage medium can be used to implement the steps of the operating method of the memory controller in the above embodiment of the present application; when the executable instruction is executed by the memory system, the third storage medium can be used to implement the steps of the operating method of the memory system in the above embodiment of the present application.

[0349] In some specific embodiments, a method for operating a memory device includes: obtaining a predicted valley voltage of the first stage based on a first result corresponding to a target read voltage of the first stage; the first result includes the number of bits flipped in two read results at the first read voltage and the second read voltage of at least one codeword formed by a preset number of memory cells in the memory device; the difference between the first read voltage and the second read voltage is less than a preset voltage; the number of storage bits of the memory cell is multiple bits, and the multiple storage bits correspond to multiple pages respectively; at least some pages correspond to multiple stages, the multiple stages include a first stage and a second stage, and the read voltage of the second stage is less than the read voltage of the first stage; obtaining a predicted valley voltage of the second stage based on the predicted valley voltage of the first stage; and performing a first read operation on at least one codeword using the predicted valley voltage of the first stage and the predicted valley voltage of the second stage.

[0350] In some specific embodiments, the operating method of the memory system includes: a memory controller in the memory system sends a first instruction, the first instruction instructing to obtain information representing the target valley voltage of multiple levels; a memory device in the memory system receives the first instruction, obtains information representing the predicted valley voltage of multiple levels according to any one of the operating methods of the memory device provided in the fourth aspect, and sends the information representing the predicted valley voltage of multiple levels to the memory controller; the memory controller uses the information representing the predicted valley voltage of multiple levels to control the memory device to perform a first read operation, and performs a first error correction decoding operation on a first read result of the first read operation.

[0351] In some specific embodiments, an operating method of a memory controller includes: obtaining a predicted valley voltage of the first stage based on a first result corresponding to a target read voltage of the first stage; the first result includes the number of bits flipped in two read results under the first read voltage and the second read voltage of at least one codeword formed by a preset number of storage cells in at least one memory device coupled to the memory controller; the difference between the first read voltage and the second read voltage is less than a preset voltage; the number of storage bits of the storage cell is multiple bits, and the multiple storage bits correspond to multiple pages respectively; at least some pages correspond to multiple stages, the multiple stages include a first stage and a second stage, and the read voltage of the second stage is less than the read voltage of the first stage; obtaining a predicted valley voltage of the second stage based on the predicted valley voltage of the first stage; and using the predicted valley voltage of the first stage and the predicted valley voltage of the second stage to control the memory device to perform a first read operation, and performing a first error correction decoding on the first read result of the first read operation.

[0352] FIG19A shows a block-level iteration count for all pages in a memory cell array of a first exemplary memory system / memory device provided by an embodiment of the present application, using a memory system / memory device according to an embodiment of the present application; FIG19B shows a block-level iteration count for all pages in a memory cell array of a second exemplary memory system / memory device according to an embodiment of the present application. As shown in FIG19A and FIG19B , compared to an average number of iterations (understood as the number of iterations of the error correction decoding algorithm) of approximately 8.07 in the first exemplary memory system / memory device, an average number of iterations (understood as the number of iterations of the error correction decoding algorithm) of approximately 2.01 in the second exemplary memory system / memory device provided by an embodiment of the present application is approximately 2.01, which reduces the number of transmissions to the memory device input / output (I / O) port and / or the number of error correction decoding operations of the memory controller, thereby saving the number of iterations of the memory controller's error correction (Low-density parity-check code, LDPC code) decoding algorithm and making the error correction decoding faster.

[0353] In the memory device and its operating method, memory system and its operating method provided in the embodiments of the present application, a first result (the size of the first result can be several bytes) is transmitted without transmitting at least one codeword (for example, the size of the codeword can be 4KB), thereby reducing the amount of data transmitted by the memory device; the process of obtaining the first result is converged within the memory device, does not occupy the space of, for example, a memory controller, and has a low degree of dependence on, for example, the memory controller; the transmission time of the input and output ports of the memory device and / or the time of the error correction decoding operation of the memory controller are reduced, saving the iteration time of the error correction decoding algorithm of the memory controller, and the error correction decoding speed is faster; and it is suitable for MLC, TLC or QLC type memory devices / memory systems.

[0354] The memory device and operating method thereof, as well as the memory system and operating method thereof, provided in the embodiments of the present application, effectively avoid the time-consuming and incomplete scenario coverage issues associated with using a reread table. This reduces the space occupied by the reread table, allows for faster and more accurate identification of the target valley voltage, and effectively reduces the latency associated with determining the target valley voltage. Furthermore, performing a read operation at the obtained target valley voltage significantly increases the probability of correctly reading stored data, improving product reliability and user experience.

[0355] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0356] The above description is only a preferred embodiment of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made using the contents of the present application description and drawings under the inventive concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application. Industrial Applicability

[0357] The memory device and operating method thereof, as well as the memory system and operating method thereof, provided in the embodiments of the present application, effectively avoid the time-consuming and incomplete scenario coverage issues associated with using a reread table. This reduces the space occupied by the reread table, allows for faster and more accurate identification of the target valley voltage, and effectively reduces the latency associated with determining the target valley voltage. Furthermore, performing a read operation at the obtained target valley voltage significantly increases the probability of correctly reading stored data, improving product reliability and user experience.

Claims

1. A memory device comprising: A memory cell array includes memory cells having a plurality of storage bits, wherein a preset number of the memory cells form a codeword, and the plurality of storage bits correspond to a plurality of pages respectively; At least part of the page corresponds to multiple levels, the multiple levels including a first level and a second level, a read voltage of the second level being lower than a read voltage of the first level; A peripheral circuit is coupled to the memory cell array and is configured to: Obtaining a predicted valley voltage of the first stage based on a first result corresponding to a target read voltage of the first stage, wherein the first result includes a number of bits flipped in at least one of the codewords read at the first read voltage and at the second read voltage; and wherein a difference between the first read voltage and the second read voltage is less than a preset voltage; Obtaining the predicted valley bottom voltage of the second stage according to the predicted valley bottom voltage of the first stage; and A first read operation is performed on at least one of the codewords using the predicted valley voltage of the first stage and the predicted valley voltage of the second stage.

2. The memory device according to claim 1, wherein The peripheral circuit is configured as follows: Using the predicted valley voltage of the first stage and the predicted valley voltage of the second stage as initial target read voltages; Obtaining a first result corresponding to the initial target read voltage; According to the first result corresponding to the initial target read voltage meeting a preset condition, determining that the initial target read voltage is a target valley voltage; or, Adjusting the initial target read voltage at least once, and obtaining a first result corresponding to the adjusted target read voltage after each adjustment; According to the first result corresponding to the adjusted target read voltage meeting a preset condition, determining the adjusted target read voltage as a target valley voltage; A second read operation is performed on at least one of the codewords according to the target valley voltage.

3. The memory device according to claim 1, wherein The peripheral circuit is configured as follows: The predicted valley voltage of the first stage is used as the initial target reading voltage to obtain the initial a first result corresponding to a target read voltage; and determining that the initial read voltage is a target valley voltage based on the first result corresponding to the initial read voltage satisfying a preset condition; or, Adjusting the initial target read voltage at least once, and obtaining a first result corresponding to the adjusted target read voltage after each adjustment; Determining a target valley voltage based on that the first result corresponding to the adjusted target read voltage meets a preset condition; Obtaining a predicted valley voltage of the second stage according to the determined target valley voltage of the first stage; and A second read operation is performed on at least one of the codewords according to the determined target valley voltage of the first stage and the predicted valley voltage of the second stage.

4. The memory device according to claim 1 or 3, wherein: Each of the plurality of pages comprises a plurality of second stages; The peripheral circuit is configured as follows: Obtaining a predicted valley voltage of a second stage having a maximum read voltage among the plurality of second stages of each page according to the predicted valley voltage of the first stage of each page / the target valley voltage of the first stage; and The predicted valley bottom voltages of the second stages with larger read voltages among the multiple second stages of each page are sequentially obtained, and the predicted valley bottom voltages of the second stages with smaller read voltages adjacent to the second stages are obtained until the predicted valley bottom voltages of each second stage of each page are obtained.

5. The memory device according to claim 1 or 3, wherein: The peripheral circuit is configured as follows: The predicted valley voltage of the second order is obtained based on the predicted valley voltage of the first order / the target valley voltage of the first order and a first mapping function, and the first mapping function is used to characterize the relationship between the predicted valley voltage of the first order / the target valley voltage of the first order and the predicted valley voltage of the second order.

6. The memory device according to claim 2 or 3, wherein: The peripheral circuit is configured as follows: In a process of adjusting the initial target read voltage at least once, taking the initial target read voltage as a reference value; Starting from the reference value, the voltage is adjusted in two opposite directions with a step length smaller than the first preset step length. In the process of adjusting in each direction, the voltage corresponding to the read voltage after the next adjustment is adjusted. The first result of the read voltage is greater than the first result corresponding to the last adjusted read voltage, performing a statistical analysis showing an upward trend, and determining the first voltage boundary and the second voltage boundary using a total statistical number greater than or equal to a preset number; During the adjustment process in two directions, if the first result corresponding to the target read voltage after one adjustment is lower than the first threshold, or if the smallest first result among the multiple first results corresponding to the target read voltage after multiple adjustments is used as the reference value, and the number of the remaining multiple first results whose differences from the reference value are less than the second threshold is greater than a preset number, the adjustment is stopped and the target read voltage corresponding to the smallest first result among the multiple first results is used as the target valley voltage.

7. The memory device according to claim 6, wherein: The peripheral circuit is configured as follows: During the adjustment in two directions, the adjusted target read voltages corresponding to the total statistical number of times being equal to the preset number are used as the first voltage boundary and the second voltage boundary respectively; During the adjustment in two directions, if the first voltage boundary and the second voltage boundary have been determined, the target read voltage of the last adjustment is the average value of the first voltage boundary and the second voltage boundary; The read voltage corresponding to the smallest first result among the multiple first results corresponding to all the adjusted target read voltages is used as the target valley voltage.

8. The memory device according to claim 1, wherein The peripheral circuit is configured as follows: The predicted valley voltage of the first stage is obtained according to the first result corresponding to the target read voltage of the first stage, the order number of the first stage, and the second mapping function; the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage, the order number of each stage and the predicted valley voltage.

9. The memory device according to claim 1, wherein The peripheral circuit is configured as follows: Reading stored data of at least one of the codewords at the first read voltage to obtain a second result; reading stored data of at least one of the codewords at the second read voltage to obtain a third result; performing a logical operation on the second result and the third result to obtain a fourth result; The first result is obtained by counting the number of bits in the fourth result that represent that the third result is flipped compared with the second result.

10. The memory device according to claim 9, wherein The peripheral circuit includes: a first latch, a second latch, and a third latch; The first latch is configured to: store the second result; The second latch is configured to: store the third result; The third latch is configured to store the fourth result.

11. A memory system comprising: One or more memory devices according to any one of claims 1 to 10; as well as A memory controller is coupled to the memory device and controls the memory device.

12. The memory system according to claim 11, wherein: The memory controller is configured to: send a first instruction, wherein the first instruction instructs obtaining information representing target valley voltages of multiple levels; The memory device is configured to: receive the first instruction, obtain information representing predicted valley voltages of multiple levels, and send the obtained information representing predicted valley voltages of multiple levels to the memory controller; The memory controller is further configured to control the memory device to perform a first read operation using the predicted valley voltage in the information representing the multi-level predicted valley voltages, and perform a first error correction decoding operation on a first read result of the first read operation.

13. The memory system according to claim 12, wherein: The memory controller is configured to: output the first read result based on the success of the first error correction decoding; or send a second instruction based on the failure of the first error correction decoding, wherein the second instruction instructs to re-acquire information representing the target valley voltage of multiple levels; The memory device is configured to: receive the second instruction, re-determine the target valley voltage of the multiple levels, and send second information representing the target valley voltage to the memory controller; The memory controller is further configured to: control the memory device to perform a second read operation using the target valley voltage in the second information, and perform a second error correction decoding operation on a second read result of the second read operation.

14. A memory controller coupled to at least one memory device, the memory device comprising a memory cell having a plurality of storage bits; the plurality of storage bits corresponding to a plurality of pages; At least part of the page corresponds to multiple levels, the multiple levels including a first level and a second level, a read voltage of the second level being lower than a read voltage of the first level; The memory controller includes a control unit configured to: Obtaining a predicted valley voltage for the first stage based on a first result corresponding to a target read voltage for the first stage; the first result comprising a number of bits flipped in at least one codeword formed by a preset number of memory cells in two read results at the first read voltage and at the second read voltage; and a difference between the first read voltage and the second read voltage being less than a preset voltage; Obtaining the predicted valley bottom voltage of the second stage according to the predicted valley bottom voltage of the first stage; and The memory device is controlled to perform a first read operation using the predicted valley voltage of the first stage and the predicted valley voltage of the second stage, and a first error correction decoding is performed on a first read result of the first read operation.

15. The memory controller according to claim 14, wherein: The control unit is configured to: According to the failure of the first error correction decoding, the predicted valley voltage of the first stage and the predicted valley voltage of the second stage are both used as initial target read voltages; and a first result corresponding to the initial target read voltage is obtained; According to the first result corresponding to the initial target read voltage meeting a preset condition, determining that the initial target read voltage is a target valley voltage; or, Adjusting the initial target read voltage at least once, and obtaining a first result corresponding to the adjusted target read voltage after each adjustment; According to the first result corresponding to the adjusted target read voltage meeting a preset condition, determining the adjusted target read voltage as a target valley voltage; The memory device is controlled to perform a second read operation on at least one of the codewords according to the target valley voltage, and a second error correction decoding is performed on a second read result of the second read operation.

16. The memory controller according to claim 14, wherein: The control unit is configured to: According to the failure of the first error correction decoding, taking the predicted valley voltage of the first stage as an initial target read voltage, and obtaining a first result of the initial target read voltage; According to the initial reading The first result corresponding to the voltage satisfies a preset condition, and the initial read voltage is determined to be the target valley voltage; or, Adjusting the initial target read voltage at least once, and obtaining a first result corresponding to the adjusted target read voltage after each adjustment; Determining a target valley voltage based on that the first result corresponding to the adjusted target read voltage meets a preset condition; Obtaining a predicted valley voltage of the second stage according to the determined target valley voltage of the first stage; and The memory device is controlled to perform a second read operation on at least one of the codewords according to the determined target valley voltage of the first stage and the predicted valley voltage of the second stage, and a second error correction decoding is performed on a second read result of the second read operation.

17. The memory controller according to claim 14 or 16, wherein: Each of the plurality of pages comprises a plurality of second stages; The control unit is configured to: Obtaining a predicted valley voltage of a second stage having a maximum read voltage among the plurality of second stages of each page according to the predicted valley voltage of the first stage of each page / the target valley voltage of the first stage; and The predicted valley bottom voltages of the second stages with larger read voltages among the multiple second stages of each page are sequentially obtained, and the predicted valley bottom voltages of the second stages with smaller read voltages adjacent to the second stages are obtained until the predicted valley bottom voltages of each second stage of each page are obtained.

18. The memory controller according to claim 14 or 16, wherein: The control unit is configured to: The predicted valley voltage of the second order is obtained based on the predicted valley voltage of the first order / the target valley voltage of the first order and a first mapping function, and the first mapping function is used to characterize the relationship between the predicted valley voltage of the first order / the target valley voltage of the first order and the predicted valley voltage of the second order.

19. The memory controller according to claim 15 or 16, wherein: The control unit is configured to: In a process of adjusting the initial target read voltage at least once, taking the initial target read voltage as a reference value; Starting from the reference value, adjusting in two opposite directions with a step size smaller than a first preset step size, and in the process of adjusting in each direction, performing a statistical analysis showing an upward trend based on the first result corresponding to the read voltage after the next adjustment being greater than the first result corresponding to the read voltage after the previous adjustment, and determining the first voltage boundary and the second voltage boundary when the total number of statistical analyses is greater than or equal to a preset number; During the adjustment process in two directions, if the first result corresponding to the target read voltage after one adjustment is lower than the first threshold, or if the smallest first result among the multiple first results corresponding to the target read voltage after multiple adjustments is used as the reference value, and the number of the remaining multiple first results whose differences from the reference value are less than the second threshold is greater than a preset number, the adjustment is stopped and the target read voltage corresponding to the smallest first result among the multiple first results is used as the target valley voltage.

20. The memory controller according to claim 19, wherein: The control unit is configured to: During the adjustment in two directions, the adjusted target read voltages corresponding to the total statistical number of times being equal to the preset number are respectively used as the first voltage boundary and the second voltage boundary; During the adjustment in two directions, if the first voltage boundary and the second voltage boundary have been determined, the target read voltage of the last adjustment is the average value of the first voltage boundary and the second voltage boundary; The read voltage corresponding to the smallest first result among the multiple first results corresponding to all the adjusted target read voltages is used as the target valley voltage.

21. The memory controller according to claim 15 or 16, wherein: The control unit is configured to: controlling the memory device to output a corresponding read result according to success of the first error correction decoding or success of the second error correction decoding; Error correction failure is determined based on the failure of the second error correction decoding.

22. The memory controller according to claim 14, wherein: The control unit is configured to: According to the first result corresponding to the target read voltage of the first stage, the stage where the first stage is located number, and a second mapping function to obtain the predicted valley voltage of the first order; the second mapping function is used to characterize the relationship between the first result corresponding to the target read voltage, the order number of each order and the predicted valley voltage.

23. A method for operating a memory device, comprising: Obtaining a predicted valley voltage of the first stage according to a first result corresponding to the target read voltage of the first stage; The first result includes the number of bits flipped in at least one codeword formed by a preset number of memory cells in the memory device in two read results at a first read voltage and a second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; the memory cell has multiple storage bits, the multiple storage bits correspond to multiple pages respectively; at least some of the pages correspond to multiple levels, the multiple levels include the first level and a second level, and the read voltage of the second level is less than the read voltage of the first level; Obtaining the predicted valley bottom voltage of the second stage according to the predicted valley bottom voltage of the first stage; and A first read operation is performed on at least one of the codewords using the predicted valley voltage of the first stage and the predicted valley voltage of the second stage.

24. A method for operating a memory system, comprising: The memory controller in the memory system sends a first instruction, wherein the first instruction instructs obtaining information representing target valley voltages of multiple levels; The memory device in the memory system receives the first instruction, obtains information representing predicted valley voltages of multiple levels according to the memory device operating method according to claim 23, and sends the information representing predicted valley voltages of multiple levels to the memory controller; The memory controller controls the memory device to perform a first read operation using information representing the predicted valley voltages of the multiple levels, and performs a first error correction decoding operation on a first read result of the first read operation.

25. A method for operating a memory controller, comprising: Obtaining a predicted valley voltage of the first stage according to a first result corresponding to the target read voltage of the first stage; The first result includes the number of bits flipped in two read results at a first read voltage and a second read voltage of at least one codeword formed by a preset number of memory cells in at least one memory device coupled to the memory controller; The difference is less than a preset voltage; the storage unit has multiple storage bits, and the multiple storage bits correspond to multiple pages respectively; At least part of the page corresponds to multiple levels, the multiple levels including the first level and a second level, a read voltage of the second level being lower than a read voltage of the first level; Obtaining the predicted valley bottom voltage of the second stage according to the predicted valley bottom voltage of the first stage; and The memory device is controlled to perform a first read operation using the predicted valley voltage of the first stage and the predicted valley voltage of the second stage, and a first error correction decoding is performed on a first read result of the first read operation.

26. A storage medium having executable instructions stored thereon, wherein the executable instructions, when executed by a processor, implement the steps of the operating method according to any one of claims 23 to 25.

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