Analog-to-digital conversion circuit, chip, and recording device

Abstract

The present application discloses an analog-to-digital conversion circuit, a chip, and a recording device. The analog-to-digital conversion circuit comprises a main path module, a dynamic range enhancement module, and a dynamic digital-to-analog conversion module. The main path module is used for converting an analog signal and an analog feedback signal into a digital signal to be processed for outputting to the dynamic range enhancement module, and obtaining a digital signal on the basis of the digital signal to be processed and a digital gain signal and outputting the digital signal. The dynamic range enhancement module is used for performing dynamic quantization processing on the digital signal to be processed to obtain a control signal, and generating the digital gain signal. The dynamic digital-to-analog conversion module is used for, on the basis of the control signal, dynamically controlling the activation and deactivation of each DAC element in a digital-to-analog conversion array, and generating an analog feedback signal. According to the analog-to-digital conversion circuit of the present application, the need for a front-end fixed-gain OPA is eliminated, reducing power consumption and reducing costs; moreover, dynamically controlling the activation and deactivation of each DAC element in the digital-to-analog conversion array further reduces the power consumption.

Description

Analog-to-digital conversion circuits, chips, and recording equipment Technical Field

[0001] The present application relates to the field of analog-to-digital conversion technology, and in particular to an analog-to-digital conversion circuit, chip, and recording equipment. Background Art

[0002] Most current recording devices use microphones to collect sound signals. The microphones then convert the received sound signals into weak electrical signals. The electrical signals are then amplified by programmable gain amplifiers (PGAs) and output to analog-to-digital converters (ADCs) to convert them into digital signals. Finally, they are digitally processed and converted into the final output signal.

[0003] In the entire signal processing path, the PGA and ADC are the main noise sources, affecting the final recording performance. Generally speaking, a low-noise PGA is easier to achieve than a low-noise ADC. Therefore, when the ADC performance is not very high, dynamically adjusting the PGA gain can improve the performance of the entire path, resulting in better recording performance. However, this will also significantly increase the power consumption and area of ​​the path.

[0004] Related technologies can also achieve gain adjustment within the ADC by adjusting the input resistor connected to the ADC input port. However, this approach requires connecting an operational amplifier (OPA) between the microphone and the ADC. The OPA provides a low-impedance output resistance path, isolating the effect of the microphone's equivalent output resistance on the gain. However, the addition of the OPA also increases power consumption.

[0005] Summary of the Invention

[0006] In view of the above problems, the present application provides an analog-to-digital conversion circuit, chip and recording device to solve the above technical problems.

[0007] In a first aspect, the present application provides an analog-to-digital conversion circuit, the analog-to-digital conversion circuit comprising a main path module, a dynamic range enhancement module, and a dynamic digital-to-analog conversion module, the dynamic digital-to-analog conversion module comprising a digital-to-analog conversion array;

[0008] a main path module, configured to convert the analog signal and the analog feedback signal from the dynamic digital-to-analog conversion module into a digital signal to be processed and output it to the dynamic range enhancement module, and to obtain a digital signal output according to the digital signal to be processed and the digital gain signal from the dynamic range enhancement module;

[0009] The dynamic range enhancement module is used to perform dynamic quantization processing on the digital signal to be processed, obtain a control signal and output it to the dynamic digital-to-analog conversion module, and generate a digital gain signal and output it to the main path module;

[0010] The dynamic digital-to-analog conversion module is used to dynamically control the opening and closing of each DAC element in the digital-to-analog conversion array according to the control signal, and output the generated analog feedback signal to the main path module.

[0011] In a possible implementation of the present application, the main path module includes a loop filter and a quantizer;

[0012] A loop filter is used to perform integral filtering on the analog signal and the analog feedback signal to obtain a first filtered signal and output it to the quantizer;

[0013] The quantizer is used to perform quantization processing on the first filtered signal to obtain a digital signal to be processed and output it to the dynamic range enhancement module.

[0014] In a possible implementation of the present application, the main path module further includes a multiplier and a digital filter;

[0015] A multiplier, configured to obtain a signal to be modulated according to the digital signal to be processed and the digital gain signal, and output the signal to the digital filter;

[0016] The digital filter is used to filter the modulated signal to obtain a digital signal.

[0017] In a possible implementation of the present application, the main path module further includes a digital filter, which is used to filter the digital signal to be processed and the digital gain signal, and obtain a digital signal based on the filtered digital signal to be processed and the digital gain signal.

[0018] In a possible implementation of the present application, the dynamic range enhancement module includes a second filtering unit, an amplitude determination unit, a dynamic power consumption control unit, a decoding unit, a dynamic quantization modulation unit, and a digital gain calculation unit;

[0019] A second filtering unit is used to filter the digital signal to be processed, obtain a second filtered signal and output it to the amplitude judgment unit;

[0020] an amplitude determination unit, configured to perform amplitude detection on the second filtered signal according to a preset maximum amplitude threshold and a hysteresis amplitude threshold, output a base adjustment signal to the dynamic quantization modulation unit according to the amplitude detection result, and output a polling number to the dynamic power consumption control unit, where the polling number is used to represent the number of polling-enabled DAC elements in the digital-to-analog conversion array, and the polling number is less than or equal to the total number of DAC elements in the digital-to-analog conversion array;

[0021] A dynamic power consumption control unit, configured to generate a first control signal according to the polling quantity and output it to the dynamic digital-to-analog conversion module;

[0022] A decoding unit, configured to convert the digital signal to be processed into a preset coded signal according to a preset number of data extension bits and output the signal to the dynamic quantization modulation unit;

[0023] a dynamic quantization modulation unit, configured to adjust a current output base value according to a base adjustment signal to obtain a target base value, dynamically quantize a preset coded signal using the target base value to obtain an activation number, output a second control signal carrying the activation number to the dynamic digital-to-analog conversion module, and output the target base value to the digital gain calculation unit, wherein the activation number is less than the polling number;

[0024] The digital gain calculation unit is used to obtain a digital gain signal according to the number of data extension bits and the target base value.

[0025] In a possible implementation of the present application, the amplitude determination unit is configured to:

[0026] If the amplitude of the second filtered signal is continuously less than the threshold difference within a preset time period, a first adjustment signal is output to the dynamic quantization modulation unit, where the first adjustment signal is used to instruct the dynamic quantization modulation unit to increase the current output base value, and the threshold difference is the difference between the maximum amplitude threshold and the hysteresis amplitude threshold;

[0027] If the amplitude of the second filtered signal continues to be greater than the threshold value sum within a preset time length, a second adjustment signal is output to the dynamic quantization modulation unit, and the second adjustment signal is used to instruct the dynamic quantization modulation unit to reduce the current output base value, and the threshold value sum is the sum of the maximum amplitude threshold and the hysteresis amplitude threshold;

[0028] If the amplitude of the second filtered signal continues to be no less than the threshold difference and no greater than the threshold sum within the preset time length, a third adjustment signal is output to the dynamic quantization modulation unit, and the third adjustment signal is used to instruct the dynamic quantization modulation unit to maintain the current output base value.

[0029] In a possible implementation of the present application, the dynamic range enhancement module further includes a jump amplitude determination unit, which is configured to:

[0030] When it is detected that the amplitude of the level jump of the digital signal to be processed is greater than a preset amplitude threshold, a reset signal is output to the amplitude judgment unit so that the amplitude judgment unit can control the reset of the dynamic quantization modulation unit based on the reset signal; and / or a reset signal is output to the dynamic quantization modulation unit so that the dynamic quantization modulation unit can reset in response to the reset signal.

[0031] In a possible implementation of the present application, the dynamic digital-to-analog conversion module includes a dynamic element matching unit, which is configured to:

[0032] Determine the number of DAC elements in the digital-to-analog conversion array that are turned off according to the first control signal, and control the corresponding number of DAC elements in the digital-to-analog conversion array to turn off, where the number of DAC elements that are turned off is the difference between the total number of DAC elements in the digital-to-analog conversion array and the polling number;

[0033] According to the second control signal and the dynamic element matching algorithm, the DAC elements in the digital-to-analog conversion array that are not turned off are dynamically controlled to be turned on in a polling manner based on the turn-on quantity, so as to selectively access the main path module to form an analog feedback signal.

[0034] In a possible implementation of the present application, the digital-to-analog conversion array includes at least one of a current source array, a resistor array, and a capacitor array.

[0035] In a second aspect, the present application also provides a chip, which includes a chip body and the above-mentioned analog-to-digital conversion circuit provided in the chip body.

[0036] In a third aspect, the present application also provides a recording device, which includes a device body, a microphone provided on the device body, and the above-mentioned analog-to-digital conversion circuit or chip.

[0037] From the above content, it can be concluded that this application has the following beneficial effects:

[0038] The analog-to-digital conversion circuit provided in the present application dynamically quantizes the digital signal to be processed output by the main path module through the dynamic range enhancement module, thereby obtaining a control signal and outputting it to the dynamic digital-to-analog conversion module, so that the dynamic digital-to-analog conversion module can dynamically control the opening and closing of each DAC element in the digital-to-analog conversion array according to the control signal, and output the generated analog feedback signal to the main path module to achieve gain adjustment, thereby eliminating the OPA with a fixed gain in the front end, reducing power consumption, and saving costs. In addition, by dynamically controlling the opening and closing of each DAC element in the digital-to-analog conversion array, power consumption is further reduced.

[0039] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0041] FIG1 is a schematic diagram of an architecture of a recording device in the related art;

[0042] FIG2 is a schematic structural diagram of a DRE module in the related art;

[0043] FIG3 is a schematic diagram of a structure for adjusting gain within an ADC in the related art;

[0044] FIG4 is a schematic diagram of a module of an analog-to-digital conversion circuit provided in an embodiment of the present application;

[0045] FIG5 is a schematic structural diagram of a main path module provided in an embodiment of the present application;

[0046] FIG6 is a schematic structural diagram of a loop filter provided in an embodiment of the present application;

[0047] FIG7 is another schematic diagram of the structure of the loop filter provided in an embodiment of the present application;

[0048] FIG8 is another structural diagram of the main path module provided in an embodiment of the present application;

[0049] FIG9 is another structural diagram of the main path module provided in an embodiment of the present application;

[0050] FIG10 is a schematic structural diagram of a dynamic range enhancement module provided in an embodiment of the present application;

[0051] FIG11 is a schematic structural diagram of a dynamic quantization modulation unit provided in an embodiment of the present application;

[0052] FIG12 is a spectrum comparison diagram of an audio signal provided in an embodiment of the present application;

[0053] FIG13 is another structural diagram of a dynamic range enhancement module provided in an embodiment of the present application;

[0054] FIG14 is a schematic structural diagram of a dynamic digital-to-analog conversion module provided in an embodiment of the present application;

[0055] FIG15 is a schematic diagram of an application scenario of the analog-to-digital conversion circuit provided in an embodiment of the present application;

[0056] FIG16 is a schematic diagram of another application scenario of the analog-to-digital conversion circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0058] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0059] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0060] Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the article or device comprising the element.

[0061] In the description of the embodiments of this application, words such as "example" or "for example" are used to indicate an example, illustration, or description. Any embodiment or design described as "for example" or "for example" in the embodiments of this application is not to be construed as being preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to clearly present relative concepts.

[0062] In addition, in the embodiments of the present application, "plurality" refers to two or more. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two, or more. For example, "including at least one" means including one, two, or more, and does not limit which ones are included. For example, "including at least one of A, B, and C" means including A, B, C, A and B, A and C, B and C, or A, B, and C.

[0063] It should be noted that in the embodiments of the present application, "and / or" describes the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects are in an "or" relationship.

[0064] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0065] Before introducing the analog-to-digital conversion circuit, chip and recording device of the present application, the relevant background information of the embodiments of the present application is first introduced.

[0066] As shown in Figure 1, Figure 1 is a schematic diagram of the architecture of a recording device in the related art. The microphone MIC receives a sound signal and generates a weak electrical signal. After being amplified by a programmable gain amplifier (PGA), the electrical signal is output to an analog-to-digital converter (ADC) to become a digital signal. The signal is then processed by a digital filter, a high-pass filter, and a digital gain module to become the final digital signal output. It is understood that the output digital signal can be stored on a disk or input into other modules that can process digital signals for subsequent processing.

[0067] In the entire channel shown in Figure 1, there are two noise sources: the PGA and the ADC, which affect the recording performance of the entire channel. A low-noise PGA is easier to achieve than a low-noise ADC.

[0068] Therefore, when the ADC performance is lower than the PGA performance, if the MIC noise is 4uV, the signal-to-noise ratio (SNR) is 70db, the PGA noise is 2uV, and the ADC noise is 10uV.

[0069] When the PGA is configured for 0dB gain and the digital module is configured for 0dB gain, the overall path has a 0dB gain. At this time, the final signal-to-noise ratio (SNR) of the entire path is 61.3dB, with a performance loss of 8.7dB.

[0070] When the PGA is configured for 26dB gain and the digital module reduces the gain by 26dB, the overall path still has a gain of 0dB. However, the final signal-to-noise ratio (SNR) of the entire path is now 69dB, with a performance loss of 1dB.

[0071] From this we can see that when the overall path gain remains unchanged at 0dB, when a small signal is input, if the PGA's 0dB gain is used for recording, the performance loss will be greater than the performance loss of using 26dB gain for recording, and the recording effect will be worse.

[0072] Since the input signal of the MIC is generally a small signal, in the related art, when the MIC signal is a small signal, a larger PGA gain is used to improve the recording performance; when the MIC signal is a large signal, a smaller PGA gain is used to avoid output swing overflow and clipping.

[0073] As shown in Figure 2, dynamically adjusting the PGA gain based on the input signal and inversely compensating the gain through digital gain to maintain the overall path gain constant improves the ADC's small-signal performance, thereby increasing the dynamic range. Therefore, as shown in Figures 1 and 2, when ADC performance is not very high, dynamically adjusting the PGA gain and inversely adjusting the digital gain through the Dynamic Range Enhancer (DRE) module output control signal can improve the performance of the overall path, resulting in better recording performance. However, this approach significantly increases the power consumption and area of ​​the overall path, which is detrimental to both cost and power consumption.

[0074] To reduce costs and power consumption, related technologies can also perform gain adjustment within the ADC. For example, this can be achieved by adjusting the current or resistance of the ADC's internal digital-to-analog conversion module. However, this approach can significantly alter the transfer function of the ADC's overall path, potentially posing a risk to stability. Furthermore, when adjusting the current or resistance, the change in current or resistance takes time to settle, and the feedback signal during this settling process can have significant deviations, potentially causing the ADC to output erroneous data.

[0075] To avoid this problem, as shown in Figure 3, the related art can also achieve gain adjustment within the ADC by adjusting the input resistor connected to the ADC input port. However, when using this method, an operational amplifier (OPA) needs to be connected between the microphone and the ADC. The OPA provides a low-impedance output resistance path to isolate the effect of the microphone's equivalent output resistance on the gain. If there is no pre-fixed gain OPA, the ADC's input resistance is constantly changing, which will cause the microphone's signal gain to deviate, making it very difficult to achieve the functional requirement of matching digital gain and analog gain in the DRE. Therefore, although this method does not require a PGA, the addition of the OPA will also lead to increased power consumption.

[0076] Based on this, the present application provides an analog-to-digital conversion circuit, chip and recording device, which are described in detail below.

[0077] First, an embodiment of the present application provides an analog-to-digital conversion circuit. Referring to Figure 4, Figure 4 is a module schematic diagram of the analog-to-digital conversion circuit provided in an embodiment of the present application. The analog-to-digital conversion circuit 100 may include a main path module 110, a dynamic range enhancement module 120 and a dynamic digital-to-analog conversion module 130. The dynamic digital-to-analog conversion module 130 includes a digital-to-analog conversion array 1301.

[0078] Among them, the main path module 110 can be used to convert the analog signal and the analog feedback signal from the dynamic digital-to-analog conversion module 130 into a digital signal to be processed and output it to the dynamic range enhancement module 120, and obtain a digital signal output based on the digital signal to be processed and the digital gain signal from the dynamic range enhancement module 120.

[0079] The dynamic range enhancement module 120 can be used to perform dynamic quantization processing on the digital signal to be processed, obtain a control signal to be output to the dynamic digital-to-analog conversion module 130 , and generate a digital gain signal to be output to the main path module 110 .

[0080] The dynamic digital-to-analog conversion module 130 can be used to dynamically control the on and off of each DAC element in the digital-to-analog conversion array 1301 according to the control signal, and output the generated analog feedback signal to the main path module 110 .

[0081] In the embodiment of the present application, the analog signal may be a signal from a sound sampling device such as a microphone, or a signal from an internal memory or other external storage module or signal processing module.

[0082] As shown in FIG4 , when the analog-to-digital conversion circuit 100 is applied to a recording device, the recording device may be equipped with a microphone MIC for collecting sound signals. The collected sound signals are converted into analog signals by the microphone MIC and then output to the main path module 110 .

[0083] In some other embodiments, the analog signal may also be sent from the memory of the recording device to the main path module 110 in response to a trigger signal from a central processing unit (CPU) or a microcontroller unit (MCU).

[0084] In some other embodiments, the analog signal may also be a signal output to the main path module 110 by an external memory or a signal processing module connected to the recording device.

[0085] The analog signal in the embodiment of the present application can be a single-ended signal, a differential signal, a signal with or without DC isolation, etc. It is understandable that the type of analog signal can be determined according to the actual application scenario and is not limited here.

[0086] In the embodiment of the present application, the dynamic digital-to-analog conversion module 130 can output an analog feedback signal to the input end of the main path module 110. It can be understood that the main path module 110 can use the analog feedback signal to perform analog gain adjustment on the analog signal.

[0087] After performing analog gain adjustment on the analog signal, the main path module 110 may further perform corresponding processing on the adjusted signal, such as integration, filtering, quantization, etc., so as to obtain a digital signal to be processed and output to the dynamic range enhancement module 120 .

[0088] In an embodiment of the present application, the dynamic range enhancement module 120 can dynamically quantize the received digital signal to be processed, determine the analog gain according to the parameter configuration of the dynamic quantization, and reversely determine the digital gain based on the analog gain, output the control signal to the dynamic digital-to-analog conversion module 130, and output the digital gain signal to the main path module 110.

[0089] After receiving the control signal, the dynamic digital-to-analog conversion module 130 can dynamically control the opening and closing of each DAC element in the digital-to-analog conversion array 1301 based on the control signal, thereby generating an analog feedback signal to be output to the main path module 110.

[0090] It can be understood that the DAC element is each small unit in the digital-to-analog conversion array 1301. In this embodiment, the digital-to-analog conversion array 1301 can include at least one of any existing current source array, resistor array, and capacitor array.

[0091] For example, if the digital-to-analog conversion array 1301 is a current source array, the DAC element is each current source in the current source array; if the digital-to-analog conversion array 1301 is a resistor array, the DAC element is each resistor in the resistor array; if the digital-to-analog conversion array 1301 is a capacitor array, the DAC element is each capacitor in the capacitor array; if the digital-to-analog conversion array 1301 is a combination of a current source array and a resistor array, the DAC element is each current source in the current source array and each resistor in the resistor array. The selection of the digital-to-analog conversion array 1301 can be determined based on the actual application scenario and is not specifically limited here.

[0092] In the embodiment of the present application, the digital gain is determined by the dynamic range enhancement module 120 in reverse based on the analog gain. Therefore, after receiving the digital gain signal, the main path module 110 can perform reverse digital gain adjustment on the digital signal to be processed based on the digital gain signal, so that the overall path gain of the analog-to-digital conversion circuit 100 remains unchanged, thereby improving its dynamic range.

[0093] The analog-to-digital conversion circuit 100 provided in the embodiment of the present application dynamically quantizes the digital signal to be processed output by the main path module 110 through the dynamic range enhancement module 120, thereby obtaining a control signal and outputting it to the dynamic digital-to-analog conversion module 130, so that the dynamic digital-to-analog conversion module 130 can dynamically control the opening and closing of each DAC element in the digital-to-analog conversion array 1301 according to the control signal, and output the generated analog feedback signal to the main path module 110 to achieve gain adjustment, thereby eliminating the OPA with a fixed gain in the front end, reducing power consumption, and saving costs. In addition, by dynamically controlling the opening and closing of each DAC element in the digital-to-analog conversion array 1301, power consumption is further reduced.

[0094] At the same time, compared with the related art in which the DRE module is independent of the ADC, the analog-to-digital conversion circuit 100 of the embodiment of the present application includes a dynamic range enhancement module 120, that is, the DRE is fully implemented inside the analog-to-digital conversion circuit 100, which can reduce the delay of the DRE inspection path and ensure a faster response speed; and, by dynamically controlling the opening and closing of each DAC element in the digital-to-analog conversion array 1301, the gain of the input analog signal is not affected, and the analog gain adjustment is also mainly achieved by the digital configuration parameters inside the dynamic range enhancement module 120, making the matching of analog gain and digital gain easier to achieve.

[0095] Next, each unit module shown in FIG4 and a specific implementation method that may be adopted in practical applications will be described in detail.

[0096] As shown in FIG. 5 , in some embodiments of the present application, the main path module 110 may include a loop filter 1101 and a quantizer 1102 .

[0097] The loop filter 1101 may be used to perform integral filtering on the analog signal and the analog feedback signal to obtain a first filtered signal which is output to the quantizer 1102 .

[0098] The quantizer 1102 may be configured to perform quantization processing on the first filtered signal to obtain a digital signal to be processed and output it to the dynamic range enhancement module 120 .

[0099] In the embodiment of the present application, the loop filter 1101 may be any type of existing loop filter, including but not limited to active loop filters, passive loop filters, etc. The quantizer 1102 may be any type of existing quantizer.

[0100] As shown in Figure 6, in one embodiment, the loop filter 1101 may include an integrator 11011 and other functional modules 11012 (other functional modules 11012 only refer to other circuits in the loop filter 1101), wherein the integrator 11011 may include a first input resistor R3, a first capacitor C1 and a first-stage operational amplifier OPA1.

[0101] Specifically, the first input resistor R3 is connected to the non-inverting input of the first-stage operational amplifier OPA1, the first capacitor C1 is connected between the non-inverting input and the output of the first-stage operational amplifier OPA1, the output of the first-stage operational amplifier OPA1 is connected to the input of the other functional module 11012, and the output of the other functional module 11012 is connected to the input of the quantizer 1102. Thus, the integrator 11011 and the other functional modules 11012 implement integration and filtering processing of the analog signal and the analog feedback signal.

[0102] It can be understood that the structure shown in FIG6 corresponds to an application scenario in which the analog signal is a single-ended signal. If the analog signal is a differential signal, then as shown in FIG7 , the integrator 11011 may further include a second input resistor R4 and a second capacitor C2. In this case, the first capacitor C1 is connected between the non-inverting input terminal and the first output terminal of the first-stage operational amplifier OPA1, the second input resistor R4 is connected to the inverting input terminal of the first-stage operational amplifier OPA1, and the second capacitor C2 is connected between the inverting input terminal and the second output terminal of the first-stage operational amplifier OPA1. The differential analog signal and the analog feedback signal are respectively input into the integrator 11011, and the integration and filtering processing of the differential analog signal and the analog feedback signal is realized by the integrator 11011 and other functional modules 11012.

[0103] In the embodiment of the present application, after the first filtered signal is quantized by the quantizer 1102 , an Mbits digital signal to be processed may be generated and output to the dynamic range enhancement module 120 .

[0104] As shown in FIG. 8 , in some embodiments of the present application, the main path module 110 may further include a multiplier 1103 and a digital filter 1104 .

[0105] The multiplier 1103 can be used to obtain a signal to be modulated according to the digital signal to be processed outputted from the quantizer and the digital gain signal, and output the signal to the digital filter 1104 .

[0106] The digital filter 1104 can be used to filter the modulated signal to obtain a digital signal output.

[0107] In this embodiment, the multiplier 1103 can adopt any existing multiplier, and the digital filter 1104 can adopt any existing filter for digital signals, as shown in Figure 8. In this embodiment, the digital gain adjustment of the digital signal to be processed is performed before the digital filter 1104.

[0108] As shown in Figure 9, in another implementation, the digital gain adjustment of the digital signal to be processed can also be performed in the digital filter 1104. At this time, the main path module 110 may include a digital filter 1104, which can be used to filter the digital signal to be processed and the digital gain signal, and obtain a digital signal based on the digital signal to be processed and the digital gain signal after filtering.

[0109] Please refer to Figure 10. In some embodiments of the present application, the dynamic range enhancement module 120 may include a second filtering unit 1201, an amplitude judgment unit 1202, a dynamic power consumption control unit 1203, a decoding unit 1204, a dynamic quantization modulation unit 1205 and a digital gain calculation unit 1206.

[0110] The second filtering unit 1201 may be configured to filter the digital signal to be processed, and obtain a second filtered signal to output to the amplitude determination unit 1202 .

[0111] In an embodiment of the present application, the second filtering unit 1201 can adopt any existing filter. In a specific implementation, the second filtering unit 1201 can be a cascaded integrator-comb decimator (CIC) filter, which can filter out high-frequency noise energy in the digital signal to be processed.

[0112] In this embodiment, the number of stages and length of the CIC filter may be adjusted by configuring registers, thereby balancing the delay and filtering effect of the CIC filter.

[0113] For example, if the number of stages and length are set too low, the CIC filter will have a smaller delay and a faster response, but the filtering effect may be poor, and the output second filtered signal may have greater jitter. On the other hand, if the number of stages and length are set too high, the CIC filter will have a better filtering effect and less jitter in the output second filtered signal, but the delay will be larger and the response will be slower. Therefore, the number of stages and length of the CIC filter can be configured according to the actual application scenario.

[0114] In an embodiment of the present application, the second filtering unit 1201 can filter the M bits of the digital signal to be processed output by the quantizer 1102 to obtain a second filtered signal from which high-frequency noise is filtered out and output to the amplitude judgment unit 1202, where M can be any value such as 2, 3, 4, 5, etc.

[0115] The amplitude judgment unit 1202 can be used to perform amplitude detection on the second filtered signal based on a preset maximum amplitude threshold, a hysteresis amplitude threshold and a preset time length, and output a base adjustment signal to the dynamic quantization modulation unit 1205 based on the amplitude detection result, and output a polling number to the dynamic power consumption control unit 1203. The polling number is used to represent the number of polling-enabled DAC elements in the digital-to-analog conversion array 1301. It can be understood that the polling number is less than or equal to the total number of DAC elements in the digital-to-analog conversion array 1301.

[0116] In this embodiment, the amplitude determination unit 1202 may be specifically configured to:

[0117] If the amplitude of the second filtered signal is continuously less than the threshold difference within a preset time period, a first adjustment signal is output to the dynamic quantization modulation unit 1205. The first adjustment signal can be used to instruct the dynamic quantization modulation unit 1205 to increase the current output base value. The threshold difference is the difference between the maximum amplitude threshold and the hysteresis amplitude threshold.

[0118] If the amplitude of the second filtered signal continues to be greater than the threshold value sum within a preset time period, a second adjustment signal is output to the dynamic quantization modulation unit 1205. The second adjustment signal can be used to instruct the dynamic quantization modulation unit 1205 to reduce the current output base value. The threshold value sum is the sum of the maximum amplitude threshold and the hysteresis amplitude threshold.

[0119] If the amplitude of the second filtered signal continues to remain between the threshold difference and the threshold sum (including the threshold difference and the threshold sum) within the preset time length, a third adjustment signal is output to the dynamic quantization modulation unit 1205, and the third adjustment signal can be used to instruct the dynamic quantization modulation unit 1205 to maintain the current output base value.

[0120] In the embodiment of the present application, the maximum amplitude threshold can be determined based on past experience or multiple experiments combined with actual application scenarios. For example, the maximum amplitude threshold can be any value between -18dBFS and -6dBFS, and the hysteresis amplitude threshold can be any value between 0dBFS and 5dBFS. The preset duration can be configured via a register. For example, the preset duration can be any value between 10μs and 2s.

[0121] For example, if the current output value is 4, the preset duration is 1 second, the maximum amplitude threshold is -15 dbFS, and the hysteresis amplitude threshold is 5 dbFS, then the threshold difference is -20 dbFS and the threshold sum is -10 dbFS.

[0122] If the amplitude of the second filtered signal is always less than -20dbFS within 1s, the amplitude judgment unit 1202 outputs a first adjustment signal to the dynamic quantization modulation unit 1205, which is used to instruct the dynamic quantization modulation unit 1205 to increase the current output base value 4 to 5 (assuming the adjustment step is 1).

[0123] If the amplitude of the second filtered signal is always greater than -10dbFS within 1s, the amplitude judgment unit 1202 outputs a second adjustment signal to the dynamic quantization modulation unit 1205, which is used to instruct the dynamic quantization modulation unit 1205 to adjust the current output base value 4 to 3 (assuming the adjustment step is 1).

[0124] If the amplitude of the second filtered signal always remains between -20 dbFS and -10 dbFS, the amplitude determination unit 1202 outputs a third adjustment signal to the dynamic quantization modulation unit 1205 to instruct the dynamic quantization modulation unit 1205 to maintain the current output base value 4 unchanged.

[0125] In order to achieve a rapid response when the signal amplitude increases and avoid distortion due to the output base value being too large due to failure to adjust the output base value in a timely manner, in one embodiment, the preset time length for judgment when the signal amplitude increases and the preset time length for judgment when the signal amplitude decreases can be set to different values ​​respectively. For example, the preset time length for judgment when the signal amplitude increases can be set to 100μs, and the preset time length for judgment when the signal amplitude decreases can be set to 1s.

[0126] At this time, if the amplitude of the second filtered signal is always less than -20dbFS within 1s, the amplitude judgment unit 1202 outputs a first adjustment signal to the dynamic quantization modulation unit 1205, which is used to instruct the dynamic quantization modulation unit 1205 to increase the current output base value 4 to 5 (assuming the adjustment step is 1).

[0127] If the amplitude of the second filtered signal is always greater than -10dbFS within 100μs, the amplitude judgment unit 1202 outputs a second adjustment signal to the dynamic quantization modulation unit 1205, which is used to instruct the dynamic quantization modulation unit 1205 to adjust the current output base value 4 to 3 (assuming the adjustment step is 1) to achieve fast response.

[0128] If the amplitude of the second filtered signal always remains between -20 dbFS and -10 dbFS, the amplitude determination unit 1202 outputs a third adjustment signal to the dynamic quantization modulation unit 1205 to instruct the dynamic quantization modulation unit 1205 to maintain the current output base value 4 unchanged.

[0129] In this embodiment, the amplitude determination unit 1202 may further obtain a polling quantity according to the amplitude and change of the second filtered signal and output the polling quantity to the dynamic power consumption control unit 1203 .

[0130] For example, the polling quantity can be divided into four segments based on the total number of DAC elements in the digital-to-analog conversion array 1301: 1 / 4, 1 / 2, 3 / 4, and all of the total number of DAC elements. Accordingly, the amplitude of the second filtered signal can be compared with multiple amplitude values ​​corresponding to the DAC elements to match different polling quantities.

[0131] For example, when the amplitude of the second filtered signal is less than 1 / 8 of the total amplitude corresponding to when all DAC elements are turned on, the polling number is 1 / 4 of the total number of DAC elements;

[0132] When the amplitude of the second filtered signal is less than 3 / 8 of the total amplitude and greater than or equal to 1 / 8 of the total amplitude, the polling number is 1 / 2 of the total number of DAC elements;

[0133] When the amplitude of the second filtered signal is less than 5 / 8 of the total amplitude and greater than or equal to 3 / 8 of the total amplitude, the polling number is 3 / 4 of the total number of DAC elements;

[0134] When the amplitude of the second filtered signal is greater than or equal to 5 / 8 of the total amplitude, the polling number is the total number of DAC elements.

[0135] In this embodiment, when the amplitude of the second filtered signal changes from low to high and exceeds a certain upper threshold, the polling quantity output by the amplitude judgment unit 1202 can immediately increase; and when the amplitude of the second filtered signal changes from high to low and crosses a certain lower threshold, the amplitude judgment unit 1202 can output a smaller polling quantity to the dynamic power consumption control unit 1203 after monitoring that the amplitude of the second filtered signal is continuously less than the lower threshold within a preset time period, thereby avoiding the adverse effects caused by short-term signal fluctuations.

[0136] In an embodiment of the present application, after receiving the polling number from the amplitude judgment unit 1202, the dynamic power consumption control unit 1203 can generate a first control signal based on the polling number and output it to the dynamic digital-to-analog conversion module 130, thereby controlling the operation of the digital-to-analog conversion array 1301 in the dynamic digital-to-analog conversion unit 130.

[0137] In the embodiment of the present application, the decoding unit 1204 can be used to convert the digital signal to be processed into a preset coded signal according to a preset number of data extension bits and output it to the dynamic quantization modulation unit 1205.

[0138] The decoding unit 1204 can adopt any existing type of decoder, and the preset number of data extension bits can take any integer value, such as 0, 1, 2, 3, etc., and can be specifically configured according to the actual application scenario.

[0139] Assuming that the number of data extension bits is N, the decoding unit 1204 can expand the bit width of the M-bit digital signal to be processed output by the quantizer 1102 according to the number of data extension bits N, so that the data output by the decoding unit 1204 has a bit width of (M+N) bits. In this embodiment, the expanded N-bit data can be achieved by supplementing 0, pseudo-random noise, or random noise generated by an analog circuit.

[0140] For example, if M is 5, the quantizer 1102 outputs a 5-bit digital signal to be processed. Assume that the data size of the digital signal to be processed is 15 (binary representation: 01111). If N is set to 4, the size of the added noise data is 5 (binary representation: 0101). Then, the output of the decoding unit 1204 after expansion, i.e., the preset coded signal, is 9 bits. The data size of the preset coded signal is 245 (binary representation: 011110101). It can be understood that when N is set to 0, it means that the digital signal to be processed is not expanded.

[0141] In an embodiment of the present application, the dynamic quantization modulation unit 1205 can be used to adjust the current output base value according to the base adjustment signal from the amplitude judgment unit 1202 to obtain a target base value, and use the target base value to dynamically quantize the preset coded signal from the decoding unit 1204 to obtain the activation number, output a second control signal carrying the activation number to the dynamic digital-to-analog conversion module 130, and output the target base value to the digital gain calculation unit 1206, wherein the activation number is less than the polling number.

[0142] In this embodiment, the dynamic quantization modulation unit 1205 can intercept and perform interception error modulation on the preset coded signal from the decoding unit 1204 .

[0143] As shown in Figure 11, the dynamic quantization modulation unit 1205 may include a dynamic quantizer 12051 and a loop filter unit 12052. The preset coding signal X is added to the signal passing through the loop filter unit 12052 to form an input signal U which is input to the dynamic quantizer 12051. The dynamic quantizer 12051 performs high-bit interception on the input signal U according to the current output base value K to obtain an output signal Y, which is the second control signal and is sent to the dynamic digital-to-analog conversion module 130. The output signal Y is obtained by rounding the result of dividing the input signal U by the current output base value K. The difference between the input and output of the dynamic quantizer 12051 is the quantization error E, which is sent to the loop filter unit 12052 to complete the feedback.

[0144] In this embodiment, a parameter K may be configured for the dynamic quantizer 12051 as an output base value for quantization. K may be any value greater than or equal to 1, such as 2, 3.5, 6, etc.

[0145] The base adjustment signal output by the amplitude determination unit 1202 is fed into the dynamic quantizer 12051. When the progress adjustment signal is the first adjustment signal, the current output base value K is increased based on a preset adjustment step size to obtain a target base value. When the progress adjustment signal is the second adjustment signal, the current output base value K is decreased based on a preset adjustment step size to obtain a target base value. When the progress adjustment signal is the third adjustment signal, the current output base value K remains unchanged, i.e., the target base value K is obtained. In this embodiment, the adjustment step size can be configured and adjusted via a register and can be a positive decimal or integer, such as 1, 1.5, 2, etc.

[0146] The dynamic quantizer 12051 re-quantizes and modulates the (M+N) bits of data sent from the decoding unit 1204 according to the adjusted current output base value K, i.e., the target base value K. After changing the output bit width of the data, a second control signal carrying the turn-on number is obtained and output to the dynamic digital-to-analog conversion module 130.

[0147] The output signal Y of the dynamic quantizer 12051 is fixed (U / K), where fixed represents rounding to zero, for example, fixed (5.4) = 5, and fixed (-3.1) = -3. The quantization error E = UY*K, and the input signal U = X+E*((1-z ^-1 ) ^n +1).

[0148] In the embodiment of the present application, the absolute value of Y output by the dynamic quantizer 12051 is the turn-on number, which represents the number of DAC elements that need to be turned on in the digital-to-analog conversion array 1301.

[0149] Compared with the preset coded signal of (M+N) bits output by the decoding unit 1204, since the target base value K is an arbitrary value greater than or equal to 1, the data bit width output by the dynamic quantizer 12051 is reduced, which is equivalent to replacing the number of DAC elements corresponding to the original data with a smaller number of DAC elements, which is equivalent to the dynamic quantizer 12051 increasing the gain by K times.

[0150] Referring to the spectrum diagram shown in Figure 12, we can see the amplitude change of the digital signal when the target base value K takes different values. From the enlarged small figure in the upper right corner of Figure 12, we can see that as the target base value K increases, the gain of the digital signal gradually changes from -32db to -12db.

[0151] It can be understood that the example of the dynamic quantization modulation unit 1205 in this embodiment is not the only implementation method of the dynamic quantization modulation unit 1205. All methods of re-adjusting the bit width through dynamic quantization to achieve dynamic adjustment gain DRE should be within the scope of protection of this application.

[0152] In the embodiment of the present application, the digital gain calculation unit 1206 can be used to obtain a digital gain signal according to the target base value of the dynamic quantization modulation unit 1205.

[0153] In this embodiment, the number of data extension bits N in the decoding unit 1204 enables the dynamic quantization modulation unit 1205 to perform more detailed quantization calculations. However, in actual applications, the number of data extension bits N is typically set to a fixed value in advance. It is understood that the analog output gain is K, and the analog gain can be configured by adjusting the target base value K. Correspondingly, the digital gain can be calculated by dividing 1 by the target base value K, i.e., 1 / K. This achieves matching between the analog gain and the digital gain, ensuring that the path gain remains unchanged.

[0154] It can be understood that in order to compensate for the signal processing delay of the main path module 110, in some embodiments of the present application, the digital gain calculation unit 1206 can also be configured with a delay unit 12061, as shown in Figure 13. The signal processing delay of the main path module 110 is compensated by the delay unit 12061, and the digital gain signal is output to the main path module 110 after the delay compensation, thereby improving the accuracy of the gain adjustment.

[0155] As shown in FIG13 , in some embodiments of the present application, the dynamic range enhancement module 120 may further include a jump amplitude determination unit 1207 . The jump amplitude determination unit 1207 may be configured to:

[0156] When it is detected that the amplitude of the level jump of the digital signal to be processed is greater than the preset amplitude threshold, a reset signal is output to the amplitude judgment unit 1202 so that the amplitude judgment unit 1202 can control the reset of the dynamic quantization modulation unit 1205 based on the reset signal; and / or a reset signal is output to the dynamic quantization modulation unit 1205 so that the dynamic quantization modulation unit 1205 can reset in response to the reset signal.

[0157] In an embodiment of the present application, the jump amplitude judgment unit 1207 can serve as an exception handling module. If the amplitude of the level jump of the digital signal to be processed is greater than a preset amplitude threshold, it means that there may be an abnormality in the analog-to-digital conversion circuit 100. At this time, the jump amplitude judgment unit 1207 can output a reset signal to the amplitude judgment unit 1202, so that the amplitude judgment unit 1202 can trigger the dynamic quantization modulation unit 1205 to reset in response to the reset signal, for example, resetting the target base value K to the initial value, etc.; in addition, the amplitude judgment unit 1202 can also control the polling number of the dynamic power consumption control unit 1203 to become the total number of DAC elements in response to the reset signal, so that all DAC elements are fully enabled.

[0158] In another implementation, the jump amplitude determination unit 1207 may also directly output a reset signal to the dynamic quantization modulation unit 1205 , so that the dynamic quantization modulation unit 1205 triggers a reset in response to the reset signal.

[0159] In another implementation, the jump amplitude determination unit 1207 may also output a reset signal to the amplitude determination unit 1202 and the dynamic quantization modulation unit 1205 simultaneously to ensure that the dynamic quantization modulation unit 1205 performs a reset operation.

[0160] As shown in FIG14 , in some embodiments of the present application, the dynamic digital-to-analog conversion module 130 may include a dynamic element matching unit 1302 . The dynamic element matching unit 1302 may be configured to:

[0161] Determine the number of DAC elements in the digital-to-analog conversion array 1301 that are turned off according to the first control signal, and control the corresponding number of DAC elements in the digital-to-analog conversion array 1301 to turn off, where the number of DAC elements that are turned off is the difference between the total number of DAC elements in the digital-to-analog conversion array 1301 and the polling number;

[0162] According to the second control signal and the dynamic element matching algorithm, the DAC elements in the digital-to-analog conversion array 1301 that are not turned off are dynamically controlled to be turned on in a polling manner based on the turn-on quantity, so as to selectively access the main path module 110 to form an analog feedback signal.

[0163] In the embodiment of the present application, after receiving the first control signal, the dynamic element matching unit 1302 can determine the number of DAC elements in the digital-to-analog conversion array 1301 to be turned off based on the polling number in the first control signal. For example, if the total number of DAC elements is 200 and the polling number is 100, the number of DAC elements to be turned off is 100. Therefore, the dynamic element matching unit 1302 can control 100 of the 200 DAC elements to be turned off.

[0164] Then, according to the second control signal and the dynamic element matching algorithm, the remaining 100 non-closed DAC elements are dynamically controlled to be turned on and off based on the number of open elements, for example, 50, so that in each round, 50 DAC elements are selectively turned on from the 100 non-closed DAC elements and connected to the main path module 110 to form an analog feedback signal.

[0165] In this embodiment, the dynamic element matching algorithm can adopt the existing dynamic element matching algorithm. Based on the dynamic element matching algorithm, the dynamic element matching unit 1302 can average the usage frequency of each DAC element in the digital-to-analog conversion array 1301, thereby reducing the performance impact caused by the mismatch between DAC elements.

[0166] It can be understood that when the target base value K is large or the digital signal to be processed is small, the number of DAC elements that need to be turned on is small, so the number of closed elements is large. By controlling the dynamic element matching unit 1302 to turn off the DAC elements that are not needed, power consumption can be saved.

[0167] On the basis of the above embodiments, an embodiment of the present application further provides a chip, which may include a chip body and the above analog-to-digital conversion circuit 100 provided in the chip body.

[0168] The chip can be mounted on an electronic device, where the electronic device includes but is not limited to a microphone signal acquisition device, a wireless microphone, a speaker with a recording function or other electronic devices.

[0169] Since the chip is provided with the analog-to-digital conversion circuit 100 of the above embodiment, it has all the beneficial effects of the analog-to-digital conversion circuit 100 in any of the above embodiments, which will not be described in detail here.

[0170] On the basis of the above embodiments, an embodiment of the present application further provides a recording device, which may include a device body, a microphone provided on the device body, and the above-mentioned analog-to-digital conversion circuit 100 or chip.

[0171] The recording equipment includes but is not limited to a microphone signal acquisition device, a wireless microphone, a speaker with a recording function or other electronic equipment.

[0172] Since the recording device is provided with the analog-to-digital conversion circuit 100 of the above embodiment, it has all the beneficial effects of the analog-to-digital conversion circuit 100 in any of the above embodiments, which will not be described in detail here.

[0173] The analog-to-digital conversion circuit of the present application is described in detail below in conjunction with specific application scenarios.

[0174] Application Scenario 1

[0175] Referring to the voice recorder shown in FIG15 , the voice recorder includes a microphone MIC, a Σ-Δ ADC, and a memory. The main path of the Σ-Δ ADC includes a loop filter and a quantizer. The output of the microphone MIC is connected to the input of the loop filter. The output of the quantizer is connected to a digital filter via a multiplier. The output of the digital filter is connected to the memory. The loop filter includes an integrator and other functional modules. The integrator includes input resistors (R5 and R6), integrating capacitors (C3 and C4), and an operational amplifier (OPA).

[0176] The Σ-Δ ADC also includes a dynamic range enhancement module and a dynamic digital-to-analog conversion module. The dynamic range enhancement module includes a jump amplitude judgment unit, a decoder, a CIC filter, a digital gain calculation unit, a dynamic quantization modulator, an amplitude judgment unit, and a dynamic power consumption control unit. The dynamic digital-to-analog conversion module includes a dynamic element matching unit and a current source array.

[0177] The signal processing process of the main path is:

[0178] The microphone MIC converts the collected sound signal into a differential analog audio signal and inputs it into the loop filter. The in-phase analog audio signal in the differential analog audio signal is input into the in-phase input terminal of the operational amplifier OPA, and the inverting analog audio signal is input into the inverting input terminal of the operational amplifier OPA. The in-phase analog feedback signal generated by the current source array is also input into the inverting input terminal of the operational amplifier OPA, and the inverting analog feedback signal is also input into the inverting input terminal of the operational amplifier OPA. The differential analog audio signal output by the microphone MIC is gain adjusted by the in-phase analog feedback signal and the inverting analog feedback signal.

[0179] After the integrator and other functional modules perform integration and filtering on the input signal, the filtered signal is output to the quantizer. After the quantizer quantizes the filtered signal, it outputs the digital signal to be processed to the multiplier. The digital gain calculation unit outputs the digital gain signal to the multiplier to perform digital gain adjustment on the digital signal to be processed, and the modulated signal is sent to the digital filter. After processing by the digital filter, the final digital audio signal is sent to the memory for storage.

[0180] The generation process of the in-phase analog feedback signal, the anti-phase analog feedback signal and the digital gain signal is as follows:

[0181] After the high-frequency noise of the digital signal to be processed output by the quantizer is filtered out by the CIC filter, the filtered signal is output and sent to the amplitude judgment unit. The amplitude judgment unit performs amplitude detection on the signal according to the preset maximum amplitude threshold, hysteresis amplitude threshold and preset time length, generates a base adjustment signal and sends it to the dynamic quantization modulator to adjust the K value of the dynamic quantization modulator, and generates a polling number and sends it to the dynamic power consumption control unit. The dynamic power consumption control unit generates a first control signal based on the polling number and sends it to the dynamic element matching unit.

[0182] After the decoder completes data bit expansion (N) and decoding of the digital signal to be processed output by the quantizer, a preset coding signal is generated and output to the dynamic quantization modulator. After the dynamic quantization modulator adjusts its own K value based on the base adjustment signal, it dynamically quantizes the preset coding signal with the adjusted K value, outputs a second control signal carrying the turn-on number to the dynamic element matching unit, and outputs the adjusted K value to the digital gain calculation unit.

[0183] The digital gain calculation unit obtains a digital gain signal based on the K value from the dynamic quantization modulator, and outputs the digital gain signal to the multiplier after compensating for the signal processing delay of the main path.

[0184] The dynamic element matching unit obtains the shutdown number according to the difference between the total number of current sources in the current source array and the polling number in the first control signal, and controls the corresponding number of current sources in the current source array to shut down based on the shutdown number, and does not use these shut-down current sources.

[0185] The dynamic element matching unit dynamically controls the non-closed current sources in the current source array according to the dynamic element matching algorithm, and polls and turns on the current sources based on the number of open states in the second control signal, that is, selectively closes the switch corresponding to the current source. After the switch is closed, the current of the current source will be injected into the input end of the operational amplifier OPA through the switch to form a corresponding analog feedback signal.

[0186] During the entire process, the jump amplitude judgment unit performs abnormality detection on the digital signal to be processed output by the quantizer based on a preset amplitude threshold. When it is detected that the amplitude of the level jump of the digital signal to be processed is greater than the preset amplitude threshold, a reset signal is output to the amplitude judgment unit and the dynamic quantization modulator, so that the amplitude judgment unit controls the reset of the dynamic quantization modulator and the dynamic quantization modulator is reset in response to the reset signal.

[0187] Application Scenario 2

[0188] Different from the voice recorder in the application scenario shown in Figure 15, in this application scenario, the dynamic power consumption control unit can output a first control signal to the current source array, thereby directly controlling the corresponding number of current sources in the current source array to turn off, and at the same time notifying the dynamic element matching unit of the current sources that have been turned off, so that the dynamic element matching unit can dynamically control the switches of the current sources that are not turned off in the current source array based on the dynamic element matching algorithm and the number of open states, so as to selectively connect the corresponding current sources to the main path to form the corresponding analog feedback signal, thereby achieving the purpose of reducing power consumption.

[0189] The above is only a preferred embodiment of the present application and does not constitute any form of limitation to the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An analog-to-digital conversion circuit, characterized in that: It includes a main path module, a dynamic range enhancement module and a dynamic digital-to-analog conversion module, wherein the dynamic digital-to-analog conversion module includes a digital-to-analog conversion array; The main path module is configured to convert the analog signal and the analog feedback signal from the dynamic digital-to-analog conversion module into a digital signal to be processed and output it to the dynamic range enhancement module, and to obtain a digital signal output according to the digital signal to be processed and the digital gain signal from the dynamic range enhancement module; The dynamic range enhancement module is used to perform dynamic quantization processing on the digital signal to be processed, obtain a control signal and output it to the dynamic digital-to-analog conversion module, and generate the digital gain signal and output it to the main path module; The dynamic digital-to-analog conversion module is used to dynamically control the opening and closing of each DAC element in the digital-to-analog conversion array according to the control signal, and output the generated analog feedback signal to the main path module.

2. The analog-to-digital conversion circuit according to claim 1, wherein: The main path module includes a loop filter and a quantizer; The loop filter is configured to perform integral filtering on the analog signal and the analog feedback signal to obtain a first filtered signal and output it to the quantizer; The quantizer is used to perform quantization processing on the first filtered signal to obtain the digital signal to be processed and output it to the dynamic range enhancement module.

3. The analog-to-digital conversion circuit according to claim 2, wherein: The main path module also includes a multiplier and a digital filter; The multiplier is configured to obtain a signal to be modulated according to the digital signal to be processed and the digital gain signal, and output the signal to the digital filter; The digital filter is used to filter the signal to be modulated to obtain the digital signal.

4. The analog-to-digital conversion circuit according to claim 2, wherein: The main path module further includes a digital filter, which is used to filter the digital signal to be processed and the digital gain signal, and obtain the digital signal according to the digital signal to be processed and the digital gain signal after filtering.

5. The analog-to-digital conversion circuit according to claim 1, wherein: The dynamic range enhancement module includes a second filtering unit, an amplitude judgment unit, a dynamic power consumption control unit, a decoding unit, a dynamic quantization modulation unit and a digital gain calculation unit; The second filtering unit is configured to filter the digital signal to be processed to obtain a second filtered signal and output it to the amplitude judgment unit; The amplitude determination unit is configured to perform amplitude detection on the second filtered signal according to a preset maximum amplitude threshold and a hysteresis amplitude threshold, output a base adjustment signal to the dynamic quantization modulation unit according to the amplitude detection result, and output a polling number to the dynamic power consumption control unit, wherein the polling number is used to represent the number of DAC elements in the digital-to-analog conversion array that are polled and turned on; The dynamic power consumption control unit is configured to generate a first control signal according to the polling quantity and output the first control signal to the dynamic digital-to-analog conversion module; The decoding unit is configured to convert the digital signal to be processed into a preset coded signal according to a preset data extension bit number and output the coded signal to the dynamic quantization modulation unit; The dynamic quantization modulation unit is configured to adjust the current output base value according to the base adjustment signal to obtain a target base value, dynamically quantize the preset coded signal using the target base value to obtain an activation number, output a second control signal carrying the activation number to the dynamic digital-to-analog conversion module, and output the target base value to the digital gain calculation unit, wherein the activation number is less than the polling number; The digital gain calculation unit is configured to obtain the digital gain signal according to the data extension bit number and the target base value.

6. The analog-to-digital conversion circuit according to claim 5, characterized in that: The amplitude judgment unit is used for: If the amplitude of the second filtered signal is continuously less than the threshold difference within a preset time period, outputting a first adjustment signal to the dynamic quantization modulation unit, wherein the first adjustment signal is used to instruct the dynamic quantization modulation unit to increase the current output base value, and the threshold difference is the difference between the maximum amplitude threshold and the hysteresis amplitude threshold; If the amplitude of the second filtered signal continues to be greater than the threshold value within the preset time length, a second adjustment signal is output to the dynamic quantization modulation unit, and the second adjustment signal is used to instruct the dynamic quantization modulation unit to reduce the current output base value, and the threshold value is the maximum amplitude threshold. and the hysteresis amplitude threshold; If the amplitude of the second filtered signal continues to be not less than the threshold difference and not greater than the threshold sum within the preset time length, a third adjustment signal is output to the dynamic quantization modulation unit, and the third adjustment signal is used to instruct the dynamic quantization modulation unit to maintain the current output base value.

7. The analog-to-digital conversion circuit according to claim 5, characterized in that: The dynamic range enhancement module further includes a jump amplitude determination unit, which is configured to: When it is detected that the amplitude of the level jump of the digital signal to be processed is greater than a preset amplitude threshold, a reset signal is output to the amplitude judgment unit so that the amplitude judgment unit can control the reset of the dynamic quantization modulation unit based on the reset signal; and / or a reset signal is output to the dynamic quantization modulation unit so that the dynamic quantization modulation unit can reset in response to the reset signal.

8. The analog-to-digital conversion circuit according to claim 5, wherein: The dynamic digital-to-analog conversion module includes a dynamic element matching unit, which is used to: Determining the number of DAC elements in the digital-to-analog conversion array to be turned off according to the first control signal, and controlling a corresponding number of DAC elements in the digital-to-analog conversion array to be turned off, wherein the number of DAC elements to be turned off is the difference between the total number of DAC elements in the digital-to-analog conversion array and the polling number; According to the second control signal and the dynamic element matching algorithm, the DAC elements in the digital-to-analog conversion array that are not turned off are dynamically controlled to be turned on in a polling manner based on the turn-on quantity, so as to be selectively connected to the main path module to form the analog feedback signal.

9. The analog-to-digital conversion circuit according to any one of claims 1 to 8, wherein: The digital-to-analog conversion array includes at least one of a current source array, a resistor array, and a capacitor array.

10. A chip, characterized in that: The invention comprises a chip body and an analog-to-digital conversion circuit according to any one of claims 1 to 9, which is arranged on the chip body.

11. A recording device, characterized in that: The device comprises a device body, a microphone provided on the device body, and the analog-to-digital conversion circuit according to any one of claims 1 to 9 or the chip according to claim 10.

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