Edge-isolated sliced cell and manufacturing method therefor

Abstract

An edge-isolated sliced cell and a manufacturing method therefor. The sliced cell comprises a silicon wafer (1); the front surface of the silicon wafer (1) is provided with a cell working area covering a boron emitter (2) and a pn junction isolation area (3) formed by removing all or part of the boron emitter (2); a front electrode (5) is arranged in the cell working area; the side surface of the silicon wafer (1) is provided with a laser slicing area (12) of which surface damage is removed; the pn junction isolation area (3) is located between the front electrode (5) and the laser slicing area (12); the pn junction isolation area (3) can cut off a transmission channel of minority carriers from the cell working area to the laser slicing area (12); and passivation layers are arranged on surfaces of the pn junction isolation area (3) and the laser slicing area (12). By forming a pn junction-free isolation structure between a laser slicing area (12) and a front electrode (5), and the laser slicing area (12) is subjected to passivation treatment, so that the technical effect of improving the efficiency of the sliced cell is achieved.

Description

Edge-isolated sliced battery and preparation method thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of crystalline silicon solar cell preparation, in particular to an edge-isolated sliced battery and a preparation method thereof. BACKGROUND

[0002] Slicing technology is a kind of photovoltaic module technology, which cuts standard specification battery pieces into the same half or multiple battery pieces along the direction perpendicular to the main grid line of the battery, and then performs welding in series. Slicing technology has the advantages of improving packaging efficiency, reducing module temperature rise, reducing shading loss, etc. However, for sliced batteries, the battery edge surface cut by laser has very significant carrier recombination, and as the small size battery perimeter area ratio becomes larger, the edge recombination becomes more and more serious. This is because the laser thermal ablation and mechanical damage caused by cutting the battery piece will produce defects on the surface or edge of the battery piece, resulting in edge recombination of carriers (electrons and holes) at these defects. For TOPCon sliced batteries, the efficiency loss caused by edge recombination will be very significant, and the efficiency loss will reach 0.2% to 0.4%.

[0003] In order to cope with the efficiency loss of TOPCon sliced batteries caused by slicing, the industry proposes to use atomic layer deposition technology (ALD) to deposit a certain thickness (about 30 nm) of aluminum oxide (AlO x ) on the edge of the silicon wafer for edge passivation after slicing the battery, which can increase the efficiency of the existing sliced battery by 0.1% to 0.2%, reducing the efficiency loss of the sliced battery to 0.1% to 0.3%. However, this technology has the following problems: 1) AlO x will be plated around the front and back of the battery, affecting the appearance of the battery. 2) 30 nm of AlO x requires a long time and a large amount of gas, resulting in smaller production capacity and higher cost. 3) The edge passivation equipment cannot be compatible with the existing TOPCon production line, requiring a large equipment installation space. 4) Based on the AlO x edge passivation technology, the efficiency of the sliced battery can only be restored by 0.1% to 0.2%, and the production cost is high, which has low cost performance for industrial application. SUMMARY

[0004] In view of the deficiencies of the prior art, the purpose of the present application is to provide a sliced battery preparation method and structure suitable for industrial application, which reduces the efficiency loss of the sliced battery.

[0005] To achieve the above object, the application provides a first aspect of an edge-isolated sliced battery, comprising a silicon wafer, the front surface of the silicon wafer having a battery working area covering a boron emitter and a pn junction isolation area formed by removing all or part of the boron emitter, a front electrode being arranged in the battery working area, the side surface of the silicon wafer having a laser slicing area with surface damage removed, the pn junction isolation area being located between the front electrode and the laser slicing area, the pn junction isolation area being capable of cutting off the transmission path of minority carriers from the battery working area to the laser slicing area, and a passivation layer being arranged on the surface of the pn junction isolation area and the laser slicing area.

[0006] The application can effectively inhibit the influence of laser slicing area minority carrier recombination dark current on the battery working area by forming an isolation structure without a pn junction between the laser slicing area and the electrode, and can substantially eliminate half-cell cutting edge recombination and leakage by passivating the laser slicing area, thereby achieving the technical effect of improving the efficiency of the half-cell.

[0007] Further, the surface of the pn junction isolation area is a textured surface with a passivation layer. The pn junction isolation area does not affect the appearance of the battery front surface, and the optical loss is low.

[0008] Further, the passivation layer arranged on the surface of the pn junction isolation area and the laser slicing area is an AlO x and SiN x stack. The pn junction isolation area and the laser slicing area have good surface passivation and do not produce additional recombination.

[0009] Further, the distance between the pn junction isolation area and the laser slicing area is 0-5 mm. The pn junction isolation area and the laser slicing area are intersected or arranged close to each other to ensure the isolation effect.

[0010] Further, the width of the pn junction isolation area is greater than 10 μm to ensure the isolation effect, and is preferably 60-300 μm.

[0011] Further, the back surface of the silicon wafer is provided with a nano-silicon oxide layer, a phosphorus-doped polysilicon layer, and a back electrode in contact with the phosphorus-doped polysilicon layer, and the back surface of the silicon wafer further has a back field isolation area formed by removing all or part of the phosphorus-doped polysilicon layer, the back field isolation area being located between the back electrode and the laser slicing area. The formation of the polysilicon isolation structure on the back surface of the sliced battery is conducive to further reducing the efficiency loss of the sliced battery.

[0012] Further, the distance between the back field isolation area and the laser slicing area is 0-5 mm. The back field isolation area and the laser slicing area are intersected or arranged close to each other to ensure the isolation effect.

[0013] Further, the width of the back field isolation region is greater than 10 μm, ensuring the isolation effect, and preferably 60-300 μm.

[0014] The second aspect of the present application provides a preparation method of the edge-isolated sliced battery, comprising the following steps:

[0015] S10, preparing a silicon wafer, texturing the front surface, and polishing the back surface;

[0016] S20, boron diffusion on the front surface of the silicon wafer to form a boron emitter;

[0017] S30, polishing the back surface of the silicon wafer, and sequentially depositing nano-silicon oxide and phosphorus-doped amorphous silicon on the back surface;

[0018] S40, high-temperature annealing treatment;

[0019] S50, using picosecond laser to perform opening etching treatment on the boron emitter on the front surface of the silicon wafer, removing the BSG and part of the emitter, and forming a pn junction isolation region;

[0020] S60, performing laser non-destructive cutting in the pn junction isolation region or on one side, and forming a laser slicing area on the side surface of the cut silicon wafer;

[0021] S70, etching the laser slicing area using an alkali solution to remove the damage layer;

[0022] S80, acid washing the pn junction isolation region to remove residual BSG in the pn junction isolation region, and alkali etching to remove residual emitter in the pn junction isolation region;

[0023] S90, etching to remove the BSG in the remaining area on the front surface of the silicon wafer;

[0024] S100, passivating the front surface, back surface and side surface of the silicon wafer;

[0025] S100, performing double-sided metallization to obtain the edge-isolated sliced battery;

[0026] Alternatively, the order of step S50 is changed to before step S30;

[0027] Alternatively, the order of step S50 and step S60 is interchanged.

[0028] The present application realizes the pn junction isolation structure by laser combined with wet etching, suppresses the significant carrier recombination in the laser slicing area, and simultaneously performs alkali etching and passivation on the laser slicing area to reduce the surface recombination, thereby reducing the loss of battery efficiency.

[0029] Further, the preparation method further comprises the following steps:

[0030] S51, performing a hole etching treatment on the back surface of the silicon wafer near the laser cutting area by using a picosecond laser to remove the doped polysilicon and form a back field isolation area; the step S51 is performed after the step S50;

[0031] S81, performing an acid washing and alkali etching on the back field isolation area to remove the residual doped polysilicon in the back field isolation area; the step S81 is performed after the step S80.

[0032] The method of laser hole etching combined with chemical etching is also applicable to the polysilicon etching on the back surface of the cell wafer to form a polysilicon isolation structure on the back surface of the cell wafer, which is beneficial to further reduce the efficiency loss of the cut cell.

[0033] Further, the preparation method further comprises the following step: S52, performing a surface treatment on the pn junction isolation area and / or the back field isolation area by using an infrared laser; the step S52 is performed after the step S51. The infrared light is used to modify the etching surface, and the defects of the pn junction isolation area / back field isolation area are partially repaired through the thermal effect of the infrared light to reduce the recombination.

[0034] In summary, the present application has the following beneficial effects compared with the prior art:

[0035] (1) The present application realizes the pn junction isolation structure by laser combined with wet etching, which suppresses the significant carrier recombination of the laser cutting area, and at the same time, the laser cutting area is subjected to alkali etching and passivation, thereby reducing the surface recombination and the efficiency loss of the cell, so that the efficiency loss of the cut cell can be controlled within 0.08%.

[0036] (2) The method of the present application can effectively remove the damage caused by laser irradiation through acid washing and alkali etching on the pn junction isolation area / back field isolation area, and good surface passivation can be achieved through subsequent deposition of a passivation film, without additional recombination.

[0037] (3) The cut cell prepared by the method of the present application has no plating winding, no appearance color difference, the pn junction isolation area maintains the textured structure and is covered with a passivation film, and no obvious laser cut marks are present.

[0038] (4) The cut cell prepared by the method of the present application has the advantages of no leakage, low saturation current density, high fill factor, and high cell efficiency.

[0039] (5) The preparation method of the present application is simple to implement, fully compatible with the existing production line process, only one or two lasers need to be added, and no changes are made to the existing cell process, which is easy to modify the production line and easy to promote the industry. The preparation method can be applied to all types of cut cells, such as all two, all three, and all multi-combined cut cells. BRIEF DESCRIPTION OF DRAWINGS

[0040] FIG. 1 is a preparation flowchart of the edge-isolated cut cell in the embodiment of the present application.

[0041] Figure 2 is a structural schematic diagram of an edge-isolated sliced battery in the embodiment of the present application.

[0042] Figure 3 is a preparation flow chart of an edge-isolated sliced battery in another embodiment of the present application.

[0043] Figure 4 is a topographic diagram of a boron emitter with BSG in Example 1 of the present application.

[0044] Figure 5 is an ECV curve diagram of a boron emitter in Example 1 of the present application.

[0045] Figure 6 is a PL diagram of a pn junction isolation region of a sample in Example 2 of the present application.

[0046] Figure 7 is a PL diagram of a portion near a laser-sliced region of a sample in Comparative Example 1 of the present application.

[0047] Figure 8 is a topographic diagram of a pn junction isolation region after laser-drilling etching in Example 4 of the present application.

[0048] Figure 9 is a topographic diagram of a pn junction isolation region after acid washing in Example 4 of the present application.

[0049] Figure 10 is a topographic diagram of a pn junction isolation region after alkali etching in Example 4 of the present application.

[0050] Figure 11 is an ECV curve diagram of a pn junction isolation region in Example 4 of the present application.

[0051] Figure 12 is a topographic diagram of a laser-sliced region after alkali solution etching in Example 4 of the present application.

[0052] BRIEF DESCRIPTION OF THE DRAWINGS DETAILED DESCRIPTION

[0053] In order to make the above objectives, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the following embodiments are only used to illustrate the implementation method and typical parameters of the present application, and do not limit the parameter range described in the present application, and any reasonable changes derived therefrom are still within the protection scope of the claims of the present application.

[0054] It is to be understood that the endpoints of the ranges and any values disclosed herein are too be understood as being approximate of a range of values. Whenever a numerical range is disclosed, any intervening value or sub-range between the stated values or inherently derived from those values is contemplated, even if not expressly stated. The number of values recited in the specification or claims are not meant to be an exhaustive list of possible values.

[0055] The specific embodiments of the present application provide a preparation method of an edge-isolated TOPCon sliced cell, in combination with FIG. 1, the preparation method comprises the following steps:

[0056] (1) Prepare a silicon wafer, perform front texturing, back polishing, and standard RCA cleaning.

[0057] (2) Perform boron diffusion on the front surface of the silicon wafer to form a boron emitter.

[0058] (3) Polish the back surface of the silicon wafer to remove BSG.

[0059] (4) Deposit nano-silicon oxide and phosphorus-doped amorphous silicon on the back surface in sequence.

[0060] (5) Perform high-temperature annealing treatment.

[0061] (6) Perform aperture etching on the emitter on the front surface of the silicon wafer using a picosecond laser to remove BSG and part of the boron emitter and form a pn junction isolation region. This step can be processed by a single laser at one time or by multiple lasers in combination at multiple times. Commonly used lasers include green light, ultraviolet light, etc., and the preferred laser is an ultraviolet laser.

[0062] (7) Perform laser non-destructive cutting in or on one side of the pn junction isolation region, and the side of the cell wafer cut by the laser forms a laser-sliced region. In specific embodiments, the order of this step can be interchanged with step (6).

[0063] (8) Etch the laser-sliced region using an alkali solution to remove the damage layer.

[0064] (9) Perform acid washing on the pn junction isolation region to remove residual BSG in the pn junction isolation region.

[0065] (10) Perform alkali etching on the pn junction isolation region to remove residual boron emitter in the pn junction isolation region.

[0066] (11) Etch to remove BSG in the remaining area on the front surface of the silicon wafer.

[0067] (12) Perform three-face passivation on the front surface, back surface, and side surface of the silicon wafer.

[0068] (13) Perform double-sided metallization on the passivated wafer to obtain an edge-isolated TOPCon sliced cell.

[0069] The above method forms an isolation structure without a pn junction between the laser slicing area and the electrode by laser combination and wet etching, suppresses the significant carrier recombination of the laser slicing area, avoids the injection of recombination dark current from the recombination center through the minority carrier channel of the pn junction to the working area of the battery, thereby reducing the efficiency loss of the battery, and the alkali etching and passivation treatment of the laser slicing area can basically eliminate the cutting edge recombination and leakage of the sliced battery, so that the efficiency loss of the sliced battery can be controlled within 0.08%.

[0070] The above method is also applicable to backside polysilicon etching, and the specific method is as follows:

[0071] In step (6), the doped polysilicon layer on the backside of the silicon wafer is subjected to hole etching by picosecond laser, and part of the doped polysilicon is removed to form a backside isolation area, and the position of the backside isolation area corresponds to the pn junction isolation area.

[0072] In steps (9) and (10), the backside isolation area is subjected to acid washing and alkali etching in sequence to remove the residual doped polysilicon in the backside isolation area.

[0073] Thus, a polysilicon isolation structure is formed on the backside of the battery piece, which is conducive to further reducing the efficiency loss of the sliced battery.

[0074] In a preferred embodiment, after completing the laser hole etching in step (6), the surface of the isolation area is treated by infrared laser to partially repair the defects of the isolation area and reduce recombination.

[0075] The typical structure of the TOPCon sliced battery prepared by the above method is shown in FIG. 2, which includes a silicon wafer 1, the silicon wafer 1 has a laser slicing area 12 formed after laser non-destructive cutting on the side surface, and the surface damage layer of the laser slicing area 12 is removed; the laser slicing area 12 has a side passivation layer 13 on the surface, and the typical structure is an aluminum oxide and silicon nitride film stack. The laser slicing area 12 is subjected to alkali etching and AlO x / SiN x passivation, and the recombination and leakage can be basically eliminated.

[0076] The front side of the silicon wafer 1 has a boron emitter 2 forming a cell working area; the boron emitter 2 is provided with a front passivation layer 4, and a typical structure is an aluminum oxide and silicon nitride film stack; the front side of the silicon wafer 1 is further provided with a front electrode 5 in contact with the boron emitter 2. The front side of the silicon wafer 1 near the laser scribing area 12 has all or part of the boron emitter 2 removed to form a pn junction isolation area 3, and the square resistance of this part is greater than 800 Ω / m, which can cut off the transmission channel of the minority carriers from the cell working area to the laser scribing area 12. The pn junction isolation area 3 intersects or approaches the laser scribing area 12, and the distance is less than or equal to 5 mm. The width of the pn junction isolation area 3 is greater than 10 μm, and is preferably 60-300 μm. The surface topography of the pn junction isolation area 3 is basically consistent with the topography of the front side of the silicon wafer, which is a textured surface or a flat surface, and the surface of the pn junction isolation area 3 has a passivation layer, and the recombination current density J0 of the area after passivation is less than or equal to 200 fA / cm 2 .

[0077] The back side of the silicon wafer 1 has a phosphorus diffusion layer 6; the phosphorus diffusion layer 6 is sequentially provided with a nano-silicon oxide layer 7 and a phosphorus-doped polysilicon layer 8; the phosphorus-doped polysilicon layer 8 is provided with a back passivation layer 10, and a typical structure is a silicon nitride film; the back side is further provided with a back electrode 11 in contact with the phosphorus-doped polysilicon layer 8. The back side of the silicon wafer 1 near the laser scribing area 12 has the phosphorus-doped polysilicon layer 8 removed to form a back field isolation area 9, and the back field isolation area 9 intersects or approaches the laser scribing area 12, and the distance is less than or equal to 5 mm. The width of the back field isolation area 9 is greater than 10 μm, and is preferably 60-300 μm. The surface topography of the back field isolation area 9 is basically consistent with the topography of the back side of the silicon wafer 1, and the surface of the back field isolation area 9 has a passivation layer, and the recombination current density J0 of the area after passivation is less than or equal to 200 fA / cm 2 .

[0078] In other specific embodiments, the laser scribing area 12, the pn junction isolation area 3 and the back field isolation area 9 can be distributed on one side of the cell or on both sides of the cell.

[0079] The above-mentioned scribed cell forms an isolation structure without a pn junction between the laser scribing area and the electrode, which can effectively suppress the influence of the laser scribing area minority carrier recombination dark current on the cell working area, thereby achieving the purpose of improving the efficiency of the scribed cell.

[0080] In another specific embodiment, the preparation method of the tunneling oxide passivation contact scribed cell is shown in FIG. 3, which comprises the following steps:

[0081] (1) Prepare a silicon wafer, perform front texturing, back polishing, and standard RCA cleaning.

[0082] (2) Boron diffusion on the front side of the silicon wafer to form a boron emitter.

[0083] (3) The emitter on the front surface of the silicon wafer is opened and etched by a picosecond laser to remove the BSG and part of the boron emitter, and form a pn junction isolation region.

[0084] (4) The back surface of the silicon wafer is polished to remove the BSG.

[0085] (5) Nano-silicon oxide and phosphorus-doped amorphous silicon are sequentially deposited on the back surface.

[0086] (6) High-temperature annealing treatment is performed.

[0087] (7) Laser non-destructive cutting is performed in the pn junction isolation region or on one side, and the side surface of the cut silicon wafer forms a laser cutting region.

[0088] (8) The laser cutting region is etched by an alkali solution to remove the damage layer.

[0089] (9) The pn junction isolation region is acid washed to remove the residual BSG in the pn junction isolation region.

[0090] (10) The pn junction isolation region is alkali etched to remove the residual boron emitter in the pn junction isolation region.

[0091] (11) The BSG in the remaining area on the front surface of the silicon wafer is etched.

[0092] (12) The front surface, back surface and side surface of the silicon wafer are passivated.

[0093] (13) The passivated wafer is double-sided metallized to obtain an edge-isolated TOPCon cutting cell.

[0094] The above preparation method sets the laser opening and etching step after the boron diffusion step, and also can obtain a cutting cell with an isolated structure of a pn junction.

[0095] The technical solutions and effects of the present application are illustrated by specific examples.

[0096] Example 1

[0097] A TOPCon structure sample is prepared, and the steps are as follows: an n-type silicon wafer is prepared, the front surface is textured, the back surface is polished, and standard RCA cleaning is performed. The front surface of the silicon wafer is boron diffused to form a boron emitter; the back surface is polished to remove the BSG. Nano-silicon oxide and phosphorus-doped amorphous silicon are sequentially deposited on the back surface. High-temperature annealing treatment is performed at 950℃ for 30 minutes to obtain a TOPCon structure sample. The surface morphology of the boron emitter with BSG on the front surface of the cell is observed, and the results are shown in FIG. 4. The ECV curve of the boron emitter is tested, and the results are shown in FIG. 5, the red dotted line represents the hole, indicating that the boron emitter exists, and the conductivity type is P-type.

[0098] Example 2

[0099] A passivated wafer sample with edge isolation was prepared as follows: the front surface of the TOPCon structure sample obtained in Example 1 was treated with an ultraviolet laser to remove most of the BSG and part of the boron emitter, forming a pn junction isolation area with a size of 1.8*1.8 cm. The pn junction isolation area was subjected to acid washing, alkali etching, and removal and acid washing, respectively, to remove the residual BSG and boron emitter. The remaining part of the sample front surface was then subjected to acid washing to remove the residual BSG on the front surface of the silicon wafer. The cleaned silicon wafer was subjected to double-sided Al2O3 passivation. Non-destructive cutting was performed on the pn junction isolation area to obtain a cut sample with edge isolation. The PL image of the pn junction isolation area of the cut sample is shown in FIG. 6, where only the edge part is dark and most of the area is bright. This is because the pn junction isolation area blocks the transport of minority carriers, making the sample cutting edge recombination unable to affect other parts.

[0100] Comparative Example 1

[0101] A passivated wafer sample without edge isolation was prepared as follows: the front surface of the TOPCon structure sample obtained in Example 1 was subjected to acid washing to remove the BSG on the front surface of the silicon wafer. The cleaned silicon wafer was subjected to double-sided Al2O3 passivation. The passivated wafer was subjected to non-destructive cutting to obtain a cut sample with a laser cutting area on the side surface. The PL image of the area near the cutting area of the cut sample is shown in FIG. 7, where the sample edge is mostly dark. This is because the minority carriers recombine along the pn junction to the cutting edge, and the recombination is severe, affecting the inside of the sample.

[0102] Example 3

[0103] A TOPCon whole wafer cell was prepared as follows: the TOPCon structure sample obtained in Example 1 was prepared, and the BSG on the front surface was removed by etching. An aluminum oxide film was prepared on the front surface of the sample, and a silicon nitride film was deposited on both sides of the sample. The sample was subjected to double-sided metallization to obtain a TOPCon whole wafer cell.

[0104] The performance of the prepared whole wafer cell was tested, and the open-circuit voltage V oc was 735 mV, the short-circuit current density J sc was 41.81 mA / cm 2 , the fill factor FF was 84.39%, and the cell efficiency Eff was 25.93%.

[0105] Example 4

[0106] A TOPCon slice cell with edge isolation was prepared, and the steps were as follows: the front surface of the TOPCon structure sample obtained in Example 1 was treated with ultraviolet laser to remove most of the BSG and part of the boron emitter, forming a pn junction isolation region, and the width of the region was 80 μm, and the surface morphology was as shown in FIG. 8. Laser non-destructive cutting was performed on the pn junction isolation region to obtain a slice sample, and a laser slice area was formed on the side surface. An alkali solution was used to etch the laser slice area to remove the damage layer, and the morphology of the laser slice area after alkali etching was as shown in FIG. 12. The pn junction isolation region was subjected to acid washing to remove residual BSG, and the surface morphology was as shown in FIG. 9. The pn junction isolation region was subjected to alkali etching to remove the residual boron emitter, and the surface morphology was as shown in FIG. 10, retaining the texture structure. The ECV curve of the pn junction isolation region was tested, and the results were as shown in FIG. 11, and the blue dotted line represented electrons, indicating that the boron emitter had been removed and the conductivity type was N-type. Then, the BSG in the remaining area of the front surface of the sample was etched. An aluminum oxide film was prepared on the front surface and the side surface of the sample, and then a silicon nitride film was deposited on the front surface, the back surface and the side surface. The sample was subjected to double-sided metallization to obtain a slice cell with edge isolation.

[0107] The performance of the prepared slice cell was tested, and the V oc was 735 mV, the J sc was 41.80 mA / cm 2 , the FF was 84.35%, and the Eff was 25.91%, with an efficiency loss of 0.02% compared with the whole cell of Example 3.

[0108] Example 5

[0109] A TOPCon slice cell with edge isolation was prepared, and the steps were as follows: the front surface of the TOPCon structure sample obtained in Example 1 was treated with ultraviolet laser to remove most of the BSG and part of the boron emitter, forming a pn junction isolation region, and the width of the region was 80 μm. The surface of the pn junction isolation region was oxidized and repaired by infrared laser. Laser non-destructive cutting was performed on the pn junction isolation region to obtain a slice sample with edge pn isolation. An alkali solution was used to etch the laser slice area to remove the damage layer. The pn junction isolation region was subjected to acid washing to remove residual BSG. The pn junction isolation region was subjected to alkali etching to remove the residual boron emitter. The BSG in the remaining area of the front surface of the sample was etched. An aluminum oxide film was prepared on the front surface and the side surface of the sample, and then a silicon nitride film was deposited on the front surface, the back surface and the side surface. The sample was subjected to double-sided metallization to obtain a slice cell with edge isolation.

[0110] The performance of the prepared slice cell was tested, and the V oc was 735 mV, the J sc was 41.80 mA / cm 2 , the FF was 84.38%, and the Eff was 25.92%, with an efficiency loss of 0.01% compared with the whole cell of Example 3.

[0111] Example 6

[0112] An edge-isolated TOPCon slice cell was prepared as follows: the TOPCon structure sample obtained in Example 1 was laser non-destructively cut to obtain a slice sample, and laser slice areas were formed on the side surfaces of the slice sample. The part of the front surface of the slice sample close to the laser slice area was treated with ultraviolet laser to remove most of the BSG and part of the boron emitter to form a pn junction isolation area, and the width of the area was 80 μm. The back surface of the cell and the position corresponding to the pn junction isolation area were treated with ultraviolet laser to remove most of the phosphorus-doped polysilicon to form a back field isolation area, and the width of the back field isolation area was 80 μm. Alkaline solution was used to etch the laser slice area to remove the damage layer. The pn junction isolation area and the back field isolation area were respectively subjected to acid washing and alkaline etching to remove the residual BSG, boron emitter and polysilicon. The BSG in the remaining area of the front surface of the sample was etched away. An aluminum oxide film was prepared on the front surface and the side surface of the sample, and then a silicon nitride film was deposited on the front surface, the back surface and the side surface. The sample was double-sided metallized to obtain an edge-isolated slice cell.

[0113] The performance of the prepared slice cell was tested, and the V oc was 735 mV, the J sc was 41.80 mA / cm 2 , the FF was 84.41%, and the Eff was 25.93%, which was almost no loss compared with the whole cell efficiency of Example 3.

[0114] Example 7

[0115] An edge-isolated TOPCon slice cell was prepared as follows: two parts of the front surface of the TOPCon structure sample obtained in Example 1 were treated with ultraviolet laser to remove most of the BSG and part of the boron emitter to form two pn junction isolation areas, and the width of each of the two pn junction isolation areas was 60 μm. The back surface of the cell and the position corresponding to the pn junction isolation area were treated with ultraviolet laser to remove most of the phosphorus-doped polysilicon to form two back field isolation areas, and the width of each of the back field isolation areas was 60 μm. The two pn junction isolation areas were aligned and laser non-destructively cut to obtain three slice samples, one of which had laser slice areas on both side surfaces and was used as a sample. Alkaline solution was used to etch the laser slice area to remove the damage layer. The pn junction isolation area and the back field isolation area were respectively subjected to acid washing and alkaline etching to remove the residual BSG, boron emitter and polysilicon. The BSG in the remaining area of the front surface of the sample was etched away. An aluminum oxide film was prepared on the front surface and the side surface of the sample, and then a silicon nitride film was deposited on the front surface, the back surface and the side surface. The sample was double-sided metallized to obtain an edge-isolated slice cell.

[0116] The performance of the slice cell with laser slice areas on both sides was tested, and the V oc was 735 V, and the Jsc 41.81 mA / cm 2 84.37%, 25.93%.

[0117] Comparative Example 2

[0118] A TOPCon slice cell was prepared as follows: a TOPCon structure sample prepared in Example 1 was prepared, and the BSG on the front side of the sample was etched and removed. An aluminum oxide film was prepared on the front side of the sample, and a silicon nitride film was deposited on both sides of the sample. The sample was double-sided metallized. Laser non-destructive cutting was performed to obtain a slice cell.

[0119] The performance of the prepared slice cell was tested, and the V oc was 735 mV, the J sc was 41.80 mA / cm 2 , the FF was 83.95%, and the Eff was 25.79%, with a loss of 0.14% in efficiency compared to the whole cell of Example 3.

[0120] Comparative Example 3

[0121] A TOPCon slice cell was prepared as follows: a TOPCon structure sample prepared in Example 1 was prepared, and the BSG on the front side of the sample was etched and removed. An aluminum oxide film was prepared on the front side of the sample, and a silicon nitride film was deposited on both sides of the sample. The sample was double-sided metallized. Laser non-destructive cutting was performed to obtain a slice cell. ALD was used to deposit an aluminum oxide film with a thickness of 30 nm on the laser cutting area.

[0122] The performance of the prepared slice cell was tested, and the V oc was 735 mV, the J sc was 41.80 mA / cm 2 , the FF was 84.05%, and the Eff was 25.82%, with a loss of 0.11% in efficiency compared to the whole cell of Example 3.

[0123] Comparative Example 4

[0124] A TOPCon slice cell was prepared as follows: a TOPCon structure sample prepared in Example 1 was prepared, and the BSG on the front side of the sample was etched and removed. An aluminum oxide film was prepared on the front side of the sample, and a silicon nitride film was deposited on both sides of the sample. The sample was double-sided metallized. Laser non-destructive cutting was performed on two parts to divide the cell into three slice cells, one of which had laser cutting areas on both sides.

[0125] The performance of the slice cell with laser cutting areas on both sides was tested, and the V oc was 734 mV, the J sc was 41.79 mA / cm 2FF is 83.52%, Eff is 25.62%, and the efficiency loss of the sliced battery is 0.31% compared with the whole battery of Example 3.

[0126] The performance of the TOPCon batteries of Examples 3-7 and Comparative Examples 2-4 is shown in Table 1 below.

[0127] Table 1 Comparison of battery performance of examples and comparative examples

[0128] The test results prove that the efficiency loss of the sliced battery can be controlled within 0.08% by using the method of the present application, the efficiency loss of the sliced battery is significantly reduced, the operation is simple, and the appearance of the battery is not affected, which is suitable for industrial popularization and application.

[0129] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. An edge-isolated sliced battery, characterized by, The silicon wafer comprises a front surface with a cell working area covered by a boron emitter and a pn junction isolation area formed by removing all or part of the boron emitter, a side surface with a laser cutting area from which surface damage is removed, and a back surface with a nanometer silicon oxide layer, a phosphorus-doped polysilicon layer, and a back electrode in contact with the phosphorus-doped polysilicon layer.

2. The edge-isolated sliced battery of claim 1, wherein, The surface of the pn junction isolation area is textured with a passivation layer.

3. The edge-isolated sliced battery of claim 1, wherein, The passivation layer arranged on the surface of the pn junction isolation region and the laser slicing region is AlO x SiN x Stacked film.

4. The edge-isolated sliced battery of claim 1, wherein, The distance between the pn junction isolation area and the laser cutting area is 0-5 mm.

5. The edge-isolated slice cell of claim 1, wherein, The width of the pn junction isolation area is greater than 10 μm.

6. The edge-isolated sliced battery of any one of claims 1-5, wherein, The back surface of the silicon wafer comprises a nanometer silicon oxide layer, a phosphorus-doped polysilicon layer, and a back electrode in contact with the phosphorus-doped polysilicon layer, and further comprises a back field isolation area formed by removing all or part of the phosphorus-doped polysilicon layer, the back field isolation area being located between the back electrode and the laser cutting area.

7. The edge-isolated sliced battery of claim 6, wherein, The distance between the back field isolation area and the laser cutting area is 0-5 mm.

8. The edge-isolated sliced battery of claim 6, wherein, The width of the back field isolation area is greater than 10 μm.

9. A method of making an edge-isolated sliced battery, characterized by, The method comprises the following steps: S10, preparing a silicon wafer, texturing the front surface, and polishing the back surface; S20, boron diffusion on the front surface of the silicon wafer to form a boron emitter; S30, polishing the back surface of the silicon wafer, and sequentially depositing a nanometer silicon oxide layer and a phosphorus-doped amorphous silicon layer on the back surface; S40, high-temperature annealing treatment; S50, using a picosecond laser to perform opening etching treatment on the boron emitter on the front surface of the silicon wafer to remove the BSG and part of the emitter and form a pn junction isolation area; S60, laser non-destructive cutting, the cutting position being in the pn junction isolation area or on one side, and the side surface of the cut silicon wafer forming a laser cutting area; S70, etching the laser cutting area using an alkali solution to remove the damage layer; S80, acid washing the pn junction isolation area to remove residual BSG in the pn junction isolation area, and alkali etching to remove residual emitter in the pn junction isolation area; S90, etching to remove the BSG in the remaining area on the front surface of the silicon wafer; S100, passivating the front surface, the back surface, and the side surface of the silicon wafer; S110, double-sided metallization to obtain an edge-isolated cut cell; Alternatively, the order of step S50 is changed to before step S30. Alternatively, the order of step S50 and step S60 is interchanged.

10. The method of claim 9, wherein the edge isolation of the sliced battery is achieved by, The method further comprises the following steps: S51, using a picosecond laser to perform opening etching treatment on the back surface of the silicon wafer near the laser cutting area to remove the doped polysilicon and form a back field isolation area; step S51 is performed after step S50; S81, acid washing and alkali etching the back field isolation area to remove residual doped polysilicon in the back field isolation area; step S81 is performed after step S80.

11. The method of claim 10, wherein the edge isolation of the sliced battery is achieved by, The method further comprises the following steps: S52, using an infrared laser to perform surface treatment on the pn junction isolation area and / or the back field isolation area; step S52 is performed after step S51.

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