Information processing system, quantum circuit generation method, and program

Abstract

According to one aspect of the present invention, provided is an information processing system, comprising at least one processor, wherein the processor is configured to execute a program for executing the following steps: an acquisition step in which a model function V1, an allowable error δ required with respect to a piecewise polynomial expression V2 which approximately represents the model function V1, and an order set {p} which is a set of candidate orders p for the piecewise polynomial expression V2 are acquired, where the model function V1 outputs a scalar value with respect to input and is defined by at least one continuous interval; a division step in which, on the basis of one specified order p1 selected from the order set {p} and a division parameter m representing an upper limit for a number of continuous interval divisions, a continuous interval for which an upper bound function representing the upper bound of the maximum value for the difference between the model function V1 and the piecewise polynomial V2 in said continuous interval is the allowable error δ or less is divided into 2m or fewer divided intervals, where the upper bound function does not depend on a variable for determining the piecewise polynomial V2, and the allowable error δ is stipulated on the basis of the division parameter m and a norm of a derivative V1(p1+1) of the (p1+1)th order differentiation of the model function V1 corresponding to the specified order p1; an approximate expression calculation step in which the piecewise polynomial expression V2 is calculated by using prescribed spline interpolation to optimize a p1th-order polynomial expression corresponding to the specified order p1 to the model function V1 per each divided interval; and in a circuit generation step, on the basis of the calculated piecewise polynomial expression V2, a quantum circuit representing a diagonalized unitary operator corresponding to the piecewise polynomial expression V2 is generated, where the quantum circuit is configured to act on n computation quantum bits encoded so as to represent position in the continuous interval, and the operation amount of a quantum gate operation included in the quantum circuit is determined on the basis of a coefficient of the piecewise polynomial expression V2.

Description

Information processing system, quantum circuit generation method and program

[0001] The present invention relates to an information processing system, a quantum circuit generation method, and a program.

[0002] Non-Patent Document 1 discloses an example of a technique for approximately implementing a function as a quantum circuit using a diagonal unitary matrix.

[0003] Welch et. al. , New J. Phys. 16, 2014

[0004] However, increasing the accuracy of the function approximation increases the computational load required to obtain a quantum circuit that approximately represents the function and the circuit depth of the quantum circuit, which may result in a quantum circuit that is not practical to run on a quantum computer.

[0005] According to one aspect of the present invention, there is provided an information processing system comprising at least one processor configured to execute a program for executing the following steps: in the acquisition step, a model function V1, a tolerance δ required for a piecewise polynomial V2 that approximately represents the model function V1, and a degree set {p} that is a set of candidates for the degree p of the piecewise polynomial V2 are acquired, the model function V1 outputs a scalar value in response to an input and is defined by at least one continuous interval; in the division step, two continuous intervals are selected based on one specific degree p1 selected from the degree set {p} and a division parameter m that indicates an upper limit of the number of divisions of the continuous intervals, such that an upper bound function that indicates an upper bound of the maximum value of the difference between the model function V1 and the piecewise polynomial V2 in the continuous intervals is equal to or smaller than the tolerance δ; ｍ The upper bound function is independent of the variables for determining the piecewise polynomial V2, and is determined by the tolerance δ and the (p1+1)th derivative V1 of the model function V1 corresponding to the specific order p1. （ｐ１＋１）and a division parameter m, and in the approximation formula calculation step, a piecewise polynomial V2 is calculated by optimizing a p1-degree polynomial corresponding to a specific degree p1 to a model function V1 for each division interval using a predetermined spline interpolation, and in the circuit generation step, a quantum circuit representing a diagonalized unitary operator corresponding to the piecewise polynomial V2 is generated based on the calculated piecewise polynomial V2, wherein the quantum circuit is configured to act on n computation qubits encoded to represent positions in continuous intervals, and the operation amount of a quantum gate operation included in the quantum circuit is determined based on the coefficients of the piecewise polynomial V2.

[0006] According to this information processing system, it is possible to obtain an approximate quantum circuit that is easy to execute on a quantum computer within an appropriate tolerance range depending on the approximation accuracy of the function.

[0007] 1 is a configuration diagram illustrating an information processing system 1. FIG. 1 is a block diagram illustrating the hardware configuration of an information processing device 2. FIG. 2 is a block diagram illustrating the hardware configuration of a quantum computer 3. FIG. 3 is a block diagram illustrating the hardware configuration of a user terminal 4. FIG. 4 is a block diagram illustrating the functional configuration of a processor 23. FIG. 5 is an activity diagram illustrating an overview of information processing executed in the information processing system 1. FIG. 6 is an activity diagram illustrating an example flow of processing based on a high-order piecewise polynomial (activity A4). FIG. 7 is a diagram illustrating an example of a quantum circuit implemented when the value of a specific order p1 is fixed to 2 or more. FIG. 8 is a diagram illustrating an example configuration of a polynomial phase gate 511 when n = 4 and p1 = 2. FIG. 9 is a diagram illustrating an example configuration of a quantum comparator 512 using a quantum Fourier transform (QFT) operation. FIG. 10 is a diagram illustrating an example result of processing based on a high-order piecewise polynomial. FIG. 11 is an activity diagram illustrating an example flow of processing based on a first-order piecewise polynomial (activity A5). FIG. 12 is a diagram illustrating an example of a quantum circuit implemented when the value of a specific order p1 is fixed to 1. FIG. 13 is a diagram illustrating an example configuration of a differential action operation 62. FIG. 14 is a diagram illustrating an example configuration of an increment operator U+1. FIG. 15 is a diagram illustrating an example configuration of a quantum circuit 7 corresponding to a Walsh operator. FIG. 16 is a diagram illustrating an example result of processing based on a first-order piecewise polynomial. FIG. 1 is an activity diagram illustrating an example of a process flow based on variable piecewise polynomials.

[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. Various features shown in the following embodiments can be combined with each other.

[0009] Incidentally, a program for realizing the software appearing in one embodiment may be provided as a non-transitory computer-readable recording medium, or may be provided so as to be downloadable from an external server, or may be provided so that the program is started on an external computer and its functions are realized on a client terminal (so-called cloud computing).

[0010] Furthermore, various information processing according to an embodiment may realize input and output corresponding to the input. Here, the form of information referenced in such information processing (hereinafter referred to as reference information) is not limited as long as an output is obtained as a result of the input. The reference information may be, for example, rule-based information such as a database, a lookup table, or a predetermined function (including a decision formula such as a regression formula constructed using a statistical method), a trained model that has previously trained the correlation between input and output, or a large-scale language model that can output a desired result by inputting a prompt.

[0011] In one embodiment, the term "unit" may include, for example, a combination of hardware resources implemented by a circuit in the broad sense and software information processing that can be specifically realized by these hardware resources. In one embodiment, various information is handled, and this information is represented, for example, by physical values ​​of signal values ​​representing voltage or current, high or low signal values ​​as a binary bit set consisting of 0 or 1, or quantum superposition (so-called quantum bits), and communication and calculations can be performed on the circuit in the broad sense.

[0012] Furthermore, a circuit in a broad sense is a circuit realized by at least an appropriate combination of a circuit, circuitry, a processor, a memory, etc. The processor may be a general-purpose processor or a dedicated circuit. That is, it includes application specific integrated circuits (ASICs), programmable logic devices (e.g., simple programmable logic devices (SPLDs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs)), etc.

[0013] 1. Hardware Configuration This section describes the hardware configuration of an information processing system 1 according to this embodiment. <Information Processing System 1> FIG. 1 is a configuration diagram illustrating the information processing system 1. The information processing system 1 includes an information processing device 2, at least one quantum computer 3, and a user terminal 4. The information processing device 2, the quantum computer 3, and the user terminal 4 are configured to be able to communicate with each other via a telecommunications line. In one embodiment, the information processing system 1 is made up of one or more devices or components. For example, if the information processing system 1 is made up of only the information processing device 2, the information processing system 1 can be the information processing device 2. These components will be described below.

[0014] 2 is a block diagram showing the hardware configuration of the information processing device 2. The information processing device 2 includes a communication unit 21, a storage unit 22, and a processor 23, and these components are electrically connected via a communication bus 20 inside the information processing device 2. Each component will be further described.

[0015] <Communication Unit 21> The communication unit 21 is preferably a wired communication means such as USB, IEEE 1394, Thunderbolt (registered trademark), or wired LAN network communication, but may also include wireless LAN network communication, mobile communication such as 3G / LTE / 5G, or BLUETOOTH (registered trademark) communication as needed. In other words, it is more preferable to implement the communication unit 21 as a collection of multiple communication means. In other words, the information processing device 2 may communicate various information from the outside via the communication unit 21 and the network.

[0016] <Storage Unit 22> The storage unit 22 stores various pieces of information defined above. This may be implemented, for example, as a storage device such as a solid state drive (SSD) that stores various programs and the like related to the information processing device 2 executed by the processor 23, or as a memory such as a random access memory (RAM) that stores temporarily required information (arguments, arrays, etc.) related to program calculations. The storage unit 22 stores various programs, variables, etc. related to the information processing device 2 executed by the processor 23.

[0017] <Processor 23> The processor 23 processes and controls the overall operations related to the information processing device 2. The processor 23 is, for example, a central processing unit (CPU) not shown. The processor 23 realizes various functions related to the information processing device 2 by reading out predetermined programs stored in the storage unit 22. In other words, information processing by software stored in the storage unit 22 is specifically realized by the processor 23, which is an example of hardware, and can be executed as each functional unit included in the processor 23. These will be described in more detail in the next section. Note that the processor 23 is not limited to being single, and multiple processors 23 may be provided for each function. A combination of these may also be used.

[0018] The processor 23 is configured as an acquisition unit to acquire various pieces of information related to quantum computing from the quantum computer 3 and the user terminal 4. The acquisition unit 231 can be configured to acquire various pieces of information by reading out various pieces of information stored in a storage area that is at least a part of the memory unit 22 and writing the read out information to a working area that is at least a part of the memory unit 22. The storage area is, for example, an area of ​​the memory unit 22 that is implemented as a storage device such as an SSD. The working area is, for example, an area that is implemented as a memory such as a RAM.

[0019] The processor 23 is configured as a quantum operation unit to be able to perform various quantum operations on the quantum bits 320. The circuit generation unit 234 may be configured to perform quantum operations directly on the quantum bits 320, or may be configured to send a command to cause the quantum processor 33 to perform a quantum operation. The circuit generation unit 234 of this embodiment causes the quantum processor 33 to perform a quantum operation by sending various quantum circuits to the quantum processor 33.

[0020] The processor 23, as a display processing unit, is configured to be able to display various types of information. The information can be presented to a user via the display unit 44 or another device. In such a case, for example, the processor 23 controls the display unit 44 to display visual information such as a screen, an image including a still image or a video, an icon, or a message. The processor 23 may generate only rendering information for displaying the visual information on the display unit 44. Note that the processor 23 may present the output information to a user without going through the display unit 44 or another device user.

[0021] <Quantum Computer 3> Fig. 3 is a block diagram showing the hardware configuration of the quantum computer 3. As shown in Fig. 3, the quantum computer 3 has a communication unit 31, a quantum memory 32, and a quantum processor 33, and these components are connected via a communication bus 30 inside the quantum computer 3. Note that the quantum computer 3 may include an error-tolerant quantum computer, an NISQ device, or both. The quantum computer 3 of this embodiment is a gate type. Each component will be further described below.

[0022] <Communication Unit 31> The communication unit 31 is used by the quantum computer 3 to communicate information with other information processing devices (including classical computers, quantum computers, or computers that combine these) or peripheral devices.

[0023] <Quantum Memory 32> The quantum memory 32 stores various pieces of information defined above. In particular, the quantum memory 32 stores various programs that can be read by the quantum processor 33, which will be described next. For example, the quantum memory 32 stores, as needed, information on the physical properties of a specific material related to the calculations of the quantum computer 3. The quantum memory 32 includes a plurality of quantum bits 320. The quantum bits 320 can be implemented using any method, such as nuclear spins, photons, ions, atoms, quantum dots, or superconducting Josephson devices. The quantum bits 320 include a computational quantum bit 321 and an ancillary bit 322. The computational quantum bit 321 functions as a quantum bit that represents the configuration of electrons contained in a substance, for example. Note that the quantum memory 32 may also include a classical memory device.

[0024] <Quantum Processor 33> The quantum processor 33 processes and controls the overall operations related to the quantum computer 3. The quantum processor 33 realizes various functions related to the quantum computer 3 by reading out a program stored in the quantum memory 32 or a predetermined program input via the communication unit 31. Note that while Fig. 3 shows a single quantum processor 33, in practice this is not limited to this, and multiple quantum processors 33 may be implemented for each function. A combination of these may also be used.

[0025] Quantum processor 33 is configured to be able to perform various quantum operations on quantum bits 320 that can be implemented on a quantum circuit. For example, the quantum circuit is configured to define a series of quantum operations on quantum bits 320. Quantum operations include, for example, quantum gate operations and observation operations. A quantum gate operation corresponds to a unitary operation on the quantum state of quantum bits 320. An observation operation corresponds to a projection operation on the quantum state of quantum bits 320.

[0026] <User Terminal 4> Next, the hardware configuration of the user terminal 4 will be described. Fig. 4 is a block diagram showing the hardware configuration of the user terminal 4. The user terminal 4 includes a communication unit 41, a memory 42, a processor 43, a display unit 44, and an input unit 45, and these components are electrically connected via a communication bus 40 inside the user terminal 4. The description of the communication unit 41, the memory 42, and the processor 43 is omitted because they are the same as the description of each unit in the information processing device 2.

[0027] <Display Unit 44> The display unit 44 may be included in the housing of the user terminal 4 or may be externally attached. The display unit 44 displays a graphical user interface (GUI) screen that can be operated by the user. This is preferably implemented by selectively using display devices such as a CRT display, a liquid crystal display, an organic EL display, or a plasma display depending on the type of user terminal 4.

[0028] <Input Unit 45> The input unit 45 may be included in the housing of the user terminal 4, or may be externally attached. For example, the input unit 45 may be implemented as a touch panel integrated with the display unit 44. A touch panel allows the user to input tapping, swiping, and the like. Of course, a switch button, a mouse, a QWERTY keyboard, or the like may be used instead of a touch panel. That is, the input unit 45 accepts an operation input made by the user. The input is transferred as a command signal to the processor 43 via the communication bus 40, and the processor 43 can execute predetermined control or calculation as necessary.

[0029] 2. Functional Configuration of the Processor 23 In this section, the functional configuration of the processor 23 of the information processing device 2 according to this embodiment will be described. Fig. 5 is a block diagram showing the functional configuration of the processor 23. The processor 23 includes an acquisition unit 231, a division unit 232, a calculation unit 233, a circuit generation unit 234, and an output unit 235.

[0030] <Acquisition unit 231> The acquisition unit 231 is configured to be able to acquire various pieces of information related to quantum computing from the quantum computer 3 and the user terminal 4. The acquisition unit 231 is configured to be able to acquire various pieces of information by reading out various pieces of information stored in a storage area that is at least a part of the memory unit 22 and writing the read out information to a working area that is at least a part of the memory unit 22. The storage area is, for example, an area of ​​the memory unit 22 that is implemented as a storage device such as an SSD. The working area is, for example, an area that is implemented as a memory such as a RAM.

[0031] <Dividing Unit 232> The dividing unit 232 is configured to divide a continuous interval in which a certain function is defined into a plurality of partial intervals based on various information.

[0032] <Calculation Unit 233> The calculation unit 233 is configured to calculate parameters necessary for generating a quantum circuit, such as a division parameter, based on various information and conditions.

[0033] <Circuit Generation Unit 234> The circuit generation unit 234 is configured to generate various quantum circuits based on the information calculated by the calculation unit and the like.

[0034] <Output Unit 235> The output unit 235 is configured to be able to output various types of information. The information can be presented to the user via the display unit 44 of the user terminal 4 or another device. In such a case, for example, the output unit 235 controls the display unit 44 of the user terminal 4 to display visual information such as a screen, an image including a still image or a video, an icon, or a message. The output unit 235 may generate only rendering information for displaying the visual information on the user terminal 4. Note that the output unit 235 may present the output information to the user without going through the user terminal 4 or another device.

[0035] 3. Information Processing In this chapter, the flow of information processing executed in the information processing system 1 described above will be described.

[0036] 3.1. Overview of Information Processing FIG. 6 is an activity diagram showing an overview of information processing executed in the information processing system 1. Note that the information processing may include any exception handling not shown in the activity diagram. Exception handling includes interruption of the information processing or omission of each process. Selection or input performed in the information processing may be based on a user operation or may be performed automatically without relying on a user operation.

[0037] [Activity A1] First, in activity A1, the acquisition unit 231 acquires a model function V1, a tolerance δ, and an order set {p}.

[0038] The model function V1 outputs a scalar value for an input and is defined in at least one continuous interval. The model function V1 may be a continuous function throughout the continuous interval or a function with discontinuities. For convenience of explanation, the model function V1 is assumed to be a one-variable function expressed as y = V1(x), in which an output y is obtained based on one variable x, and is assumed to be a continuous function (e.g., a local function) whose domain is one continuous interval [0, L] defined by the variable x. L denotes the interval length of the continuous interval [0, L].

[0039] The degree set {p} is a set of candidates for the degree p of the piecewise polynomial V2, and can be obtained in the form of, for example, a sequence or a list. The piecewise polynomial V2 is an approximate function of the model function V1, obtained by dividing the domain of the model function V1 into at least one partial interval (hereinafter also referred to as a divided interval) and performing polynomial approximation based on spline interpolation for each partial interval.

[0040] The allowable error δ is a scalar value required for the piecewise polynomial V2 that approximately represents the model function V1, and is set to a value equal to or greater than an upper bound function depending on the analysis target for performing analysis using the model function V1. The upper bound function is a function (value) that indicates the upper bound of the error between the model function V1 and the piecewise polynomial V2. The upper bound function may be defined using one or more mathematical expressions, or may be defined using a lookup table or the like. An example of a method for defining the upper bound function will be described later.

[0041] [Activity A2] Next, in activity A2, the processor 23 determines the number of elements in the degree set {p}. If the number of elements is 1, the processor 23 proceeds to activity A100. If the number of elements is 2 or more, the processor 23 proceeds to activity A6. First, the process when the process proceeds to activity A100 will be described. Activity A100 is a process for applying spline interpolation so that the degree of each piecewise polynomial V2 in the divided intervals divided from the continuous interval [0, L] becomes a common value (specific degree p1). As a result, the piecewise polynomial V2 is obtained as a constant-degree polynomial. Activity A100 includes activities A3 to A5.

[0042] [Activity A3] In activity A3, the processor 23 selects the only order p included in the order set {p} as the only candidate for the specific order p1. In other words, if the number of elements in the order set {p} is 1, the calculation unit 233 fixes the specific order p1 to the value of the only candidate order p throughout the entire continuous interval [0, L]. The processor 23 then determines whether the value of the specific order p is 1 or 2 or greater. Note that if the value of the candidate for the specific order p is 0, the processor 23 determines that there is an error in the manner in which the candidate order p was obtained, and may discontinue this information processing, for example.

[0043] [Activity A4] If the value of the specific order p1 is 2 or greater, in activity A4, processor 23 performs processing based on a high-order piecewise polynomial having terms of order 2 or greater. As a result, output unit 235 outputs information (e.g., coefficients for each order) that defines piecewise polynomial V2 having terms of order 2 or greater that is approximated to model function V1 within a range that satisfies the tolerance δ. Then, circuit generation unit 234 generates a quantum circuit configured to output the state of computation qubit 321 that represents piecewise polynomial V2, based on the output information.

[0044] [Activity A5] On the other hand, if the value of the specific degree p1 is 1, in activity A5, processor 23 performs processing based on a linear piecewise polynomial that does not have second- or higher-order terms. As a result, output unit 235 outputs information (e.g., values ​​at the endpoints of the divided intervals of model function V1) that defines a linear piecewise polynomial V2 that is approximated to model function V1 within a range that satisfies the tolerance δ. Then, based on the output information, circuit generation unit 234 generates a quantum circuit configured to output the state of computation qubit 321 that represents piecewise polynomial V2. As described below, in this embodiment, the algorithm for generating a quantum circuit in activity A4 is different from the algorithm for generating a quantum circuit in activity A5, but the algorithm for generating a quantum circuit in activity A5 can also be the same as the algorithm for generating a quantum circuit in activity A4.

[0045] [Activity A7] After processing activity A4 or activity A5, processor 23 executes processing based on the generated quantum circuit in activity A7. This allows for obtaining computation qubit 321 of quantum computer 3 that takes a quantum state corresponding to piecewise polynomial V2. Processor 23 may further perform a quantum operation corresponding to a physical quantity on computation qubit 321 that takes such a quantum state, and perform a quantum operation (projection operation) such as observing the state after the quantum operation.

[0046] [Activity A8] Then, in activity A8, the acquisition unit 231 acquires the result of the processing in activity A7. Based on the obtained result, the calculation unit 233 may calculate various information about the quantum state corresponding to the piecewise polynomial V2 (e.g., expected values ​​of physical quantities in the state). Then, the information processing system 1 ends this information processing.

[0047] [Activity A6] On the other hand, if the number of elements in the degree set {p} determined in activity A2 is two or more, processor 23 proceeds to activity A6 and performs processing based on the variable piecewise polynomial. Activity A100 obtains a piecewise polynomial V2 having a common degree for each divided interval, whereas activity A6 selects an optimal specific degree p1 for each interval and obtains a piecewise polynomial V2 in which the degree is allowed to differ for each interval. By performing activity A6, output unit 235 outputs information for identifying piecewise polynomial V2 (e.g., the division manner of the continuous interval [0, L], the specific degree p1 for each divided interval, the coefficients of piecewise polynomial V2 for each divided interval, etc.), and circuit generation unit 234 generates a quantum circuit configured to output the state of computation qubit 321 representing piecewise polynomial V2 based on the information for identifying piecewise polynomial V2. In this embodiment, the algorithm for generating the quantum circuit used in activity A6 is the same as the algorithm for generating the quantum circuit used in activity A4.

[0048] After activity A6, the processor 23 sequentially executes the processing of activity A7 and activity A8, in the same way as if the processing had passed through activity A100. Thereafter, the information processing system 1 ends this information processing.

[0049] 3.2. Example of Processing Based on High-Order Piecewise Polynomials (Activity A4) Next, an example of processing based on high-order piecewise polynomials (Activity A4) will be described. Figure 7 is an activity diagram showing an example of the flow of processing based on high-order piecewise polynomials (Activity A4). This processing can be performed when the number of elements in the degree set {p} is 1 and the specific degree p1 is fixed to a value of 2 or greater.

[0050] As shown in FIG. 7, first, in activity A41, the calculation unit 233 calculates an upper bound function, a tolerance δ, and a (p1+1)-th derivative V1 of the model function V1. （ｐ１＋１） and the norm of the division parameter m. With this configuration, the calculation load for obtaining the division parameter m can be reduced.

[0051] The upper bound function indicates the upper bound of the maximum difference between the model function V1 and the piecewise polynomial V2 in the continuous interval [0, L]. The upper bound function does not depend on the variables for determining the piecewise polynomial V2, but on the allowable error δ and the (p1+1)th derivative V1 of the model function V1 corresponding to the specific order p1. （ｐ１＋１） and the division parameter m.

[0052] Here, an example of an upper bound function will be described. First, a method for evaluating the error between the model function V1 and the piecewise polynomial V2 will be described. For convenience of explanation, let x_j be the representative value of the variable x in the j-th divided interval, and let N be the number of divided intervals.

[0053] For example, when the tolerance δ represents the degree to which a local deviation between the model function V1 and the piecewise polynomial V2 is tolerated, the error evaluation between the model function V1(x) and the piecewise polynomial V2 can be formulated as the maximum value of the representative values ​​{x_j: j=0, 1, 2, 3, ..., N-1}, for example, as follows:

[0054] The left side of the above equation represents the error between V1 and V2, and the right side of the above equation represents the error between V1 and V2 converted into an error as a continuous function.

[0055] It is preferable to set an upper bound function so that the right side of the above formula is guaranteed to be equal to or smaller than the allowable error δ. When the piecewise polynomial V2 is obtained using spline interpolation, the upper bound function is determined by the interval length L of the continuous interval [0, L] and the infinity norm |||| ∞ and the optimal constant C of the spline interpolation corresponding to the specific degree p1. ｐ１ Using the above, it can be expressed as the following equation (1).

[0056] The optimal constant C that minimizes the value of the upper bound function ｐ１ The value of is analytically obtained according to the spline interpolation algorithm to obtain the piecewise polynomial V2. Therefore, the optimal constant C ｐ１ is set to a value equal to or greater than the value at which the value of the upper bound function is smallest. The allowable error δ can be set to a value equal to or greater than the upper bound function defined in equation (1). In other words, the upper bound function does not need to coincide with the upper limit of the error between V1 and V2.

[0057] Here, when there is one candidate for the order p and the value of the order p is substantially fixed, the minimum division parameter m that satisfies the above formula (1)=the allowable error δ can be expressed as follows:

[0058] Here, ceil[·] in formula (2) represents a ceiling function. As a result, the division parameter m is minimized within a range that satisfies the allowable error δ, and therefore, a division with appropriate approximation accuracy for the allowable error δ can be obtained. In this embodiment, the calculation unit 233 calculates the division parameter m using the above formula (2).

[0059] [Activity A42] Next, in activity A42, the dividing unit 232 may divide the continuous section [0, L] into M equal primary divided sections based on the calculated division parameter m. The number M of primary divided sections is 2 ｍIt is arbitrary as long as it is configured to be equal to or smaller than the allowable error δ. Preferably, the number of primary division sections M=2 ｍ is.

[0060] [Activity A43] Then, in activity A42, the dividing unit 232 may merge two adjacent linear divided intervals if the value of the upper bound function in the two adjacent linear divided intervals is equal to or less than the allowable error δ. This divides the continuous interval [0, L] into divided intervals. With this configuration, the model function V1 can be approximately implemented on a quantum circuit as a piecewise polynomial of a smaller number of divided intervals.

[0061] As an example, the division unit 232 obtains the final divided interval from the primary divided interval by integrating the primary divided intervals in the following procedure. Note that, here, it is assumed that each primary divided interval is obtained by equally dividing the continuous interval [0, L]. It is also assumed that an index from 0 to M-1 is assigned in order to each point at which the continuous interval [0, L] is divided. For ease of explanation, the point corresponding to each index j is referred to as the jth division point. (Step 1) Let j_1 = 0 and j_2 = 1. (Step 2) Increment the value of j_2 by 1. (Step 3) Increment the value of the interval [j_1 x L / 2 ｍ , j_2×L / 2 ｍ ] the uniform norm (maximum norm) of the (p1+1)th derivative of the model function V1 in ｊ＿１，ｊ＿２ （ｐ１＋１） || ∞ (Step 4) Determine whether the uniform norm satisfies the following relational expression (3). (Step 5) If the following relational expression (3) is satisfied, return to (Step 2). If not, store (j_2-1) in the storage unit 22, update j_1 to j_2-1, and update j_2 to j_1+1, and then return to (Step 2). In this case, M ～ (≦2 ｍ ) sparse division into divided intervals is obtained according to the values ​​stored in the storage unit 22.

[0062] As a result, the number of divisions M corresponding to the division parameter m is ～ ≦2 ｍIn other words, the dividing unit 232 divides the continuous interval [0, L] into 2 intervals where the upper bound function is equal to or smaller than the allowable error δ, based on one specific order p1 selected from the order set {p} and the division parameter m indicating the upper limit of the number of divisions of the continuous interval [0, L]. ｍ Divide into the following number of intervals:

[0063] [Activity A44] Next, in activity A44, the calculation unit 233 calculates a piecewise polynomial V2 by optimizing a p1-degree polynomial corresponding to a specific degree p1 to the model function V1 for each divided section using a predetermined spline interpolation. Here, a common specific degree p1 is obtained for each divided section. For example, the calculation unit 233 calculates a piecewise polynomial V2 by optimizing a p1-degree polynomial corresponding to a specific degree p1 to the model function V1 for each divided section using a predetermined spline interpolation. ～ As individual knots, M ～ of the divided sections (M ～ Using the (p+1) division points, the polynomial coefficients for each division interval are calculated by applying the p1-th order spline algorithm. [Activity A45] Based on the calculated piecewise polynomial V2, the circuit generation unit 234 generates a quantum circuit representing a diagonalized unitary operator corresponding to the piecewise polynomial V2. The quantum circuit is configured to operate on n computation qubits 321 encoded to represent positions in the continuous interval [0, L], and the operation quantities of the quantum gate operations included in the quantum circuit are determined based on the coefficients of the piecewise polynomial V2. This configuration makes it possible to obtain a quantum circuit that implements the piecewise polynomial V2 approximated with appropriate division intervals according to the tolerance δ, thereby improving the efficiency of the process for obtaining a quantum circuit, such as reducing computational resources and shortening computation time. The number n of computation qubits 321 corresponds to the resolution for approximately representing the continuous interval [0, L] as a discrete value and is also referred to as a grid parameter.

[0064] Here, it is assumed that the value of the specific order p1 is fixed to 2 or greater, and the circuit generation unit 234 generates quantum circuit 5 as a first quantum circuit. Fig. 8 is a diagram showing an example of a quantum circuit that is generated when the value of the specific order p1 is fixed to 2 or greater. For convenience of explanation, it is assumed here that n computational qubits 321 are allocated from quantum memory 32, and each of the observable states of a group of quantum bits configured by the n computational qubits 321 is encoded to represent a position in the continuous interval [0, L], and at least some of these are encoded to correspond to the division points of the primary division interval (and at least some of these are encoded to correspond to the division points of the final division interval).

[0065] As shown in Fig. 8, the quantum circuit 5 is configured to operate on n computation qubits 321 and one auxiliary bit 322. The auxiliary bit 322 is used to indicate a certain partial continuous interval [0, L] in the continuous interval [0, L] as an entire state together with the n computation qubits 321. The quantum circuit 5 operates by repeatedly executing M ～ Quantum operations 51 (51-1 to 51-M ～ Each quantum operation 51 is configured to adjust the weight of the state of a group of quantum bits constituted by the computation quantum bits 321 based on the coefficients of the calculated piecewise polynomial V2. As an example, each quantum operation 51 includes a phase gate operation 511 and a quantum comparator 512. Hereinafter, for convenience of explanation, the phase gate operation 511 will be referred to as a polynomial phase gate 511.

[0066] The polynomial phase gate 511 is configured to operate on n computation quantum bits 321 corresponding to each of the divided intervals. Note that in this embodiment, the polynomial phase gate 511 operates only on the n computation quantum bits 321, and does not operate on the auxiliary bits 322. The polynomial phase gate 511 is configured to adjust the weights of states corresponding to a partial continuous interval [0, L] specified in consideration of the auxiliary bits 322, in accordance with the calculated coefficients of each interval. Here, the polynomial phase gate 511 is configured to adjust the weights of states corresponding to a partial continuous interval [0, L] from an end point (e.g., 0 or L) of the continuous interval [0, L] to one of the division points defining the final divided interval, which is represented using the auxiliary bits 322. This configuration can reduce the processing load on the quantum circuit 5 compared to adjusting the weights of states corresponding to each of the final divided intervals. For example, the operation amount of the polynomial phase gate 511 is the value of the section corresponding to the polynomial phase gate 511 in the piecewise polynomial V2 and the value of the section adjacent to the section (function f ｊ ) and the difference (f ｊ－１ -f ｊ ) can be set based on the above. With this configuration, high-order piecewise polynomial approximation can be implemented on a quantum circuit more efficiently within the range of the tolerance δ.

[0067] 9 is a diagram showing an example of the configuration of the polynomial phase gate 511 when n=4 and p1=2. In this case, the piecewise polynomial V2 is approximated by a second-order polynomial, so the coefficient a ｋ (k=0, 1, 2). The global phase of the state of the computation qubit 321 shown in FIG. 9 is specified by exp(−i×a ０ ) where i is the imaginary unit. As shown in FIG. 9, the polynomial phase gate 511 is expressed using a Z gate operation (and a controlled Z gate operation), and the operation amount is a coefficient a ｋ and the unit of length represented by the computation qubit 321, l=L / N (where N=2 ｎ ) The polynomial phase gate 511 can be determined by, for example, the unitary operator U ｐｈ It is expressed as:

[0068] |j> represents the j-th state among the eigenstates formed by n computation qubits 321. g represents a piecewise polynomial V2 in a certain interval, and its coefficients are a ｊ In the formula, x is a variable representing a position in the continuous interval [0, L]. For example, when p=2, the polynomial phase gate 511 is expressed as follows:

[0069] As shown in FIG. 9, the polynomial phase gate 511 performs Z gate operation as a Z rotation gate operation R ｚ can be implemented as an approximate polynomial phase gate 511a when the global phase is negligible by replacing

[0070] The quantum comparator 512 is configured to operate on m computation qubits 321, which are the value of the division parameter m, among the n computation qubits 321, and one auxiliary bit 322. The quantum comparator 512 is configured to change the state of the auxiliary bit 322 in accordance with the states of the m computation qubits 321 (e.g., eigenstates of a quantum bit group composed of the m computation qubits 321), thereby causing the polynomial phase gate 511 to operate on components of the states of the n computation qubits 321 corresponding to each of the final division intervals. With this configuration, high-order piecewise polynomial approximation can be implemented on a quantum circuit more efficiently within the range of the allowable error δ.

[0071] 10 is a diagram showing an example of the configuration of a quantum comparator 512 using a quantum Fourier transform (QFT) operation. As shown in FIG. 10, the quantum comparator 512 includes a first gate operation 5121 that operates on multiple computation qubits 321 and one ancillary bit 322, and a second gate operation 5122 that operates only on the multiple computation qubits 321 after the first gate operation 5121. Each of the gate operations 5121 and 5122 includes a pair of QFT operations U ＱＦＴ , U † ＱＦＴ and the pair of QFT operations U ＱＦＴ , U † ＱＦＴThe amount of operation of the Z gate operation is determined by the parameter k ｌ = y ｌ / (L / M) (where l is 0 to M) ～ Quantum comparator 512 determines the state of output computation qubit 321 by comparing it with the state of input computation qubit 321 (|j ～ >) and j ～ <k ｌ If j is ～ ≧k ｌ Change the state of the auxiliary bit 322 (|j ～ <k ｌ >). That is, the comparison result of the two values ​​is configured to be output as the state of the auxiliary bit 322. This makes it possible to adjust the weight of the state corresponding to a specific section by using a control gate operation in which the polynomial phase gate 511 operates according to the state of the auxiliary bit 322.

[0072] In addition, the processor 23 may function as an abort unit to abort the generation of a quantum circuit (e.g., quantum circuit 5) when the calculated division parameter m is greater than the number n of computational qubits 321. This configuration can prevent the waste of forcibly generating a quantum circuit when computational resources are insufficient. In this case, the processor 23 may further compare the division parameter m with the number n of allocated computational qubits 321, and, when the division parameter m is greater than the number n of computational qubits 321, may function as an allocation unit to reallocate the computational qubits 321 so that the number n of computational qubits 321 is equal to or greater than the division parameter m. This configuration can improve the efficiency of generating quantum circuits. Furthermore, the processing based on the high-order piecewise polynomial described in this section can also be applied when p1 = 1.

[0073] Next, an example of the results of a comparison between the model function V1 and the piecewise polynomial V2 and the division intervals when processing based on a high-order piecewise polynomial is performed will be described. FIG. 11 is a diagram illustrating an example of the results of processing based on a high-order piecewise polynomial. Note that "Exact" in the diagram corresponds to the model function V1, "Approx." corresponds to the piecewise polynomial V2, and "sample." is the division point of the final division interval. The interval between two division points corresponds to one division interval. As shown in FIG. 11, the model function V1 and the piecewise polynomial V2 can be obtained with relatively good approximation accuracy. Furthermore, in regions where the amount of change in the model function V1 is small, the length of the division interval is shorter than in regions where the change in the model function V1 is large (e.g., x = 7.5 to 12.5). In this way, this information processing makes it possible to obtain a piecewise polynomial V2 with good approximation accuracy within the range of the allowable error δ while reducing the number of division intervals (in other words, the number of divisions).

[0074] 3.3 Example of Processing Based on a First-Order Piecewise Polynomial (Activity A5) Next, we will explain an example of processing based on a first-order piecewise polynomial (activity A5) that is performed when the value of the specific degree p1 is fixed to 1. Figure 12 is an activity diagram showing an example of the flow of processing based on a first-order piecewise polynomial (activity A5).

[0075] [Activity A51] As shown in Fig. 12, first, in activity A51, the calculation unit 233 calculates the division parameter m in the same procedure as in activity A41.

[0076] [Activity A52] Next, in activity A52, the dividing unit 232 divides the continuous section [0, L] into equal divided sections. Here, the dividing unit 232 divides the continuous section [0, L] into 2 ｍ Divide it into equal intervals.

[0077] [Activity A53] After that, the circuit generation unit 234 generates quantum circuit 6 as a second quantum circuit.

[0078] Fig. 13 is a diagram showing an example of a quantum circuit when the value of the specific degree p1 is fixed to 1. As shown in Fig. 13, the quantum circuit 6 includes a diagonal unitary operation 61 and a differential action operation 62 as (n-m) control gate operations.

[0079] The diagonal unitary operation 61 is an oracle operator that implements a diagonal unitary matrix, for example, the operator U Ｍ It can be defined as:

[0080] In the above formula, V means the model function V1, and x ～ ｋ = kL / 2 ｍ represents the position of a point (for example, the kth division point) in the kth continuous interval [0, L].

[0081] The differential action operation 62 uses each of (n-m) computational qubits 321 out of the n computational qubits 321 as a control bit, and uses the other m computational qubits 321 as target bits. Furthermore, each of the differential action operations 62 (62-1 to 62-(n-m)) acts on a state corresponding to each part of the divided interval, thereby linearly interpolating the phases of the diagonal components represented by the m computational qubits 321 according to the values ​​at the endpoints of the divided interval of the model function V1 (for example, the values ​​at the divided points). This configuration can further improve the computational efficiency when obtaining a piecewise polynomial with a linear function. Each of the differential action operations 62 acts on the state corresponding to each part of the divided intervals, for example, by adjusting the states of the 2nd, 4th, 6th, and 8th divided intervals when n=3 and m=1 and the control bit is the top bit, and adjusting the states of the 3rd, 4th, 7th, and 8th divided intervals when the control bit is the second bit, depending on the value of the model function V1 at the divided point.

[0082] 14 is a diagram showing a configuration example of the differential action operation 62. As shown in FIG. 14, the differential action operation 62 is, for example, an operator U Ｍ （ｊ） , U Ｍ （ｊ）†and an increment operator U as a control gate operation acting on m computation qubits 321 depending on the states of n−m computation qubits 321. ＋１ and the decremental action operator U ＋１ † In FIG. 14, the difference operation 62 can be defined using the operator W ｊ (j=1 to nm).

[0083] Operator U Ｍ （ｊ） , U Ｍ （ｊ）† is the operator U Ｍ is an oracle operator that implements diagonal unitary matrices similarly to

[0084] Increment operator U ＋１ and the decrement operator U ＋１ † is a gate operation that transitions the states of n computation qubits 321 from the kth state to the k+1th state or the k−1th state, respectively, and is defined as follows:

[0085] FIG. 15 shows the increment operator U ＋１ As shown in FIG. 15, the increment operator U ＋１ is a pair of QFT operations U ＱＦＴ , U † ＱＦＴ and the Z-gate operation acting on each computation quantum bit 321. The amount of operation of the Z-gate operation is determined independently of the coefficients of the piecewise polynomial V2. Also, as shown in FIG. 15, the increment operator U ＋１ In the case where the global phase can be ignored, the Z-rotation gate operation R ｚ It can also be implemented using the decrement operator U －１ is the increment operator U ＋１ Since it can be implemented as a Hermitian operator, the explanation will be omitted.

[0086] The quantum circuit 6 configured in this way can adjust the weights of the states corresponding to each divided section all at once, unlike the quantum circuit 5 obtained from the processing based on the above-mentioned high-order piecewise polynomial. Therefore, when the allowable error δ is relatively large in the case of p1=1, it is possible to reduce the number of gate operations and the circuit depth compared to when the quantum circuit 5 is used. Note that the order of the circuit depth is O(δ －１／２ ) In this case, the auxiliary bit 322 is not required, so it is also possible to reduce the number of quantum bits 320.

[0087] The quantum circuit 6 may operate on the auxiliary bits 322. In this case, a piecewise polynomial V2 corresponding to a more general model function V1 can be output as a quantum state. Furthermore, the processor 23 may, as an aborting unit, abort the generation of a quantum circuit (e.g., the quantum circuit 6) when the calculated partitioning parameter m is greater than the number n of computational qubits 321. This configuration can prevent the waste of forcibly generating a quantum circuit when computational resources are insufficient. In this case, the processor 23 may further, for example, compare the partitioning parameter m with the number n of allocated computational qubits 321, and, as an allocating unit, reallocate the computational qubits 321 so that the number n of computational qubits 321 is equal to or greater than the partitioning parameter m when the partitioning parameter m is greater than the number n of computational qubits 321. This configuration can improve the efficiency of generating quantum circuits.

[0088] Furthermore, in processing based on a linear piecewise polynomial, processor 23 may generate quantum circuit 6 according to the above-described procedure when (number n of computational qubits 321)>(partition parameter m), and may generate quantum circuit 7 that outputs a quantum state corresponding to piecewise polynomial V2 using a Walsh operator when (number n of computational qubits 321)≦(partition parameter m). Figure 16 is a diagram showing an example configuration of quantum circuit 7 corresponding to a Walsh operator.

[0089] Next, an example of the comparison result between the model function V1 and the piecewise polynomial V2 when processing based on a linear piecewise polynomial will be described. FIG. 17 is a diagram showing an example of the result of processing based on a linear piecewise polynomial. In the figure, "Exact" corresponds to the model function V1, and "Approx." corresponds to the piecewise polynomial V2. In this processing, the continuous interval is 2 ｍ Since the model function V1 is divided into equal intervals, the division points are omitted. Portions of the model function V1 corresponding to each of the intervals are approximated using a linear function. As shown in FIG. 17, the model function V1 and the piecewise polynomial V2 can be obtained with relatively good approximation accuracy. In this way, this information processing makes it possible to obtain the piecewise polynomial V2 with good approximation accuracy within the range of the allowable error δ while reducing the number of intervals (in other words, the number of divisions).

[0090] 3.4 Example of Processing Based on Variable Piecewise Polynomials (Activity A6) Next, an example of processing based on variable piecewise polynomials (activity A6) that is performed when the number of elements in the degree set {p} is 2 or more will be described. Figure 18 is an activity diagram showing an example of the flow of processing based on variable piecewise polynomials.

[0091] [Activity A61] First, in activity A61, the acquisition unit 231 acquires candidates for the division parameter m that are equal to or less than the number n of computational quantum bits 321. The candidates for the division parameter m may be specified in the form of a sequence or list, for example, {m}={1, 2, 3, ..., n}. Then, the processor 23 executes the processes of activities A62 to A64, described below, for each of the acquired candidates for the division parameter m.

[0092] [Activity A62] First, in activity A62, the processor 23 identifies an allowable value for the degree p of the piecewise polynomial V2 from among the candidate degrees p, based on the allowable error δ and the like, for each candidate for the division parameter m. The allowable value for the degree p is a candidate value for the degree p at which the value of the upper bound function is equal to or less than the allowable error δ. The allowable value for the degree p is the upper limit for the degree p of the entire piecewise polynomial V2. In this embodiment, the processor 23 determines the smallest degree pk at which the value of the upper bound function is equal to or less than the allowable error δ as the only allowable value for the degree p. In the k-th division interval, the smallest degree pk can be defined, for example, as follows:

[0093] [Activity A63] Next, the dividing unit 232 divides the continuous section [0, L] into two ｍ At this time, if the number of elements in the degree set {p} is two or more and there is only one permissible value of the degree p for each interval (for example, as described above, when the smallest degree pk is determined as the only permissible value of the degree p), the dividing unit 232 may first divide the continuous interval [0, L] into equal primary divided intervals.

[0094] Then, the dividing unit 232 may divide the continuous interval [0, L] into divided intervals by merging two adjacent primary divided intervals if the allowable values ​​of the degree p in the two adjacent primary divided intervals are the same and the value of the upper bound function is equal to or less than the allowable error δ. With this configuration, it is possible to generate a quantum circuit that implements a piecewise polynomial with a smaller number of divided intervals within a range that satisfies the allowable error δ. Note that the merging of the primary divided intervals is performed, for example, according to a procedure similar to the procedure described above.

[0095] [Activity A64] Next, in activity A64, the division unit 232 calculates the value of the objective function F based on the division parameter m, the continuous interval [0, L], and the degree pk. The objective function F is calculated by finding the optimal division parameter m from among the candidates for the division parameter m. ＊ The objective function F is a function for determining the degree p, and is defined so that the input variables are the tolerance of the specified degree p, the division parameter m, and the division mode of the continuous interval [0, L]. ＊is optimal, for example, depending on the calculation time, processing load, tolerance δ, etc. In this way, the processor 23 determines the order pk and the division interval for a certain division parameter m, and can obtain the value of the objective function for these elements.

[0096] [Activity A65] After the value of the objective function F is obtained for each candidate of the division parameter m in this way, in activity A65, the processor 23 selects the optimal division parameter m from the candidates of the division parameter m based on the objective function. ＊ Determine.

[0097] [Activity A66] Next, in activity A66, the calculation unit 233 calculates the optimal division parameter m ＊ and m ＊ For example, the calculation unit 233 calculates a piecewise polynomial V2 based on the determined division parameter m ＊ The calculation unit 233 determines a degree p equal to or greater than pk as a tolerance value corresponding to pk as a specific degree p1 of the piecewise polynomial in each divided interval. Thereafter, the calculation unit 233 calculates a piecewise polynomial V2 by optimizing the p1-degree polynomial corresponding to the specific degree p1 to the model function V1 for each divided interval using spline interpolation. With this configuration, a piecewise polynomial in which the optimal specific degree p1 is set for each interval can be obtained from among the candidate degrees p, making it possible to generate a quantum circuit capable of implementing a piecewise polynomial with higher qualitative approximation accuracy within a range that satisfies the tolerance δ.

[0098] [Activity A67] Then, based on information about the piecewise polynomial V2 calculated in activity A66 (e.g., coefficients in each divided interval of the piecewise polynomial V2, etc.), processor 23 generates quantum circuit 5 that can output the piecewise polynomial V2 as the quantum state of computational quantum bit 321. Note that the algorithm for generating quantum circuit 5 based on the piecewise polynomial V2 obtained by processing based on the variable piecewise polynomial is similar to the algorithm for generating quantum circuit 5 based on the piecewise polynomial V2 obtained by processing based on a high-order piecewise polynomial, and therefore detailed description thereof will be omitted.

[0099] <Others> The above-described embodiment can be appropriately implemented in the following aspects, for example, within the scope of technical inconsistency.

[0100] The model function V1 is not limited to this and may be any function, for example, a multivariate function that explicitly depends on multiple variables x1 and x2. In this case, the piecewise polynomial V2 can be obtained by sequentially performing the above-described single-variable processing on each of the multiple variables x1 and x2.

[0101] A part of the processing of the processor 23 may be converted into a calculation algorithm that can be executed by a quantum computer, and then the quantum computer 3 may be made to execute the calculation algorithm.

[0102] The information processing device 2 may be a classical computer, a quantum computer, or a combination thereof.

[0103] The information processing system 1 can be applied to various information processes related to quantum computation, such as quantum measurement and quantum communication.

[0104] The above-described embodiment is not limited to the information processing system 1, and may be an information processing method or an information processing program. The information processing method includes each step of the information processing system 1. The information processing program causes at least one computer to execute each step of the information processing system 1.

[0105] The information processing system 1 and the like may be provided in the following aspects.

[0106] (1) An information processing system, comprising at least one processor, configured to execute a program for executing the following steps: in an acquisition step, a model function V1, a tolerance δ required for a piecewise polynomial V2 that approximately represents the model function V1, and an order set {p} that is a set of candidates for the order p of the piecewise polynomial V2 are acquired; wherein the model function V1 outputs a scalar value in response to an input and is defined by at least one continuous interval; in a division step, based on one specific order p1 selected from the order set {p} and a division parameter m that indicates an upper limit of the number of divisions of the continuous interval, the continuous intervals are divided into two such that an upper bound function that indicates an upper bound of the maximum value of the difference between the model function V1 and the piecewise polynomial V2 in the continuous interval is equal to or smaller than the tolerance δ; ｍ The upper bound function does not depend on the variables for determining the piecewise polynomial V2, and is determined by the tolerance δ and the (p1+1)th derivative V1 of the model function V1 corresponding to the specific order p1. （ｐ１＋１） and the division parameter m, wherein in the approximation formula calculation step, for each of the divided sections, a p1-degree polynomial corresponding to the specific degree p1 is optimized to the model function V1 using a predetermined spline interpolation to calculate the piecewise polynomial V2, and in the circuit generation step, a quantum circuit representing a diagonalized unitary operator corresponding to the piecewise polynomial V2 is generated based on the calculated piecewise polynomial V2, wherein the quantum circuit is configured to act on n computation qubits encoded to represent positions in the continuous sections, and an operation amount of a quantum gate operation included in the quantum circuit is determined based on a coefficient of the piecewise polynomial V2.

[0107] According to this configuration, it is possible to obtain a quantum circuit that implements the piecewise polynomial V2 that is approximated in an appropriate division interval according to the allowable error δ, thereby making it possible to improve the efficiency of the process for obtaining a quantum circuit, such as reducing computational resources and shortening computation time.

[0108] (2) In the information processing system described in (1) above, when the number of elements of the order set {p} is 1, the division parameter calculation step further includes fixing the specific order p1 to the value of the only candidate order p in the entire continuous section, and calculating the upper bound function, the allowable error δ, and the (p1+1)-th derivative V1 of the model function V1. （ｐ１＋１） and a norm of

[0109] With this configuration, the calculation load for obtaining the division parameter m can be reduced.

[0110] (3) In the information processing system described in (2) above, when the value of the specific order p1 is fixed to 2 or more, the circuit generation step generates a first quantum circuit as the quantum circuit, and the first quantum circuit comprises a phase gate operation that acts on the n computation quantum bits corresponding to each of the division intervals, and a quantum comparator that acts on m computation quantum bits, which are the value of the division parameter m, among the n computation quantum bits, and one auxiliary bit, and the quantum comparator is configured to change the state of the auxiliary bit in accordance with the state of the m computation quantum bits, thereby causing the phase gate operation to act on the n computation quantum bits having states corresponding to the division interval.

[0111] With this configuration, high-order piecewise polynomial approximation can be implemented on a quantum circuit more efficiently within the range of the allowable error δ.

[0112] (4) In the information processing system described in (3) above, the operation amount of the phase gate operation is set based on the difference between the value of the interval corresponding to the phase gate operation in the piecewise polynomial V2 and the value of the interval adjacent to the interval.

[0113] With this configuration, high-order piecewise polynomial approximation can be implemented on a quantum circuit more efficiently within the range of the allowable error δ.

[0114] (5) In the information processing system described in (3) or (4) above, when the specific order p1 is fixed to a value of 2 or more, the division step divides the continuous interval into equal primary division intervals, and when the value of the upper bound function in two adjacent primary division intervals is equal to or less than the allowable error δ, the two primary division intervals are merged to divide the continuous interval into the division intervals.

[0115] With this configuration, the model function V1 can be approximately implemented on the quantum circuit as a piecewise polynomial with a smaller number of divided intervals.

[0116] (6) In the information processing system according to any one of (3) to (5), the stop step further includes stopping the generation of the first quantum circuit when the calculated division parameter m is greater than the number n of computational quantum bits. An information processing system.

[0117] With this configuration, it is possible to prevent the waste of forcibly generating quantum circuits when there is a shortage of computational resources.

[0118] (7) In the information processing system described in any one of (3) to (6) above, in the allocation step, when the division parameter m is greater than the number n of the computational quantum bits, the information processing system allocates the computational quantum bits so that the number n of the computational quantum bits is equal to or greater than the division parameter m.

[0119] With this configuration, it is possible to improve the efficiency of generating quantum circuits.

[0120] (8) In the information processing system according to any one of (2) to (4), when the value of the specific order p1 is fixed to 1, in the division step, the continuous interval is divided into equal divided intervals, and in the circuit generation step, a second quantum circuit is generated as the quantum circuit, and the second quantum circuit has (n-m) control gate operations in which each of (n-m) computational quantum bits out of the n computational quantum bits is a control bit, and m computational quantum bits other than the (n-m) computational quantum bits are target bits, and each of the control gate operations acts on a state corresponding to a part of the divided interval, thereby linearly interpolating the phases of diagonal components represented by the m computational quantum bits in accordance with the value of the model function V1 at the endpoints of the divided interval.

[0121] According to this configuration, it is possible to further improve the calculation efficiency when obtaining a piecewise polynomial using a linear function.

[0122] (9) In the information processing system according to any one of (1) to (8) above, when the number of elements of the degree set {p} is 2 or more, the candidate acquisition step further acquires candidates for the division parameter m that are equal to or less than the number n of the computational quantum bits, and in the division step, for each of the candidates for the division parameter m, divide the continuous section into 2 ｍan interval order determination step of determining an optimum partitioning parameter m from among the candidates for the partitioning parameter m based on an objective function having as input variables the specified allowable value of the order p, the partitioning parameter m, and a partitioning mode of the continuous intervals; a specific order determination step of determining the order p that is equal to or greater than the allowable value and that corresponds to the determined partitioning parameter m as a specific order p1 of the piecewise polynomial in the partitioned interval; and a specific order calculation step of calculating the piecewise polynomial V2 by optimizing a p1-degree polynomial corresponding to the specific order p1 to the model function V1 using the spline interpolation for each partitioned interval.

[0123] With this configuration, it is possible to obtain a piecewise polynomial in which the optimal specific degree p1 is set for each interval from among the candidate degrees p, and therefore it is possible to generate a quantum circuit that can implement a piecewise polynomial with higher qualitative approximation accuracy within a range that satisfies the allowable error δ.

[0124] (10) In the information processing system described in (9) above, when the number of elements in the degree set {p} is two or more and there is only one allowable value of the degree p for each interval, the division step divides the continuous interval into equal primary divided intervals, and when the allowable values ​​of the degree p in two adjacent primary divided intervals are the same and the value of the upper bound function is less than or equal to the allowable error δ, the information processing system divides the continuous interval into the divided intervals by merging the two primary divided intervals.

[0125] With this configuration, it is possible to generate a quantum circuit that implements a piecewise polynomial with a smaller number of divided intervals within a range that satisfies the tolerance δ.

[0126] (11) In the information processing system according to any one of (1) to (10) above, the upper bound function is a function of the interval length L of the continuous interval and an infinity norm ||·||∞ and the optimal constant C of the spline interpolation corresponding to the specific order p1. ｐ１ The information processing system is expressed as the following equation (1) using [Equation 1].

[0127] (12) A method for generating a quantum circuit, the method including each step of the information processing system described in any one of (1) to (11) above.

[0128] (13) A program that causes at least one computer to execute each step of the information processing system described in any one of (1) to (11) above. Of course, this is not a limitation.

[0129] Finally, while various embodiments of the present invention have been described, these are presented by way of example only and are not intended to limit the scope of the invention. The novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. Such embodiments and modifications are intended to be included within the scope and spirit of the invention, as well as within the scope of the inventions and their equivalents as defined in the accompanying claims.

[0130] 1: Information processing system, 2: Information processing device, 20: Communication bus, 21: Communication unit, 22: Memory unit, 23: Processor, 231: Acquisition unit, 232: Division unit, 233: Calculation unit, 234: Circuit generation unit, 235: Output unit, 3: Quantum computer, 30: Communication bus, 31: Communication unit, 32: Quantum memory, 320: Quantum bit, 321: Computational quantum bit, 322: Auxiliary bit, 33: Quantum processor, 4: User terminal 40: communication bus, 41: communication unit, 42: memory, 43: processor, 44: display unit, 45: input unit, 5: quantum circuit, 51: quantum operation, 511: polynomial phase gate, 511a: polynomial phase gate, 512: quantum comparator, 5121: first gate operation, 5122: second gate operation, 521: quantum comparator, 6: quantum circuit, 61: diagonal unitary operation, 62: differential action operation, 7: quantum circuit, δ: tolerance

Claims

1. An information processing system, comprising at least one processor, configured to execute a program that executes the following steps: an acquisition step acquires a model function V1, a tolerance δ required for a piecewise polynomial V2 that approximately represents the model function V1, and an order set {p} that is a set of candidates for the order p of the piecewise polynomial V2, wherein the model function V1 outputs a scalar value in response to an input and is defined by at least one continuous interval; and a division step divides the continuous interval into two intervals such that an upper bound function that indicates an upper bound of the maximum value of the difference between the model function V1 and the piecewise polynomial V2 in the continuous interval is equal to or smaller than the tolerance δ, based on one specific order p1 selected from the order set {p} and a division parameter m that indicates an upper limit of the number of divisions of the continuous interval. ｍ The upper bound function does not depend on the variables for determining the piecewise polynomial V2, but is determined by the allowable error δ and the (p1+1)th derivative V1 of the model function V1 corresponding to the specific order p1. （ｐ１＋１） and the division parameter m, wherein in an approximation formula calculation step, for each of the division intervals, a p1-degree polynomial corresponding to the specific degree p1 is optimized to the model function V1 using a predetermined spline interpolation to calculate the piecewise polynomial V2, and in a circuit generation step, a quantum circuit representing a diagonalized unitary operator corresponding to the piecewise polynomial V2 is generated based on the calculated piecewise polynomial V2, wherein the quantum circuit is configured to act on n computation qubits encoded to represent positions in the continuous intervals, and an operation amount of a quantum gate operation included in the quantum circuit is determined based on a coefficient of the piecewise polynomial V2.

2. In the information processing system according to claim 1, when the number of elements in the order set {p} is 1, the division parameter calculation step further comprises fixing the specific order p1 to the value of the only candidate order p in the entire continuous section, and calculating the upper bound function, the allowable error δ, and the (p1+1)th derivative V1 of the model function V1. （ｐ１＋１） and a norm of 3. An information processing system according to claim 2, wherein, when the value of the specific order p1 is fixed to 2 or greater, the circuit generation step generates a first quantum circuit as the quantum circuit, and the first quantum circuit comprises: a phase gate operation that acts on the n computational quantum bits corresponding to each of the division intervals; and a quantum comparator that acts on m computational quantum bits, which are the value of the division parameter m, among the n computational quantum bits, and one auxiliary bit, and the quantum comparator is configured to change the state of the auxiliary bit in accordance with the state of the m computational quantum bits, thereby applying the phase gate operation to the n computational quantum bits having states corresponding to the division interval.

4. An information processing system according to claim 3, wherein the amount of operation of the phase gate operation is set based on the difference between the value of the interval corresponding to the phase gate operation in the piecewise polynomial V2 and the value of the interval adjacent to the interval.

5. An information processing system according to claim 3 or claim 4, wherein, when the specific order p1 is fixed to a value of 2 or greater, the division step divides the continuous interval into equal primary division intervals, and when the value of the upper bound function in two adjacent primary division intervals is equal to or less than the allowable error δ, the two primary division intervals are merged to divide the continuous interval into the division intervals.

6. An information processing system according to any one of claims 3 to 5, wherein the abort step further aborts the generation of the first quantum circuit if the calculated division parameter m is greater than the number n of computational quantum bits.

7. An information processing system according to any one of claims 3 to 6, wherein in the allocation step, if the division parameter m is greater than the number n of computational quantum bits, the computational quantum bits are allocated so that the number n of computational quantum bits is equal to or greater than the division parameter m.

8. An information processing system according to any one of claims 2 to 4, wherein, when the value of the specific order p1 is fixed to 1, the dividing step divides the continuous interval into equal divided intervals, and the circuit generation step generates a second quantum circuit as the quantum circuit, the second quantum circuit comprising (n-m) control gate operations having each of (n-m) computational quantum bits out of the n computational quantum bits as control bits, and m computational quantum bits other than the (n-m) computational quantum bits as target bits, each of the control gate operations acting on a state corresponding to a part of the divided interval, thereby linearly interpolating the phases of the diagonal elements represented by the m computational quantum bits in accordance with the value of the model function V1 at the endpoints of the divided interval.

9. In an information processing system according to any one of claims 1 to 8, when the number of elements in the degree set {p} is two or more, the candidate acquisition step further acquires candidates for the division parameter m that are equal to or less than the number n of computational quantum bits, and the division step further divides the continuous section into two for each candidate for the division parameter m. ｍ an interval order determination step of determining an optimum partitioning parameter m from among the candidates for the partitioning parameter m based on an objective function having as input variables the specified allowable value of the order p, the partitioning parameter m, and a partitioning mode of the continuous intervals; a specific order determination step of determining the order p that is equal to or greater than the allowable value and that corresponds to the determined partitioning parameter m as a specific order p1 of the piecewise polynomial in the partitioned interval; and a specific order calculation step of calculating the piecewise polynomial V2 by optimizing a p1-order polynomial corresponding to the specific order p1 to the model function V1 using the spline interpolation for each partitioned interval.

10. An information processing system according to claim 9, wherein, when the number of elements in the degree set {p} is two or more and there is only one allowable value of the degree p for each interval, the division step divides the continuous interval into equal primary divided intervals, and when the allowable values ​​of the degree p in two adjacent primary divided intervals are the same and the value of the upper bound function is less than or equal to the allowable error δ, the two primary divided intervals are merged to divide the continuous interval into the divided intervals.

11. An information processing system according to any one of claims 1 to 10, wherein the upper bound function is a function of the interval length L of the continuous interval and an infinity norm ||·|| ∞ and the optimal constant C of the spline interpolation corresponding to the specific order p1. ｐ１ The information processing system is expressed as the following equation (1) using 12. A method for generating a quantum circuit, comprising the steps of an information processing system according to any one of claims 1 to 11.

13. A program that causes at least one computer to execute each step of the information processing system according to any one of claims 1 to 11.

Images