Microfabrication of low-resistance molybdenum interconnects

Abstract

Provided herein are methods and apparatus for fabricating a semiconducting substrate using a template layer to form a film of molybdenum having a low resistance attributed to the large size of its internal crystalline grains. The method and apparatus described herein may be used to fabricate molybdenum lines or interconnects in an integrated circuit. Fabricated molybdenum lines may be robust against oxidative damage during air break and downstream processing and be able to maintain low resistance. The method may be used to deposit molybdenum to fill features as a liner layer and / or fill features.

Description

MICROFABRICATION OF LOW-RESISTANCE MOLYBDENUM INTERCONNECTSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in their entireties and for all purposes.BACKGROUND

[0002] Deposition of conductive materials is an integral part of many semiconductor fabrication processes. These materials may be used for horizontal interconnects, vias between adjacent metal layers, contacts between metal layers and devices, and as lines in memory devices. In an example of deposition, a tungsten (W) layer may be deposited on a titanium nitride (TiN) barrier layer to form TiN / W bilayer by chemical vapor deposition (CVD) processes using tungsten hexafluoride (WFe). However, as devices shrink and more complex patterning schemes are utilized in the industry, the deposition of thin tungsten becomes a challenge. The continued decrease in feature size and film thickness brings various challenges to TiN / W film stacks. These include high resistivity for thinner films and deterioration of TiN barrier properties. Deposition in complex high aspect ratio structures such as 3D NAND structures is particularly challenging.

[0003] Damascene copper (Cu) is the state of the art for many metal fill applications for which W is too resistive. Cu integration requires the use of a barrier (typically l-2nm of TaN) to prevent Cu diffusion into the dielectric substrate. It also typically requires the use of a liner (typically 2-3nm of Co) to enable void free Cu fill and prevent electromigration (EM) failures of the copper line. As feature sizes get smaller, the volume remaining for conductive copper becomes vanishingly small. Additionally, due to the geometry of the damascene substrate, Cu grain size is typically constrained to roughly the size of the line, increasing its resistivity.

[0004] For some applications, molybdenum (Mo) offers several benefits over other metals such as cobalt (Co), ruthenium (Ru), tungsten (W), and Cu: (i) barrierless and linerless deposition is more feasible on oxides and nitrides as compared to deposition of cobalt, ruthenium, and tungsten, and has fewer contamination and electromigration concerns when implemented with Cu intergration, (ii) Mo resistivity scaling is better than that of tungsten, (iii) Mo intermixing with underlying Co is not expected compared to Ru intermixing with Co at temperatures lessthan 450°C, and (iv) there is relatively easy Mo integration into current W schemes compared to copper and ruthenium.

[0005] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.SUMMARY

[0006] Provided herein are methods and apparatus for fabricating a semiconducting substrate using a template layer to form a film of molybdenum having a low resistance attributed to the large size of its internal crystalline grains.

[0007] One general aspect includes a subtractive integration method for forming via interconnect. The method involves providing a substrate having a first via interconnect where the first via interconnect is adjacent to a first dielectric material; depositing a template layer over the first via interconnect and the first dielectric material; depositing a molybdenum- containing material on the template layer, where the template layer templates the rain growth in the molybdenum-containing material; etching the molybdenum-containing material to form a second via interconnect over the first via interconnect; and forming a second dielectric material over the second via interconnect. Implementations may include one or more of the following features.

[0008] In some embodiments, the method further involves depositing an adhesion layer over the second via interconnect prior to forming a second dielectric material. In some embodiments, the method further involves depositing a hermetic dielectric layer over the second via interconnect prior to forming the second dielectric material, where the hermetic dielectric layer is configured to hermetically seal the second via interconnect from atmospheric exposure.

[0009] In some embodiments, the method further involves depositing a dielectric etch stop layer over the second dielectric material and the exposed second via interconnect.

[0010] In some embodiments, etching the molybdenum-containing material forms an etch byproduct. The byproduct may be removed in some implementations.

[0011] In some embodiments, the method further involves, after depositing the molybdenum- containing material on the template layer and prior to etching the molybdenum-containing material, depositing a patterning mask or a photoresist over the molybdenum-containing material. In some embodiments, the method further involves, after depositing the molybdenum-containing material on the template layer and prior to etching the molybdenum-containing material, planarizing the molybdenum-containing material.

[0012] One general aspect includes a method that involves providing a metallic template layer on a substrate and depositing a molybdenum-containing material on the metallic template layer. The metallic template layer templates the grain growth of the molybdenum-containing material. Implementations may include one or more of the following features. In some embodiments, the template layer is selectively deposited on a portion of the substrate.

[0013] In some embodiments, the molybdenum-containing material is elemental molybdenum, deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or plasma-enhanced atomic layer deposition (PEALD) process.

[0014] In some embodiments, the template layer is an elemental tungsten film, deposited using PVD, CVD, ALD, or PEALD process.

[0015] In some embodiments, the method further includes depositing an adhesion layer on the substrate prior to depositing the tungsten template layer. In some embodiments, the adhesion layer is a molybdenum-containing material.

[0016] In some embodiments, prior to deposition of the molybdenum-containing material, a portion of the template layer is etched away to prevent molybdenum-containing material from depositing in the etched areas.

[0017] In some embodiments, the method further involves removing oxide from the template layer prior to depositing the molybdenum-containing material. In some embodiments, the removal of the oxide and the deposition of the molybdenum-containing material occurs concurrently.

[0018] In some embodiments, the method further involves etching the molybdenum-containing material, where the template layer acts as an etch stop layer.

[0019] In some embodiments, the method may be performed in an apparatus having separate modules for forming an adhesion layer, a template layer, and the molybdenum-containing material. In some embodiments, two or more of the modules are connected to a common low- pressure backbone to prevent atmospheric exposure of the substrate.

[0020] Other general aspects include a method for subtractive integration that involves exposing patterned molybdenum features on a template layer to atmosphere, thereby forming an oxide on the patterned molybdenum features; removing the oxide from the patterned molybdenum features; and selectively depositing molybdenum on the patterned molybdenum feature.

[0021] In some embodiments, the method further includes chemical mechanical planarization(CMP) and dielectric capping, where the patterned molybdenum features are exposed to the atmosphere between CMP and dielectric capping.

[0022] In some embodiments, the atmospheric exposure occurs between etching molybdenum to form the patterned molybdenum feature and dielectric fill.

[0023] Other general aspects include a method for subtractive integration, where a hermetic dielectric deposition module is integrated with a subtractive molybdenum etch chamber configured to hermetically seal etched molybdenum by a dielectric before atmospheric exposure.

[0024] In some embodiments, the subtractive molybdenum etch chamber is integrated with a molybdenum ALD or CVD chamber.

[0025] In some embodiments, a hermetic dielectric deposition module is integrated with a subtractive molybdenum etch chamber configured to hermetically seal etched molybdenum by a dielectric before subsequent atmospheric exposure.

[0026] In some embodiments, the subtractive molybdenum etch chamber, a molybdenum ALD or CVD chamber, and a hermetic dielectric deposition module are integrated into the same low- pressure platform to prevent air exposure.BRIEF DESCRIPTIONS OF DRAWINGS

[0027] Figures 1 A and IB are schematic examples of material stacks that include molybdenum (Mo) according to various embodiments.

[0028] Figures 2A - 2L are schematic examples of various structures into which molybdenum may be deposited in accordance with disclosed embodiments.

[0029] Figure 3 shows an example of a molybdenum (Mo) interconnect according to various embodiments.

[0030] Figure 4 shows examples of patterned features into which selective deposition of a Mo film may be performed according to various embodiments.

[0031] Figure 5 provides a process flow diagram illustrating operations for forming a molybdenum material on a template layer.

[0032] Figure 6 displays a schematic illustration of the subtractive molybdenum integration according to certain embodiments.

[0033] Figure 7 is a graph showing the resistivity of the deposited molybdenum layer as a function of the thickness of the molybdenum layer.

[0034] Figure 8 is a graph showing the resistivity of the deposited molybdenum layer as a function of the molybdenum layer thickness deposited via various methods.

[0035] Figures 9, 10A, and 10B show examples of processing systems that may be used to implement the methods described herein.DETAILED DESCRIPTION

[0036] In the following descriptions, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.

[0037] The implementations disclosed below describe the deposition of a material on a substrate, such as a wafer, substrate, or other workpiece. The workpiece may be of various shapes, sizes, and materials. In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art would understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of the many stages of integrated circuit fabrication thereon. A wafer or substrate used in the semiconductor device industry typically has a diameter of 200 mm, 300 mm, or 450 mm. In addition to semiconductor wafers, other workpieces that may be used for implementations disclosed herein include various articles such as printed circuit boards and the like.

[0038] Provided herein are methods and apparatus for fabricating a semiconducting substrate wherein a film of molybdenum having a low resistance due to the large size of its internal crystalline grains is formed using a template layer, which may be a tungsten template layer. The method and apparatus described herein may be used to fabricate molybdenum lines or interconnects in an integrated circuit. In some implementations, fabricating molybdenum lines involves subtractive metal line integration. Fabricated molybdenum lines, according to certain embodiments, may be robust against oxidative damage during air break and downstream processing and able to maintain low resistance. The methods described herein may be used for logic and memory applications and may be used to deposit molybdenum in a semiconductor substrate with features such as vias, wordlines such as dynamic random-access memory (DRAM) buried wordline (bWL), and trenches. The method may be used to deposit molybdenum to fill features as a liner layer and / or fill features.

[0039] Figures 1A and IB are schematic examples of material stacks that include Mo layersaccording to various embodiments. Figures 1A and IB illustrate the order of materials in examples of particular stacks and may be used with any appropriate architecture application, as described further below with respect to Figures 2A - 2L. Figure 1A shows a first material stack 111 featuring a substrate 102 and a molybdenum layer 108 deposited thereon. The substrate 102 may be a silicon or other semiconductor wafer, e.g., a 200-nm wafer, a 300-nm wafer, or a 450-nm wafer, including wafers having one or more layers of material, such as dielectric, conducting, or semiconductive materials deposited thereon. In some embodiments, the substrate 102 may be or include silicon (Si) or silicon germanium (SiGe). The method may also be applied to form metallization stack structures on other substrates, such as glass, plastic, and the like.

[0040] The stack 111 has a dielectric layer 104 on the substrate 102. The dielectric layer 104 may be deposited directly on a semiconductor surface (e.g., a Si or SiGe surface) of the substrate 102, or there may be any number of intervening layers. For example, the substrate 102 may include any number of layers deposited in various arrangements on a semiconductor substrate.

[0041] Examples of dielectric layers include doped and undoped silicon oxide, silicon nitride, and aluminum oxide layers, with specific examples including doped or undoped layers of silicon nitride (SiN), silicon dioxide (SiO2), and aluminum oxide (AI2O3). The stack 111 has a layer 106 disposed between the molybdenum layer 108 and the dielectric layer 104. The layer 106 may be a diffusion barrier and / or adhesion layer, for example. A diffusion barrier is a layer that prevents the diffusion of species between layers. An adhesion layer is a layer that promotes adhesion of layer to an underlying layer. Examples of diffusion barrier and adhesion layers include titanium nitride (TiN), titanium / titanium nitride (Ti / TiN), tungsten (W), tungsten nitride (WN), and tungsten carbon nitride (WCN). The molybdenum layer 108 is the main conductor of the structure. In some embodiments, the molybdenum layer 108 may or may not include a molybdenum nucleation layer. In some embodiments, molybdenum layer is an amorphous molybdenum-containing layer. In the depicted example of Figure 1A, the molybdenum layer 108 is deposited directly on the layer 106. In other embodiments (not depicted), the molybdenum layer 108 may be deposited on a separate layer, such as a growth initiation layer that includes another material, such as a tungsten (W) or W-containing growth initiation layer. The growth initiation layer may be used to facilitate nucleation and growth of molybdenum layer 108.

[0042] Figure IB shows another example of a stack 121. In this example, the stack 121 includes the substrate 102, dielectric layer 104, with molybdenum layer 208 deposited directly on thedielectric layer 104, without an intervening diffusion barrier or adhesion layer. The molybdenum layer 108 is as described with respect to Figure 1A, by using molybdenum as the main conductor, low-resistivity thin films can be obtained. Examples of low-resistivity thin films include films with resistivity less than 40 uQm-cm at 60 angstroms thickness and less than 15 uQm-cm at 200 angstroms thickness.

[0043] In some embodiments, a stack (not shown) may include a substrate, a conductive layer, and a molybdenum layer deposited onto the conductive layer. As used herein, a conductive layer is a layer having a conductivity of at least 104Q’1-cm’1at room temperature. Examples include molybdenum on a metal layer (e.g., a W layer, or another Mo layer). In these embodiments, there is no dielectric layer between the molybdenum layer and the conductively layer. Similarly, the stack may include molybdenum deposited directly on a metal compound layer. Examples include molybdenum on metal nitride layer (e.g., TiN, WN, or MoN). In still some other embodiments of stack (not shown), the stack may include a substrate and a molybdenum layer deposited directly on the substrate, including directly on a semiconductor surface, on a dielectric surface, or a conductive surface. Figures 1 A and IB illustrates examples of the order of materials in a particular stack and may be used with any appropriate architecture and applications, with examples described further below with respect to Figures 2A - 2L.

[0044] The methods described herein are performed on a substrate that may be housed in a chamber. The substrate may be a silicon or other semiconductor wafer, including wafers having one or more layers of materials, such as dielectric, conducting, or semiconducting material deposited thereon. The methods are not limited to semiconductor substrates and may be performed to fill any features with molybdenum.

[0045] Substrates may have features such as vias or contact holes, which may be characterized by one or more narrow and / or re-entrant openings, constrictions within the feature, and high aspect ratios. Used herein, via may be a conductive via and may be referred to as a conductive via, via feature, a feature, via interconnect. A feature may be formed in one or more of the above-described stacks or layers within a stack. For example, the features may be formed at least partially in a dielectric layer. In some embodiments, a feature may have an aspect ratio of at least about 2:1, at least about 4:1, at least about 6:1, at least about 10:1, at least about 25:1, or higher. One example of a feature is a hole or via in a semiconductor substrate or a layer on the substrate.

[0046] Figure 2A depicts a schematic example of a DRAM architecture, including a Mo buried wordline (bWL) 208 in a silicon substrate 202. The Mo bWL is formed in a trench etched in the silicon substrate 202. Lining the trench is a conformal barrier layer 206 and an insulatinglayer 204. The conformal barrier layer 206 is disposed between the insulating layer 204 and the silicon substrate 202. In this example, the insulating layer 204 may be a gate oxide layer formed from a high-k dielectric material such as silicon oxide or silicon nitride material. In some embodiments disclosed herein, the conformal barrier layer 206 is TiN or tungsten- containing layer, such as WN or WCN layer. In some embodiments, a conformal tungsten- containing growth initiation layer (not shown) may be present between the conformal barrier layer 206 and the molybdenum bWL 208. Alternatively, the molybdenum bWL 208 may be deposited directly on a Tin or other diffusion barrier. In some embodiments, one or both of layers 204 and 206 is not present.

[0047] The bWL structure shown in Figure 2A is one example of an architecture that includes a molybdenum fill layer. During fabrication of the WL, molybdenum is deposited into a feature that may be defined by an etched recess in the silicon substrate 204 that is conformally lined with layers 206 and / or 204, if present.

[0048] Figures 2B - 2H are additional schematic examples of various structures into which molybdenum may be deposited in accordance with disclosed embodiments. Figure 2B shows an example of a cross-sectional depiction of a vertical feature 201 to be filled with Mo. The feature can include a feature hole 205 in a silicon substrate 202. The feature hole 205 may have an underlayer 203 lining the sidewall or interior of the feature hole 205 and may form the interior surfaces. The feature hole 205 or other features may have a dimension near the opening, e.g., an opening diameter or line width of between about 10 nm to 500 nm, for example, between about 25 nm to about 300 nm. The feature hole 205 can be referred to as an unfilled feature or simply a feature. The vertical feature 201, and any feature, may be characterized in part by an axis 218 that extends through the length of the feature, with vertically oriented feature having vertical axes and horizontally oriented feature having horizontal axes. The underlayer 203 can be, for example, a diffusion barrier layer, an adhesion layer, a nucleation layer, a combination thereof, or any other applicable material. Non-limiting examples of underlayers can include dielectric layers and conducting layers. Examples of dielectric materials include oxides, such as SiCE, AI2O3; nitrides, such as SiN; carbides, such as nitrogen- doped silicon carbide (NDC) and oxygen-doped silicon carbide (ODC); and low k dielectrics, such as carbon doped SiCF. In particular implementations, an underlayer can be one or more of titanium, titanium nitride, tungsten nitride, titanium aluminide, tungsten, and molybdenum. In some embodiments, the underlayer is tungsten-free. In some embodiments, the underlayer is molybdenum-free.

[0049] In some embodiments, features are wordline features in a 3D NAND structure. Forexample, a substrate may include a wordline structure having an arbitrary number of wordlines (e.g., 50 to 450) with vertical channels at least 200 A deep. Examples of wordline features are described further below. Another example of a feature is a trench in a substrate or layer. Features may be of any depth. In various embodiments, the features may have an underlayer, such as a barrier layer or adhesion layer. Non-limiting examples of underlayers include dielectric layers and conducting layers, e.g., silicon oxides, silicon nitrides, silicon carbides, metal oxides, metal nitrides, metal carbides, and metal layers.

[0050] Figure 2C shows an example of a vertical feature 201 that has a re-entrant profile. A reentrant profile is a profile that narrows from the bottom, closed-end, or interior of the feature to the feature opening. According to various implementations, the profile may narrow gradually and / or include an overhang at the feature opening. Figure 2C shows an example of the latter, with an underlayer 213 lining the sidewall or interior surfaces of the feature hole 205. Similar to Figure 2B, underlayer 213 can be a diffusion barrier layer, an adhesion layer, a nucleation layer, a combination thereof, or any other applicable material. Non-limiting examples of underlayers can include dielectric layers and conducting layers. The underlayer 213 forms an overhang 215 such that the underlayer 13 is thicker near the opening of the vertical feature 201 than inside the vertical feature 201.

[0051] In some implementations, features have one or more constrictions within the feature may be filled. Figure 2D shows examples of views of various filled features having constrictions. Each of the examples (a), (b), and (c) in Figure 2D includes a constriction 209 at a midpoint within the feature. The constriction 209 can be, for example, between about 15 nm - 20 nm wide. Constrictions can cause pinch off during the deposition of molybdenum in the feature using conventional techniques, with deposited metal blocking further deposition past the constriction before that portion of the feature is filled, resulting in voids in the feature. Example (b) further includes an overhang 215 (such as, a liner / barrier overhand) at the feature opening. Such an overhang could also be a potential pinch-off point. Example (c) includes a constriction 212 further away from the field region than the overhang 215 in example (b).

[0052] Horizontal features, such as in 3D memory structures, can also be filled. Figure 2E shows an example of a horizontal feature 250 that includes a constriction 251. For example, horizontal feature 250 may be a wordline in a 3D NAND (also referred to as vertical NAND or VNAND) structure. In some implementations, the constrictions can be due to the presence of pillars in a 3D NAND or other structure. Figure 2F presents a cross-sectional side view of a 3D NAND structure 210 (formed on a silicon substrate 202) having 3D NAND stack (left 225 and right 226), central vertical structure 230, and the plurality of stacked horizontal wordlinefeatures 220 with opening 222 on opposite sidewalls 240 of central vertical structure 230. Note that Figure 2F displays two “stacks” of the exhibited 3D NAND structure 210, which together form the “trench-like” central vertical structure 230. However, in certain embodiments, there may be more than two such stacks arranged in sequence and running spatially parallel to one another, the gap between each adjacent pair of s stacks forming a central vertical structure 230, like that explicitly illustrated in Figure 2F. In this embodiment, the horizontal wordline features 220 are 2D memory wordline features that are fluidically accessible from the central vertical structure 230 through the openings 222. Although not explicitly indicated in the figure, the horizontal wordline feature 220 present in both the 3D NAND stacks 225 and 226 shown in Figure 2F (i.e., the left 3D NAND stack 225 and the right 3D NAND stack 226) are also accessible from the other sides of the stacks (far left and far right, respectively) through similar vertical structures formed by additional 3D NAND stacks (to the far left and far right, but now shown). Each 3D NAND stack 225, 226 contains a stack of wordline features that are fluidically accessible from both sides of the 3D NAND stack through a central vertical structure 230. In the particular example schematically illustrated in Figure 2F, each 3D NAND stack contains 6 pairs of stacked wordlines. However, 3D NAND memory layout may contain any number of vertically stacked pairs of wordlines.

[0053] The wordline features in a 3D NAND stack can be formed by depositing an alternating stack of silicon oxide and silicon nitride layers, and then selectively removing the nitride layers leaving a stack of oxides layers having gaps between them. These gaps are the wordline features. Any number of wordlines maybe vertically stacked in such a 3D NAND structure so long as there is a technique for forming them available, as well as a technique available to successfully accomplish (substantially) void-free fills of the vertical features. Thus, for example, a VNAND stack may include between 2 and 512 horizontal wordline features, between 2 and 256 horizontal wordline features, between 8 and 128 horizontal wordline features, or between 16 and 64 wordline features, and so forth (the listed ranges understood to include either recited endpoints).

[0054] Figure 2G presents a cross-sectional top-down view of the same 3D NAND structure 210 shown in the side view in Figure 2F with the cross-section taken through the horizontal section 260 as indicated by the dashed horizontal line in Figure 2F. The cross-section of Figure 2G illustrates several rows of pillars 255, which are shown in Figure 2F to run vertically from the base of the substrate 202 to the top of the 3D NAND structure 210. In some embodiments, the pillars 255 are formed from a polysilicon material and are structurally and functionally significant to the 3D NAND structure 210. In some embodiments, such polysilicon pillars mayserve as gate electrodes for stacked memory cells formed within the pillars. The top-view of Figure 2G illustrates that the pillars 255 form constrictions in the opening 222 to wordline feature 220. Fluidic accessibility of wordline features 220 from the central vertical structure 230 via opening 222 (as indicated by the arrows in Figure 2G) is inhibited by pillars 255. In some embodiments, the size of the horizontal gap between adjacent polysilicon pillars is between about 1 and 20 nm. This reduction in fluidic accessibility increases the difficulty of uniformly filling wordline features 220 with the material. The structure of the wordline features 220 and the challenges of uniformly filling the with molybdenum material due to the presence of pillars 255 is further illustrated in Figures 2H, 21, and 2 J.

[0055] Figure 2H exhibits a vertical cut through a 3D NAND structure similar to that shown in figure 2F, but here focused on a single pair of wordline features 220 and additionally schematically illustrating a fill process which resulted in the formation of a void 275 in the filled wordline feature 220. Figure 21. also schematically illustrates void 275, but in this figure illustrated via a horizontal cut through pillars 255, similar to the horizontal cut exhibited in Figure 2G. Figure 2J illustrates the accumulation of molybdenum material around the constriction-forming pillars 255, the accumulation resulting in the pinch-off of opening 222, so that no additional molybdenum material can be deposited in the region of voids 275. Apparent from Figures 2H and 21 is that void-free molybdenum fill relies on migration of sufficient quantities of deposition precursor down through central vertical structure 230, through openings 222, past the constricting pillars 255, and into the furthest reaches of the wordline feature 220, prior to the accumulated deposition of molybdenum around pillars 255 causing a pinch-off of the openings 222 and preventing further precursor migration into wordline features 220. Similarly, Figure 2J exhibits a single wordline feature 220 viewed cross- sectionally from above and illustrates how a generally conformal deposition of molybdenum material begins to pinch-off the interior of wordline feature 220 due to the fact that the significant width of pillars 255 acts to particularly block, and / or narrow, and / or constrict what would otherwise be an open path through wordline feature 220. (It should be noted that the example in Figure 2J can be understood as a 2D rendering of the 3D features of the structure of the pillar constrictions shown in Figure 31, thus illustrating constrictions that would be seen in plan view rather than in a cross-sectional view.)

[0056] Three-dimensional structures may need longer and / or more concentrated exposure to precursors to allow the innermost and bottommost areas to be filled. Three-dimensional structures can be particularly challenging when employing molybdenum halide and / or molybdenum oxyhalide precursors because of their proclivity to etch, with longer and moreconcentrated exposure allowing for more etch as parts of the structure.

[0057] Figures 2K and 2L show examples of asymmetric trench structure DRAM bWL. Some fill processes for DRAM bWL trenches can distort the trenches such that the final trench width and resistance Rs are significantly non-uniform. Figure 2K shows an unfilled feature 261 and filled feature 265 that exhibits the line bending after fill. In this example, the features are a narrow asymmetric trench structure DRAM bWL. As shown, multiple features 283 are depicted on a substrate. These features 283 are spaced apart, and in some embodiments, adjacent features have a pitch between about 20 nm and about 60 nm or between about 20 nm and 40 nm. The pitch is defined as the distance between the middle axis of one feature to the middle axis of an adjacent feature. The unfilled feature 261 may be generally V-shaped, as shown in feature 283, having sloped sidewalls where the width of the feature narrows from the top of the feature to the bottom of the feature. The features widen from the feature bottom 273b to the feature top 273a. After some fill operations, line bending may be observed within the filled feature 265. In some situations, a cohesive force between opposing surfaces of a trench pulls the trench sides together, as depicted by arrows 267. The phenomenon is illustrated in Figure 2L and may be characterized as “zipping up” the feature. As feature 283 is filled, more force is exerted from the center axis 299 of feature 283, causing line bending. For example, molybdenum may be deposited on the sidewalls of the feature 283. Deposited molybdenum 284a and 284b on the sidewalls of feature 283, thereby interacting in close proximity, where the molybdenum-molybdenum bond radius r is small, thereby causing cohesive interatomic forces between the smooth growing surfaces of molybdenum and pulling the sidewalls together, thereby causing line bending.

[0058] Figure 3 depicts yet another example of a feature 300 according to various embodiments. Figure 3 depicts an example of a feature 300 according to various embodiments. The feature 300 includes a bottom surface 302 and one or more sidewall surfaces 304. An etch stop layer (ESL) 306 is also shown. The bottom surface 302 may be a metal-containing surface. The structure 300 is filled with molybdenum to form a Mo interconnect 308 that provides an electrical connection to the underlying contact.

[0059] In some embodiments, the bottom surface 302 is a metal-containing surface. The metalcontaining surface may contain any appropriate metal, such as cobalt (Co), ruthenium (Ru), copper (Cu), tungsten (W), molybdenum (Mo), nickel (Ni), iridium (Ir), rhodium (Rh), tantalum (Ta), and titanium (Ti). In some embodiments, the metal-containing surface 302 is an elemental metal surface. There may be some oxide formed on the metal-containing surface due to exposure to moisture. In some embodiments, the metal-containing surface is a metalcompound with examples including a titanium nitride (TiN), molybdenum nitride (MoNx), tungsten nitride (WN), tungsten carbon nitride (WCxNy), a titanium aluminum carbide (TiAlxCy), titanium silicide (TiSi2), or tantalum nitride (TaN) surface. These surfaces may exhibit selectivity with respect to dielectric oxides.

[0060] As used herein, oxide surfaces include alkoxides such as tetraethyl orthosilicate (TEOS), fluorosilicate glass (FSG), flowable oxides, spin-on-glasses, carbon-doped oxides, etc. In some embodiments, the oxide surface is a silicon-based oxide with examples given above.

[0061] The one or more sidewall surfaces 304 are dielectric surfaces. Such surfaces include alkoxides such as poly(2-ethyl-2-oxazoline) (PEOX) and silicon-based oxides, including tetraethyl orthosilicate (TEOS) oxide, flowable silicon-based oxides, carbon-doped silicon- based oxides, SiO2, etc. These surfaces may be part of the main dielectric layer surrounding the feature. Selectivity refers to the preference in deposition on a metal surface, such as Co, W, or Cu surface, relative to a dielectric surface. It may be quantified as a ratio of deposition rates or as a ratio of deposition thicknesses after a certain number of deposition cycles.

[0062] In some embodiments, the sidewall surfaces may be nitrides (e.g., SixNy) rather than oxides. The nitrides may be silicon-based nitrides or silicon-based oxynitrides. Selectivity of Mo film deposition on elemental metal with respect to nitrides is similar to that with respect to oxides.

[0063] The Mo interconnect 308 may be part of any appropriate part of a partially fabricated semiconductor device, including a source / drain (S / D) connection, a middle of the line (MOL) structure or a back end of line (BEOL) structure.

[0064] Figure 4 shows example embodiments of patterned features in which selective deposition of a Mo film may be performed. A patterned feature may be a via or a trench or other appropriate feature formed as a result of a patterning operation in a dielectric layer. Feature 410 shows an example of a patterned feature having an open profile that expands gradually from the bottom of the feature to the feature opening 414.

[0065] Feature 420 shows an example of a patterned feature having a re-entrant profile that narrows from the bottom of the feature to the feature opening 414. A re-entrant profile may also include an overhang at the feature opening 414. Feature 430 shows a feature with a metal undercut profile. According to various implementations, the profile has the metal-containing surface below the sidewall base 418 of the feature 430. There may be voids between the bottom surface 402 and the sidewall base 418. In each of the above profiles, the bottom surface 402 may be a metal-containing surface, for example, a metal or metal nitride surface. There maybe oxide 416 formed on the bottom surface 402 of the metal or metal nitride.

[0066] Metallization of the back end of the line (BEOL) interconnects ideally involves a stack of material processed by a manufacturing process that is not susceptible to introducing defects, both immediately after manufacturing and over time. Metallization in integrated circuit fabrication may involve damascene or subtractive integration schemes or any other suitable methods. In damascene processing schemes, lines and via features may be etched into a dielectric substrate, the features filled with metal, and excess metal is removed by chemical / mechanical polishing (CMP). In contrast, the subtractive processing schemes involve the formation of a planar metal layer, etching the lines into the metal, filling the area between the lines with a dielectric or some structure to maintain an air gap, then removing any excess dielectric with CMP. As the devices and the feature sizes shrink, less conductive materials that may be present for the manufacture, and stability of the stack can begin to consume more portion of the available interconnect volume relative to the primary conducting material, which can contribute to increased in-line resistance of the resulting device.

[0067] One example of metalizing partially fabricated semiconductor substrates is forming copper (Cu) interconnects via the damascene process. In damascene Cu integration, a barrier layer (e.g., about 1 to 2 nm of tantalum nitride) may be deposited on the feature bottom and sidewalls of the underlying dielectric layer to prevent diffusion of copper into the underlying dielectric layer(s). Additionally, a liner layer (e.g., about 2 to 3 nm of cobalt-containing material) may be used to encourage void-free copper fill of the feature(s) and to prevent electromigration failures (i.e., diffusion) of the copper lines. As the device and features get smaller, the volume for copper fill, or the ratio of the copper relative to the underlying barrier and / or liner layer, can become vanishingly small. Moreover, due to the geometry of the damascene substrate (i.e. width of the feature bottom is narrower than the width near the feature opening), copper grain size can be constrained approximately to the size of the line, increasing its resistivity.

[0068] An approach to address challenges associated with copper interconnects is using ruthenium (Ru), as an alternative to copper, via a subtractive ruthenium integration process. In the subtractive integration process for ruthenium, a barrier layer may not be necessary due to the negligible electromigration of ruthenium, and a thinner liner layer may be used to facilitate the adhesion of the ruthenium during the feature fill. Moreover, the geometry of the subtractive substrate (i.e., the width of the feature opening is narrower than the width of the feature bottom) is favorable compared to the geometry of the damascene substrate. This is because the width at or near the bottom of the line in a subtractive substrate is wider, whereas in a damascenesubstrate, the width at or near the bottom of the line is narrower. Despite these advantages, Ru lines formed via subtractive processing are primarily competitive at very small critical dimensions due to the substantially larger bulk resistivity of ruthenium compared to the bulk resistivity of copper (i.e., the resistivity of Ru is about 4 times greater than copper). Ruthenium with a large grain size can be deposited, but typically requires high resistance single crystalline substrates (e.g., sapphire) that are not suitable for interconnect integration. Moreover, ruthenium as a metal for interconnect integration is not a practical substitute for copper due to its high cost and rarity of the element.

[0069] Molybdenum offers several advantages compared to ruthenium. For example, molybdenum can be deposited without using a barrier and / or liner layer without significantly compromising the electromigration or diffusion performance of the molybdenum to the underlying dielectric material. Moreover, the bulk resistivity of molybdenum is lower than ruthenium, and it is more cost-effective and more available since it is more abundant than ruthenium. While molybdenum may be advantageous, the resistivity of molybdenum is still significantly higher than copper, and the molybdenum films are not competitive in terms of resistance for interconnect lines, where the conduction across the barriers is less significant than it is for vias. In many cases, grain boundary scattering is a primary driver of resistivity in thin films, its effect becoming more dominant as the features and devices shrink. Subtractive molybdenum integration is not a viable alternative to copper damascene unless the resistivity of the molybdenum is improved.

[0070] Compared to the damascene process, subtractive metal line integration has additional challenges associated with alignment or misalignment of the metal line and etch pattern mask. In subtractive processing, proper alignment of the metal line and etch pattern mask is more challenging since the alignment is carried out while a relatively thick metal film often obscures via upon which a line is to land. When the metal line and etch pattern mask are misaligned or partially misaligned, the etched metal line can penetrate into the via and potentially result in connection failures. The issues arising from the misalignment may be addressed by incorporating an etch stop layer between the line and via layers. However, such an etch stop layer would cover the top of the via, contributing to via resistance. Any such layer should be as conductive as possible for low via resistance.

[0071] The method described herein provides an approach for forming low-resistance molybdenum lines or interconnects by incorporating a template layer on which molybdenum is formed. In various implementations, molybdenum films formed on a template layer have a substantially larger grain size than those formed without a template layer. A large-grainmolybdenum film may be formed using the method outlined herein without a single crystalline substrate. In various implementations, a large grain of molybdenum is formed on a conductive template layer. The large grains of molybdenum formed on a conductive template layer have improved conductivity compared to those formed without a template layer.

[0072] In some embodiments, the molybdenum grains formed on a template layer are several times larger than the thickness of the deposited molybdenum film.

[0073] In some embodiments, the molybdenum formed on a template layer has a low resistance, approaching the resistance of epitaxial molybdenum. The resistance of the molybdenum formed on a template layer is significantly lower than the molybdenum deposited on less favorable substrates (e.g., substrates without a template layer) and substantially lower than the resistance of a typical ruthenium film.

[0074] Figure 5 provides a process flow diagram illustrating operations in a process for forming a conductive material on a template layer. Process 500 for depositing a molybdenum- containing material begins with operation 501, where a substrate is provided. Following operation 501, operation 503 is performed. In operation 503, a template layer is formed on the substrate. Following operation 503, an optional operation 505 may be performed where oxide on the substrate is removed. In operation 507, molybdenum-containing material is deposited on the template layer. After operation 507, optional operations 509 and 511 may be performed to further process the substrate. In operation 509, subtractive metal patterning may be performed, and in operation 511, molybdenum-containing material may be etched. In operation 513, the etched material may be encapsulated in dielectric material to isolate the metal lines and facilitate integration for subsequent processing.

[0075] Returning to operation 501, in some embodiments, the substrate provided in operation 401 is a substrate having an interconnect structure, a featured substrate, a substrate according to Figures 1A, IB, 2A - 2L, 3, and 4, or any other suitable partially fabricated semiconductor substrate. In some embodiments, the substrate having the interconnect structure may have one or more vias. Vias may be formed through processing the substrate with a single damascene integration, or any other suitable process. In some embodiments, when viewed from the top, the substrate may have a planar surface.

[0076] In some embodiments, the substrate may have exposed molybdenum and / or other metal in vias. The metal in the vias may be the metal used to form the via during the single damascene processing, e.g., molybdenum (Mo), tungsten (W), ruthenium (Ru), cobalt (Co), or copper (Cu). In some implementations, the substrate may have an exposed etch stop layer. The etch stop layer may be an oxide such as aluminum oxide (e.g., AI2O3), a nitride such as aluminumnitride (AIN), or aluminum nitride and oxy gen-doped silicon carbide (ODC).

[0077] After operation 501, a template layer may be deposited on the substrate in operation 503. The template layer generally contains a material with similar or nearly identical lattice parameters and / or chemically similar to molybdenum. The similarities in lattice parameters and / or chemical compatibility contribute to favorable conditions for growing large-grain molybdenum. In some embodiments, small differences in lattice parameters and surface chemistry between the template and molybdenum can be critical to the growth of large-grain molybdenum. The template layer can be different or separate from the nucleation layer. The nucleation layer is a thin layer of the material that promotes the deposition of subsequent material. In various embodiments, the nucleation layer may be amorphous.

[0078] In some embodiments, the template layer is a tungsten-containing layer.

[0079] The tungsten-containing layer is advantageous as it may be deposited without first depositing an adhesion layer. For example, a tungsten-containing layer may be deposited via a physical vapor deposition (PVD) technique without an adhesion layer or a nucleation layer. Without an intervening adhesion layer (which may be resistive) between the via and the trench, the conductive tungsten-containing template layer can serve as an etch stop to safeguard against misaligned trench and vias during the subtractive integration process.

[0080] In some embodiments, the tungsten-containing template layer is deposited on a thin layer of molybdenum-containing material. In some embodiments, the tungsten-containing template layer is deposited via chemical vapour deposition (CVD), deposited on a tungsten nucleation layer. However, the tungsten-containing template layer deposited on the tungsten nucleation layer can have increased resistivity. To circumvent the increase in resistivity in the tungsten-containing template layer deposited via CVD, in some implementations, the tungsten- containing template layer is deposited by CVD on the thin layer of molybdenum or other molybdenum-containing material.

[0081] In some embodiments, the tungsten-containing template layer has a low resistivity. The low-resistivity tungsten-containing layer may have a large grain size, providing a template for large Mo grain growth. In some embodiments, the grain size (i.e., the width of the crystallite on the substrate) of the template layer is between about 1 and 10 times the thickness of the template layer. For example, the grain size of the template layer is between about 2 and 3 times the thickness of the template layer. In some embodiments, the grain size of the template layer is between about 12 nm and 18 nm when the thickness of the template layer is about 6 nm.

[0082] In some embodiments, the template layer is a tungsten-containing nucleation layer or a bulk tungsten-containing layer, which itself may be deposited on a nucleation layer. In someembodiments, the tungsten-containing layer is deposited by a physical vapor deposition technique. In some embodiments, the tungsten-containing template layer may be deposited by chemical vapour deposition (CVD), atomic layer deposition (ALD), or any other suitable method.

[0083] In some embodiments, a tungsten-containing template layer is an elemental tungsten layer deposited by a suitable method such as sputtering or physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed nucleation layer (PNL) technique, and chemical vapor deposition (CVD). Elemental W is distinguished from binary tungsten films such as WC or WN and ternary films like WCN, though elemental tungsten film may include some amount of impurities. Elemental W has at least 90%, at least 95%, at least 99%, or at least 99.9% (atomic) tungsten. Similarly, elemental metal is differentiated from binary, ternary metal, or metal compounds, etc., and includes primarily a single element, although some amounts of impurities may be present. The elemental metal is at least 90%, at least 95%, at least 99%, or at least 99.9% pure metal.

[0084] In some embodiments, the tungsten-containing layer described herein may include some amount of other compounds, dopants, and / or impurities such as nitrogen, carbon, oxygen, boron, phosphorus, sulfur, silicon, germanium, and the like, depending on the particular precursors and processes used. The tungsten content in the film may range from 20% to 100% (atomic) tungsten. In various implementations, the template layer is tungsten-rich, having at least 50% (atomic) tungsten or even at least about 60%, 75%, 90%, or 99% (atomic) tungsten. In some implementations, the template layer may be a mixture of elemental tungsten (W) and other tungsten-containing compounds such as tungsten carbide (WC), tungsten nitride (WN), or tungsten carbonitride (WCN).

[0085] In some embodiments, the tungsten-containing layer is a low-fluorine tungsten layer.

[0086] In some embodiments, the tungsten-containing layer is deposited using a tungsten chloride (WC1X) precursor, such as tungsten hexachloride (WCk) or tungsten pentachloride (WC15).

[0087] In some embodiments, the tungsten-containing layer is deposited using one or more of a boron-containing reducing agent (e.g., B2H6) or a silicon-containing reducing agent (e.g., SilL) as a co-reactant. For example, one or more S / W cycles, where S / W refers to a pulse of silane followed by a pulse of tungsten hexafluoride (WFe) or other tungsten-containing precursor. In another example, one or more B / W cycles, where B / W refers to a pulse of diborane followed by a pulse of tungsten hexafluoride or other tungsten-containing precursors.

[0088] In some embodiments, the tungsten-containing template layer is deposited by a plasma-enhanced ALD process by sequential or alternating exposures to tungsten halide precursors (WC16, WCI5, WOCI4, WO2CI2) and Fk-containing plasma, and optionally an inert plasma annealing, depositing a large grain size for the template layer.

[0089] The tungsten-containing template layer is not limited to examples given above but may be any tungsten or tungsten-containing layer deposited by any appropriate methods, including atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any of which may be thermal- or plasma-enhanced.

[0090] In some embodiments, the template layer may be a layer containing other suitable metals. For example, the template layer may be a tantalum-containing layer or a molybdenum- containing layer. In some embodiments, a molybdenum-containing layer may be molybdenum that is deposited via liner-less deposition techniques, or any other molybdenum-containing layer deposited via any suitable deposition methods, such as PVD. Additional detail on depositing molybdenum-containing material is provided below.

[0091] In some embodiments, an adhesion layer may be deposited prior to depositing a template layer. In various embodiments, the adhesion layer contains dielectric materials.

[0092] In various implementations, the template layer is deposited by any appropriate method, including atomic layer deposition (ALD), chemical vapor deposition (CVD), any of which may be thermal- or plasma-enhanced. In some embodiments, it is deposited by PVD.

[0093] In some embodiments, the template layer is a thin layer. In some embodiments, the thickness of the template layer is between about 1 nm and 6 nm (e.g., about 3 nm or about 2 nm). In some embodiments, the thickness of the template layer is at least 2 nm or at least 3 nm. For example, the template layer may be a tungsten-containing layer having a 2 nm thickness. In some embodiments, the thickness of the template layer is no more than about 6 nm, no more than 10 nm, or no more than 13 nm. For example, the thickness of the tungsten-containing layer is no more than 13 nm.

[0094] In various implementations, the template layer is sufficiently planar or conformal. In some embodiments, after depositing the template layer, the template layer may be planarized (e.g., by chemical mechanical planarization) to remove excess material and to form a thin and conformal layer.

[0095] In some embodiments, the template layer is sufficiently conductive such that it may remain in the interconnect after subtractive molybdenum integration. In some embodiments, a sufficiently conductive template layer has a conductivity of at least 104Q’1-cm’1at room temperature.

[0096] In various embodiments, the template layer has a different etch selectivity thanmolybdenum and can serve as an etch stop during the subtractive molybdenum etching process.

[0097] In some implementations, after operation 503, the substrate is transferred to another tool to perform operations 505 and 507.

[0098] In some cases, after operation 503, the substrate may be exposed to the atmosphere and oxygen.

[0099] After operation 503, operation 505 may optionally be performed. In operation 505, native oxides on the surface of the substrate (surface of the template layer) may be removed. In some embodiments, native oxide on the surface of the template layer is removed by exposing the substrate to an H2 plasma (which may be a direct plasma) for a short period of time (e.g., no more than about 60 seconds, such as 15 seconds, or no more than 5 minutes).

[0100] Following operation 505, operation 507 is performed. In operation 507, a layer of molybdenum-containing material is deposited on a template layer. In various implementations, operation 507 forms templated large-grain molybdenum film on a substrate.

[0101] In some embodiments, the grain size of the deposited molybdenum-containing layer is between about 2 and 10 times greater, e.g., between 4 and 5 times, than the thickness of the molybdenum-containing layer. For example, the grain size of the molybdenum-containing layer is between 40 nm and 50 nm when the thickness of the molybdenum-containing layer is about 10 nm. In various implementations, the average grain size of the molybdenum-containing layer is the same or larger than the average grain size of the template layer upon which it is deposited.

[0102] The molybdenum-containing material refers to any material that contains molybdenum. This includes pure molybdenum and substantially pure molybdenum. Substantially pure molybdenum may contain no more than trace amounts of other materials. For example, substantially pure molybdenum may be at least 99% molybdenum. In some embodiments, the molybdenum-containing material can contain some amounts of other compounds, dopants, and / or impurities depending on the particular precursors and precursors used to deposit the molybdenum-containing layer. In some embodiments, the molybdenum-containing material may be a compound material. For example, the molybdenum-containing material includes some amount of oxygen.

[0103] In some embodiments, the layer of molybdenum-containing material is deposited by a suitable CVD, PVD, or ALD process by sequential or simultaneous exposure to a molybdenum precursor and H2. In some embodiments, molybdenum precursors are a molybdenum halide or molybdenum oxyhalide such as M0CI5, MoOCU, MOO2CI2, or MoFe. In various implementations, the temperature of the substrate during the deposition is between about 300°Cand 500°C, for example, about 400°C. In some embodiments, the pressure of the process chamber during the deposition is between 10 Torr and 300 Torr, for example, about 50 Torr. Molybdenum-containing material in operation 507 may be deposited by using any suitable method. Additional details of the molybdenum deposition are provided herein.

[0104] In some embodiments, operations 505 and 507 are performed in the same processing tool under a common vacuum. In some embodiments, a molybdenum precursor may be capable of removing native oxide from the exposed surface of the template layer and forming a molybdenum-containing layer on the template layer. In some embodiments, exposing the substrate to molybdenum precursor concurrently removes the oxide from the exposed surfaces of a substrate and deposits a molybdenum-containing layer.

[0105] In some embodiments, operations 503 and 507 are performed on different tools. In some embodiments, the adhesion layer, template layer, and molybdenum-containing layers are deposited on a separate tool.

[0106] In some embodiments, after depositing a layer of molybdenum-containing material, the substrate may be planarized via a suitable CMP process.

[0107] After operation 507, operation 509 may optionally be performed. In operation 509, the layer of molybdenum-containing material is patterned. In some embodiments, the molybdenum-containing material is patterned using a photoresist and a hard mask, or by any other suitable method and combination of materials.

[0108] Following operation 509, operation 511 may optionally be performed. In operation 511, the layer of molybdenum-containing material is etched. In some embodiments, operation 511 forms interconnect lines from the large grain molybdenum-containing material.

[0109] In some embodiments, over-etching of the molybdenum-containing material, which may lead to misaligned vias, is prevented by an underlying template layer acting as an etch stop. In some embodiments, the underlying template layer is tungsten-containing material, and the difference between the etch rate between molybdenum and tungsten prevents over-etching of the molybdenum-containing material.

[0110] In some embodiments, after etching the molybdenum-containing material, if necessary, byproducts formed during the etch process are removed from the substrate and / or the process chamber.

[0111] In some embodiments, etching of the molybdenum-containing material and deposition or patterning of the molybdenum-containing layer are performed on different apparatuses. In some cases, transferring the substrate from the deposition or patterning apparatus to an apparatus etching the molybdenum-containing material can expose the substrate to theatmosphere / air, thereby leading to oxidation of the exposed surfaces (i.e., oxidation of the molybdenum-containing material).

[0112] In some embodiments, an adhesion layer may be optionally, deposited over the patterned or etched molybdenum-containing feature. In some cases, the adhesion layer acts as a hermetic seal in downstream processes, offering protection against oxidation of the underlying molybdenum-containing material. The adhesion layer may be a dielectric adhesion layer and can be deposited prior to depositing another template layer.

[0113] In some embodiments, the substrate may be exposed to a flowable dielectric material or undergo processing for forming air gaps between the metal lines.

[0114] In some embodiments, the substrate may be planarized to expose at least one of the underlying molybdenum-containing materials and / or dielectric material. In some implementations, planarization also exposes a portion of the dielectric adhesion layer. In various embodiments, planarization is accomplished via CMP.

[0115] In some embodiments, a layer of dielectric material may be deposited over the exposed surfaces of molybdenum-containing material and / or dielectric material. In various embodiments, the layer of dielectric material is an etch-stop material.

[0116] Operations in Figure 5 may be repeated to form interconnects with the desired architecture.

[0117] In some embodiments, the molybdenum line or interconnect is formed via subtractive processing. Figure 6 displays schematic illustrations of the subtractive molybdenum integration flow. As depicted in Figure 6, subtractive molybdenum integration 600 begins by providing a substrate 601, which may have vias 621 (e.g., Mo, W, Ru, Co, or Cu) formed by single damascene processing, and an etch stop layer 611 (e.g., aluminum oxide, aluminum nitride, and ODC). As depicted by 603, the vias 621 may be separated by dielectric material 622 and etch stop layers 611. Subsequently, as depicted in 603, a template layer 613 (e.g., tungsten template layer) is formed on the substrate. As shown in 605, large-grain molybdenum 625a is deposited on the template layer 613. If needed, large-grain molybdenum is planarized 625b (by CMP) as depicted in 607. As depicted in 609 and 611, a mask and / or photoresist 627a is formed in 609 on a large-grain molybdenum 625b layer and patterned in 611, thereby forming a patterned mask or photoresist 625b. Large-grain molybdenum 625b is then etched in 613 to form vias 625c. In some cases, the substrate may be cleaned to remove the byproducts 630 formed during the molybdenum etch, as shown in 615. In some cases, as depicted in 617, an adhesion layer 631 (e.g., dielectric layer) may be formed on the etched molybdenum, which may act as a hermetic seal to prevent oxidation. Then, as depicted in 619, the substrate may beexposed to a flowable dielectric and depositing dielectric material 632, or air gap forming process. As shown in 621, the substrate may be planarized by CMP, exposing the underlying molybdenum vias 625c. Following the planarization, dielectric etch stops 635 may be deposited over the exposed surfaces of molybdenum vias 625c and the underlying dielectric material 632. In various implementations, operations depicted in 601-623 may be repeated.

[0118] In various implementations, each of the operations (e.g., depositing a template layer 603, depositing molybdenum 605, patterning operations 609 and 611, etching molybdenum 613, and depositing adhesion layers 617) can be performed on different apparatuses. The substrates may be exposed to the atmosphere / air, and the substrates may be susceptible to oxidation during the transfer between the apparatus. For example, the substrate may be exposed to the atmosphere after planarization and before depositing dielectric (etch stop) material (i.e., between 621 and 623). In another example, the substrate may be exposed to the atmosphere between etching the molybdenum-containing material 613 and the dielectric fill / air gap process flow (i.e., 619). One or more of the following strategies can be adopted to manage oxidation in subtractive molybdenum processing.

[0119] In some embodiments, an integrated module is used to control the interface conditions and to address potential issues related to oxidation from exposure to the atmosphere. The integrated module connects two or more of the processing stations / apparatuses with a shared low-pressure ‘backbone’ to prevent atmospheric exposure between the different operations. For example, in the molybdenum subtractive integration process, a station / chamber for forming the dielectric adhesion layer (i.e., 617) may be integrated with a station / chamber for etching the molybdenum-containing material 613, forming a dielectric adhesion layer that hermetically seals the molybdenum-containing layer from subsequent exposure to the atmosphere. In some embodiments, an additional station / chamber may be employed to clean or otherwise condition the etched material before the deposition of the adhesion layer (i.e., 615). Moreover, in the molybdenum subtractive integration process, the deposition module for reflowable or otherwise fillable dielectric material 619 may be integrated with the station / chamber performing molybdenum etch 613. This may prevent molybdenum from being directly exposed to the atmosphere during the transfer to the next process tool. In various implementations, the integrated module generally improves the molybdenum line.

[0120] Alternatively or additionally, oxidation management may be achieved by, prior to exposing the molybdenum / substrates to the atmosphere, passivating the molybdenum oxides in controlled conditions and forming a layer of passivating oxide (e.g., molybdenum oxide). The passivating oxides can protect the underlying molybdenum against additional oxidationwhen exposed to the atmosphere. In some embodiments, passivated molybdenum surfaces are additionally modified by depositing an adhesive dielectric layer over the passivating oxides.

[0121] In some embodiments, passivating oxides are removed by etching the molybdenum oxides, and selectively depositing molybdenum-containing material to replenish the lost molybdenum-containing material. In some embodiments, the passivating oxides are etched by exposing the substrate to molybdenum chloride (M0CI5), or any suitable method. In some embodiments, etching the molybdenum oxide and selectively depositing the molybdenum- containing material are performed in the same process chamber.

[0122] Figure 7 is a graph showing the resistivity of the deposited molybdenum layer as a function of the thickness of the molybdenum layer. Figure 7 provides a comparison of the templated grain size and resistivity of Mo deposited on a PVD TiN substrate (top, dashed) and a PVD W substrate (bottom, solid). As shown in Figure 7, the grain size of the molybdenum deposited over the template layer is significantly larger (nearly epitaxial or epitaxial) than the molybdenum deposited without a template layer. In some embodiments, the average grain size of the molybdenum grown on the template layer is nearly 3 times the thickness of the deposited molybdenum layer, whereas the average grain size of the molybdenum grown without the template layer is less than 0.5 times the thickness of the deposited molybdenum layer. In some embodiments, the average grain size of the molybdenum grown on the template layer is at least 2 times, at least 3 times, or at least 5 times the thickness of the deposited molybdenum layer.

[0123] Figure 8 is a graph showing the resistivity of the deposited molybdenum layer as a function of the molybdenum layer thickness deposited via various methods. Figure 8 shows the resistivities of the molybdenum films deposited on various thicknesses (6nm, 3nm, and 2nm) of the tungsten template layer deposited by PVD, resistivity of the molybdenum film deposited without the template layer (i.e., deposited directly on a titanium nitride), and the resistivity of a ruthenium film deposited via PVD. As illustrated in Figure 8, the 6nm and 3nm tungsten template layers deposited via PVD produced similarly low-resistance molybdenum films. The 2nm tungsten template layers deposited via PVD led to higher resistivity than the fully templated films, although still substantially lower than the resistivity of the ruthenium and the molybdenum deposited on the TiN.Molybdenum deposition

[0124] In the methods described herein, molybdenum deposition may be performed to deposit molybdenum-containing material in the feature, such as those depicted in Figures 1A, IB, 2A - 2L, 3 and 4. Deposition of molybdenum as described herein involves reacting a Mo- containing precursor, also referred to as a molybdenum precursor. In some embodiments, amolybdenum halide compound as described above is used. In methods including surface treatment using a molybdenum halide compound, the same or different compound may be used for deposition.

[0125] In some embodiments, a Mo precursor is a molybdenum chloride (MoClx) compound also referred to as a molybdenum chloride precursor or MoClxprecursor. In some embodiments, Mo deposition may use a molybdenum oxyhalide precursor. Molybdenum chloride precursors are given by the formula MoClx, where x is 2, 3, 4, 5, or 6, and include molybdenum dichloride (MoCh), molybdenum trichloride (MoCh), molybdenum tetrachloride (M0CI4), molybdenum pentachloride (M0CI5), and molybdenum hexachloride (MoCh). In some embodiments, M0CI5 or MoCh, are used. While the description chiefly refers to MoClxprecursors, in other embodiments, other molybdenum halide precursors may be used. Molybdenum halide precursors are given by the formula MoXz, where X is a halogen (fluorine (F), chlorine (Cl), bromine (Br), or iodine (I)) and z is 2, 3, 4, 5, or 6. Examples of MoXzprecursors include molybdenum fluoride (MoFe). In some embodiments, a non-fluorine- containing MoXzprecursor is used to prevent fluorine etch or incorporation. In some embodiments, a non-bromine-containing and / or a non-iodine-containing MoXzprecursor is used to prevent etch or bromine or iodine incorporation.

[0126] In some embodiments, the feature may be filled using a molybdenum oxyhalide precursor. Molybdenum oxyhalide precursors are given by the formula MoOyXz, where X is a halogen (fluorine (F), chlorine (Cl), bromine (Br), or iodine (I)), and y and z are numbers greater than 0 such that MoOyXzforms a stable compound. Examples of molybdenum oxyhalides include molybdenum dichloride dioxide (MOO2CI2), molybdenum tetrachloride oxide (MoOCU), molybdenum tetrafluoride oxide (M00F4), molybdenum dibromide dioxide (MoO2Br2), and the molybdenum iodides MOO2I, and MO4O11I. It should be understood that as used herein the term molybdenum oxyhalide precursor may refer to a molybdenum oxyhalide precursor as described above or a molybdenum-containing oxyhalide precursor that includes molybdenum, oxygen, a halide and one or more other elements. In some embodiments, molybdenum oxyhalide or molybdenum-containing oxyhalides may include multiple different halogens (e.g., F and Cl and / or I and / or Br, etc.). A feature may be filled with molybdenum using a MoClxprecursor, MoOyXzprecursor, or a combination thereof.

[0127] For deposition of molybdenum into the feature, the molybdenum precursor may be reacted with a co-reactant. Examples of co-reactants include hydrogen (H2), silane (SiFE), diborane (B2H6), germane (GeFE), ammonia (NH3), and hydrazine (N2H4).

[0128] In some embodiments, deposition of molybdenum may use a plasma-based process.Gas may be fed into a remote or in- situ plasma generator to generate plasma species. Examples of gas that may be used to generate plasma may be a hydrogen-containing gas, such as H2, nitrogen-containing gas, such as nitrogen (N2) and other gases, such as Ar and NH3. The plasma species may be inert or react with the molybdenum precursor to form a film.

[0129] A feature may be filled with molybdenum by atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD). Thermal ALD or plasma enhanced ALD (PEALD) may be used. Similarly, thermal CVD or plasma enhanced CVD (PECVD) may be used.

[0130] ALD is a surface-mediated deposition technique in which doses of a precursor and a reactant are sequentially introduced into a deposition chamber. One or more cycles of sequential doses of a molybdenum precursor and reactant may be used to deposit Mo. Lor example, in the deposition of an initial molybdenum laye, M0CI5 may be used as a precursor and H2 as a reducing agent. Doses of M0CI5 and H2 are sequentially introduced into the deposition chamber with a purge gas, such as argon, flowed between. Lor ALD, the temperature of the substrate and the pressure of the chamber may be controlled. Lor example, the substrate may be heated between 200°C and 800°C, e.g., between 250°C and 550°C or between 350°C and 450°C. In some embodiments, the chamber may be pressurized between 10 Torr and 200 Torr, e.g., between 50 Torr and 90 Torr. In some embodiments, the temperature and / or pressure may be used to control the rate of reactions. In some embodiments, the temperature and / or pressure may be used to control selectivity.

[0131] In some embodiments, molybdenum fill may involve CVD. In a CVD process, the molybdenum precursor and reactant are in vapor phase together in the deposition chamber. Generally speaking, a CVD process fills a feature faster than an ALD process. In one example, the precursor may be a molybdenum oxychloride, such as MOO2CI2, and is flowed into the chamber with a reactant, such as H2. In this example, the wafer is simultaneously exposed to the precursor and reactant, which react and fill features with Mo.

[0132] In still some other embodiments, a feature may be filled using a pulsed CVD process. The pulsed CVD process continuously flows a reactant into a chamber while pulses of a precursor flow into the chamber. Lor example, H2 gas may be flowed into the chamber and is continuously flowing into the chamber while the molybdenum-containing precursor is intermittently flowing into the chamber. The temperature of the substrate and pressure in the chamber may be controlled during a CVD operation.

[0133] Molybdenum may be selectively deposited into a feature using the methods described herein. Selective deposition refers to preferential deposition on a first material with respect toa second material. Molybdenum deposition and growth may be easier on a metal material relative to molybdenum deposition and growth on a dielectric material. For example, a feature may have a sidewall surface of SiCh and a TiN plug in the bottom portion of the feature. In selective deposition, molybdenum is deposited into the feature and may grow on the TiN plug but not grow (or grow to a lesser extent) on the SiCh sidewall surfaces.

[0134] Process conditions such as the precursor gas, the reducing agent, process temperature, process pressure, and exposure time may affect the selectivity of the molybdenum film being deposited. Different precursor gases may have different process windows in which molybdenum film may be selectively deposited. Generally speaking, M0CI5 gas has a large process window, i.e., a large temperature and pressure range, where the precursor gas retains its selectivity. For example, M0CI5 may be selectively deposited on a metal material with respect to a dielectric material where the process temperature is 200°C to 800°C, e.g., 250°C to 550°C, or 300°C to 500°C. Generally speaking, higher process temperatures and higher process pressures reduce the selectivity of the deposited gas. For example, at higher temperatures, a precursor gas such as M0CI5 may lose its selectivity and deposit molybdenum film on both a metal surface and a dielectric surface within a feature.

[0135] M0CI5 may be reacted with different reactants to deposit a molybdenum film. Described below are examples of deposition of molybdenum film within a feature using a M0CI5 precursor and different process controls. In a first example, the M0CI5 precursor is reacted with a hydrogen (H2) reactant using the deposition methods described above. In the description herein, the metal precursors are reacted with hydrogen (H2) as a co-reactant (also referred to as a hydrogen reactant or H2 reactant). However, other reactants may be used instead of hydrogen, including other hydrogen-containing reactants such as SiH4, B2H6, NH3, as appropriate. While reactants such as B2H6 and / or SiH4 are stronger reducing agents, they can also result in higher resistivity. Thus, in some embodiments, using H2 as described herein is advantageous. Process temperatures for selective deposition of the molybdenum film may be between 200°C and 800°C, e.g., 250°C to 550°C, or 300°C to 500°C. At these temperatures, the molybdenum film is selectively deposited on conductive metal or metal compound surfaces, such as a TiN surface, in a feature relative to dielectric surfaces. The molybdenum film grows from the locations where the conductive surfaces are located in a feature. If the conductive surface is a TiN plug at the bottom of the feature, the molybdenum film may be deposited and grown from the bottom of the feature. In a second example, the molybdenum film may be deposited using the M0CI5 precursor and the H2 reactant, but at higher temperatures, i.e., above 800°C. This process window may have the molybdenum film deposited on both the dielectricand conductive surfaces within the feature. The deposition of the molybdenum film on the dielectric surface may be used to create a barrierless molybdenum layer in the feature.

[0136] In some embodiments, selective deposition is performed using a molybdenum oxyhalide precursor. As described above, the surface treatments described above significantly improve the selectivity of Mo deposition from MOO2CI2. As indicated above, examples of MoOyXz precursors include MOO2CI2, MoOCU, MoOF4, MoO2Br2, MOO2I, and MO4O11I. The feature may be filled using ALD, plasma-enhanced ALD, chemical vapor deposition (CVD), or plasma-enhanced CVD. For ALD or CVD, H2 may be the reducing agent. Molybdenum deposits more quickly using a molybdenum oxyhalide precursor than the MoClxprecursor used in the surface treatment. For example, a MoOyXzprecursor may deposit molybdenum at a deposition rate at least twice as fast as a MoClxprecursor for a non-plasma process. Plasma- enhanced processes may be used to fill features at lower temperatures and / or increase deposition rates.

[0137] In some embodiments, filling a feature can involve depositing a nucleation layer. A nucleation layer is a thin layer that supports bulk deposition. It may be conformal to the feature. In many embodiments, a nucleation layer is deposited by an ALD process. In some embodiments, a Mo nucleation layer is deposited using one or more of a boron-containing reducing agent (e.g., B2H6) or a silicon-containing reducing agent (e.g., SilL) as a co-reactant. For example, one or more S / Mo cycles or Mo / S cycles may be used to deposit a Mo nucleation layer. In another example, one or more B / Mo cycles or Mo / B cycles may be used to deposit a Mo nucleation layer on which a bulk Mo layer is deposited. B refers to a pulse of diborane or other boron-containing reducing agent and S to a pulse of silane or other silicon-containing reducing agent, such that S / Mo refers to a pulse of silane followed by a pulse of a Mo- containing precursor. B / Mo and S / Mo cycles (or Mo / B and / or Mo / S) may both be used to deposit a Mo nucleation layer, e.g., x(B / Mo) + y(S / Mo), with x and y being integers. Examples of boron-containing reactants include diborane (B2H6), alkyl boranes, alkyl boron, aminoboranes (CH3)2NB(CH2)2, carboranes such as C2BnHn+2, and other boranes. Examples of boranes include BnHn+4, BnHn+6, BnHn+8, BnHm, where n is an integer from 1 to 10, and m is a different integer than m. Examples of silicon-containing reducing agents including silane (SiFL) and other silanes such as disilane (Si2H6).

[0138] In some embodiments, deposition of a Mo nucleation layer may involve using a non- oxygen-containing precursor, e.g., molybdenum hexafluoride (MoFe) or molybdenum pentachloride (M0CI5). Oxygen in oxy gen-containing precursors may react with a silicon- or boron-containing reducing agent to form MoSixOyor MoBxOy, which are impure, highresistivity films. In some embodiments, oxy gen-containing precursors may be used for nucleation layer deposition with oxygen incorporation minimized. Oxygen incorporation can be minimized by high reducing agent flows (e.g., greater than 100:1 volumetric flow rate of reducing agent to oxy gen-containing Mo precursor).

[0139] In some embodiments, H2 may be used as a reducing gas for Mo nucleation layer deposition instead of a boron-containing or silicon-containing reducing gas. Example thicknesses for deposition of a Mo nucleation layer range from 5 A to 30 A. Films at the lower end of this range may not be continuous; however, as long as they can help initiate continuous bulk Mo growth, the thickness may be sufficient.

[0140] In some embodiments, the reducing agent pulses during deposition of a nucleation or bulk Mo layer may be done at lower substrate temperatures than the Mo precursor pulses. For example, or B2H6 or a SitU (or other boron- or silicon-containing reducing agent) pulse may be performed at a temperature below 300 °C, with the Mo pulse at temperatures greater than 300 °C.

[0141] In some embodiments, the reducing agent is NH3 or other nitrogen-containing reducing agents such as hydrazine (N2H4). NH3 chemisorption on dielectrics is more favorable than that of H2. In some embodiments, the reducing agent and precursor are selected such that they react without reducing agent dissociation. NH3 reacts with metal oxychlorides and metal chlorides without dissociation. This is in contrast to, for example, AED from metal oxychlorides that use H2 as a reducing agent; H2 dissociates on the surface to form adsorbed atomic hydrogen, which results in very low concentrations of reactive species and low surface coverage during initial nucleation of metal on the dielectric surface. By using NH3 and metal oxychloride or metal chloride precursors, nucleation delay is reduced or eliminated at deposition temperatures up to hundreds of degrees lower than those used by H2 reduction of the same metal precursors.

[0142] In some embodiments, the reducing agent may be a boron-containing or silicon- containing reducing agent such as B2H6 or SitU. These reducing agents may be used with metal chloride precursors, with metal oxychlorides; however, the B2H6 and SitU may react with water formed as a byproduct during the AED process and form solid B2O3 and S i O2. These are insulating and can remain in the film, increasing resistivity. Use of NH3 also has improved adhesion over B2H6 and SitU ALD processes on certain surfaces, including AI2O3. The resulting nucleation layer is generally not a pure elemental film but a metal nitride or metal oxynitride film. In some embodiments, there may be residual chlorine or fluorine from the deposition, particularly if the deposition is performed at low temperatures. In some embodiments, there may be no more than a trace amount of residual chlorine or fluorine. Insome embodiments, the nucleation layer is an amorphous layer. Impurities in the film (e.g., oxygen, NH3, chlorine, or other halogens) facilitate the growth of an amorphous microstructure. In some embodiments, the nucleation layer as deposited is an amorphous molybdenum oxynitride layer or an amorphous molybdenum nitride layer. The amorphous character templates large grain growth in the subsequently deposited conductor. The surface energy of nitride or oxynitride relative to an oxide surface is much more favorable than that of a metal on an oxide surface, facilitating the formation of a continuous and smooth film on the dielectric. This allows formation of thin, continuous layers. Example thicknesses of the nucleation layer range from 5-30A as deposited. Depending on the temperature, this may be about 5-50 ALD cycles, for example.Etch

[0143] Etch operations may be used in the methods for filling features with Mo films. Etch operations remove materials such as metals, oxides, and nitrides from the feature. For example, an etch process may partially or completely remove a liner layer from a feature. In another example, the etch process may be used to reduce the thickness of a liner layer. The etch operation, in some embodiments, may involve soaking the feature soaked in a Mo halide. In some embodiments, an etch operation involves soaking the feature with a MoClx such as MoCl- 5. In some embodiments, the soak may be done continuously with the Mo halide gas. In some embodiments, the soak may be pulsed, cycling the Mo halide with a purge gas, such as argon (Ar).

[0144] A MoClx precursor may be used for both deposition and etch operations. For example, in certain process windows, a M0CI5 precursor may concurrently grow a Mo film and etch away a portion of the film in the feature. The process is considered a net etch operation if the rate of material removed is greater than the material deposited by the precursor. The speed at which the precursor deposits material and etches material may be controlled by a variety of process conditions, including the type of reactant used and the process temperature. Generally speaking, the lower the temperature, the higher the ratio of etching away material is relative to the deposition of material. At higher temperatures, the same precursor and reactant may be used as a net deposition operation, i.e., the amount of material deposited is greater than the material removed. For example, M0CI5 precursor and H2 reactant may be used in an etch operation when the process temperature is below 400 °C. The same precursor of M0CI5 and H2 reactant may be used in a deposition operation when the process temperature is above 550 °C.

[0145] In some embodiments, the MoClx precursor at high temperatures, e.g., above 550 °C, may continue to etch material at a faster rate than depositing material. For example, M0CI5may be used to etch a feature by a soak without a reactant. In this example, the temperature may be as high as 700 °C, and will continue to etch away material from the feature. In operations where the feature is soaked in a M0CI5 without a reactant, the increased temperature may increase the rate at which material is etched from the feature.

[0146] A feature may have surface oxide or contaminants on it. For example, the surface of an underlying TiN, WN, or W layer may be oxidized. If left, the oxidized surface can result in higher resistivity. Clean operations are used to remove such oxides and contaminants. In some embodiments, the clean operation may have the feature soaked in a Mo precursor gas, typically a Mo halide. Similar to the etch operations described above, the precursor gas may be a MoClxprecursor. In some embodiments, the soak may be done continuously. In some embodiments, the soak may be pulsed, cycling MoClxand a purge gas, such as argon (Ar). The precursor may be a non-oxygen Cl-containing Mo compound able to remove oxidation from the feature’s surfaces. Examples of MoClxcompounds are given ae. A Cl-containing precursor may be used where traditional cleaning with thermal or plasma H2 does not work, such as where the oxidized surface is stable on the surface material. A Cl-containing precursor is less likely to over-etch a feature’s liner layer or attack a feature’s surfaces than an F-containing compound.Apparatus

[0147] Figure 9 depicts a schematic illustration of an embodiment of an process station 900 having a process chamber 902 for maintaining a low-pressure environment. In some embodiments, a plurality of process stations may be included in a common low-pressure process tool environment. For example, Figures 10A and 10B depict embodiments of a multi-station processing tool 1000. In some embodiments, one or more hardware parameters of process station 900, including those discussed in detail below, may be adjusted programmatically by one or more computer controllers 1050. In some other embodiments, a process chamber may be a single station chamber. In various embodiments, molybdenum- containing material may be deposited using the process stations illustrated in Figures 9, 10A, or 10B. In some embodiments, a tungsten-containing layer or a template layer can be deposited in the same process station being used to deposit the molybdenum-containing material.

[0148] The process station 900 fluidly communicates with reactant delivery system 901a for delivering process gases to a distribution showerhead 906. Reactant delivery system 901a includes a mixing vessel 904 for blending and / or conditioning process gases, such as a Mo precursor-containing gas, a hydrogen-containing gas, an argon or other carrier gas, or other reactant-containing gas, for delivery to showerhead 906. One or more mixing vessel inlet valves 920 may control introduction of process gases to mixing vessel 904. In variousembodiments, deposition of an initial Mo layer is performed in process station 900 and in some embodiments, other operations such as in-situ clean or Mo gap fill may be performed in the same or another station of the multi-station processing tool 1000 as further described below with respect to Figure 10A.

[0149] As an example, the embodiment of Figure 9 includes a vaporization point 903 for vaporizing liquid reactant to be supplied to the mixing vessel 904. In some embodiments, vaporization point 903 may be a heated vaporizer. In some embodiments, a liquid precursor or liquid reactant may be vaporized at a liquid injector (not shown). For example, a liquid injector may inject pulses of a liquid reactant into a carrier gas stream upstream of the mixing vessel 904. In one embodiment, a liquid injector may vaporize the reactant by flashing the liquid from a higher pressure to a lower pressure. In another example, a liquid injector may atomize the liquid into dispersed microdroplets that are subsequently vaporized in a heated delivery pipe. Smaller droplets may vaporize faster than larger droplets, reducing a delay between liquid injection and complete vaporization. Faster vaporization may reduce a length of piping downstream from vaporization point 903. In one scenario, a liquid injector may be mounted directly to mixing vessel 904. In another scenario, a liquid injector may be mounted directly to showerhead 906.

[0150] In some embodiments, a liquid flow controller (LFC) upstream of vaporization point 903 may be provided for controlling a mass flow of liquid for vaporization and delivery to process chamber 902. For example, the LFC may include a thermal mass flow meter (MFM) located downstream of the LFC. A plunger valve of the LFC may then be adjusted responsive to feedback control signals provided by a proportional-integral-derivative (PID) controller in electrical communication with the MFM. However, it may take one second or more to stabilize liquid flow using feedback control. This may extend a time for dosing a liquid reactant. Thus, in some embodiments, the LFC may be dynamically switched between a feedback control mode and a direct control mode. In some embodiments, this may be performed by disabling a sense tube of the LFC and the PID controller.

[0151] Showerhead 906 distributes process gases toward substrate 912. In the embodiment shown in Figure 9, the substrate 912 is located beneath showerhead 906 and is shown resting on a pedestal 908. Showerhead 906 may have any suitable shape and may have any suitable number and arrangement of ports for distributing process gases to substrate.

[0152] In some embodiments, pedestal 908 may be raised or lowered to expose substrate 912 to a volume between the substrate 912 and the showerhead 906. In some embodiments, pedestal 908 may be temperature controlled via heater 910. Pedestal 908 may be set to anysuitable temperature, such as between about 250°C and about 800°C during operations for performing various disclosed embodiments. It will be appreciated that, in some embodiments, pedestal height may be adjusted programmatically by a suitable computer controller. At the conclusion of a process phase, pedestal 908 may be lowered during another substrate transfer phase to allow removal of substrate 912 from pedestal 908.

[0153] In some embodiments, a position of showerhead 906 may be adjusted relative to pedestal 908 to vary a volume between the substrate 912 and the showerhead 906. Further, it will be appreciated that a vertical position of pedestal 908 and / or showerhead 906 may be varied by any suitable mechanism within the scope of the present disclosure. In some embodiments, pedestal 908 may include a rotational axis for rotating an orientation of substrate 912. It will be appreciated that, in some embodiments, one or more of these example adjustments may be performed programmatically by one or more suitable computer controllers 950. The computer controller 950 may include any of the features described below with respect to controller 950 of Figure 9.

[0154] In some embodiments where plasma may be used as discussed above, showerhead 906 and pedestal 908 electrically communicate with a radio frequency (RF) power supply 914 and matching network 916 for powering a plasma. In some embodiments, the plasma energy may be controlled by controlling one or more of a process station pressure, a gas concentration, an RF source power, an RF source frequency, and a plasma power pulse timing. For example, RF power supply 914 and matching network 916 may be operated at any suitable power to form a plasma having a desired composition of radical species. Likewise, RF power supply 914 may provide RF power of any suitable frequency. In some embodiments, RF power supply 914 may be configured to control high- and low-frequency RF power sources independently of one another. Example low-frequency RF frequencies may include, but are not limited to, frequencies between 0 kHz and 900 kHz. Example high-frequency RF frequencies may include, but are not limited to, frequencies between 1.8 MHz and 2.45 GHz, or greater than about 13.56 MHz, or greater than 27 MHz, or greater than 80 MHz, or greater than 60 MHz. It will be appreciated that any suitable parameters may be modulated discretely or continuously to provide plasma energy for the surface reactions.

[0155] In some embodiments, the plasma may be monitored in- situ by one or more plasma monitors. In one scenario, plasma power may be monitored by one or more voltage, current sensors (e.g., VI probes). In another scenario, plasma density and / or process gas concentration may be measured by one or more optical emission spectroscopy sensors (OES). In some embodiments, one or more plasma parameters may be programmatically adjusted based onmeasurements from such in-situ plasma monitors. For example, an OES sensor may be used in a feedback loop for providing programmatic control of plasma power. It will be appreciated that, in some embodiments, other monitors may be used to monitor the plasma and other process characteristics. Such monitors may include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure transducers.

[0156] In some embodiments, instructions for a controller 950 may be provided via input / output control (IOC) sequencing instructions. In one example, the instructions for setting conditions for a process phase may be included in a corresponding recipe phase of a process recipe. In some cases, process recipe phases may be sequentially arranged, so that all instructions for a process phase are executed concurrently with that process phase. In some embodiments, instructions for setting one or more reactor parameters may be included in a recipe phase. For example, a first recipe phase may include instructions for setting a flow rate of an inert and / or a reactant gas (e.g., a Mo precursor), instructions for setting a flow rate of a carrier gas (such as argon), and time delay instructions for the first recipe phase. A second, subsequent recipe phase may include instructions for modulating or stopping a flow rate of an inert and / or a reactant gas, and instructions for modulating a flow rate of a carrier or purge gas and time delay instructions for the second recipe phase. A third recipe phase may include instructions for modulating a flow rate of a second reactant gas such as Fh, instructions for modulating the flow rate of a carrier or purge gas, instructions for igniting a plasma, and time delay instructions for the third recipe phase. A fourth, subsequent recipe phase may include instructions for modulating or stopping a flow rate of an inert and / or a reactant gas, and instructions for modulating a flow rate of a carrier or purge gas and time delay instructions for the fourth recipe phase. It will be appreciated that these recipe phases may be further subdivided and / or iterated in any suitable way within the scope of the present disclosure.

[0157] Further, in some embodiments, pressure control for process station 900 may be provided by butterfly valve 918. As shown in the embodiment of Figure 9, butterfly valve 918 throttles a vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of process station 900 may also be adjusted by varying a flow rate of one or more gases introduced to the process station 900.

[0158] Figure 10A and Figure 10B show examples of processing systems. Figure 10A shows an example of a processing system including multiple chambers. The system 1000 includes a transfer module 1003. The transfer module 1003 provides a clean, vacuum environment to minimize risk of contamination of substrates being processed as they are moved between various modules. Mounted on the transfer module 1003 is a multi- station chamber 1009capable of performing in-situ clean and / or ALD processes described above. Surface treatment and / or initial Mo layer deposition may be performed in the same or different station or chamber as the subsequent Mo gap fill.

[0159] Chamber 1009 may include multiple stations 1011, 1013, 1015, and 1017 that may sequentially perform operations in accordance with disclosed embodiments. For example, chamber 1009 may be configured such that station 1011 performs an in-situ treatment using a MoClx precursor. Station 1013 may be configured to selectively treat the field region and upper sidewalls and stations 1015 and 1017 may be configured to perform ALD of bulk Mo using an molybdenum oxyhalide precursor and H2. In another example, chamber 1009 may be configured such that station 1011 performs in-situ clean, station 1013 performs ALD of an initial Mo layer, station 1013 selectively treats the layer, and 1014 deposition of bulk Mo. In another example, the chamber 1009 may be configured to do parallel processing of substrates, with each station performing multiple processes sequentially.

[0160] Two or more stations may be included in a multi-station chamber, e.g., 2-6, with the operations appropriately distributed. For example, a two-station chamber may be configured to perform ALD of an initial Mo layer in a first station followed by ALD of bulk Mo in a second station. Stations may include a heated pedestal or substrate support, one or more gas inlets or showerhead or dispersion plate.

[0161] Also mounted on the transfer module 1003 may be one or more single or multi-station modules 1007. In some embodiments, a preclean as described above may be performed in a module 1007, after which the substrate is transferred under vacuum to another module (e.g., another module 1007 or chamber 1009) for ALD. In another example, a module for selective treatment of a film may be mounted on the transfer module.

[0162] The system 1000 also includes one or more wafer source modules 1001, where wafers are stored before and after processing. An atmospheric robot (not shown) in the atmospheric transfer chamber 1019 may first remove wafers from the source modules 1001 to loadlocks 1021. A wafer transfer device (generally a robot arm unit) in the transfer module 1003 moves the wafers from loadlocks 1021 to and among the modules mounted on the transfer module 1003.

[0163] In some embodiments, ALD of Mo is performed in a first chamber, which may be part of a system like system 1000, with CVD or PVD of W or Mo or other conductive material deposited as an overburden layer performed in another chamber, which may not be coupled to a common transfer module, but part of another system.

[0164] Figure 10B is an embodiment of a system 1000. The system 1000 in Figure 10B haswafer source modules 1001, a transfer module 1003, atmospheric transfer chamber 1019, and loadlocks 1021, as described above with reference to Figure 10A. The system in Figure 10B has three single station modules 1057a-17875c. The system 1000 may be configured to sequentially perform operations in accordance with disclosed embodiments. For example, the single station modules 1057a-1057c may be configured so that a first module 1057a performs a surface treatment, a second module 1057b performs ALD of an initial Mo layer using a molybdenum halide precursor, and a third module 1057c performs ALD of bulk Mo using a molybdenum oxyhalide precursor. In this example, an in- situ clean may be optionally performed in second module 1057b instead of or in addition to a preclean in first module 1057a. In another example, the single station modules 1057a-1057c may be configured so that a first module 1057a performs a deposition of an initial metal layer, a second module 1057b performs selective treatment, and a third module 1057c performs ALD of bulk Mo using a molybdenum oxyhalide precursor. In yet another example, one module may be configured for deposition, another module for selective treatment, and another module for etch.

[0165] Stations may include a heated pedestal or substrate support, one or more gas inlets or showerhead or dispersion plate as described above with reference to Figure 17.

[0166] Referring to Figures 10A and 10B, in various embodiments, a system controller 1029 is employed to control process conditions during deposition. The controller 1029 will typically include one or more memory devices and one or more processors. A processor may include a CPU or computer, analog and / or digital input / output connections, stepper motor controller boards, etc. Such a system controller may be employed in control of any of the processes and apparatus described herein.

[0167] The controller 1029 may control all the activities of the apparatus. The system controller 1029 executes system control software, including sets of instructions for controlling the timing, mixture of gases, chamber pressure, chamber temperature, wafer temperature, radio frequency (RF) power levels, wafer chuck or pedestal position, and other parameters of a particular process. Other computer programs stored on memory devices associated with the controller 1029 may be employed in some embodiments.

[0168] Typically, there will be a user interface associated with the controller 1029. The user interface may include a display screen, graphical software displays of the apparatus and / or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc.

[0169] System control logic may be configured in any suitable way. In general, the logic can be designed or configured in hardware and / or software. The instructions for controlling thedrive circuitry may be hard coded or provided as software. The instructions may be provided by “programming.” Such programming is understood to include logic of any form, including hard coded logic in digital signal processors, application-specific integrated circuits, and other devices which have specific algorithms implemented as hardware. Programming is also understood to include software or firmware instructions that may be executed on a general- purpose processor. System control software may be coded in any suitable computer readable programming language.

[0170] The computer program code for controlling the Mo precursor pulses, hydrogen pulses, and argon flow, and other processes in a process sequence can be written in any conventional computer readable programming language: for example, assembly language, C, C++, Pascal, Fortran, or others. Compiled object code or script is executed by the processor to perform the tasks identified in the program. Also as indicated, the program code may be hard coded.

[0171] The controller parameters relate to process conditions, such as, for example, process gas composition and flow rates, temperature, pressure, cooling gas pressure, substrate temperature, and chamber wall temperature. These parameters are provided to the user in the form of a recipe and may be entered utilizing the user interface.

[0172] Signals for monitoring the process may be provided by analog and / or digital input connections of the system controller 1029. The signals for controlling the process are output on the analog and digital output connections of the deposition apparatus.

[0173] The system software may be designed or configured in many ways. For example, various chamber component subroutines or control objects may be written to control operation of the chamber components necessary to carry out the deposition processes in accordance with the disclosed embodiments. Examples of programs or sections of programs for this purpose include substrate positioning code, process gas control code, pressure control code, and heater control code.

[0174] In some implementations, a controller 1029 is part of a system, which may be part of the above-described examples. Such systems can include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and / or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems. The controller 1029, depending on the processing requirements and / or the type of system, may be programmed to control any of the processes disclosed herein, including thedelivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and / or load locks connected to or interfaced with a specific system.

[0175] Broadly speaking, the controller may be defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0176] The controller 1029, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller 1029 may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. The parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, such as byincluding one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

[0177] Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a PVD chamber or module, a CVD chamber or module, an ALD chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and / or manufacturing of semiconductor wafers.

[0178] As noted above, depending on the process step or steps to be performed by the tool, the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0179] The controller 1029 may include various programs. A substrate positioning program may include program code for controlling chamber components that are used to load the substrate onto a pedestal or chuck and to control the spacing between the substrate and other parts of the chamber such as a gas inlet. A substrate tilt and rotation program may include for tilt and rotation. A process gas control program may include code for controlling gas composition, flow rates, pulse times, and optionally for flowing gas into the chamber prior to deposition in order to stabilize the pressure in the chamber. A pressure control program may include code for controlling the pressure in the chamber by regulating, e.g., a throttle valve in the exhaust system of the chamber. A heater control program may include code for controlling the current to a heating unit that is used to heat the substrate. Alternatively, the heater control program may control delivery of a heat transfer gas such as helium to the wafer chuck.

[0180] Examples of chamber sensors that may be monitored during deposition include mass flow controllers, pressure sensors such as manometers, and thermocouples located in the pedestal or chuck. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain desired process conditions.

[0181] The foregoing describes implementation of disclosed embodiments in a single or multi-chamber semiconductor processing tool. The apparatus and process described herein may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, though not necessarily, such tools / processes will be used or conducted together in a common fabrication facility. Lithographic patterning of a film typically includes some or all of the following steps, each step provided with a number of possible tools: (1) application of photoresist on a workpiece, i.e., substrate, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or UV curing tool; (3) exposing the photoresist to visible or UV or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove resist and thereby pattern it using a tool such as a wet bench; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma- assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.

Claims

CLAIMSWhat we claim is:

1. A method comprising: providing a substrate having a first via interconnect, wherein the first via interconnect is adjacent to a first dielectric material; depositing a template layer over the first via interconnect and the first dielectric material; depositing a molybdenum-containing material on the template layer, wherein the template layer templates the grain growth in the molybdenum-containing material; etching the molybdenum-containing material to form a second via interconnect over the first via interconnect; and forming a second dielectric material over the second via interconnect.

2. The method of claim 1, further comprising depositing an adhesion layer over the second via interconnect prior to forming a second dielectric material.

3. The method of claim 1 , further comprising depositing a hermetic dielectric layer over the second via interconnect prior to forming the second dielectric material, wherein the hermetic dielectric layer is configured to hermetically seal the second via interconnect from atmospheric exposure.

4. The method of claim 1, further comprising planarizing and exposing the second via interconnect.

5. The method of claim 1 , further comprising depositing a dielectric etch stop layer over the second dielectric material and the exposed second via interconnect.

6. The method of claim 1, wherein etching the molybdenum-containing material forms an etch byproduct.

7. The method of claim 6, further comprising removing the etch byproduct.

8. The method of claim 1 further comprising, after depositing the molybdenum- containing material on the template layer and prior to etching the molybdenum-containing material, depositing a patterning mask or a photoresist over the molybdenum-containing material.

9. The method of claim 1 further comprising, after depositing the molybdenum- containing material on the template layer and prior to etching the molybdenum-containing material, planarizing the molybdenum-containing material.

10. A method comprising: providing a metallic template layer on a substrate; and depositing a molybdenum-containing material on the metallic template layer, wherein the metallic template layer templates grain growth in the molybdenum-containing material.

11. The method of claim 10, wherein the molybdenum-containing material is elemental molybdenum.

12. The method of claim 10, wherein the molybdenum-containing material is deposited using a CVD, ALD, PVD, or PEALD process.

13. The method of claim 10, wherein the metallic template layer is an elemental tungsten film deposited by PVD, CVD, ALD, or PEALD.

14. The method of claim 13, further comprising depositing an adhesion layer on the substrate prior to depositing the metallic template layer.

15. The method of claim 14, wherein the adhesion layer is a molybdenum- containing material.

16. The method of any of claims 10-15, in which the metallic template layer is selectively deposited on a portion of the substrate.

17. The method of any of claims 10-15, wherein, prior to deposition of the molybdenum-containing material, a portion of the metallic template layer is etched to prevent molybdenum deposition in the etched areas.

18. The method of any of claims 10-15, further comprising removing oxide from the metallic template layer prior to depositing the molybdenum-containing material.

19. The method of claim 18, wherein the removal of the oxide and deposition of the molybdenum-containing material occur concurrently.

20. The method of claim 10, further comprising etching the molybdenum- containing material, wherein the metallic template layer acts as an etch stop.

21. An apparatus for the formation of the films in claims 10-16 comprising separate modules for the adhesive, template, and molybdenum-containing material.

22. The apparatus of claim 21, wherein two or more of the modules are connected to a common low-pressure backbone to prevent atmospheric exposure of the substrate.

23. A method comprising: exposing patterned molybdenum features on a template layer to an atmosphere, thereby forming oxide on the patterned molybdenum features; removing the oxide from the patterned molybdenum features; and selectively depositing molybdenum on the patterned molybdenum features.

24. The method of claim 23, further comprising chemical mechanical planarization (CMP) and dielectric capping, wherein the patterned molybdenum features are exposed to the atmosphere between CMP and dielectric capping.

25. The method of claim 23, wherein the atmospheric exposure is between etch molybdenum to form the patterned features and dielectric fill.

26. A subtractive integration process wherein a hermetic dielectric deposition module is integrated with a subtractive molybdenum etch chamber configured to hermetically seal etched molybdenum by a dielectric before subsequent atmospheric exposure.

27. A subtractive integration process wherein a subtractive molybdenum etch chamber is integrated with a molybdenum ALD / CVD chamber28. A subtractive integration process wherein a hermetic dielectric deposition module is integrated with a subtractive molybdenum etch chamber configured to hermetically seal etched Mo by a dielectric before subsequent atmospheric exposure.

29. A subtractive integration process in which a hermetic dielectric deposition module is integrated with a molybdenum ALD / CVD deposition module configured to hermetically seal deposited Mo by a dielectric before subsequent atmospheric exposure.

30. A subtractive integration process in which a subtractive molybdenum etch chamber, a molybdenum ALD / CVD chamber, and a hermetic dielectric deposition module are all integrated on the same low-pressure platform such that air exposure of samples does not occur between any of these steps.

Images