Gate driver on array circuit of display panel, driving method for display panel, and display apparatus

Abstract

Provided are a gate driver on array circuit of a display panel, a driving method for a display panel, and a display apparatus, which relate to the technical field of display. Among multiple stages of driving units comprised in the gate driver on array circuit, a first input control circuit of each stage of driving unit can, under the control of a synchronous emission control signal, control an input end of the current stage of driving unit to be connected to input ends of the other stages of driving units, so that an emission signal is simultaneously transmitted to the multiple stages of driving units. In addition, a second input control circuit of each stage of driving unit can, under the control of a sequential emission control signal, control an output end of the current stage of driving unit to be connected to the input end of another stage of the driving units, so that the emission signal is transmitted to the multiple stages of driving units stage by stage. Thus, the gate driver on array circuit can not only simultaneously output the emission signal to a plurality of rows of pixels to drive the plurality of rows of pixels to synchronously emit light, but also sequentially output the emission signal to the plurality of rows of pixels to drive the plurality of rows of pixels to sequentially emit light. The described gate driver on array circuit has diverse driving modes and a good driving effect.

Description

Gate driving circuit and driving method for display panel, display device

[0001] This application claims priority to Chinese Patent Application No. 202411666894.8, filed on November 20, 2024, entitled “Gate driving circuit and driving method for display panel, display device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and in particular to a gate driving circuit and driving method for a display panel, and a display device. Background Technology

[0003] A gate drive circuit is a circuit used to transmit gate drive signals, such as light emission signals, to pixels in a display panel to drive the pixels to emit light. It is an indispensable part of a display device.

[0004] In related technologies, gate driving circuits typically include multiple cascaded driving units. These driving units are connected one-to-one with multiple rows of pixels in the display panel and are used to output light-emitting signals to the multiple rows of pixels row by row to drive the multiple rows of pixels to emit light row by row, thus realizing progressive scanning.

[0005] However, the current gate drive circuits have a relatively simple driving method and poor driving effect. Summary of the Invention

[0006] A gate driving circuit and driving method for a display panel, as well as a display device, are provided. The technical solution is as follows:

[0007] On one hand, a gate driving circuit for a display panel is provided, the gate driving circuit comprising: cascaded multi-stage driving units, the driving unit comprising: a first input control circuit, a second input control circuit, and an output circuit;

[0008] The first input control circuit is connected to the synchronous light emission control terminal, the input terminal of the output circuit, and the input terminals of other cascaded driving units, respectively, and is used to control the switching between the input terminal of the output circuit and the input terminals of the other driving units in response to the synchronous light emission control signal provided by the synchronous light emission control terminal, so that the signal received by the input terminal of the output circuit is transmitted to the input terminal of the other driving units.

[0009] The second input control circuit is connected to the sequential light emission control terminal, the output terminal of the output circuit, and the input terminal of the other driving units, respectively. It is used to control the switching between the output terminal of the output circuit and the input terminal of the other driving units in response to the sequential light emission control signal provided by the sequential light emission control terminal, so that the signal output by the output terminal of the output circuit is transmitted to the input terminal of the other driving units. In the same time period, the potential of the sequential light emission control signal is opposite to the potential of the synchronous light emission control signal.

[0010] The input terminal of the output circuit is used to receive the light emission signal, the clock terminal of the output circuit is used to receive the clock signal, the output terminal of the output circuit is used to connect to the pixel in the display panel, and the output circuit is used to sample the light emission signal based on the clock signal and output it to the pixel through the output terminal.

[0011] Optionally, the output circuit includes: a flip-flop;

[0012] The output circuit is used to sample the light emission signal based on the rising edge of the clock signal and then output it to the pixel via the output terminal.

[0013] Optionally, the trigger is a double-edge D flip-flop; the second input control circuit is connected to the intermediate state terminal of the double-edge D flip-flop; the driving unit further includes: logic circuitry;

[0014] The logic circuit is used to connect between the output terminal of the double-edge D flip-flop and the pixel, and the logic circuit is also connected to the intermediate state terminal of the double-edge D flip-flop. The logic circuit is used to perform logical operations on the signals output from the output terminal and the intermediate state terminal of the double-edge D flip-flop and then output them to the pixel.

[0015] Optionally, the logical operation is an AND operation, and the logic circuit includes an AND gate;

[0016] The two inputs of the AND gate are connected to the output and intermediate state of the dual-edge D flip-flop, respectively, and the output of the AND gate is used to connect to the pixel.

[0017] Optionally, the driving unit further includes: a third input control circuit, a first forward scan control circuit, and a first reverse scan control circuit;

[0018] The first input control circuit is connected to the input terminal of the other driving unit via the third input control circuit, and the third input control circuit is also connected to the synchronous light emission control terminal. The first input control circuit and the third input control circuit are used to control the on / off state of the input terminal of the output circuit and the input terminal of the other driving unit in response to the synchronous light emission control signal, so that the signal received by the input terminal of the output circuit is transmitted to the input terminal of the other driving unit, or the signal received by the input terminal of the other driving unit is transmitted to the input terminal of the output circuit.

[0019] Both the first forward scan control circuit and the first reverse scan control circuit are connected between the first input control circuit and the third input control circuit. The first forward scan control circuit is also connected to the forward scan control terminal, and the first reverse scan control circuit is also connected to the reverse scan control terminal. The first forward scan control circuit is used to control the on / off state of the first input control circuit and the third input control circuit in response to the forward scan control signal provided by the forward scan control terminal, so that the signal received at the input terminal of the output circuit is transmitted sequentially through the first input control circuit and the third input control circuit to the input terminal of the other driving units. The first reverse scan control circuit is used to control the on / off state of the first input control circuit and the third input control circuit in response to the reverse scan control signal provided by the reverse scan control terminal, so that the signal received at the input terminal of the other driving units is transmitted sequentially through the third input control circuit and the first input control circuit to the input terminal of the output circuit.

[0020] During the same time period, the potential of the reverse scan control signal is opposite to that of the forward scan control signal.

[0021] Optionally, the first input control circuit and the third input control circuit are also connected to the sequential light emission control terminal and are used to control the connection and disconnection between the input terminal of the output circuit and the input terminal of the other stage driving unit in response to the synchronous light emission control signal and the sequential light emission control signal.

[0022] The first forward scan control circuit is also connected to the reverse scan control terminal and is used to control the on / off state of the first input control circuit and the third input control circuit in response to the forward scan control signal and the reverse scan control signal.

[0023] The first reverse scan control circuit is also connected to the forward scan control terminal and is used to control the on / off state of the first input control circuit and the third input control circuit in response to the forward scan control signal and the reverse scan control signal.

[0024] Optionally, the first input control circuit includes a first transmission gate; the third input control circuit includes a second transmission gate; the first forward scan control circuit includes a third transmission gate and a fourth transmission gate; and the first reverse scan control circuit includes a fifth transmission gate and a sixth transmission gate.

[0025] The control terminals of the first and second transmission gates are respectively connected to the synchronous light emission control terminal and the sequential light emission control terminal. The control terminals of the third to sixth transmission gates are respectively connected to the forward scan control terminal and the reverse scan control terminal. The input terminal of the first transmission gate is connected to the input terminal of the output circuit. The output terminal of the first transmission gate is connected to the input terminal of the third transmission gate and the output terminal of the fifth transmission gate. The output terminal of the third transmission gate is connected to the input terminal of the fourth transmission gate. The input terminal of the fifth transmission gate is connected to the output terminal of the sixth transmission gate. The output terminals of the fourth and sixth transmission gates are both connected to the output terminal of the second transmission gate. The input terminal of the second transmission gate is connected to the input terminal of the other driving units.

[0026] Optionally, the driving unit further includes: a first enhancement circuit and / or a second enhancement circuit;

[0027] The first enhancement circuit is connected between the third transmission gate and the fourth transmission gate, and is used to enhance the signal output by the third transmission gate before transmitting it to the fourth transmission gate;

[0028] The second enhancement circuit is connected between the fifth transmission gate and the sixth transmission gate, and is used to enhance the signal output by the sixth transmission gate before transmitting it to the fifth transmission gate.

[0029] Optionally, the first enhancement circuit includes an even number of first inverters connected in series; the second enhancement circuit includes an even number of second inverters connected in series.

[0030] The input terminals of the even-numbered series-connected first inverters are connected to the output terminal of the third transmission gate, and the output terminals of the even-numbered series-connected first inverters are connected to the input terminal of the fourth transmission gate.

[0031] The input terminals of the even-numbered series-connected second inverters are connected to the output terminal of the sixth transmission gate, and the output terminals of the even-numbered series-connected second inverters are connected to the input terminal of the fifth transmission gate.

[0032] Optionally, the driving unit further includes: a fourth input control circuit, a second forward scan control circuit, and a second reverse scan control circuit;

[0033] The fourth input control circuit is connected to the sequential light emission control terminal, the input terminal of the output circuit, and the output terminal of the other driving units, respectively, and is used to control the connection and disconnection between the output terminal of the other driving units and the input terminal of the output circuit in response to the sequential light emission control signal, so that the signal output by the output terminal of the other driving units is transmitted to the input terminal of the output circuit.

[0034] The second forward scan control circuit is connected between the output terminal of the output circuit and the second input control circuit, and is also connected to the forward scan control terminal. It is used to control the on / off state of the output terminal of the output circuit and the second input control circuit in response to the forward scan control signal provided by the forward scan control terminal, so that the signal output by the output terminal of the output circuit is transmitted to the input terminal of the other stage drive unit through the second input control circuit.

[0035] The second backscan control circuit is connected between the input terminal of the output circuit and the fourth input control circuit, and is also connected to the backscan control terminal. It is used to control the on / off state of the input terminal of the output circuit and the fourth input control circuit in response to the backscan control signal provided by the backscan control terminal, so that the signal output by the output terminal of the other stage drive unit is transmitted to the input terminal of the output circuit through the fourth input control circuit.

[0036] During the same time period, the potential of the reverse scan control signal is opposite to that of the forward scan control signal.

[0037] Optionally, both the second input control circuit and the fourth input control circuit are further connected to the sequential light emission control terminal. The second input control circuit is used to control the connection and disconnection between the output terminal of the output circuit and the input terminal of the other stage driving unit in response to the synchronous light emission control signal and the sequential light emission control signal. The fourth input control circuit is used to control the connection and disconnection between the output terminal of the other stage driving unit and the input terminal of the output circuit in response to the synchronous light emission control signal and the sequential light emission control signal.

[0038] The second forward scan control circuit is also connected to the reverse scan control terminal and is used to control the connection and disconnection between the output terminal of the output circuit and the second input control circuit in response to the forward scan control signal and the reverse scan control signal.

[0039] The second reverse scan control circuit is also connected to the forward scan control terminal and is used to control the on / off state of the input terminal of the output circuit and the fourth input control circuit in response to the forward scan control signal and the reverse scan control signal.

[0040] Optionally, the second input control circuit includes a seventh transmission gate; the fourth input control circuit includes an eighth transmission gate; the second forward scan control circuit includes a ninth transmission gate; and the second reverse scan control circuit includes a tenth transmission gate.

[0041] The control terminals of the seventh and eighth transmission gates are respectively connected to the synchronous light emission control terminal and the sequential light emission control terminal. The control terminals of the ninth to tenth transmission gates are respectively connected to the forward scan control terminal and the reverse scan control terminal. The input terminal of the seventh transmission gate is connected to the output terminal of the ninth transmission gate. The output terminal of the seventh transmission gate is connected to the input terminal of the other driving units. The input terminal of the ninth transmission gate is connected to the output terminal of the output circuit. The input terminal of the eighth transmission gate is connected to the output terminal of the other driving units. The output terminal of the eighth transmission gate is connected to the input terminal of the tenth transmission gate. The output terminal of the tenth transmission gate is connected to the input terminal of the output circuit.

[0042] Optionally, the driving unit further includes: an inverting circuit;

[0043] The inverting circuit is connected between the output terminal of the output circuit and the pixel, and is used to invert the signal output from the output terminal of the output circuit and then transmit it to the pixel.

[0044] Optionally, the inverting circuit includes: a third inverter;

[0045] The input terminal of the third inverter is connected to the output terminal of the output circuit, and the output terminal of the third inverter is used to connect to the pixel.

[0046] On the other hand, a driving method for a display panel is provided, applied in a gate driving circuit as described in the above aspect; the method includes:

[0047] In response to the synchronous light emission command, the first input control circuit responds to the synchronous light emission control signal provided by the synchronous light emission control terminal, and controls the input terminal of the output circuit to be connected to the input terminals of other driving units, so that the signal received by the input terminal of the output circuit is transmitted to the input terminals of the other driving units. The output circuits in each driving unit sample the received light emission signal based on the received clock signal and output it synchronously to the multiple rows of pixels in the display panel to synchronously light up the multiple rows of pixels.

[0048] In response to the sequential light emission command, the second input control circuit, in response to the sequential light emission control signal provided by the sequential light emission control terminal, controls the connection and disconnection between the output terminal of the output circuit and the input terminal of the other driving units, so that the signal output by the output terminal of the output circuit is transmitted to the input terminal of the other driving units. The output circuits in each driving unit sample the received light emission signal based on the received clock signal and then sequentially output it to multiple rows of pixels in the display panel to light up the multiple rows of pixels in sequence.

[0049] In another aspect, a display device is provided, the display device comprising: a display panel, and a gate driving circuit as described in the preceding aspect;

[0050] The display panel includes multiple rows of pixels, and the gate driving circuit is connected to the multiple rows of pixels and is used to drive the multiple rows of pixels to emit light. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 is a schematic diagram of a gate driving circuit provided in an embodiment of this application;

[0053] Figure 2 is a schematic diagram of the structure of a driving unit provided in an embodiment of this application;

[0054] Figure 3 is a schematic diagram of another driving unit provided in an embodiment of this application;

[0055] Figure 4 is a schematic diagram of another driving unit provided in an embodiment of this application;

[0056] Figure 5 is a partial structural schematic diagram of a driving unit provided in an embodiment of this application;

[0057] Figure 6 is a partial structural schematic diagram of another driving unit provided in an embodiment of this application;

[0058] Figure 7 is a partial structural schematic diagram of another driving unit provided in an embodiment of this application;

[0059] Figure 8 is a partial structural schematic diagram of another driving unit provided in an embodiment of this application;

[0060] Figure 9 is a partial structural schematic diagram of another driving unit provided in an embodiment of this application;

[0061] Figure 10 is a partial structural schematic diagram of another driving unit provided in an embodiment of this application;

[0062] Figure 11 is a partial structural schematic diagram of another driving unit provided in an embodiment of this application;

[0063] Figure 12 is a schematic diagram of the overall circuit structure of a driving unit provided in an embodiment of this application;

[0064] Figure 13 is a schematic diagram of a circuit structure of multiple cascaded driving units provided in an embodiment of this application;

[0065] Figure 14 is a schematic diagram of the driving timing of a gate driving circuit provided in an embodiment of this application;

[0066] Figure 15 is a flowchart illustrating a driving method for a display panel according to an embodiment of this application;

[0067] Figure 16 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0069] It is understood that the transistors used in the embodiments of this application can all be thin film transistors (TFTs), field-effect transistors, or other devices with the same characteristics. An example of a field-effect transistor can be a metal-oxide-semiconductor (MOS) field-effect transistor, also known as a MOS transistor. Based on their function in the circuit, the transistors used in the embodiments of this application are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of this application, the source is referred to as the first electrode, and the drain as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is designated as the control electrode, also known as the gate; the signal input terminal is the source; and the signal output terminal is the drain. Furthermore, the switching transistors used in the embodiments of this application can include either P-type switching transistors or N-type switching transistors. A P-type switching transistor conducts when the gate is low and is cut off when the gate is high, while an N-type switching transistor conducts when the gate is high and is cut off when the gate is low. In addition, multiple signals in the various embodiments of this application correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has two state quantities, and do not mean that the first potential or the second potential has a specific value in the whole text.

[0070] With the development of display technology, various types of displays have emerged. Among them, a typical example is the silicon-based organic light-emitting diode (OLED) microdisplay. Silicon-based OLED microdisplays are active-matrix organic light-emitting diode display devices fabricated using single-crystal silicon as the active driving backplane, combining complementary metal-oxide-semiconductor (CMOS) technology and OLED technology. Silicon-based OLED microdisplays are widely used in devices such as augmented reality (AR), virtual reality (VR), mixed reality (MR), electronic viewfinders (EVF), first-person view (FPV), drones, thermal imagers, night vision devices, infrared cameras, and / or medical equipment due to their numerous advantages, including high resolution, high PPI, high contrast, high brightness, low power consumption, small size, and light weight. PPI refers to the number of pixels per inch, reflecting the pixel density of the display.

[0071] Structurally, the display driver integrated circuit (DDIC) and silicon backplane (Si-BP) of a silicon-based OLED microdisplay can be integrated onto the same IC. The Si-BP typically includes a pixel driver circuit array (active area), a gate driver on array (GOA) circuit, and a source driver circuit. The GOA circuit is also called the GOA control circuit. This application primarily studies the GOA circuit in the Si-BP, which is mainly implemented using digital circuitry and aims to provide control signals for the row driving of the pixel circuit array. For example, the emission signal (EM_SIGNAL), or simply the EM signal.

[0072] Understandably, the EM signal is typically transmitted to the light-emitting control transistor (LED) in the pixel circuit array, which is connected between the pull-up power line VDD (or, the OLED light-emitting element) and the driving transistor, to control the LED to turn on or off. When the LED is on, a path is formed between the pull-up power line VDD and the pull-down power line VSS connected to the OLED, thereby driving the OLED to emit light and enabling the silicon-based OLED microdisplay to display an image.

[0073] In some embodiments, the GOA circuit typically includes multiple cascaded driving units (also called shift register GOA units). These GOA units are connected one-to-one with multiple rows of pixels and output light-emitting signals to each row of pixels sequentially, driving each row of pixels to emit light. The light-emitting element in the pixel generally refers to the aforementioned self-emissive OLED. That is, unlike a liquid crystal display (LCD), where all pixels emit light simultaneously, OLEDs do not have the same illumination time. This results in each pixel in the OLED operating at a different duration.

[0074] For example, in an example where the pixels are designed to display the three primary colors of red, green, and blue, some pixels may display blue for a relatively longer time. Consequently, the blue attenuation of that pixel will be greater than other pixels, resulting in a paler blue display when that pixel tries to display blue again later. The same issue occurs when displaying red and green. This ultimately leads to a poorer display quality.

[0075] Based on this, this application proposes a novel GOA circuit for OLED display products such as silicon-based OLED microdisplays. This GOA circuit can not only output emission signals EM to multiple rows of pixels sequentially to drive them to emit light row by row, but also output emission signals EM to multiple rows of pixels simultaneously to drive them to emit light synchronously, enabling the entire display panel to emit light synchronously (Global Emission). This not only enriches the driving methods of the gate driving circuit but also improves its driving effect, enabling the gate driving circuit to reliably drive the display panel and improve its display performance. Of course, its application is not limited to silicon-based OLED microdisplays.

[0076] Figure 1 is a gate driving circuit (also called GOA circuit or GOA control circuit) for a display panel provided in an embodiment of this application. As shown in Figure 1, the gate driving circuit includes: cascaded multi-stage driving units 00 (also called GOA units).

[0077] Optionally, the nth driving unit 00 can be cascaded with the (n+i)th driving unit 00. Where 1 ≤ n ≤ Mi, M is the total number of driving units 00, M ≥ 1, and i is a positive integer greater than or equal to 1. For example, referring to Figure 1, in the gate driving circuit shown therein, every two adjacent driving units 00 are cascaded, i.e., i = 1.

[0078] Based on Figure 1, taking the nth-level drive unit 00 in the multi-level drive unit 00 as an example, Figure 2 shows a schematic diagram of the structure of a drive unit 00. Combining Figures 1 and 2, it can be seen that the drive unit 00 includes: a first input control circuit 01, a second input control circuit 02, and an output circuit 03.

[0079] The first input control circuit 01 is connected to the synchronous light emission control terminal EN_GLOBAL, the input terminal D of the output circuit 03, and the input terminals of other cascaded driving units 00. Furthermore, the first input control circuit 01, in response to the synchronous light emission control signal provided by the synchronous light emission control terminal EN_GLOBAL, controls the switching of the input terminal D of the output circuit 03 on and off with the input terminals of the other driving units 00, so that the signal received at the input terminal D of the output circuit 03 is transmitted to the input terminals of the other driving units 00.

[0080] It is understood that, in conjunction with Figure 2, the input terminal of the other-stage driving unit 00 described in the embodiments of this application may refer to the input terminal D of the output circuit 03 in the other-stage driving unit 00. Based on this, for example, the first input control circuit 01 can control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be connected to the input terminal D of the output circuit 03 in other stage driving units 00 when the potential of the synchronous light emission control signal provided by the synchronous light emission control terminal EN_GLOBAL is the first potential, so that the signal received by the input terminal D of the output circuit 03 in the current stage driving unit 00 can be transmitted to the input terminal D of the output circuit 03 in other stage driving units 00; and the first input control circuit 01 can control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be disconnected from the input terminal D of the output circuit 03 in other stage driving units 00 when the potential of the synchronous light emission control signal provided by the synchronous light emission control terminal EN_GLOBAL is the second potential, so that the signal received by the input terminal D of the output circuit 03 in the current stage driving unit 00 cannot be transmitted to the input terminal D of the output circuit 03 in other stage driving units 00.

[0081] In other words, for each driving unit 00, the first input control circuit 01 in that driving unit 00, under the control of the synchronous light emission control signal, can directly connect the input terminal D of the output circuit 03 in that driving unit 00 to the input terminals D of the output circuit 03 in other driving units 00. This allows the signal to be directly transmitted to the input terminals of each driving unit 00 without passing through the output circuit 03. Thus, the input terminals D of the output circuit 03 in each driving unit 00 can simultaneously receive the signals input to the input terminals D of the output circuit 03 in that driving unit 00. In other words, the input terminals D of the output circuit 03 in each driving unit 00 can simultaneously receive the same signal.

[0082] Optionally, the first potential can be an effective potential, and the second potential can be an ineffective potential, with the first potential being higher than the second potential. That is, the first potential can be higher, and the second potential can be lower. Of course, in some embodiments, the first potential can also be lower than the second potential. Furthermore, for an N-type transistor, the effective potential (i.e., the first potential) can be higher, and the ineffective potential (i.e., the second potential) can be lower. For a P-type transistor, the effective potential (i.e., the first potential) can be lower, and the ineffective potential (i.e., the second potential) can be higher.

[0083] The second input control circuit 02 is connected to the sequential light emission control terminal EN_GLOBAL', the output terminal Q of the output circuit 03, and the input terminals of other driving units 00. Furthermore, this second input control circuit 02 is used to control the switching of the output terminal Q of the output circuit 03 with the input terminals of other driving units 00 in response to the sequential light emission control signal provided by the sequential light emission control terminal EN_GLOBAL', so that the signal output from the output terminal Q of the output circuit 03 is transmitted to the input terminals of other driving units 00.

[0084] As mentioned above, the input terminal of other-level driving units 00 can refer to the input terminal D of the output circuit 03 included in other-level driving units 00. Based on this, for example, the second input control circuit 02 can, when the potential of the sequential light emission control signal provided by the sequential light emission control terminal EN_GLOBAL' is the first potential, control the output terminal Q of the output circuit 03 in the current-level driving unit 00 to be connected to the input terminal D of the output circuit 03 in other-level driving units 00, so that the signal output by the output terminal Q of the output circuit 03 in the current-level driving unit 00 can be transmitted to the input terminal D of the output circuit 03 in other-level driving units 00; and the second input control circuit 02 can, when the potential of the sequential light emission control signal provided by the sequential light emission control terminal EN_GLOBAL' is the second potential, control the output terminal Q of the output circuit 03 in the current-level driving unit 00 to be disconnected from the input terminal D of the output circuit 03 in other-level driving units 00, at which time the signal output by the output terminal Q of the output circuit 03 in the current-level driving unit 00 cannot be transmitted to the input terminal D of the output circuit 03 in other-level driving units 00. In the diagram, the output terminal Q of the current nth stage drive unit 00 is labeled as Qn.

[0085] That is, for each driving unit 00, the second input control circuit 02 in that driving unit 00, under the control of the sequential light emission control signal, controls the output terminal Q of the output circuit 03 in that driving unit 00 to be connected to the input terminal D of the output circuit 03 in other driving units 00, so that the signal is transmitted to the input terminal of other driving units 00 after passing through the output circuit 03. In this way, the input terminal D of the output circuit 03 in each driving unit 00 can sequentially receive the signal output from the output terminal Q of the output circuit 03 in that driving unit 00. In other words, the input terminal D of the output circuit 03 in each driving unit 00 can sequentially receive the same signal. For example, in a scenario where two adjacent drive units 00 are cascaded, the input terminal D of the output circuit 03 in the second-stage drive unit 00 can first receive the signal output by the output terminal Q of the output circuit 03 in the first-stage drive unit 00. Then, the input terminal D of the output circuit 03 in the third-stage drive unit 00 can receive the signal output by the output terminal Q of the output circuit 03 in the second-stage drive unit 00, and so on, to achieve cascaded signal transmission.

[0086] Within the same time period, the potential of the sequential light emission control signal is opposite to that of the synchronous light emission control signal. That is, when the potential of the synchronous light emission control signal is the first potential, the potential of the sequential light emission control signal can be the second potential; conversely, when the potential of the synchronous light emission control signal is the second potential, the potential of the sequential light emission control signal can be the first potential. The first potential can be, for example, a high potential, and the second potential can be, for example, a low potential.

[0087] Thus, as described in the above examples, when the first input control circuit 01 controls the input terminal D of the output circuit 03 to be connected to the input terminals of other stage drive units 00, so that signals are simultaneously transmitted to the input terminals of each stage drive unit 00, the second input control circuit 02 can control the output terminal Q of the output circuit 03 to be disconnected from the input terminals of other stage drive units 00; when the second input control circuit 02 controls the output terminal Q of the output circuit 03 to be connected to the input terminals of other stage drive units 00, so that signals are sequentially cascaded to the input terminals of each stage drive unit 00, the first input control circuit 01 can control the input terminal D of the output circuit 03 to be disconnected from the input terminals of other stage drive units 00. That is, it is possible to ensure that within a certain time period, the input terminals of each stage drive unit 00 either receive signals simultaneously or receive signals sequentially.

[0088] The input terminal D of the output circuit 03 is used to receive the light emission signal EM, the clock terminal CK of the output circuit 03 is used to receive the clock signal CLK, and the output terminal Q of the output circuit 03 is used to connect to a pixel (not shown in the figure) in the display panel. Furthermore, the output circuit 03 is used to sample the light emission signal EM based on the clock signal CLK and then output it to the pixel via the output terminal Q. That is, under the control of the clock signal CLK, the output circuit 03 can sample the light emission signal EM received at the input terminal D and then output it to the pixel via the output terminal Q.

[0089] Optionally, as can be seen from Figures 1 and 2, in each stage of the driving unit 00, the input terminal D of the output circuit 03 can also be connected to the light-emitting signal line Dn to receive the light-emitting signal EM provided by the light-emitting signal line Dn. Here, Dn can refer to the light-emitting signal line connected to the input terminal D of the output circuit 03 in the nth stage driving unit 00. Correspondingly, Dn+1 can refer to the light-emitting signal line connected to the input terminal D of the output circuit 03 in the (n+1)th stage driving unit 00.

[0090] Correspondingly, cascading the nth-level driving unit 00 and the (n+1)th-level driving unit 00 can mean that the output terminal Q of the output circuit 03 in the nth-level driving unit 00 is connected to the input terminal D of the output circuit 03 in the (n+1)th-level driving unit 00. In this embodiment, the output terminal Q of the output circuit 03 in the nth-level driving unit 00 can be connected to the input terminal D of the output circuit 03 in the (n+1)th-level driving unit 00 via the second input control circuit 02. The figure only schematically shows the light-emitting signal line Dn+1 connected to the input terminal D of the output circuit 03 in the (n+1)th-level driving unit 00. Of course, the input terminal D of the output circuit 03 in the first-level driving unit 00 can be connected to a separate turn-on signal line STV to receive the turn-on signal provided by the turn-on signal line STV, which is the light-emitting signal EM. Of course, the turn-on signal line STV can be connected to the DDIC to receive the light-emitting signal EM provided by the DDIC.

[0091] Furthermore, the output terminal Q of the output circuit 03 in the multi-level driving unit 00 can be connected one-to-one with multiple rows of pixels in the display panel. That is, the output terminal Q of the output circuit 03 in each level of the driving unit 00 can be connected to one row of pixels, and the output terminal Q of the output circuit 03 in each level of the driving unit 00 can be connected to different rows of pixels. Of course, it is not limited to this one-to-one connection method. For example, in some other embodiments, the output terminal Q of the output circuit 03 in each level of the driving unit 00 can be connected to two or more rows of pixels.

[0092] Thus, as described above, under the control of the synchronous light emission control signal, the input terminals D of the output circuits 03 in each stage of the driving unit 00 can simultaneously receive the same light emission signal EM that has not been transmitted by the output circuit 03. Therefore, the output circuits 03 in each stage of the driving unit 00 can simultaneously sample the same light emission signal EM based on the received clock signal CLK and output it simultaneously to multiple rows of pixels in the display panel via the output terminal Q, thereby driving these multiple rows of pixels to emit light simultaneously. For example, they can be simultaneously output to the gates of the light emission control transistors in the multiple rows of pixels, causing the light emission control transistors in each pixel to turn on synchronously, thereby making multiple rows of pixels in the display panel emit light synchronously for the same duration, achieving the effect of global emission.

[0093] Under the control of the second input control circuit 02 in response to the sequential emission control signal, the input terminal D of the output circuit 03 in each stage of the driving unit 00 can sequentially receive the emission signal EM transmitted after passing through the output circuit 03. Therefore, the output circuit 03 in each stage of the driving unit 00 can, based on the received clock signal CLK, sequentially sample the same emission signal EM and output it sequentially through the output terminal Q to multiple rows of pixels in the display panel, thereby driving these multiple rows of pixels to emit light sequentially. For example, outputting it row by row to the gate of the emission control transistor in each row of pixels causes the emission control transistor in each pixel to turn on sequentially, thus causing multiple rows of pixels in the display panel to emit light row by row, achieving the effect of sequential emission display.

[0094] That is, the gate driving circuit described in this application embodiment is compatible with both Global Emission and Sequential Emission emission modes. Furthermore, since the potential of the sequential emission control signal is opposite to that of the synchronous emission control signal during the same time period, it can be known that under the control of the first input control circuit 01 and the second input control circuit 02, these two emission modes can be freely switched to execute according to display requirements, thereby achieving the purpose of adapting to various usage scenarios.

[0095] In summary, this application provides a gate driving circuit. Because the gate driving circuit includes multiple driving units, the first input control circuit in each driving unit can, under the control of a synchronous emission control signal, control the input terminal of the current driving unit to be connected to the input terminals of other driving units, so that the emission signal is simultaneously transmitted to the multiple driving units; and the second input control circuit in each driving unit can, under the control of a sequential emission control signal, control the output terminal of the current driving unit to be connected to the input terminals of other driving units, so that the emission signal is transmitted sequentially to the multiple driving units. Therefore, this gate driving circuit can not only simultaneously output emission signals to multiple rows of pixels to drive multiple rows of pixels to emit light synchronously, but also sequentially output emission signals to multiple rows of pixels to drive multiple rows of pixels to emit light sequentially. That is, this gate driving circuit is compatible with both Global Emission and Sequential Emission emission modes, and its driving method is diversified, resulting in better driving performance.

[0096] Furthermore, by controlling the simultaneous and synchronous illumination of multiple rows of pixels, the problem of poor display uniformity caused by inconsistent illumination timing can be improved. In other words, it ensures better display performance of the display panel.

[0097] Optionally, in some embodiments, the output circuit 03 may include a trigger. Accordingly, the output circuit 03 may be used to sample the light emission signal EM based on the rising edge of the clock signal CLK and output it to the pixel via the output terminal.

[0098] For example, the rising edge of the clock signal CLK can refer to the rising edge of the clock signal CLK changing from a low potential to a high potential. That is, the output circuit 03 can sample the light emission signal EM and output it to the pixel via the output terminal when the rising edge of the clock signal CLK arrives. Accordingly, the flip-flop included in the output circuit 03 can be a rising edge flip-flop.

[0099] Of course, in some other embodiments, the trigger can also be a falling edge trigger. That is, the transition edge of the clock signal CLK can also refer to the falling edge of the clock signal CLK changing from a high potential to a low potential.

[0100] Alternatively, referring to the structural schematic diagram of another driving unit 00 shown in Figure 3, it can be seen that the trigger is, for example, a double-edge D flip-flop (DFF).

[0101] Accordingly, as shown in Figure 3, the second input control circuit 02 can be connected to the intermediate state terminal Q_INTER of the double-edge D flip-flop DFF. Furthermore, the driving unit 00 may also include: logic circuit 04.

[0102] Logic circuit 04 can be connected between the output Q of the dual-edge D flip-flop (DFF) and the pixel, and can also be connected to the intermediate state terminal Q_INTER of the DFF. Logic circuit 04 can perform logical operations on the signals output from the output Q and intermediate state terminal Q_INTER of the DFF before outputting them to the pixel.

[0103] It is understandable that a double-edge D flip-flop (DFF) is a type of D flip-flop that can sample the input signal on both the rising and falling edges of the clock signal. Using a double-edge DFF can improve data processing efficiency. In a double-edge DFF, the intermediate state terminal Q_INTER serves as an intermediate output terminal, temporarily storing the input signal until the next clock signal edge updates the output, thus ensuring stable output even when the clock signal's potential changes. For example, when the rising edge of the clock signal arrives, the input signal can be sampled and stored in the intermediate state terminal Q_INTER. When the falling edge of the clock signal arrives, the input signal is then output through the intermediate state terminal Q_INTER. In this way, two data sampling and output updates can be completed within one clock cycle. Furthermore, referring to Figure 3, Q' in the double-edge DFF refers to the inverting output terminal; the signal output through Q' has the opposite potential to the signal output through output terminal Q. Additionally, the double-edge DFF also has a reset terminal Rn, which receives the reset signal RST for flexible initialization under the control of the reset signal RST.

[0104] Optionally, based on setting the output circuit 03 as a double-edge D flip-flop (DFF), the second input control circuit 02 can be connected to the intermediate state terminal Q_INTER of the double-edge D flip-flop (DFF) and used to control the on / off state of the intermediate state terminal Q_INTER and the input terminals of other stage drive units 00 under the control of the sequential light emission control signal.

[0105] Optionally, in some embodiments, the logic operation processing can be AND processing. AND processing means that the logic circuit 04 outputs a high-level signal only when the potentials of all received signals are high; otherwise, it outputs a low-level signal. Accordingly, as can be seen from the structural schematic diagram of another driving unit 00 shown in Figure 4, the logic circuit 04 may include an AND gate.

[0106] The two inputs A and B of the AND gate can be connected to the output Q and intermediate state Q_INTER of a dual-edge D flip-flop, respectively. The output OUT of the AND gate can be used to connect to a pixel.

[0107] Of course, it is not limited to AND processing, and correspondingly, logic circuit 04 is not limited to the design of AND gates. For example, in some embodiments, logic circuit 04 may include multiple gate circuits combined together.

[0108] Optionally, Figure 5 is a partial structural schematic diagram of a driving unit 00 provided in an embodiment of this application. As shown in Figure 5, the driving unit 00 may further include: a third input control circuit 05, a first forward scan control circuit 06, and a first reverse scan control circuit 07.

[0109] The first input control circuit 01 can be connected to the input terminals of other driving units 00 via the third input control circuit 05, and the third input control circuit 05 can also be connected to the synchronous light emission control terminal EN_GLOBAL. The first input control circuit 01 and the third input control circuit 05 can be used to control the switching of the input terminal D of the output circuit 03 with the input terminals of other driving units 00 in response to the synchronous light emission control signal, so that the signal received at the input terminal D of the output circuit 03 is transmitted to the input terminals of other driving units 00, or the signal received at the input terminals of other driving units 00 is transmitted to the input terminal D of the output circuit 03.

[0110] For example, the first input control circuit 01 and the third input control circuit 05 can, when the potential of the synchronous light emission control signal is the first potential, control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be connected to the input terminal D of the output circuit 03 in other stage driving units 00, so that the signal received by the input terminal D of the output circuit 03 in the current stage driving unit 00 is transmitted in the positive direction to the input terminal D of the output circuit 03 in other stage driving units 00, or the signal received by the input terminal D of the output circuit 03 in other stage driving units 00 is transmitted in the negative direction to the input terminal D of the output circuit 03 in the current stage driving unit 00. The first input control circuit 01 and the third input control circuit 05 can, when the potential of the synchronous light emission control signal is the second potential, control the input terminal D of the output circuit 03 in the current stage driving unit 00 to be disconnected from the input terminal D of the output circuit 03 in other stage driving units 00. At this time, the signal received at input terminal D of output circuit 03 in the current stage drive unit 00 cannot be transmitted to input terminal D of output circuit 03 in other stage drive units 00, and the signal received at input terminal D of output circuit 03 in other stage drive units 00 also cannot be transmitted to input terminal D of output circuit 03 in the current stage drive unit 00. Here, "signal" can refer to the light emission signal EM.

[0111] That is, the first input control circuit 01 and the third input control circuit 05 can jointly respond to the synchronous light emission control signal to control the forward and reverse transmission of the signal (e.g., the light emission signal EM) received at the input terminal D of the output circuit 03 in each cascaded driving unit 00, so as to achieve global emission while also being compatible with forward and reverse scanning functions. The forward and reverse scanning functions include forward scanning and reverse scanning. Forward scanning can refer to transmitting signals along the direction from the first row of pixels to the last row of pixels to scan multiple rows of pixels, and reverse scanning can refer to transmitting signals along the direction from the last row of pixels to the first row of pixels to scan multiple rows of pixels.

[0112] The first forward scan control circuit 06 and the first reverse scan control circuit 07 can both be connected between the first input control circuit 01 and the third input control circuit 05. The first forward scan control circuit 06 can also be connected to the forward scan control terminal GSD_FW, and the first reverse scan control circuit 07 can also be connected to the reverse scan control terminal GSD_BW. The first forward scan control circuit 06 can be used to control the on / off state of the first input control circuit 01 and the third input control circuit 05 in response to the forward scan control signal provided by the forward scan control terminal GSD_FW, so that the signal received at the input terminal D of the output circuit 03 is transmitted sequentially through the first input control circuit 01 and the third input control circuit 05 to the input terminals of other drive units 00. The first reverse scan control circuit 07 can be used to control the on / off state of the first input control circuit 01 and the third input control circuit 05 in response to the reverse scan control signal provided by the reverse scan control terminal GSD_BW, so that the signals received at the input terminals of other drive units 00 are transmitted sequentially through the third input control circuit 05 and the first input control circuit 01 to the input terminal D of the output circuit 03.

[0113] For example, the first forward scan control circuit 06 can control the first input control circuit 01 and the third input control circuit 05 to be turned on when the potential of the forward scan control signal provided by the forward scan control terminal GSD_FW is at the first potential, so that the signal received by the input terminal D of the output circuit 03 in the current stage drive unit 00 is transmitted sequentially to the input terminal D of the output circuit 03 in other stage drive units 00 through the first input control circuit 01 and the third input control circuit 05; and can control the first input control circuit 01 and the third input control circuit 05 to be disconnected when the potential of the forward scan control signal provided by the forward scan control terminal GSD_FW is at the second potential. At this time, the signal received by the input terminal D of the output circuit 03 in the current stage drive unit 00 cannot be transmitted sequentially to the input terminal D of the output circuit 03 in other stage drive units 00 through the first input control circuit 01 and the third input control circuit 05.

[0114] Similarly, when the backscan control signal provided by the backscan control terminal GSD_BW is at the first potential, the first input control circuit 01 and the third input control circuit 05 can be turned on, so that the signal received by the input terminal D of the output circuit 03 in other driving units 00 can be transmitted sequentially through the third input control circuit 05 and the first input control circuit 01 to the input terminal D of the output circuit 03 in the current driving unit 00; and when the backscan control signal provided by the backscan control terminal GSD_BW is at the second potential, the first input control circuit 01 and the third input control circuit 05 can be disconnected. At this time, the signal received by the input terminal D of the output circuit 03 in other driving units 00 cannot be transmitted sequentially through the third input control circuit 05 and the first input control circuit 01 to the input terminal D of the output circuit 03 in the current driving unit 00.

[0115] In other words, under the control of the first forward scan control circuit 06 and the first reverse scan control circuit 07, and in conjunction with the first input control circuit 01 and the third input control circuit 05, forward and reverse scans can be achieved, and the signal transmission paths under forward and reverse scans are independent of each other. Specifically, the signal transmission path under forward scan is as follows: it enters through the input terminal D of the output circuit 03 in the current stage drive unit 00, and then sequentially passes through the first input control circuit 01, the first forward scan control circuit 06, and the third input control circuit 05 to the input terminal D of the output circuit 03 in other stage drive units 00. The signal transmission path under reverse scan is as follows: it enters through the input terminal D of the output circuit 03 in other stage drive units 00, and then sequentially passes through the third input control circuit 05, the first reverse scan control circuit 07, and the first input control circuit 01 to the input terminal D of the output circuit 03 in the current stage drive unit 00. From a signal transmission perspective, this design can relatively avoid crosstalk between forward and reverse scans, thereby improving the signal transmission efficiency during circuit operation.

[0116] Within the same time period, the potential of the reverse scan control signal is opposite to that of the forward scan control signal. That is, when the potential of the forward scan control signal is the first potential, the potential of the reverse scan control signal can be the second potential; conversely, when the potential of the forward scan control signal is the second potential, the potential of the reverse scan control signal can be the first potential. Thus, as described in the above example, when the first forward scan control circuit 06 controls the first input control circuit 01 and the third input control circuit 05 to conduct, achieving forward scan, the first reverse scan control circuit 07 can control the first input control circuit 01 and the third input control circuit 05 to disconnect; when the first reverse scan control circuit 07 controls the first input control circuit 01 and the third input control circuit 05 to conduct, achieving reverse scan, the first forward scan control circuit 06 can control the first input control circuit 01 and the third input control circuit 05 to disconnect. In other words, it is possible to perform either forward scan or reverse scan simultaneously within a given time period while implementing Global Emission.

[0117] Optionally, referring to Figure 5, the first input control circuit 01 and the third input control circuit 05 can also be connected to the sequential light emission control terminal EN_GLOBAL'. Furthermore, the first input control circuit 01 and the third input control circuit 05 can be used to control the on / off state of the input terminal D of the output circuit 03 and the input terminals of other stage drive units 00 in response to the synchronous light emission control signal and the sequential light emission control signal.

[0118] For example, the first input control circuit 01 and the third input control circuit 05 can control the input terminal D of the output circuit 03 in the current stage drive unit 00 to be connected to the input terminal D of the output circuit 03 in other stage drive units 00 when the potential of the synchronous light emission control signal and / or the potential of the sequential light emission control signal is a first potential; and can control the input terminal D of the output circuit 03 in the current stage drive unit 00 to be disconnected from the input terminal D of the output circuit 03 in other stage drive units 00 when the potential of the synchronous light emission control signal and the potential of the sequential light emission control signal are both a second potential.

[0119] That is, the first input control circuit 01 and the third input control circuit 05 can control the on / off state of the input terminal D of the output circuit 03 in the current stage drive unit 00 and the input terminal D of the output circuit 03 in other stage drive units 00 under the control of the synchronous light emission control signal and the sequential light emission control signal. In this way, the control reliability and flexibility can be improved.

[0120] Optionally, in some embodiments, the potentials of the synchronous light emission control signal and the sequential light emission control signal can be exactly opposite. That is, assuming the first potential (i.e., the effective potential) of the synchronous light emission control signal is high, the first potential (i.e., the effective potential) of the sequential light emission control signal can be low. Conversely, assuming the first potential (i.e., the effective potential) of the synchronous light emission control signal is low, the first potential (i.e., the effective potential) of the sequential light emission control signal can be high. Based on this, in some embodiments, only the synchronous light emission control terminal EN_GLOBAL can be set, and then an inverter can be set to invert the synchronous light emission control signal provided by the synchronous light emission control terminal EN_GLOBAL to obtain the desired sequential light emission control signal, without needing to set an additional sequential light emission control terminal EN_GLOBAL'. Alternatively, only the sequential light emission control terminal EN_GLOBAL' can be set, and then an inverter can be set to invert the sequential light emission control signal provided by the sequential light emission control terminal EN_GLOBAL' to obtain the desired synchronous light emission control signal, without needing to set an additional synchronous light emission control terminal EN_GLOBAL. This simplifies the number of signal terminals that need to be set up, thus making wiring easier.

[0121] Optionally, referring to Figure 5, the first forward scan control circuit 06 can also be connected to the reverse scan control terminal GSD_BW. Furthermore, the first forward scan control circuit 06 can be used to control the on / off state of the first input control circuit 01 and the third input control circuit 05 in response to the forward scan control signal and the reverse scan control signal.

[0122] For example, the first forward scan control circuit 06 can control the first input control circuit 01 and the third input control circuit 05 to be turned on when the potential of the forward scan control signal and / or the potential of the reverse scan control signal is a first potential; and can control the first input control circuit 01 and the third input control circuit 05 to be disconnected when the potentials of the forward scan control signal and the reverse scan control signal are both a second potential. That is, like the first input control circuit 01 and the third input control circuit 05, the first forward scan control circuit 06 can control the on / off state of the first input control circuit 01 and the third input control circuit 05 under the control of the two control signals, the forward scan control signal and the reverse scan control signal. This improves control reliability and flexibility.

[0123] Optionally, referring to Figure 5, the first reverse scan control circuit 07 can also be connected to the forward scan control terminal GSD_FW. Furthermore, this first reverse scan control circuit 07 can be used to control the on / off state of the first input control circuit 01 and the third input control circuit 05 in response to the forward scan control signal and the reverse scan control signal.

[0124] For example, the first reverse scan control circuit 07 can control the first input control circuit 01 and the third input control circuit 05 to be turned on when the potential of the forward scan control signal and / or the potential of the reverse scan control signal is a first potential; and can control the first input control circuit 01 and the third input control circuit 05 to be disconnected when the potentials of the forward scan control signal and the reverse scan control signal are both a second potential. That is, similar to the first forward scan control circuit 06, the first reverse scan control circuit 07 can also control the on / off state of the first input control circuit 01 and the third input control circuit 05 under the control of the two control signals, the forward scan control signal and the reverse scan control signal. In this way, the control reliability and flexibility can be improved.

[0125] Optionally, in some embodiments, the potentials of the forward scan control signal and the reverse scan control signal can be exactly opposite. That is, assuming the first potential (i.e., effective potential) of the forward scan control signal is high, the first potential (i.e., effective potential) of the reverse scan control signal can be low. Conversely, assuming the first potential (i.e., effective potential) of the forward scan control signal is low, the first potential (i.e., effective potential) of the reverse scan control signal can be high. Based on this, in some embodiments, only the forward scan control terminal GSD_FW can be set, and then an inverter can be set to invert the forward scan control signal provided by the forward scan control terminal GSD_FW to obtain the required reverse scan control signal, without needing to set an additional reverse scan control terminal GSD_BW. Alternatively, only the reverse scan control terminal GSD_BW can be set, and then an inverter can be set to invert the reverse scan control signal provided by the reverse scan control terminal GSD_BW to obtain the required forward scan control signal, without needing to set an additional forward scan control terminal GSD_FW. This simplifies the number of signal terminals that need to be set, thereby facilitating wiring.

[0126] It is understandable that the potentials of the forward scan control signals received by the first forward scan control circuit 06 and the first reverse scan control circuit 07 can be exactly opposite, and the potentials of the received reverse scan control signals can also be exactly opposite. That is, assuming that the first potential of the forward scan control signal received by the first forward scan control circuit 06 is high and the first potential of the received reverse scan control signal is low, then the first potential of the forward scan control signal received by the first reverse scan control circuit 07 can be low, and the first potential of the received reverse scan control signal can be high. Assuming that the second potential of the forward scan control signal received by the first forward scan control circuit 06 is low and the second potential of the received reverse scan control signal is high, then the second potential of the forward scan control signal received by the first reverse scan control circuit 07 can be high, and the second potential of the received reverse scan control signal can be low. In this way, only one control circuit in the first forward scan control circuit 06 and the first reverse scan control circuit 07 can control the first input control circuit 01 and the third input control circuit 05 to conduct within a certain period of time, realizing forward scan or reverse scan.

[0127] For example, let 1 represent a high potential and 0 represent a low potential. The first potential of the forward scan control signal received by the first forward scan control circuit 06 is high potential 1, and the first potential of the received reverse scan control signal is low potential 0; the first potential of the forward scan control signal received by the first reverse scan control circuit 07 is low potential 0, and the first potential of the received reverse scan control signal is high potential 1. Table 1 below schematically shows the truth table for the forward scan control signal provided by the forward scan control terminal GSD_FW and the reverse scan control signal provided by the reverse scan control terminal GSD_BW when implementing forward and reverse scans:

[0128] Table 1

[0129] Based on Table 1 and the above description, when the forward scan control signal provided by the forward scan control terminal GSD_FW is at a high potential (1) and the reverse scan control signal provided by the reverse scan control terminal GSD_BW is at a low potential (0), the first forward scan control circuit 06 can control the first input control circuit 01 and the third input control circuit 05 to be turned on. This allows the signal received by the input terminal D of the output circuit 03 in the current stage drive unit 00 to be transmitted forward through the first input control circuit 01, the first forward scan control circuit 06, and the third input control circuit 05 to the input terminal D of the output circuit 03 in other stage drive units 00, thus achieving forward scan. That is, in the first value case 1 mode: GSD_FW = 1 and GSD_BW = 0, the scan state can be forward scan. At this time, the first reverse scan control circuit 07 can control the first input control circuit 01 and the third input control circuit 05 to be disconnected.

[0130] When the forward scan control signal provided by the forward scan control terminal GSD_FW is at a low potential (0) and the reverse scan control signal provided by the reverse scan control terminal GSD_BW is at a high potential (1), the first reverse scan control circuit 07 can control the first input control circuit 01 and the third input control circuit 05 to be turned on. This allows the signal received by the input terminal D of the output circuit 03 in other stage drive units 00 to be transmitted in reverse through the third input control circuit 05, the first reverse scan control circuit 07, and the first input control circuit 01 to the input terminal D of the output circuit 03 in the current stage drive unit 00, thus achieving reverse scan. That is, in the second value case (Value Case 2): GSD_FW = 0 and GSD_BW = 1, the scan state can be reverse scan. At this time, the first forward scan control circuit 06 can control the first input control circuit 01 and the third input control circuit 05 to be disconnected.

[0131] Optionally, based on Figure 5 and referring to Figure 6, the first input control circuit 01 may include a first transmission gate TG1. The third input control circuit 05 may include a second transmission gate TG2. The first forward scan control circuit 06 may include a third transmission gate TG3 and a fourth transmission gate TG4. The first reverse scan control circuit 07 may include a fifth transmission gate TG5 and a sixth transmission gate TG6.

[0132] The control terminals T&T' of the first transmission gate TG1 and the second transmission gate TG2 can be connected to the synchronous emission control terminal EN_GLOBAL and the sequential emission control terminal EN_GLOBAL', respectively. The control terminals T&T' of the third transmission gate TG3 through the sixth transmission gate TG6 can be connected to the forward scan control terminal GSD_FW and the reverse scan control terminal GSD_BW, respectively. The input terminal IN of the first transmission gate TG1 can be connected to the input terminal D (not shown in the figure) of the output circuit 03. The output terminal OUT of the first transmission gate TG1 can be connected to the input terminal IN of the third transmission gate TG3 and the output terminal OUT of the fifth transmission gate TG5. The output terminal OUT of the third transmission gate TG3 can be connected to the input terminal IN of the fourth transmission gate TG4. The input terminal IN of the fifth transmission gate TG5 can be connected to the output terminal OUT of the sixth transmission gate TG6. The output terminal OUT of the fourth transmission gate TG4 and the input terminal IN of the sixth transmission gate TG6 can both be connected to the output terminal OUT of the second transmission gate TG2. The input terminal IN of the second transmission gate TG2 can be connected to the input terminals of other stage drive units 00 (not shown in the figure).

[0133] It is understandable that a transmission gate generally consists of N-type transistors and P-type transistors connected in parallel. Based on this, the control terminal T of the transmission gate can refer to the gate of the N-type transistor, the control terminal T' can refer to the gate of the P-type transistor, the input terminal IN can refer to the first terminals of the N-type transistor and the P-type transistor connected in parallel, and the output terminal OUT can refer to the second terminals of the N-type transistor and the P-type transistor connected in parallel.

[0134] Based on this, and referring to the above embodiments and Figure 6, it can be seen that the control terminal T of the first transmission gate TG1 and the control terminal T of the second transmission gate TG2 can both be connected to the synchronous emission control terminal EN_GLOBAL, and the control terminals T' of the first transmission gate TG1 and the second transmission gate TG2 can both be connected to the sequential emission control terminal EN_GLOBAL'. In the third transmission gate TG3 and the fourth transmission gate TG4 included in the first forward scan control circuit 06, the control terminal T of each transmission gate can be connected to the forward scan control terminal GSD_FW, and the control terminal T' of each transmission gate can be connected to the reverse scan control terminal GSD_BW. In the fifth transmission gate TG5 and the sixth transmission gate TG6 included in the first reverse scan control circuit 07, the control terminal T of each transmission gate can be connected to the reverse scan control terminal GSD_BW, and the control terminal T' of each transmission gate can be connected to the forward scan control terminal GSD_FW. In this way, only one of the first forward scan control circuit 06 and the first reverse scan control circuit 07 can control the first input control circuit 01 and the third input control circuit 05 to be turned on during the same period, so as to realize forward scan or reverse scan.

[0135] Optionally, referring further to Figure 6, the drive unit 00 may also include: a first enhancement circuit 08 and / or a second enhancement circuit 09.

[0136] The first enhancement circuit 08 can be connected between the third transmission gate TG3 and the fourth transmission gate TG4. Furthermore, this first enhancement circuit 08 can be used to enhance the signal output from the third transmission gate TG3 before transmitting it to the fourth transmission gate TG4. This solves the signal attenuation problem that occurs when the signal is transmitted from the third transmission gate TG3 to the fourth transmission gate TG4, thereby ensuring that the signal received by the current stage drive unit 00 is reliably transmitted to other stage drive units 00 via the third transmission gate TG3.

[0137] The second enhancement circuit 09 can be connected between the fifth transmission gate TG5 and the sixth transmission gate TG6. Furthermore, this second enhancement circuit 09 can be used to enhance the signal output from the sixth transmission gate TG6 before transmitting it to the fifth transmission gate TG5. This solves the signal attenuation problem that occurs when the signal is transmitted from the sixth transmission gate TG6 to the fifth transmission gate TG5, thereby ensuring that signals received by other stage drive units 00 are reliably transmitted to the current stage drive unit 00 via the sixth transmission gate TG6.

[0138] Optionally, based on Figure 6 and referring further to Figure 7, the first enhancement circuit 08 may include an even number of first inverters F1 connected in series. The second enhancement circuit 09 may include an even number of second inverters F2 connected in series.

[0139] The input terminal IN of an even number of cascaded first inverters F1 can be connected to the output terminal OUT of the third transmission gate TG3, and the output terminal OUT of an even number of cascaded first inverters F1 can be connected to the input terminal IN of the fourth transmission gate TG4.

[0140] The input terminal IN of an even number of cascaded second inverters F2 can be connected to the output terminal OUT of the sixth transmission gate TG6, and the output terminal OUT of an even number of cascaded second inverters F2 can be connected to the input terminal IN of the fifth transmission gate TG5.

[0141] Of course, an even number of first inverters F1 connected in series can mean that the input terminal IN of every two adjacent first inverters F1 is connected to the output terminal OUT. Similarly, an even number of second inverters F2 connected in series can also mean that the input terminal IN of every two adjacent second inverters F2 is connected to the output terminal OUT.

[0142] Thus, by setting an even number of series-connected first inverters F1 and an even number of series-connected second inverters F2, the signal can be reliably amplified. Of course, in some other embodiments, the even number of series-connected first inverters F1 can be replaced with a buffer, achieving the same signal amplification. The even number of series-connected second inverters F2 can be replaced similarly.

[0143] Optionally, the number of first inverters F1 included in the first enhancement circuit 08 and the number of second inverters F2 included in the second enhancement circuit 09 can be the same. This ensures that the enhancement effect on the transmitted signal remains consistent during forward and reverse scanning, resulting in better display uniformity during both modes. Of course, the number of first inverters F1 included in the first enhancement circuit 08 and the number of second inverters F2 included in the second enhancement circuit 09 can also be different. For example, Figure 7 schematically shows two first inverters F1 connected in series and two second inverters F2 connected in series.

[0144] As described above, the partial structure shown in Figures 5 to 7 can control the simultaneous transmission of the light-emitting signal EM to the input terminal D of the output circuit 03 (e.g., DFF) in each cascaded driving unit 00, without requiring sequential transmission through the DFF. This allows the light-emitting signal EM to simultaneously enter the output circuit 03 in each driving unit 00, enabling synchronous processing and ultimately keeping the light-emitting signals EM output to the pixels from each cascaded driving unit 00 synchronized. This allows the display panel to emit light synchronously across the entire surface, enabling it to operate in Global Emission mode. Accordingly, the partial structure shown in Figures 5 to 7 can also be referred to as a data transmission control module.

[0145] Furthermore, based on the control display panel operating in Global Emission mode, it can also be used in conjunction with the third input control circuit 05, the first forward scan control circuit 06, and the first reverse scan control circuit 07 (i.e., a structure composed of a transmission gate and an inverter) to achieve compatibility with both forward and reverse scan functions. Also, during normal display, only one state exists: forward scan or reverse scan.

[0146] For example, referring to Figure 7, in the forward scan state, the signal transmission path can be the path shown in Figure 7 (1). That is, the light-emitting signal EM can be entered from above, first passing through a first transmission gate TG1 controlled by EN_GLOBAL=1, then through a third transmission gate TG3 controlled by GSD_FW=1, followed by two series-connected first inverters F1 to enhance the light-emitting signal EM to avoid attenuation of the light-emitting signal EM, and finally through a fourth transmission gate TG4 controlled by GSD_FW=1 and then through a second transmission gate TG2 controlled by EN_GLOBAL=1. The setting of the fourth transmission gate TG4 can also be used to prevent the light-emitting signal EM from flowing back, to ensure a single path for signal transmission, that is, to ensure that the light-emitting signal EM is transmitted either forward or backward. In the reverse scan state, the signal transmission path can be the path shown in Figure 7 (2). The number of devices that the light-emitting signal EM passes through is the same, and the functions of each device are the same. The difference is that the light-emitting signal EM is entered from below, and GSD_BW=1.

[0147] Wherein, EN_GLOBAL=1 can mean that the first potential of the synchronous light emission control signal provided by the synchronous light emission control terminal EN_GLOBAL is a high potential 1; GSD_FW=1 can mean that the first potential of the forward scan control signal provided by the forward scan control terminal GSD_FW is a high potential 1; GSD_BW=1 can mean that the first potential of the reverse scan control signal provided by the reverse scan control terminal GSD_BW is a high potential 1.

[0148] Optionally, in some embodiments, the third transmission gate TG3, the fourth transmission gate TG4, and an even number of series-connected first inverters F1 on the forward scan path (1) can be replaced by a tri-state buffer, which can also achieve the purpose of controlling the forward scan. The fifth transmission gate TG5, the sixth transmission gate TG6, and an even number of series-connected second inverters F2 on the forward scan path (1) can be replaced in the same way.

[0149] Optionally, FIG8 is a schematic diagram of another part of a drive unit 00 provided in an embodiment of the present application. As shown in FIG8, the drive unit 00 may further include: a fourth input control circuit 10, a second forward scan control circuit 11, and a second reverse scan control circuit 12.

[0150] The fourth input control circuit 10 can be connected to the sequential light emission control terminal EN_GLOBAL', the input terminal D of the output circuit 03, and the output terminals of other driving units 00. Furthermore, the fourth input control circuit 10 can be used to control the switching between the output terminals of other driving units 00 and the input terminal D of the output circuit 03 in response to the sequential light emission control signal, so that the signals output from the output terminals of other driving units 00 are transmitted to the input terminal D of the output circuit 03.

[0151] It is understood that, referring to Figure 8, the output terminal of the other-level driving unit 00 described in the embodiments of this application can refer to the output terminal Q of the output circuit 03 in the other-level driving unit 00. Of course, based on the output circuit 03 being a double-edge D flip-flop (DFF), the output terminal of the other-level driving unit 00 here can refer to the intermediate state terminal Q_INTER of the output circuit 03 in the other-level driving unit 00. Figure 8 labels it as Q_INTERn+1, indicating that the other-level driving unit 00 is the (n+1)th level driving unit 00.

[0152] Based on this, for example, the fourth input control circuit 10 can control the output terminal Q of the output circuit 03 in other driving units 00 to be connected to the input terminal D of the output circuit 03 in the current driving unit 00 when the potential of the sequential light emission control signal is the first potential, so that the signal output by the output terminal Q of the output circuit 03 in other driving units 00 is transmitted to the input terminal D of the output circuit 03 in the current driving unit 00; and can control the output terminal Q of the output circuit 03 in other driving units 00 to be disconnected from the input terminal D of the output circuit 03 in the current driving unit 00 when the potential of the sequential light emission control signal is the second potential, so that the signal output by the output terminal Q of the output circuit 03 in other driving units 00 cannot be transmitted to the input terminal D of the output circuit 03 in the current driving unit 00.

[0153] That is, the second input control circuit 02 and the fourth input control circuit 10 can respond to the sequential emission control signal provided by the sequential emission control terminal EN_GLOBAL' to control the forward and reverse transmission of the signal (e.g., emission signal EM) output by the output terminal Q of the output circuit 03 in each cascaded driving unit 00, so as to realize Sequential Emission and also be compatible with forward and reverse scanning functions.

[0154] The second forward scan control circuit 11 can be connected between the output terminal Q (e.g., intermediate state terminal Q_INTER) of the output circuit 03 and the second input control circuit 02, and can also be connected to the forward scan control terminal GSD_FW. This second forward scan control circuit 11 can be used to control the on / off state of the output terminal Q of the output circuit 03 and the second input control circuit 02 in response to the forward scan control signal provided by the forward scan control terminal GSD_FW, so that the signal output from the output terminal Q of the output circuit 03 is transmitted to the input terminal of other drive units 00 via the second input control circuit 02.

[0155] For example, the second forward scan control circuit 11 can control the output terminal Q of the output circuit 03 in the current stage drive unit 00 to be connected to the second input control circuit 02 when the potential of the forward scan control signal provided by the forward scan control terminal GSD_FW is the first potential, so that the signal output by the output terminal Q of the output circuit 03 in the current stage drive unit 00 is transmitted to the input terminal D of the output circuit 03 in other stage drive units 00 through the second input control circuit 02; and can also control the output terminal Q of the output circuit 03 in the current stage drive unit 00 to be disconnected from the second input control circuit 02 when the potential of the forward scan control signal provided by the forward scan control terminal GSD_FW is the second potential. At this time, the signal output by the output terminal Q of the output circuit 03 in the current stage drive unit 00 cannot be transmitted to the input terminal D of the output circuit 03 in other stage drive units 00 through the second input control circuit 02.

[0156] The second backscan control circuit 12 can be connected between the input terminal D of the output circuit 03 and the fourth input control circuit 10, and can also be connected to the backscan control terminal GSD_BW. This second backscan control circuit 12 can be used to control the on / off state of the input terminal D of the output circuit 03 and the fourth input control circuit 10 in response to the backscan control signal provided by the backscan control terminal GSD_BW, so that the signals output from the output terminals of other drive units 00 are transmitted to the input terminal D of the output circuit 03 via the fourth input control circuit 10.

[0157] For example, the second backscan control circuit 12 can control the input terminal D of the output circuit 03 in the current stage drive unit 00 to be connected to the fourth input control circuit 10 when the potential of the backscan control signal provided by the backscan control terminal GSD_BW is the first potential, so that the signal output by the output terminal Q (e.g., the intermediate state terminal Q_INTERn+1) of the output circuit 03 in other stage drive units 00 is transmitted to the input terminal D of the output circuit 03 in the current stage drive unit 00 through the fourth input control circuit 10; and can also control the input terminal D of the output circuit 03 in the current stage drive unit 00 to be disconnected from the fourth input control circuit 10 when the potential of the backscan control signal provided by the backscan control terminal GSD_BW is the second potential. At this time, the signal output by the output terminal Q of the output circuit 03 in other stage drive units 00 cannot be transmitted to the input terminal D of the output circuit 03 in the current stage drive unit 00 through the fourth input control circuit 10.

[0158] That is, under the control of the second forward scan control circuit 11 and the second reverse scan control circuit 12, and in conjunction with the second input control circuit 02 and the fourth input control circuit 10, forward and reverse scans can be achieved, and the signal transmission paths under forward and reverse scans are independent of each other. Specifically, the signal transmission path under forward scan is: input through the output terminal Q of the output circuit 03 in the current stage drive unit 00, and then sequentially transmitted through the second forward scan control circuit 11 and the second input control circuit 02 to the input terminal D of the output circuit 03 in other stage drive units 00. The signal transmission path under reverse scan is: input through the output terminal Q of the output circuit 03 in other stage drive units 00, and then sequentially transmitted through the fourth input control circuit 10 and the second reverse scan control circuit 12 to the input terminal D of the output circuit 03 in the current stage drive unit 00. Similarly, from the perspective of signal transmission, this design can relatively avoid crosstalk between the transmitted signals during forward and reverse scans, thereby improving the signal transmission efficiency during circuit operation.

[0159] As described above, within the same time period, the potential of the reverse scan control signal is opposite to that of the forward scan control signal. Therefore, combining this with the example described above, when the second forward scan control circuit 11 controls the output terminal Q of the output circuit 03 in the current stage drive unit 00 to be connected to the second input control circuit 02 to achieve forward scan, the second reverse scan control circuit 12 can control the input terminal D of the output circuit 03 in the current stage drive unit 00 to be disconnected from the fourth input control circuit 10; when the second reverse scan control circuit 12 controls the input terminal D of the output circuit 03 in the current stage drive unit 00 to be connected to the fourth input control circuit 10 to achieve reverse scan, the second forward scan control circuit 11 can control the output terminal Q of the output circuit 03 in the current stage drive unit 00 to be disconnected from the second input control circuit 02. That is, it is possible to perform either forward scan or reverse scan simultaneously within a certain time period while achieving Sequential Emission.

[0160] Optionally, referring to Figure 8, both the second input control circuit 02 and the fourth input control circuit 10 can be connected to the sequential light emission control terminal EN_GLOBAL'. Furthermore, the second input control circuit 02 can be used to control the on / off state of the output terminal Q of the output circuit 03 and the input terminals of other stage driving units 00 in response to the synchronous light emission control signal and the sequential light emission control signal. The fourth input control circuit 10 can be used to control the on / off state of the output terminals of other stage driving units 00 and the input terminal D of the output circuit 03 in response to the synchronous light emission control signal and the sequential light emission control signal.

[0161] For example, the second input control circuit 02 can control the output terminal Q of the output circuit 03 in the current stage drive unit 00 to be connected to the input terminal D of the output circuit 03 in other stage drive units 00 when the potential of the synchronous light emission control signal and / or the potential of the sequential light emission control signal is a first potential; and can control the output terminal Q of the output circuit 03 in the current stage drive unit 00 to be disconnected from the input terminal D of the output circuit 03 in other stage drive units 00 when the potential of the synchronous light emission control signal and the potential of the sequential light emission control signal are both a second potential.

[0162] Similarly, the fourth input control circuit 10 can control the output terminal Q of the output circuit 03 in other driving units 00 to be connected to the input terminal D of the output circuit 03 in the current driving unit 00 when the potential of the synchronous light emission control signal and / or the potential of the sequential light emission control signal is the first potential; and can control the output terminal Q of the output circuit 03 in other driving units 00 to be disconnected from the input terminal D of the output circuit 03 in the current driving unit 00 when the potential of the synchronous light emission control signal and the potential of the sequential light emission control signal are both the second potential.

[0163] That is, like the first input control circuit 01 and the third input control circuit 05, the second input control circuit 02 and the fourth input control circuit 10 can also control the on / off state of the connected ends under the control of the synchronous light emission control signal and the sequential light emission control signal. In this way, the reliability and flexibility of control can be improved.

[0164] It is understood that the potential of the synchronous light emission control signal received by each input control circuit in the second input control circuit 02 and the fourth input control circuit 10 can be exactly opposite to the potential of the synchronous light emission control signal received by each input control circuit in the first input control circuit 01 and the second input control circuit 02, and the potential of the received sequential light emission control signal can also be exactly opposite.

[0165] In other words, taking the first input control circuit 01 and the second input control circuit 02 as examples for comparison, assuming that the first potential of the synchronous light emission control signal received by the first input control circuit 01 is high and the first potential of the sequential light emission control signal received is low, then the first potential of the synchronous light emission control signal received by the second input control circuit 02 can be low, and the first potential of the sequential light emission control signal received can be high. Similarly, assuming that the second potential of the synchronous light emission control signal received by the first input control circuit 01 is low and the second potential of the sequential light emission control signal received is high, then the second potential of the synchronous light emission control signal received by the second input control circuit 02 can be high, and the second potential of the sequential light emission control signal received can be low. This ensures that within a given time period, only one input control circuit in the first input control circuit 01 and the second input control circuit 02 controls the two ends of the connection to be connected, achieving Global Emission or Sequential Emission.

[0166] In other words, in this embodiment, a synchronous emission control terminal EN_GLOBAL can be set to provide a synchronous emission control signal to switch between Global Emission and Sequential Emission modes. For example, when EN_GLOBAL = 1, it is in Global Emission mode, and when EN_GLOBAL = 0, it is in Sequential Emission mode. Here, EN_GLOBAL = 1 can mean that the potential of the synchronous emission control signal provided by the synchronous emission control terminal EN_GLOBAL is a high potential (1); EN_GLOBAL = 0 can mean that the potential of the synchronous emission control signal provided by the synchronous emission control terminal EN_GLOBAL is a low potential (0).

[0167] Optionally, referring to Figure 8, the second forward scan control circuit 11 can also be connected to the reverse scan control terminal GSD_BW. Furthermore, this second forward scan control circuit 11 can be used to control the on / off state of the output terminal Q of the output circuit 03 and the second input control circuit 02 in response to the forward scan control signal and the reverse scan control signal.

[0168] For example, the second forward scan control circuit 11 can control the output terminal Q of the output circuit 03 in the current stage drive unit 00 to be connected to the second input control circuit 02 when the potential of the forward scan control signal and / or the potential of the reverse scan control signal is a first potential; and can control the output terminal Q of the output circuit 03 in the current stage drive unit 00 to be disconnected from the second input control circuit 02 when the potentials of the forward scan control signal and the reverse scan control signal are both a second potential. That is, similar to the first forward scan control circuit 06, the second forward scan control circuit 11 can also control the connection and disconnection of the output terminal Q of the output circuit 03 in the current stage drive unit 00 with the second input control circuit 02 under the control of the two control signals, the forward scan control signal and the reverse scan control signal. In this way, the control reliability and flexibility can be improved.

[0169] Optionally, referring to Figure 8, the second reverse scan control circuit 12 can also be connected to the forward scan control terminal GSD_FW. Furthermore, this second reverse scan control circuit 12 can be used to control the on / off state of the input terminal D of the output circuit 03 and the fourth input control circuit 10 in response to the forward scan control signal and the reverse scan control signal.

[0170] For example, the second reverse scan control circuit 12 can control the input terminal D of the output circuit 03 in the current stage drive unit 00 to be connected to the fourth input control circuit 10 when the potential of the forward scan control signal and / or the potential of the reverse scan control signal is a first potential; and can control the input terminal D of the output circuit 03 in the current stage drive unit 00 to be disconnected from the fourth input control circuit 10 when the potentials of the forward scan control signal and the reverse scan control signal are both a second potential. That is, similar to the second reverse scan control circuit 07, the second reverse scan control circuit 12 can also control the connection and disconnection of the input terminal D of the output circuit 03 in the current stage drive unit 00 and the fourth input control circuit 10 under the control of the two control signals, the forward scan control signal and the reverse scan control signal. In this way, the control reliability and flexibility can be improved.

[0171] It is understandable that the potentials of the forward scan control signals received by the second forward scan control circuit 11 and the second reverse scan control circuit 12 can be exactly opposite, and the potentials of the received reverse scan control signals can also be exactly opposite. Furthermore, the potentials of the forward scan control signals received by the second forward scan control circuit 11 and the first forward scan control circuit 06 can be the same, and the potentials of the received reverse scan control signals can be the same; similarly, the potentials of the forward scan control signals received by the second reverse scan control circuit 12 and the first reverse scan control circuit 07 can be the same, and the potentials of the received reverse scan control signals can be the same. The potential design can refer to the above description of the first forward scan control circuit 06 and the first reverse scan control circuit 07, and will not be repeated here. Thus, it is possible that within a certain time period, only one control circuit in the second forward scan control circuit 11 and the second reverse scan control circuit 12 controls the two ends of the connection to be turned on, realizing either forward scan or reverse scan.

[0172] Optionally, based on Figure 8 and referring to Figure 9, the second input control circuit 02 may include a seventh transmission gate TG7. The fourth input control circuit 10 may include an eighth transmission gate TG8. The second forward scan control circuit 11 may include a ninth transmission gate TG9. The second reverse scan control circuit 12 may include a tenth transmission gate TG10.

[0173] Specifically, the control terminals T&T' of the seventh transmission gate TG7 and the eighth transmission gate TG8 can be connected to the synchronous emission control terminal EN_GLOBAL and the sequential emission control terminal EN_GLOBAL', respectively. The control terminals T&T' of the ninth transmission gate TG9 to the tenth transmission gate TG10 can be connected to the forward scan control terminal GSD_FW and the reverse scan control terminal GSD_BW, respectively. The input terminal IN of the seventh transmission gate TG7 can be connected to the output terminal OUT of the ninth transmission gate TG9. The output terminal OUT of the seventh transmission gate TG7 can be connected to the input terminal IN of other stage drive units 00. The input terminal IN of the ninth transmission gate TG9 can be connected to the output terminal OUT of the output circuit 03. The input terminal IN of the eighth transmission gate TG8 can be connected to the output terminal OUT of other stage drive units 00. The output terminal OUT of the eighth transmission gate TG8 can be connected to the input terminal IN of the tenth transmission gate TG10. The output terminal OUT of the tenth transmission gate TG10 can be connected to the input terminal IN of the output circuit 03.

[0174] Furthermore, as described above and shown in Figure 9, the control terminals T of the seventh transmission gate TG7 and the eighth transmission gate TG8 can both be connected to the sequential emission control terminal EN_GLOBAL', and the control terminals T' of the seventh transmission gate TG7 and the eighth transmission gate TG8 can both be connected to the synchronous emission control terminal EN_GLOBAL. The control terminal T of the ninth transmission gate TG9 in the second forward scan control circuit 11 can be connected to the forward scan control terminal GSD_FW, and its control terminal T' can be connected to the reverse scan control terminal GSD_BW. The control terminal T of the tenth transmission gate TG10 in the second reverse scan control circuit 12 can be connected to the reverse scan control terminal GSD_BW, and its control terminal T' can be connected to the forward scan control terminal GSD_FW. Thus, it is possible to ensure that only one control circuit in the second forward scan control circuit 11 and the second reverse scan control circuit 12 controls the two ends connected to be conducting at the same time, achieving either forward scan or reverse scan. Furthermore, in a forward scan scenario, only one of the control circuits in the first input control circuit 01 and the second input control circuit 02 can be activated at the same time, achieving Global Emission or Sequential Emission. Similarly, in a reverse scan scenario, only one of the control circuits in the first input control circuit 01 and the fourth input control circuit 04 can be activated at the same time, achieving Global Emission or Sequential Emission.

[0175] Optionally, based on Figure 9, and continuing to refer to Figure 10, it can be seen that the driving unit 00 may also include: an inverting circuit 13.

[0176] The inverter circuit 13 can be connected between the output terminal Q of the output circuit 03 and a pixel (not shown in the figure). Furthermore, the inverter circuit 13 can invert the signal output from the output terminal Q of the output circuit 03 before transmitting it to the pixel. In this way, two signals with opposite potentials can be output to flexibly adapt to the potential requirements of the N-type and P-type transistors in the pixel, thus expanding the range of applications.

[0177] Optionally, based on Figure 10, referring to Figure 11, it can be seen that the inverter circuit 13 may include: a third inverter F3.

[0178] The input terminal IN of the third inverter F3 can be connected to the output terminal Q of the output circuit O3, and the output terminal OUT of the third inverter F3 can be used to connect to a pixel.

[0179] Optionally, referring to Figures 3 to 11, it can also be seen that in the embodiments of this application, the double-edge D flip-flop DFF, each transmission gate and each inverter can also have a power supply terminal Vdd and a ground terminal GND. The power supply terminal Vdd can be used to receive the power supply signal, and the double-edge D flip-flop DFF, each transmission gate and each inverter can be used to work reliably under the control of the power supply signal.

[0180] As can be understood from the preceding description, the partial structure shown in Figures 8 to 11 can control the sequential transmission of the light-emitting signal EM to the input terminal D of the output circuit 03 (e.g., DFF) in each cascaded driving unit 00. The signal must pass through the DFF before being transmitted sequentially. In this way, the light-emitting signal EM can sequentially enter the output circuit 03 in each driving unit 00, where it is processed step-by-step. Ultimately, the cascaded driving units 00 output the light-emitting signal EM sequentially (e.g., row by row) to multiple rows of pixels, causing the pixels to emit light in sequence, thus enabling the display panel to operate in Sequential Emission mode. Correspondingly, the partial structure shown in Figures 8 to 11 can also be called a signal shift register module.

[0181] Based on the control panel operating in Sequential Emission mode, it can also be used with the fourth input control circuit 10, the second forward scan control circuit 11, and the second reverse scan control circuit 12 to achieve compatible forward and reverse scan functions. Furthermore, during normal display, only one state exists: forward scan or reverse scan.

[0182] For example, referring to Figure 9, in the forward scan state, the signal transmission path can be the path shown in Figure 9 (1). That is, the light-emitting signal EM can be entered from above, first passing through a ninth transmission gate TG9 controlled by GSD_FW=1, and then exiting through a seventh transmission gate TG7 controlled by EN_GLOBAL=0. In the reverse scan state, the signal transmission path can be the path shown in Figure 9 (2). The number of devices that the light-emitting signal EM passes through is the same, and the functions of each device are the same. The difference is that the light-emitting signal EM is entered from below, and GSD_BW=1.

[0183] Optionally, from the circuit structure perspective, this module may include a DFF (Distributed Front-End Gate), transmission gates, AND gates, and inverters. The two uppermost transmission gates (i.e., the ninth transmission gate TG9 and the tenth transmission gate TG10) can serve as forward / reverse scan control switches in Sequential Emission mode, while the two lowermost transmission gates (i.e., the seventh transmission gate TG7 and the eighth transmission gate TG8) can serve as control switches for signal transmission or non-transmission in Sequential Emission mode and Global Emission mode. For example, in Sequential Emission mode, EN_GLOBAL = 0, the seventh transmission gate TG7 is in the on state, and the light-emitting signal EM can be transmitted through the DFF stage; in Global Emission mode, EN_GLOBAL = 1, the seventh transmission gate TG7 is in the off state, and the light-emitting signal EM cannot be transmitted through the DFF stage. However, regardless of the mode, the light-emitting signal EM is always output after passing through an AND gate.

[0184] Optionally, referring to Figures 7 and 11, Figure 12 schematically shows an overall circuit structure diagram of a driving unit 00. Furthermore, referring to Figure 12 and the foregoing description, the driving unit 00 in the gate driving circuit provided in this application embodiment can mainly include two modules: a data transmission control module and a signal shift register module. Under the control of the data transmission control module, the multi-level driving unit 00 can simultaneously transmit the same light-emitting signal EM to multiple rows of pixels in the display panel at the same time, enabling the display panel to achieve a synchronized light-emitting display effect across the entire surface, thus allowing the display panel to operate in Global Emission mode. Under the control of the signal shift register module, the multi-level driving unit 00 can sequentially transmit the light-emitting signal EM row by row to multiple rows of pixels in the display panel, causing the multiple rows of pixels to be lit sequentially, thus enabling the display panel to operate in Sequential Emission mode. Moreover, the display panel can be flexibly controlled to operate in either Global Emission mode or Sequential Emission mode at the same time. In addition, while supporting the display panel to operate in both Global Emission mode and Sequential Emission mode, this application embodiment also retains forward and reverse scanning functions. This gate drive circuit can be adapted to the needs of more display products.

[0185] For example, Figure 12 illustrates two signal transmission paths in Global Emission mode and Sequential Emission mode, using forward scanning as an example. Referring to Figure 12, in Global Emission mode, the signal can be transmitted via path A. That is, the signal can enter from the input D of the double-edge D flip-flop DFF in the current stage driver unit 00, and sequentially pass through the first transmission gate TG1, the third transmission gate TG3, the two first inverters F1, the fourth transmission gate TG4, and the second transmission gate TG2 to the input D of the double-edge D flip-flop DFF in other stage driver units 00. In Sequential Emission mode, the signal can be transmitted via path B. That is, the signal can enter from the output Q of the double-edge D flip-flop DFF in the current stage driver unit 00, and sequentially pass through the ninth transmission gate TG9 and the seventh transmission gate TG7 to the input D of the double-edge D flip-flop DFF in other stage driver units 00.

[0186] As mentioned earlier, when the control display panel is in Global Emission mode, the light emission time, light emission start point, and even light emission end point of multiple rows or even all rows of pixels in the display panel can be kept consistent. This means that the entire panel of pixels can be displayed simultaneously, which can alleviate the problem of poor display effect caused by inconsistent light emission time to a certain extent.

[0187] Optionally, taking the structure shown in Figure 12 as an example, with two adjacent driving units 00(1) and 00(2) cascaded, and each driving unit 00 connected to a row of pixels, Figure 13 schematically shows a cascaded circuit structure. Referring to Figure 13, it can be seen that in Global Emission mode, the light emission signal EM can be simultaneously transmitted to the input terminal D of the DFF in the two driving units 00 via the data transmission control module on the left. This allows the DFF in the two driving units 00 to simultaneously output the light emission signal EM received at their respective input terminals D via their respective output terminals Q when the rising edge of the clock signal arrives, and after processing by their respective AND logic gates, simultaneously output to the connected row of pixels. In this way, the two rows of pixels connected by the two driving units 00 can be displayed simultaneously. Among them, Line1 Output shown in Figure 13 refers to the light emission signal EM output by the first driving unit 00(1) to the connected first row of pixels; Line2 Output refers to the light emission signal EM output by the second driving unit 00(2) to the connected second row of pixels.

[0188] In other words, as can be seen from the timing diagram shown in Figure 14, in Global Emission mode, light emission signals EM with the same potential can be output to multiple rows of pixels simultaneously, allowing multiple rows of pixels to start emitting light and stop emitting light simultaneously. Figure 14 schematically shows the light emission signals EM output to 10 rows (Line 1 to Line 10) of pixels.

[0189] It is understood that the gate driving circuit described in the embodiments of this application is not limited to outputting a light-emitting signal EM. For example, in some other embodiments, it can also be used to output a gate driving signal GATE.

[0190] In summary, this application provides a gate driving circuit. Because the gate driving circuit includes multiple driving units, the first input control circuit in each driving unit can, under the control of a synchronous emission control signal, control the input terminal of the current driving unit to be connected to the input terminals of other driving units, so that the emission signal is simultaneously transmitted to the multiple driving units; and the second input control circuit in each driving unit can, under the control of a sequential emission control signal, control the output terminal of the current driving unit to be connected to the input terminals of other driving units, so that the emission signal is transmitted sequentially to the multiple driving units. Therefore, this gate driving circuit can not only simultaneously output emission signals to multiple rows of pixels to drive multiple rows of pixels to emit light synchronously, but also sequentially output emission signals to multiple rows of pixels to drive multiple rows of pixels to emit light sequentially. That is, this gate driving circuit is compatible with both Global Emission and Sequential Emission emission modes, and its driving method is diversified, resulting in better driving performance.

[0191] Furthermore, by controlling the simultaneous and synchronous illumination of multiple rows of pixels, the problem of poor display uniformity caused by inconsistent illumination timing can be improved. In other words, it ensures better display performance of the display panel.

[0192] This application also provides a driving method for a display panel, applied in the gate driving circuit described in the above embodiments. As shown in FIG15, the method includes:

[0193] Step 1501: In response to the synchronous light emission command, the first input control circuit responds to the synchronous light emission control signal provided by the synchronous light emission control terminal, and controls the input terminal of the output circuit to be connected with the input terminals of other driving units, so that the signal received by the input terminal of the output circuit is transmitted to the input terminals of other driving units. The output circuits in each driving unit sample the received light emission signal based on the received clock signal and output it synchronously to the multiple rows of pixels in the display panel to synchronously light up the multiple rows of pixels.

[0194] Step 1502: In response to the sequential light emission command, the second input control circuit responds to the sequential light emission control signal provided by the sequential light emission control terminal, controlling the on / off state of the output terminal of the output circuit and the input terminals of other driving units, so that the signal output by the output terminal of the output circuit is transmitted to the input terminals of other driving units. The output circuits in each driving unit sample the received light emission signal based on the received clock signal and then sequentially output it to multiple rows of pixels in the display panel to light up multiple rows of pixels in sequence.

[0195] Optionally, the synchronous illumination command and the sequential illumination command can be generated by the DDIC. Furthermore, the DDIC can provide the synchronous illumination control signal and the sequential illumination control signal described above based on the aforementioned commands, so as to synchronously illuminate multiple rows of pixels or sequentially illuminate multiple rows of pixels.

[0196] It is understood that since the driving method of the display panel can have essentially the same implementation method and technical effect as the gate driving circuit of the display panel described in the previous embodiments, the implementation method and technical effect of the driving method of the display panel will not be described again here for the purpose of brevity.

[0197] This application also provides a display device. As shown in FIG16, the display device includes: a display panel 100, and a gate driving circuit 000 as described in the above embodiments.

[0198] The display panel 100 includes multiple rows of pixels. A gate driving circuit 000 is connected to the multiple rows of pixels and is used to drive the multiple rows of pixels to emit light. Figure 16 only schematically shows the display panel 100.

[0199] Optionally, the display device described in this application embodiment can be any product or component with display function, such as an organic light-emitting diode (OLED) display device or a silicon-based OLED display device. Furthermore, the display device can be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and e-books, etc., any product or component with display function.

[0200] Since the display device can have essentially the same technical effect as the gate driving circuit described in the previous embodiments, the technical effect of the gate driving circuit will not be described again here for the sake of brevity.

[0201] It should be noted that the terminology used in the embodiments of this application is for illustrative purposes only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in the implementation of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0202] For example, the terms "first," "second," or "third," and similar words used in the patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "an" or "a," and similar words do not indicate a quantity limitation, but rather indicate the presence of at least one. Terms such as "comprising" or "including" mean that the element or object preceding "comprising" or "including" encompasses the element or object listed after "comprising" or "including" and its equivalents, and do not exclude other elements or objects. "Above," "below," "left," or "right," etc., are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. "Connected" or "coupled" refers to an electrical connection. "And / or" indicates that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0203] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A gate driving circuit for a display panel, the gate driving circuit comprising: A cascaded multi-stage drive unit, the drive unit comprising: a first input control circuit, a second input control circuit, and an output circuit; The first input control circuit is connected to the synchronous light emission control terminal, the input terminal of the output circuit, and the input terminals of other cascaded driving units, respectively, and is used to control the switching between the input terminal of the output circuit and the input terminals of the other driving units in response to the synchronous light emission control signal provided by the synchronous light emission control terminal, so that the signal received by the input terminal of the output circuit is transmitted to the input terminal of the other driving units. The second input control circuit is connected to the sequential light emission control terminal, the output terminal of the output circuit, and the input terminal of the other driving units, respectively. It is used to control the switching between the output terminal of the output circuit and the input terminal of the other driving units in response to the sequential light emission control signal provided by the sequential light emission control terminal, so that the signal output by the output terminal of the output circuit is transmitted to the input terminal of the other driving units. In the same time period, the potential of the sequential light emission control signal is opposite to the potential of the synchronous light emission control signal. The input terminal of the output circuit is used to receive the light emission signal, the clock terminal of the output circuit is used to receive the clock signal, the output terminal of the output circuit is used to connect to the pixel in the display panel, and the output circuit is used to sample the light emission signal based on the clock signal and output it to the pixel through the output terminal.

2. The gate driving circuit according to claim 1, wherein, The output circuit includes: a flip-flop; The output circuit is used to sample the light emission signal based on the rising edge of the clock signal and then output it to the pixel via the output terminal.

3. The gate driving circuit according to claim 2, wherein, The flip-flop is a double-edge D flip-flop; the second input control circuit is connected to the intermediate state terminal of the double-edge D flip-flop; the driving unit further includes: logic circuitry; The logic circuit is used to connect between the output terminal of the double-edge D flip-flop and the pixel, and the logic circuit is also connected to the intermediate state terminal of the double-edge D flip-flop. The logic circuit is used to perform logical operations on the signals output from the output terminal and the intermediate state terminal of the double-edge D flip-flop and then output them to the pixel.

4. The gate driving circuit according to claim 3, wherein, The logical operation is an AND operation, and the logic circuit includes an AND gate. The two inputs of the AND gate are connected to the output and intermediate state of the dual-edge D flip-flop, respectively, and the output of the AND gate is used to connect to the pixel.

5. The gate drive circuit according to any one of claims 1 to 4, wherein, The drive unit further includes: a third input control circuit, a first forward scan control circuit, and a first reverse scan control circuit; The first input control circuit is connected to the input terminal of the other driving unit via the third input control circuit, and the third input control circuit is also connected to the synchronous light emission control terminal. The first input control circuit and the third input control circuit are used to control the on / off state of the input terminal of the output circuit and the input terminal of the other driving unit in response to the synchronous light emission control signal, so that the signal received by the input terminal of the output circuit is transmitted to the input terminal of the other driving unit, or the signal received by the input terminal of the other driving unit is transmitted to the input terminal of the output circuit. Both the first forward scan control circuit and the first reverse scan control circuit are connected between the first input control circuit and the third input control circuit. The first forward scan control circuit is also connected to the forward scan control terminal, and the first reverse scan control circuit is also connected to the reverse scan control terminal. The first forward scan control circuit is used to control the on / off state of the first input control circuit and the third input control circuit in response to the forward scan control signal provided by the forward scan control terminal, so that the signal received at the input terminal of the output circuit is transmitted sequentially through the first input control circuit and the third input control circuit to the input terminal of the other driving units. The first reverse scan control circuit is used to control the on / off state of the first input control circuit and the third input control circuit in response to the reverse scan control signal provided by the reverse scan control terminal, so that the signal received at the input terminal of the other driving units is transmitted sequentially through the third input control circuit and the first input control circuit to the input terminal of the output circuit. During the same time period, the potential of the reverse scan control signal is opposite to that of the forward scan control signal.

6. The gate driving circuit according to claim 5, wherein, The first input control circuit and the third input control circuit are also connected to the sequential light emission control terminal and are used to control the connection and disconnection between the input terminal of the output circuit and the input terminal of the other stage driving unit in response to the synchronous light emission control signal and the sequential light emission control signal. The first forward scan control circuit is also connected to the reverse scan control terminal and is used to control the on / off state of the first input control circuit and the third input control circuit in response to the forward scan control signal and the reverse scan control signal. The first reverse scan control circuit is also connected to the forward scan control terminal and is used to control the on / off state of the first input control circuit and the third input control circuit in response to the forward scan control signal and the reverse scan control signal.

7. The gate driving circuit according to claim 6, wherein, The first input control circuit includes a first transmission gate; the third input control circuit includes a second transmission gate; the first forward scan control circuit includes a third transmission gate and a fourth transmission gate; the first reverse scan control circuit includes a fifth transmission gate and a sixth transmission gate. The control terminals of the first and second transmission gates are respectively connected to the synchronous light emission control terminal and the sequential light emission control terminal. The control terminals of the third to sixth transmission gates are respectively connected to the forward scan control terminal and the reverse scan control terminal. The input terminal of the first transmission gate is connected to the input terminal of the output circuit. The output terminal of the first transmission gate is connected to the input terminal of the third transmission gate and the output terminal of the fifth transmission gate. The output terminal of the third transmission gate is connected to the input terminal of the fourth transmission gate. The input terminal of the fifth transmission gate is connected to the output terminal of the sixth transmission gate. The output terminals of the fourth and sixth transmission gates are both connected to the output terminal of the second transmission gate. The input terminal of the second transmission gate is connected to the input terminal of the other driving units.

8. The gate driving circuit according to claim 7, wherein, The driving unit further includes: a first enhancement circuit and / or a second enhancement circuit; The first enhancement circuit is connected between the third transmission gate and the fourth transmission gate, and is used to enhance the signal output by the third transmission gate before transmitting it to the fourth transmission gate; The second enhancement circuit is connected between the fifth transmission gate and the sixth transmission gate, and is used to enhance the signal output by the sixth transmission gate before transmitting it to the fifth transmission gate.

9. The gate driving circuit according to claim 8, wherein, The first enhancement circuit includes an even number of first inverters connected in series; the second enhancement circuit includes an even number of second inverters connected in series. The input terminals of the even-numbered series-connected first inverters are connected to the output terminal of the third transmission gate, and the output terminals of the even-numbered series-connected first inverters are connected to the input terminal of the fourth transmission gate. The input terminals of the even-numbered series-connected second inverters are connected to the output terminal of the sixth transmission gate, and the output terminals of the even-numbered series-connected second inverters are connected to the input terminal of the fifth transmission gate.

10. The gate driving circuit according to any one of claims 1 to 9, wherein, The drive unit further includes: a fourth input control circuit, a second forward scan control circuit, and a second reverse scan control circuit; The fourth input control circuit is connected to the sequential light emission control terminal, the input terminal of the output circuit, and the output terminal of the other driving units, respectively, and is used to control the connection and disconnection between the output terminal of the other driving units and the input terminal of the output circuit in response to the sequential light emission control signal, so that the signal output by the output terminal of the other driving units is transmitted to the input terminal of the output circuit. The second forward scan control circuit is connected between the output terminal of the output circuit and the second input control circuit, and is also connected to the forward scan control terminal. It is used to control the on / off state of the output terminal of the output circuit and the second input control circuit in response to the forward scan control signal provided by the forward scan control terminal, so that the signal output by the output terminal of the output circuit is transmitted to the input terminal of the other stage drive unit through the second input control circuit. The second backscan control circuit is connected between the input terminal of the output circuit and the fourth input control circuit, and is also connected to the backscan control terminal. It is used to control the on / off state of the input terminal of the output circuit and the fourth input control circuit in response to the backscan control signal provided by the backscan control terminal, so that the signal output by the output terminal of the other stage drive unit is transmitted to the input terminal of the output circuit through the fourth input control circuit. During the same time period, the potential of the reverse scan control signal is opposite to that of the forward scan control signal.

11. The gate driving circuit according to claim 10, wherein, The second input control circuit and the fourth input control circuit are both connected to the sequential light emission control terminal. The second input control circuit is used to control the connection and disconnection between the output terminal of the output circuit and the input terminal of the other stage driving unit in response to the synchronous light emission control signal and the sequential light emission control signal. The fourth input control circuit is used to control the connection and disconnection between the output terminal of the other stage driving unit and the input terminal of the output circuit in response to the synchronous light emission control signal and the sequential light emission control signal. The second forward scan control circuit is also connected to the reverse scan control terminal and is used to control the connection and disconnection between the output terminal of the output circuit and the second input control circuit in response to the forward scan control signal and the reverse scan control signal. The second reverse scan control circuit is also connected to the forward scan control terminal and is used to control the on / off state of the input terminal of the output circuit and the fourth input control circuit in response to the forward scan control signal and the reverse scan control signal.

12. The gate driving circuit according to claim 11, wherein, The second input control circuit includes a seventh transmission gate; the fourth input control circuit includes an eighth transmission gate; the second forward scan control circuit includes a ninth transmission gate; the second reverse scan control circuit includes a tenth transmission gate. The control terminals of the seventh and eighth transmission gates are respectively connected to the synchronous light emission control terminal and the sequential light emission control terminal. The control terminals of the ninth to tenth transmission gates are respectively connected to the forward scan control terminal and the reverse scan control terminal. The input terminal of the seventh transmission gate is connected to the output terminal of the ninth transmission gate. The output terminal of the seventh transmission gate is connected to the input terminal of the other driving units. The input terminal of the ninth transmission gate is connected to the output terminal of the output circuit. The input terminal of the eighth transmission gate is connected to the output terminal of the other driving units. The output terminal of the eighth transmission gate is connected to the input terminal of the tenth transmission gate. The output terminal of the tenth transmission gate is connected to the input terminal of the output circuit.

13. The gate drive circuit according to any one of claims 1 to 12, wherein, The driving unit further includes: an inverting circuit; The inverting circuit is connected between the output terminal of the output circuit and the pixel, and is used to invert the signal output from the output terminal of the output circuit and then transmit it to the pixel.

14. The gate drive circuit according to claim 13, wherein, The inverting circuit includes: a third inverter; The input terminal of the third inverter is connected to the output terminal of the output circuit, and the output terminal of the third inverter is used to connect to the pixel.

15. A driving method for a display panel, applied in a gate driving circuit as described in any one of claims 1 to 14; the method comprising: In response to the synchronous light emission command, the first input control circuit responds to the synchronous light emission control signal provided by the synchronous light emission control terminal, and controls the input terminal of the output circuit to be connected to the input terminals of other driving units, so that the signal received by the input terminal of the output circuit is transmitted to the input terminals of the other driving units. The output circuits in each driving unit sample the received light emission signal based on the received clock signal and output it synchronously to the multiple rows of pixels in the display panel to synchronously light up the multiple rows of pixels. In response to the sequential light emission command, the second input control circuit, in response to the sequential light emission control signal provided by the sequential light emission control terminal, controls the connection and disconnection between the output terminal of the output circuit and the input terminal of the other driving units, so that the signal output by the output terminal of the output circuit is transmitted to the input terminal of the other driving units. The output circuits in each driving unit sample the received light emission signal based on the received clock signal and then sequentially output it to multiple rows of pixels in the display panel to light up the multiple rows of pixels in sequence.

16. A display device, the display device comprising: The display panel, and the gate driving circuit as described in any one of claims 1 to 14; The display panel includes multiple rows of pixels, and the gate driving circuit is connected to the multiple rows of pixels and is used to drive the multiple rows of pixels to emit light.

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