Methods to produce and recycle substates for iii-nitride materials with electrochemical etching

Abstract

Methods to produce and recycle substrates for III-nitride materials with electrochemical etching of highly doped n-type sacrificial layers and a fast hydride vapor phase epitaxy (HVPE) layer deposition to tackle the problems brought by wafer bowing and off-angle distribution in the substrate production process. These methods also showcase designs for sacrificial layers with specific fabrication structures, enabling high-quality substrate recycling, reducing the cost of buffer layer growth or mask layer fabrication, and resulting in a consistently smooth, epi-ready substrate surface that is suitable for direct regrowth without additional polishing steps, thereby enhancing efficiency and reducing processing costs.

Description

[0001] METHODS TO PRODUCE AND RECYCLE SUBSTATES

[0002] FOR III-NITRIDE MATERIALS WITH ELECTROCHEMICAL ETCHING

[0003] CROSS REFERENCE TO RELATED APPLICATIONS

[0004] This application claims the benefit under 35 U.S.C. Section 119(e) of the following co-pending and commonly-assigned application:

[0005] U.S. Provisional Patent Application Serial No. 63 / 722,720, filed on November 20, 2024. by Yifan Yao, Hanyu Bi, Michael Iza. Shuji Nakamura and Steven P. DenBaars, entitled ‘METHODS TO PRODUCE AND RECYCLE SUBSTATES FOR III-NITRIDE MATERIALS WITH ELECTROCHEMICAL ETCHING,” docket number G&C 30794.0864USP1 (UC -2025-357-1); which application is incorporated by reference herein.

[0006] This application is related to the following co-pending and commonly- assigned applications:

[0007] P.C.T. International Patent Application Serial No. PCT / US25 / 48683, filed on September 30, 2025, by Yifan Yao, Hanyu Bi, Michael Iza, Shuji Nakamura and Steven P. DenBaars, entitled ‘ METHOD TO LIFT-OFF III-NITRIDE MATERIALS WITH AN ELECTROCHEMICAL ETCH,” docket number G&C 30794.0861W0U1 (UC 2025-344-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Patent Application Serial No. 63 / 700,896, filed on September 30, 2024. by Yifan Yao, Hanyu Bi, Michael Iza, Shuji Nakamura and Steven P. DenBaars, entitled “METHOD TO LIFTOFF III-NITRIDE MATERIALS WITH AN ELECTROCHEMICAL ETCH,” docket number G&C 30794.0861USP1 (UC 2025-344-1);

[0008] P.C.T. International Patent Application Serial No. PCT / US25 / 53692, filed on November 3. 2025. by Yifan Yao, Hanyu Bi, Michael Iza, Shuji Nakamura and Steven P. DenBaars, entitled “METHOD TO FABRICATE STRAIN-RELAXED III- NITRIDE MATERIALS WITH AN ELECTROCHEMICAL ETCH,” docket number G&C 30794.0863WOU1 (UC 2025-351-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly -as signed U.S.

[0009] Provisional Patent Application Serial No. 63 / 715,058, filed on November 1, 2024, by Yifan Yao, Hanyu Bi, Michael Iza, Shuji Nakamura and Steven P. DenBaars. entitled “METHOD TO FABRICATE STRAIN-RELAXED III-NITRIDE MATERIALS WITH AN ELECTROCHEMICAL ETCH." docket number G&C 30794.0863USP1 (UC-2025-351-1);

[0010] U.S. Provisional Patent Application Serial No. 63 / 794,481, filed on April 25, 2025. by Michael Iza, Yifan Yao, Hanyu Bi. Steven P. DenBaars and Shuji Nakamura, entitled “ELECTROCHEMICAL LIFT-OFF AND TRANSFER OF III- NITRIDE DEVICE LAYERS FOR HETEROGENEOUS INTEGRATION,” docket number G&C 30794.0873USP1 (UC 2025-381-1);

[0011] U.S. Provisional Patent Application Serial No. 63 / 798,679, filed on May 2, 2025, by Michael Iza, Yifan Yao, Hanyu Bi, Steven P. DenBaars and Shuji Nakamura, entitled “ELECTROCHEMICAL LIFT-OFF AND INTEGRATION OF III-NITRIDE THIN FILMS FOR PHOTONIC AND QUANTUM APPLICATIONS,” docket number G&C 30794.0878USP1 (UC-2025-388-1);

[0012] U.S. Provisional Patent Application Serial No. 63 / 814,824, filed on May 30, 2025, by Michael Iza, Yifan Yao, Hanyu Bi, Steven P. DenBaars and Shuji Nakamura, entitled “III-NITRIDE POWER DEVICES WITH BONDED THIN FILMS, POLARITY CONTROL AND THERMALLY OPTIMIZED CARRIER INTEGRATION,” docket number G&C 30794.0883USP1 (UC 2025-391-1);

[0013] U.S. Provisional Patent Application Serial No. 63 / 836,785, filed on July 1, 2025, by Yifan Yao, Hanyu Bi, Michael Iza, Shuji Nakamura and Steven P. DenBaars, entitled “SENSING DEVICE USING III-NITRIDE LIFT-OFF TECHNOLOGY FOR RAMAN SPECTROSCOPY AND FLUORESCENCE,” docket number G&C 30794.0875USP1 (UC -2025-382-1);

[0014] U.S. Provisional Patent Application Serial No. 63 / 846,495, filed on July 18, 2025, by Michael Iza, Xianqing Li, Kittamet Chanchai worawit, Stephen Gee, Hanyu Bi, Yifan Yao, Steven P. DenBaars and Shuji Nakamura, entitled “III-NITRIDE- BASED VERTICAL CAVITY SURFACE EMITTING LASER (VCSEL) UTILIZING AN ELECTROCHEMICAL ETCH BASED LIFT-OFF,” docket number G&C 30794.0876USP1 (UC 2025-384-1); and

[0015] U.S. Provisional Patent Application Serial No. 63 / 907,194, filed on October 29, 2025, by Michael Iza, Toru Inatome, Yifan Yao, Hanyu Bi, Steven P. DenBaars and Shuji Nakamura, entitled “NITRIDE SEMICONDUCTOR DEVICES INCORPORATING DEFECT REDUCTION LAYERS AND ELECTROCHEMICAL LIFT-OFF SACRIFICIAL LAYERS,” docket number G&C 30794.0896USP1 (UC 2026-793-1); all of which applications are incorporated by reference herein.

[0016] BACKGROUND OF THE INVENTION

[0017] 1. Field of Invention

[0018] The invention relates to methods to produce and recycle substrates for III- nitride materials or devices by depositing and electrochemically etching sacrificial layers.

[0019] 2. Description of the Related Art

[0020] (Note: This application references several different publications as indicated throughout the specification by one or more reference numbers within brackets, e.g., [x], A list of these different publications ordered according to these reference numbers can be found below in the section entitled "References”. Each of these publications is incorporated by reference herein.)

[0021] (Note: The terms “III-N” or “Group-Ill nitride” or “Ill-nitride” or “nitride” as used herein refer to any alloy composition of (Ga, Al, In, B)N having the formula GanAlxInyBzN, where 0<n<l, 0<x<l, 0<y<l, 0<z<l and n+x+y+z=l.)

[0022] The substrate market for the Ill-nitride material system has been expanding for decades across optoelectronics and power electronics for both research and industry'. To achieve a higher mass production level, researchers endeavor to grow and fabricate III-N-based semiconductor devices on larger, 4- to 6-inch, bulk substrates with lower threading dislocation density (TDD) and reduced material bowing, while keeping the entire manufacturing process cost-effective. Simultaneously optimizing all three parameters - TDD, crystal bowing, and the cost -could be challenging with only traditional substrate manufacturing processes.

[0023] Bulk GaN Substrates Production

[0024] Single crystal bulk GaN is mainly grown with three methods: liquid phase methods (ammonothermal and Na-flux methods), metal-organic chemical vapor deposition (MOCVD), and hydride vapor phase epitaxy (HVPE). Since the growth rate of HVPE (around 100 microns / hour) is almost 10 times faster than MOCVD and 50 times faster than the liquid phase method, with acceptable TDD (1 x 104cm'2to 1 xl06cm'2), HVPE grown bulk GaN substrates dominate the current market [1] [2] .

[0025] Most bulk GaN growth techniques rely on foreign substrates, such as sapphire, GaAs, and SiC. Due to the lattice mismatch betw een these substrates and freestanding GaN, direct HVPE deposition can introduce a high density of defects, resulting in increased TDD and exacerbating wafer bowing when the GaN crystal thickness exceeds a few millimeters. To address these challenges, methods like epitaxial lateral overgrowth (ELOG) and the development of free-standing GaN layers are commonly used to reduce TDD and relieve accumulated stress in GaN layers [3],

[0026] Bulk GaN substrate fabricated by ELOG techniques also face a range of challenges. Since III-N materials do not readily grow on SiO2 or SiN hard masks used in ELOG, this technique promotes lateral growth over the mask regions, allowing partial relaxation of the bulk GaN and effectively reducing threading dislocation density (TDD) during this phase. Although the enhanced cry stal quality by ELOG strengthens the market appeal of bulk GaN substrates, this growth process requires extra time and expenses on fabrication. Additionally, crystal bowing is a persistent challenge, primarily due to the off-angle distribution during the GaN coalescence process using ELOG, which limits the crystal's achievable thickness due to accumulated stress and the potential for microcracks after laser lift-off (LLO) [1], Concurrently, a high off-angle distribution can alter device characteristics, such as alloy composition and polarization, due to deviations in the exposed crystal plane. As a result, reduced wafer bowing and minimal off-angle distribution are generally- preferred to achieve consistent device performance and structural integrity [1J.

[0027] On the other hand, growing on free-standing GaN can reduce stress accumulation and wafer bowing, lower the TDD, and simplify the foreign wafer liftoff process, leading multiple groups to develop methodologies for this type of substrate growth strategy. Oshima et al. employed a TiN layer on a GaN nucleation layer, followed by high-temperature annealing to create voids for relaxed GaN regrowth on a free-standing nano-net, resulting in this method being named void- assisted separation (VAS) [4], However, the TiN film may introduce defects in III-N regrowth due to lattice mismatches. In 2018. Fujikura et al. demonstrated a similar VAS method by annealing an MOCVD-grown GaN seed layer on a sapphire substrate, then regrowing an ELOG buffer with HVPE, followed by rapid GaN deposition on the c-plane [3], This method achieved a microdefect-free GaN over 6 mm thick. Recently, Sumitomo used EC porosification of a heavily doped n-type layer to regrow bulk GaN on a relaxed GaN layer, utilizing the thermal coefficient differences between sapphire and GaN to lift off the single-crystal GaN [5] . Nevertheless, all these methods used voids for relaxation or substrate liftoff, which did not achieve full relaxation due to incomplete detachment of the upper bulk GaN.

[0028] Substrate Recycling

[0029] For substrate reuse, it is essential that the surface of the detached substrates achieves sub-nanometer root-mean-square (RMS) roughness while maintaining the quality of both the substrate and buffer layers to enable direct regrowth. Only a few lift-off methods can achieve this level of smoothness, and most still face significant challenges with limited applications in substrate reuse. One widely used method, LLO, is primarily employed in the semiconductor industry- for III-N structures on sapphire substrates. LLO uses deep UV laser pulses on sapphire substrates to decompose an interfacial GaN layer by exploiting the bandgap difference between AI2O3 and GaN [6], However, this technique is not applicable for bulk GaN, Si, or SiC substrates due to their lower bandgaps. It can also introduce dislocations, add processing steps, and increase costs for residual gallium removal [7], Additionally, LLO struggles to lift off buffer layers selectively if there is no low-bandgap material layer immediately beneath them. Another commonly used method is chemical lift-off (CLO), which has long been explored for Ill-nitride materials, particularly in GaN- based LED production. CLO methods, including photoelectrochemical (PEC) etching, offer greater flexibility in choosing electrolytes, material types, etch layer thicknesses, and process positioning. However, PEC etching has stringent requirements for the sacrificial layer’s bandgap. compatible light source intensity and wavelength, and lattice-matched sacrificial layers, thus limiting its applicability due to challenges with material compatibility and growth constraints.

[0030] Electrochemical Etching

[0031] Compared to LLO and PEC methods, EC etching offers a better approach for selectively removing Ill-nitrides through an oxidation process driven by an external voltage bias. This method provides greater flexibility in selecting the lift-off layer, choosing compatible electrolytes, and controlling the etched surface morphology. Specifically, conductivity-based selective EC etching offers additional design flexibility by removing the need for specific alloy compositions in sacrificial layers or the assistance of external light sources compared to PEC etching and LLO techniques.

[0032] In 2012, Zhang et al. demonstrated successful lift-off of a blue LED structure regrown on porous layers formed through selective EC etching of highly and lightly- doped n-GaN [8], Although the porous structure aids lift-off, quick surface recovery by regrowing on porous layers poses substantial challenges.

[0033] In 2014, Park et al. demonstrated blue emission from a nanomembrane formed by EC etching of a heavily Si-doped layer in HF solution, illustrating the potential of EC etching for device lift-off without degrading epitaxial structures [9] . However, oxides, commonly used as passivation materials in complete device fabrication, may encounter challenges with HF as the etching electrolyte. Additionally, lift-off interface smoothness remained largely unexplored at that time.

[0034] By 2023, Liu et al. conducted doping-series electrochemical etching experiments on GaN, finding that interface roughness (RMS) could be reduced to 0.3 nm by using a doping concentration of 5* 1019cm3and a 10V bias

[0010] , which aligns with the observations of the inventors in the related patent applications cross- referenced above.

[0035] Nonetheless, there is a need in the art for further improvements in substrate recycling, including complete procedures and specialized designs not addressed in previous studies. The present invention satisfies that need.

[0036] SUMMARY OF THE INVENTION

[0037] The present invention describes methods to produce and recycle substrates for Ill-nitride materials with EC etching of highly doped n-type sacrificial layers and a fast HVPE layer deposition to tackle the problems brought by wafer bowing and off- angle distribution in the substrate production process. Furthermore, the present invention also showcases the designs for sacrificial layers with specific fabrication structures, enabling high-quality substrate recycling, reducing the cost of buffer layer growth or mask layer fabrication, and resulting in a consistently smooth, epi-ready substrate surface that is suitable for direct regrowth without additional polishing steps, thereby enhancing efficiency and reducing processing costs.

[0038] The present invention introduces a series of strategies for selectively separating epitaxial layers from the substrate, utilizing the epitaxial growth of a material structure combined with EC etching to offer potential solutions to the challenges faced by the III-N substrate industry, primarily from production and recycling perspectives. Although the proposed methods herein will be mainly demonstrated by an example of bulk GaN substrate production, its application could potentially be extended to other Ill-nitride materials.

[0039] In contrast to prior Bulk GaN Substrates Production, the present invention can achieve 100% detachment in selected regions, which potentially enables a lower bowing and off-angle distribution for a thicker bulk GaN regrowth. Meanwhile, it drastically simplifies or even eliminates the need for slicing and polishing after substrate growth. Specific advantages of the present invention, compared to existing techniques, will be discussed in detail below.

[0040] In contrast to prior Electrochemical Etching, the present invention proposes an EC etching approach for substrate recycling that largely eliminates the repetition of buffer layer growth on new foreign wafers, as sacrificial layers can be placed above the buffer structures, enabling wafers to be recycled with epi -ready structures and surface morphology for various applications after EC etching.

[0041] BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Referring now to the drawings in which like labels represent corresponding parts throughout:

[0043] Fig. 1 illustrates the step-by-step process for the detachment of Ill-nitride layers using EC etching, followed by preparing the substrate for subsequent regrowth. Each step is designed to achieve a smoother epi-ready surface without additional polishing, differentiating this method from traditional lift-off processes that may require additional surface treatment.

[0044] Fig. 2, using material stacking charts, illustrates Ill-nitride sample layers, which can be bulk or thin film structures, and a lift-off process, via the present invention.

[0045] Figs. 3(a), 3(b). 3(c), and 3(d) illustrate an exemplary EC etching direction and methods of exposing the sacrificial layer with trench etching for full wafer lift-off as shown in Fig. 3(a), Ill-nitride layer lift-off as shown in Fig. 3(b), single device lift-off as shown in Fig. 3(c), and low-damage patterns formed with dots for large-area liftoff as show n in Fig. 3(d), which can be fabricated from the top or the backside of substrates.

[0046] Fig. 4 illustrates a process flow chart of bulk Ill-nitride growth on freestanding Ill-nitride templates for substrate production followed by substrate recycling.

[0047] Fig. 5, using material stacking charts, illustrates a process of creating freestanding structures and bulk Ill-nitride layers for substrate production, via the present invention.

[0048] Fig. 6 is a schematic of the EC etching setup in the present invention.

[0049] Fig. 7 is a 2x2 pm2atomic force microscopy (AFM) image of the newly created surface after lifting off the epilayers by using the present invention with a 7.5V voltage bias applied, wherein the RMS roughness of the scanned surface is 0.534 nm.

[0050] Fig. 8 is a schematic of the substrate fabrication process, illustrating the potential method of separating a single Ill-nitride boule grown on a partially detached Ill-nitride template into multiple pieces of bulk Ill-nitride substrates by the EC etching method.

[0051] Fig. 9, using material stacking structures, illustrates a process of recycling the mask and buffer layers, along with growth substrates used in the epitaxial growth structure, via the present invention.

[0052] Figs. 10(a), 10(b), 10(c) and 10(d) describe AlGaN layers, wherein Fig. 10(a) is a microscopic image of AlGaN layers after a trench etch; Fig. 10(b) is a microscopic image after the AlGaN layers are partially detached from the substrate; and Figs. 10(c) and 10(d) are reciprocal space mappings (RSMs) of a (105) reflection of AlGaN layers strained to thick GaN layers after the trench etch (Fig. 10(c)) and the AlGaN layers fully relaxed after being detached and lifted off from the substrate (Fig. 10(d)), respectively.

[0053] Figs. 11(a) and 11(b) are scanning electron microscope (SEM) images with 250 times magnification (Fig. 11(a)) and 12k magnification (Fig. 11(b)) of a 100x100 pm device detached from the substrate after a 3-minute EC etching with a 15V bias applied.

[0054] Fig. 12(a) is an image of a testing setup of an electrically pumped UV-LED that is transferred onto a carrier substrate or submount using the present invention; and Fig. 12(b) is a graph of intensity vs. wavelength that exhibits a spectrum of the tested UV-LED.

[0055] DETAILED DESCRIPTION OF THE INVENTION

[0056] In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized, and structural changes may be made without departing from the scope of the present invention.

[0057] An Overview Of A Substrate Recycling Process

[0058] Process Flow

[0059] Fig. 1 is a process flow diagram for relatively thin epitaxial layers deposition (total epitaxial layer thickness is smaller than or equal to a single bulk substrate (around 400 microns), in which the substrate recycling process comprises the steps of: providing a growth substrate or wafer, and optionally depositing a buffer layer on the substrate (101), depositing a sacrificial layer on or above the substrate (102) before epitaxially growing Ill-nitride layers on or above the sacrificial layer (103), EC etching of the sacrificial layer (104), separating the Ill-nitride layers from the substrate (105), and finally recycling the substrate and the buffer layers (106), so that steps (102)-(106) can be repeated for future epitaxial regrowth of additional III -nitride layers.

[0060] Depositing a buffer layer in step (101 ) is optional, in case the III -nitride layers are lattice matched to the intrinsic substrate, in which buffer layers are not necessary. For example, if a 400-micron GaN layer will be grown on a bulk GaN substrate for substrate production purposes, the epitaxial growth of the Ill-nitride layer in step (103) will have the same lattice constant as the substrate, eliminating the need for buffer layers. For lattice-mismatched epitaxial growth on bulk GaN substrates, buffer layers such as a Ill-nitride layers with intermediate compositions, compositionally- graded compositions, and a superlattice structure or mask layers for lateral overgrowth can also be recycled for the next round of epi-ready regrowth. More details of the process will be discussed in the embodiments described below-.

[0061] As shown in Fig. 1. each step in this process flow reduces substrate preparation time by directly achieving the required surface quality through controlled EC etching, unlike LLO methods that require additional polishing and chemical processes.

[0062] Epitaxial Layer Design

[0063] The process flow and characteristics of the proposed method can also be interpreted from the materials stacking perspective. Schematics of the epitaxial structure before and after EC etching are shown in Fig. 2, wherein the epitaxial structure comprises a growth substrate 201, buffer layer 202, sacrificial layer 203, and Ill-nitride layers 204.

[0064] As shown in structure (i) of Fig. 2, a substrate 201 is provided and the buffer layer 202 is optionally deposited on the substrate 201.

[0065] As shown in structure (ii) of Fig. 2, the sacrificial layer 203 is deposited on the substrate 201 or above the substrate 201 on the buffer layer 202, by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or other Ill-nitride thin film deposition techniques.

[0066] It is critical that the sacrificial layer 203 has a high enough n-type carrier concentration to be selectively etched during the EC etching. More precisely, all the sacrificial layers presented herein can be comprised of a single layer or multiple layers, wherein the electron concentration should be between 1 xlO19cm'3and 1 xl021cm'?, and preferably above 1 xlO20cm'3. The high carrier concentration can be from bulk n-type doping, such as Si, Ge, and other n-type dopants, or polarization charges (e.g. 2DEG) from Ill-nitride heterostructure interface, or a combination of the above. The electron concentration can also be achieved by, but not limited to. various ion implantation techniques such as common plasma immersion, focused ion beam, molecular beam assisted, and high-energy ion implantation.

[0067] The thickness of the sacrificial layer 203 should be thick enough for its complete removal during EC etching, but thin enough to keep the surface from deteriorating from the high doping. Eleavy Si doping is known to cause surface roughening in thick films. Therefore, the sacrificial layer 203 should have a thickness below 100 nm, and preferably below 50 nm.

[0068] As shown in structure (iii) of Fig. 2, when the Ill-nitride layers 204 deposited on or above the sacrificial layer 203 are thinner than a few hundred microns, they can be removed and transferred onto a carrier substrate 205 after EC etching of the sacrificial layer 203 using an adhesion layer 206. To keep III -nitride layers 204 from being etched during the EC etching, the highest electron concentration should be one order of magnitude lower than the carrier concentration in the sacrificial layer 203.

[0069] Thereafter, recycling of the substrate 201 may be performed. It is worth mentioning that the buffer layer 202 can be grown and fabricated with extra steps such as creating a hard mask and experiencing dry7etching with layers 203 and 204, so that recycling the buffer layer 202 with the substrate 201 would simplify the material growth procedures and reduce the cost.

[0070] Exposing And EC Etching Of The Sacrificial Layer - Substrate Recycling

[0071] For device lift-off and wafer recycling purposes, after the material deposition, the sacrificial layer will be etched away during EC etching laterally to undercut the epitaxial Ill-nitride layer. Figs. 3(a), 3(b), 3(c) and 3(d) show a few designs to expose the sacrificial layer and the direction of lateral EC etching directions for each design. For the removal of the Ill-nitride layers from an entire wafer 301, the EC etching starts from the side of the wafer’s edge and proceeds towards the center of the wafer to undercut the entire nitride layer as shown in Fig. 3(a).

[0072] In another embodiment, some areas 302 can be etched away with photolithography and dry etch to expose the sacrificial layer from the sidewall of patterns 302, as shown in Fig. 3(b), so that the lateral EC etching can proceed radially from the patterns 302 until the entire sacrificial layer is etched away.

[0073] For a small area (e.g. single device) Ill-nitride layer lift-off, trenches 303 can be made around the device region 304 with photolithography and dry etch to expose the sidewall of the sacrificial layers, so that the lateral EC etching can undercut the device region 304, as shown in Fig. 3(c). It is advisable to have trenches 303 not fully enclose the device region 304, so that after the EC etching, adjacent devices are still interconnected by a joint area 305. It is to be understood that the designs shown here are not a complete list and other embodiments can be utilized without departing from the scope of the present invention.

[0074] To shorten the time for doing whole epitaxial layer liftoff while keeping most of the epilayers intact, dot patterns 306 in Fig. 3(d) can be beneficial to keep most of the thin film intact.

[0075] Samples After The Lift-off Process

[0076] After the EC etching of the sacrificial layer 203, the Ill-nitride layers 204 are separated from the growth substrate 201 and ready for transfer, as shown in structure (ii) of Fig. 2. In one embodiment, the adhesion layer 206 (e.g. polymer stamps or adhesive tapes) will be applied on top of the Ill-nitride layers 204, and used to lift-off and remove the Ill-nitride layers 204 from the growth substrate 201, and then bonded to another carrier substrate 205, as shown in structure (iii) of Fig. 2. In another embodiment, the top of the Tll-nitri de layers 204 can be bonded to another carrier substrate 205 using common semiconductor wafer bonding techniques. Depending on specific designs and applications, the wafer bonding step between the III -nitride layers 204 and the carrier substrate 205 can be before or after the EC etching step. The Ill-nitride layers 204 comprise thin-fdm optoelectronic and power devices, thin- film single crystals, and bulk Ill-nitride for substrate production. After the removal of the Ill-nitride layers 204. the bottom surface of the Ill-nitride layers 204 is exposed. More specifically, for c-plane ITI-nitride materials, the exposed bottom surface of the Ill-nitride layers 204 after the transfer will be N-polar. The collected substrate 201 with the buffer layer 202 on the top, then can be reused according to various purposes.

[0077] An Overview Of A Substrate Production Process

[0078] Fig. 1 and Fig. 2 provide a general process flow for substrate production with traditional buffer layers 202 on foreign wafers 201 and bulk III -nitride layers 204 grown on or above the sacrificial layer 203. This section will focus on the method that could potentially allow larger (4 to 6 inch diameter) and thicker (at least millimeter level) bulk Ill-nitride substrate production by employing the structure of a freestanding Ill-nitride template fabricated with the proposed EC etching method.

[0079] Process Flow

[0080] Fig. 4 shows a process flow for millimeter-level bulk substrates production. The process comprises: fabricating a buffer layer (401) on a foreign wafer which has a different lattice constant or crystal structure compared to the later grown bulk epitaxial Ill-nitride layers, depositing at least one sacrificial layer (402), depositing thin-film Ill-mtride layers that are lattice matched with the later bulk epitaxial growth (403), EC etching the sacrificial layer (404) to partially detach the thin-film Ill-nitride layers (405) from the buffer layers, regrowing bulk Ill-nitride layers to a millimeterlevel on the relaxed partially-detached thin-film Ill-nitride layers (406), fully detaching the bulk Ill-nitride layers from the substrate either by another EC etch on any remaining sacrificial layer (407), collecting the bulk Ill-nitride layers after the grow th by either EC etching away the rest of the attached sacrificial regions or mechanically separating the substrate and buffer layers from the bulk Ill-nitride layers due to the assistance from the partially-etched sacrificial layer (408), and finally recycling the substrate with the buffer layers (409), in order to repeat the process from step (402) for another next round of the millimeter-level bulk Ill-nitride layers regrowth. If the bulk Ill-nitride layers are grown on an intrinsic / lattice-matched wafer, then steps (401 ), (403), (404), (405), and the buffer layer in step (406) can be optional, depending on the threading dislocation density of the substrate provided.

[0081] Epitaxial Layer Design

[0082] To further illustrate the process flow shown in Fig. 4, Fig. 5 shows the development of epitaxial structures with the essential material properties for obtaining the bulk Ill-nitride substrates. This figure displays a common stacking of the sample prepared for performing bulk III -nitride regrowlh on the free-standing template.

[0083] As shown in structure (i) of Fig. 5, a foreign substrate 501 (such as sapphire, SiC, or GaAs) is provided and a buffer layer 502 is deposited on the substrate 501 for reducing the stress accumulation as the epilayer becomes thicker.

[0084] As shown in structure (ii) of Fig. 5, the sacrificial layer 503 with high electron carrier concentration is deposited on or above the substrate 501 and the buffer layer 502, followed by thin-film Ill-nitride layers 504 that are more lattice-matched with the layers above it (507, 508) and more lattice-mismatched with the substrate 501.

[0085] As shown in structure (iii) of Fig. 5, EC etching of the sacrificial layer 503 resulting in an EC-etched sacrificial region 505 allows the initially strained lattice mismatched Ill-nitride layers 504 to become relaxed Ill-nitride layers 506 by being partially detached from the layers 501, 502 below.

[0086] As shown in structure (iv) of Fig. 5, a second buffer layer 507 is grown on or above the partially -detached Ill-nitride layers 506. followed by thick strain-relaxed Ill-nitride layers 508, which enables the thick strain-relaxed Ill-nitride layers 508 to be grown with much less crystal stress that otherwise may lead to high degrees of wafer bowing. The second buffer layer 507 is optional but is recommended if the TDD does not reach the expected value (e.g. 1 x 105 / cm’2). As shown in structure (v) of Fig. 5, the partially-detached Ill-nitride layers 506, second buffer layer 507, and thick strain-relaxed Ill-nitride layers 508, may be removed from substrate 501 and first buffer layer 502, which allows the substrate 501 and buffer layer 502 to be recycled together.

[0087] Mask Design For EC Etching Of The Sacrificial Layer - Substrate Production

[0088] Similar to the process mentioned in the substrate recycling section, sacrificial layers are also need to be exposed in order to perform EC etching to separate the produced bulk single crystal from the growth substrate, but protecting the produced bulk III -nitride epilayers from being damaged by trench formation is critical during this process.

[0089] For substrate growth based on the presented free-standing Ill-nitride layers, bottom wafer removal is relatively easy since Ill-nitnde layers 506 are mostly detached from the lower layers. A short EC etching or a small mechanical force can be used to conveniently obtain the bulk epitaxial substrate. Ideally, the trench mask for the sacrificial layer 505 should allow most of the detached Ill-nitride layers 506 to be intact during dry etching but can not be readily removed during the later bulk crystal re-growth. This requires masks that make the etched area as small as possible to be used in this process, like those shown in Fig. 3(d).

[0090] However, for substrate production without the assistance from the voids or detached region, any type of the mask made from the top will become destructive for the bulk Ill-nitride epilayers. Therefore, Fig. 3(a) would be the most ideal solution for the whole substrate lift-off To further shorten the time for the whole epitaxial layer liftoff while keeping most of the epilayers intact, dot patterns 306 in Fig. 3(d) can also be fabricated from the backside of the substrate 201, 501, as long as the acid can access the sacrificial layers during the EC etching 104, 404 to at least partially separate buffer 202, 502 and Ill-nitride layers 204, 506. Since a few micrometer square dot size is large enough for the electrolyte of EC etching to react with the conductive sacrificial layer, the growth of the bulk single crystals will not be largely affected as the fast coalescence could happen within a few micrometers of the material grow th.

[0091] Additionally, for lifting off a III -nitride thin film and transferring / bonding it onto a foreign wafer to form a new substrate, which will be elaborated in Embodiment 5 below, the mask shown in Fig. 3(d) could be a suitable choice. The pattern either created from the top Ill-nitride layers 204 or from the bottom of the substrate 201 could w ork for such a design.

[0092] Electrochemical Etching Setup

[0093] The EC etching of the sacrificial layer is conducted by connecting a specimen 601 with a sacrificial layer to a positive terminal of an electrical DC power supply source 602 and connecting a negative electrode comprised of platinum (Pt) electrode 603 immersed in an electrolyte 604 to form a circuit, as shown in Fig. 6. The electrolyte 604 contains at least some nitric acid, oxalic acid or other acid solutions. The lateral etching speed is proportional to the current and depends on the carrier concentration of the sacrificial layer and the applied voltage. The typical DC applied voltage can range from 3V to 30V. and preferably around 10V for a carrier concentration of 1020 / cm3in the sacrificial layer.

[0094] Embodiment 1: Substrate Recycling With Sub-nm Surface Smoothness Via EC Etching

[0095] The present invention is less expensive than the current widely used LLO method and has simpler post-lift-off procedures to prepare for the regrow th on the recycled substrates. To be specific, even though dominating the lift-off of the III- nitride materials, LLO may cause potential damage to the device layer by generating new dislocations. This results in additional steps, such as gallium droplet removal, and leads to suboptimal regrowth surface conditions on recycled substrates, which could further limit its applications and introduce additional costs [7], With conventional methods, chemical mechanical polishing (CMP) or additional polishing methods are often needed to make the epitaxial surface ready for growing on the remaining substrate again. Comparatively, the present EC etching method allows both the bottom surface of the lifted-off epitaxial Ill-nitride layers and the top surface of the remaining substrate layers to be much smoother than that of the LLO. which immediately reaches the epi-ready morphology right after the lift-off.

[0096] Fig. 7 is the atomic force microscopy (AFM) image conducted on the backside of the thin film Ill-nitride device layers after transfer. The root-mean-square (RMS) roughness is only around 0.534 nm for a 2X2 pm2scan area, and almost all of the measured RMS roughness results with the same scan size on both newly created surfaces are less than 2 nm (with < 1 nm RMS for most of the scans) at appropriate EC etching voltage bias, which is 7.5V for the sample used in experiments by the inventors. Therefore, the thin-film Ill-nitride device layers are even suitable for plasma activation wafer bonding, which typically has the most strict smoothness standard, with other substrates or subsequent device processing steps. Furthermore, the remaining smooth substrate layers are straightly ready for epitaxial regrowth for substrate reuse, which requires little to no extra preparation procedures, significantly reducing the time and effort in the production line.

[0097] The present invention utilizing EC etching enables recycling not only of sapphire substrates, but also bulk GaN, SiC, and AIN substrates, that cannot be achieved with conventional liftoff methods such as LLO. The typical laser source used in LLO needs to have photon energy higher than the bandgaps of epitaxial materials but lower than that of substrate materials, which makes it impossible for epitaxially grown layers to be lifted off and for substrates with similar or smaller bandgap energy to be recycled. In contrast, the sacrificial layer in this invention can be deposited between any substrate and Ill-nitride layers as long as it can be selectively etched with a high electron carrier concentration. This approach allows for the recycling of expensive substrates such as bulk GaN or bulk AIN substrates after removing the device layers grown on them, thereby significantly reducing the costs of devices grown on such substrates. Additionally, the insertion of such sacrificial layers does not degrade the cry stal quality7or the device grown above the sacrificial layers. Highly efficient LEDs were grown directly on the sacrificial layer and have comparable performance compared with reference LEDs grown without the sacrificial layers.

[0098] Embodiment 2: Free-standing Substrate Production With Reduced Stress And Wafer Bowing Via EC Etching

[0099] This embodiment comprises a design of a general epitaxial structure for producing bulk Ill-nitride substrates as show n in Fig. 5. To relieve the stress and mitigate the wafer bowing issue, an MOCVD-grown free-standing template 506 can be fabricated by performing EC etching on a sacrificial layer 503 to form EC etched sacrificial region 505. Then, a buffer layer 507 for reducing the TDD and bulk III- nitride layers 508 are deposited by HVPE on or above the 111-nitride layers 506 as shown in structure (iv) of Fig. 5. The material stacking of this design is illustrated in the “Epitaxial Layer Design” subsection of the “An Overview of A Substrate Production Process” section set forth above, and details about the template 506 formation of this structure are elaborated in co-pending and commonly-assigned P.C.T. International Patent Application Serial No. PCT / US25 / 53692, filed on November 3, 2025, by Yifan Yao, Hanyu Bi, Michael Iza, Shuji Nakamura and Steven P. DenBaars, entitled “METHOD TO FABRICATE STRAIN-RELAXED III- NITRIDE MATERIALS WITH AN ELECTROCHEMICAL ETCH,” docket number G&C 30794.0863WOU1 (UC 2025-351-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly -as signed U.S. Provisional Patent Application Serial No. 63 / 715,058, filed on November 1, 2024, by Yifan Yao, Hanyu Bi, Michael Iza, Shuji Nakamura and Steven P. DenBaars. entitled “METHOD TO FABRICATE STRAIN-RELAXED III-NITRIDE MATERIALS WITH AN ELECTROCHEMICAL ETCH,” docket number G&C 30794.0863USP1 (UC-2025-351-1), both of which are cross-referenced above and incorporated by reference herein. In contrast to existing methods, such as VAS and EC porosification, the present invention achieves superior substrate relaxation and defect minimization by utilizing a sacrificial layer with a precisely controlled electron carrier concentration, allowing for complete detachment of the targeted Ill-nitride layers 506. Traditional VAS and EC porosification methods rely on voids or porosification, which can introduce structural irregularities and incomplete relaxation due to partial detachment of the epitaxial layers. The approach of the present invention, however, allows for full, targeted detachment at the sacrificial layer, minimizing stress accumulation and wafer bowing while preserving crystal integrity, which could further allow a thicker single-crystal growth with controlled bowing and off-angle distribution. Furthermore, unlike the TiN layer used in the VAS method, Ill-nitride layers 506 do not have lattice mismatches with the bulk Ill-nitride layers 508, which makes the later buffer structures growth (such as ELOG) become optional; in other words, the present method allow s a lower TDD bulk GaN to be obtained in an more efficient way with significant cost reduction.

[0100] Embodiment 3: Bulk Substrate Boule Separating Into Wafers Via EC Etching Fig. 8 is a schematic that illustrates the material stacking structures of the design for separating the grown single crystal boule into pieces with controlled thickness for substrate production, wherein structure (i) of Fig. 8 includes substrate 801, first buffer layer 802, EC etched sacrificial region 803. partially-detached relaxed Ill-nitride layers 804, optional second buffer layer 805, strain-relaxed bulk Ill-nitride layers 806, and sacrificial layer 807, wherein second buffer layer 805, strain-relaxed bulk Ill-nitride layers 806, and sacrificial layer 807, may be repeated n times (x) as a unit.

[0101] Similar to the growth method presented in Embodiment 2. the free-standing template 804 is fabricated after the EC etching of the sacrificial layer 803 grow n on the buffer layers 802, and then an optional second buffer layer 805 can be grown to reduce the TDD (not necessary if cry stal quality has already met the target standard), which is followed by the epitaxial growth of the bulk Ill-nitride layers 806 and a new sacrificial layer 807 on or above the partially-detached relaxed Ill-nitride layers 804. Multiple substrates 801 would be obtained by looping the process of depositing layers from 805 to 807, and EC etching away all the sacrificial layers 803. 807 in the sample, as shown in structure (ii) of Fig. 8. During the deposition of such a loop, various material deposition mechanisms can be adopted as long as the electron concentration in the sacrificial layer 803, 807 is sufficient for the newly exposed surface to meet the roughness standard. Preferably, MOCVD can be used for sacrificial layer 807 deposition and HVPE for growing bulk Ill-nitride layers 806. Eventually, as produced substrates, multiple pieces of crystals containing 805 and 806 are separated and polished simultaneously by the EC etching process.

[0102] This approach has the potential to simplify or eliminate the slicing and polishing processes typically required in conventional substrate production. Specifically, traditional wire saws used for slicing boules employ diamond wires with diameters in the range of hundreds of micrometers, resulting in the loss of at least 20% of the crystal boule when the target substrate thickness is approximately 0.5 mm. Following slicing, an additional chemical mechanical polishing (CMP) step is necessary to remove surface irregularities, a process that is both time-intensive and costly. In contrast, the proposed substrate separation method sacrifices less than 0.0002% of the crystal boule and can achieve sub-nanometer surface smoothness through EC etching, potentially eliminating the need for CMP. Furthermore, the proposed method is significantly less expensive and easier to operate than conventional wire saws and CMP equipment.

[0103] Embodiment 4: Substrate Recycling With Mask Materials Or Buffer Layers Via EC Etching

[0104] Fig. 9 is a schematic that illustrates the material stacking structures of the design for substrate recycling with mask materials or buffer layers via EC etching, which includes substrate 901, first (optional) buffer or nucleation layer 902, mask layer 903, second (optional) buffer layer 904, sacrificial layer 905, and Ill-nitride layers or devices 906. This embodiment focuses on the mask layer 903 or buffer layers 902, 904 that can be recycled using the present invention along with the substrate 901.

[0105] As shown in structure (i) of Fig. 9, a substrate 901 is provided and the first buffer or nucleation layer 902 is optionally deposited on the substrate 901, followed by the mask layer 903, and the second (optional) buffer layer 904.

[0106] As shown in structure (ii) of Fig. 9, to achieve low dislocation density or strain relaxation, ELOG techniques were often used during the growth in which a layer 903 of mask materials patterned by photolithography was often deposited, before depositing the sacrificial layer 905 and the epitaxial growth of the Ill-nitride layers 906. The layer 903 of mask materials can contain at least some TiN, SiN, SiO2. etc.

[0107] As shown in structure (iii) of Fig. 9, by depositing a sacrificial layer 905 on or above the mask layer 903 and removing the Ill-nitride layers 906 above the sacrificial layer 905 by EC etching as described in the previous embodiment, the substrate 901 as well as the mask layer 903 can be readily used in the next growth on the recycled substrate 901.

[0108] Moreover, the present invention can also be used to recycle buffer layers 902, 904. For example, when growing thin films on lattice-mismatched substrates, superlattice or other types of buffer layers were often grown on the substrate first for strain relaxation (Fig. 2); as for the bulk GaN layer grown on foreign substrates such as sapphire, a buffer layer containing nano-voids was often created [1] [3] [4] [5] to relieve the growth stress and reduce the wafer-bowing effect for thick substrate growth. Similarly, by depositing a sacrificial layer on or above the buffer layers (such as 202, 502, 802, 805, 902. and 904) and removing the materials above the sacrificial layer by EC etching, the substrate as well as the buffer materials can be readily used in the next growth. The sacrificial layer that was lattice matched to this invention is advantageous in high-volume production because it eliminates the need to fabricate the mask or buffer materials repeatedly, where the process of depositing and fabricating the mask or buffer materials can be lengthy and costly. However, such a re-utilization of the masks or buffer layers is ty pically too hard or complicated to be achieved by conventional LLO or PEC methods due to their limitations mentioned in the previous sections.

[0109] Embodiment 5: Strain relaxed Ill-ni tride Template On An Arbitrary Substrate Via EC Etching And Wafer Bonding

[0110] This embodiment comprises an application of using the presented EC etching to lift off thin-film Ill-nitride epitaxial layers (such as 204 and 906) and wafer bonding these fully relaxed layers to foreign wafers for later re-growth or processing on the newly formed substrates that have been shown by layers 204-206 in structure (iii) of Fig. 2 or layers 906-908 in structure (iii) of Fig. 9. These fully relaxed singlecrystal layers may be comprised of AlxInyGazN, where x+y+z=l. Depending on the transfer or bonding methods used, the adhesion layer (206, 907) could be optional. A complete process of new substrate creation contains EC etching aw ay selected regions of sacrificial layers to partially detach most of the epitaxial layers and allow them to be relaxed, bonding a foreign wafer onto the substrate with the partially detached thin film layer, and separating the original substrate from the foreign wafer with bonded thin film by either doing the EC etching again to utterly remove the sacrificial layers or mechanically separate them as most part of the thin film has already been detached from the old substrate.

[0111] The methods of wafer bonding include direct or fusion bonding with no intermediate layer, thermocompression bonding with metal layers, hybrid bonding with exposed metal connections from both wafers to be bonded, metal diffusion with metallic bonds formation (such as Au-Au, In-In. and Al-Al bonding), plasma- activated surface bonding with no assistance from metals, and eutectic wafer bonding with metal layers to create eutectic compositions which can be formed below the melting point of the substrate. Generally, the low-temperature bonding process may lead to a higher risk of debonding if the following regrowth or processing temperatures are sufficiently high; therefore, the non-metal-assisted bonding techniques could be more beneficial for regrowth purposes afterward because those bonding processes could sustain relatively higher temperatures without limits on the melting points of metals (e.g. indium). As for device fabrication purposes, the wafer bonding process could adopt any suitable method mentioned above as long as the highest temperature used during fabrication is sufficiently lower than the bonding temperature.

[0112] As indicated by the microscopic images in Fig. 10(a) and 10(b), the crystal quality of an ultraviolet (UV) LED thin film was successfully obtained without creating any observable V-shape defects during the EC etching. Similarly, Figs. 11(a) and 11(b) show a whole 100X100 pm2UV-LED device layer being lifted off from the substrate with a smooth etching interface by the proposed method, which also embodies the preserved crystal quality of both device layers and the substrate. Moreover, Fig. 12(a) shows a testing setup of an electrically-pumped 100X100 pm2UV-LED that is transferred onto a earner substrate or submount using the present invention; and Fig. 12(b) exhibits a spectrum of the tested UV-LED, after being lifted off from the substrate shown in Fig. 10(b), which further implies the crystal quality7was preserved during the EC etching. In other words, the transferred and bonded thin film would not experience severe degradation of crystal quality. Furthermore, reciprocal space mappings (RSMs) of an AlGaN / GaN (105) peak reflection on the UV-LED epilayer before (Fig. 10(a)) and after (Fig. 10(b)) lifting off via the proposed EC etching method and then transferring onto a carrier wafer are shown in Figs. 10(c) and 10(d), respectively. Unlike the strained AlGaN layers, the transferred AlGaN- based LEDs are fully relaxed.

[0113] These thin film properties mean that, if the composition of the thin film to be bonded was tuned to a similar or the same as that of the regrowth layers, the substrate that consists of a carrier wafer and the composition-customizable relaxed thin-film epilayers bonded on the top would allow less to zero lattice-mismatch or materials stress to happen on the regrown epitaxial layers. In this w ay. the newly formed substrate would have more flexibility' in the critical thickness of growing lattice- mismatched materials and an expanded percentage for Ill-nitride materials composition designs in the epitaxial layers. For instance, AlGaN layers will have a lower refractive index if Al composition is higher, which can be applied to some of the visible or UV-range laser diode waveguide or cladding layers designed for optical mode confinement. However, because of the lattice mismatch between the InGaN, AlGaN, and GaN involved in the laser structure, the thickness of AlGaN, Al composition, and optical confinement factor are always kept low if none of the strainrelaxation methods were used. By employing the presented EC etching method in the production of substrate topped with a relaxed AlGaN thin film that has a lattice- matched Al composition with the desired AlGaN waveguide or cladding layer, then a thicker AlGaN layer can be grown without cracking, which will lead to better optical confinement of the laser structures.

[0114] A Brief Summary Of Advantages

[0115] The substrate market for the III-N material system has been expanding for decades across optoelectronic and power electronics for both research and industry. The present invention discloses methods to produce high-quality Ill-nitride substrate and to recycle Ill-nitride substrates for direct regrow th. There is a strong desire to develop on this invention because of the folloyving key advantages.

[0116] For substrate recycling:

[0117] (1) Reducing cost by recycling arbitrary high-cost substrates as well as buffer or mask materials for device fabrication, making the technology' more economical.

[0118] (2) Producing a smooth, epi-ready substrate surface, suitable for direct regrowth without additional polishing steps after liftoff and further reducing processing costs,

[0119] For substrate production: (1) Improving the crystal quality by minimizing the wafer bowing and off- angle distribution, allowing for thicker, high-quality' substrates to be produced, which is superior than the conventional free-standing substrate growth assisted by LLO. porous structure, and VAS.

[0120] (2) Minimizing the material loss in the wafer slicing (conventionally accomplished by wire saw equipment) and eliminating the polishing process (conventionally accomplished by CMP), further saving time and costs.

[0121] (3) Allowing fully relaxed Ill-nitride materials to be bonded onto foreign substrates for heterogeneous integration and creating pseudo Ill-nitride substrates on other material platforms with the epi-ready surface morphology7that could be achieved by the conventional lift-off methods.

[0122] References

[0123] The following publications are incorporated by reference herein:

[0124] [1] Sumitomo Chemical Technical Report, 5, 1-20 (2018).

[0125] [2] Proc. IEEE, 98, 1230-1246 (2010).

[0126] [3] Jpn. J. Appl. Phys. 57, 065502 (2018).

[0127] [4] Jpn. J. Appl. Phys. 42, LI (2003).

[0128] [5] Appl. Phys. Express 17 055502 (2024).

[0129] [6] Appl. Phys. Lett. 72, 599-601 (1998).

[0130] [7] Appl. Phys. Lett. 90, 251110 (2007).

[0131] [8] Appl. Phys. Lett. 100, 181908 (2012).

[0132] [9] Nano Lett. 14, 8, 4293-4298 (2014).

[0133]

[0010] J. Phys. D: Appl. Phys. 57 105105 (2024).

[0134] Conclusion

[0135] This concludes the description of the preferred embodiment of the present invention. The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

WHAT IS CLAIMED IS:

1. A method for fabricating Ill-nitride layers, comprising: epitaxially growing Ill-nitride layers including a sacrificial layer on or above a substrate, wherein the sacrificial layer has an electron carrier concentration between l *1019cm'3and l xl021cm'3; exposing a portion of the sacrificial layer to an electrolyte for an electrochemical etching; using electrochemical etching to etch away the sacrificial layer to detach the Ill-nitride layers from the substrate, so that the substrate is a recycled substrate; and epitaxially growing additional Ill-nitride layers on the recycled substrate.

2. The method of claim 1, wherein a total thickness of the detached III- nitride layers is more than 50 nanometers.

3. The method of claim 1, wherein a total thickness of the detached III- nitride layers is more than 10 microns.

4. The method of claim 1, wherein a total thickness of the detached III- nitride layers is more than 100 microns.

5. The method of claim 1, wherein a layer of mask material and / or a buffer layer structure are deposited on and / or above the substrate.

6. The method of claim 5, wherein the mask material contains at least some SiO2. SiN, TiN, or other mask material.

7. The method of claim 5, wherein the buffer layer structure contains voids or epitaxially lateral overgrowth structures.

8. The method of claim 5, wherein the substrate including the mask material and the buffer layer structure remains intact after the Ill-nitride layers are detached, thereby allowing the substrate including the mask material and / or the buffer layer to be recycled for subsequently growing additional Ill-nitride layers.

9. The method of claim 1, wherein the III -nitride layers are grown by hydride vapor phase epitaxy (HVPE).

10. The method of claim 1, wherein the sacrificial layer can be grown by hydride vapor phase epitaxy (HVPE), metal organic vapor phase epitaxy (MOVPE), or another thin film Ill-nitride deposition techniques.

11. The method of claim 1, wherein the sacrificial layer is a single layer or multiple layers that are comprised of at least two periods of alternating layers of AlxInyGai-x-yN and AlaInbGai-a-bN, where 0<x<l, 0<y<l, and 0<a<l, 0<b<l, and y b.

12. The method of claim 1, wherein at least one layer of the Ill-nitride layer structure has a formula of GanAlxN where 0<n<l, 0<x< 1, and n+x=l.

13. The method of claim 1, wherein at least one layer of the device structure has a formula of GanlmN where: 0<n<l, 0<x<l, and n+x=l.

14. The method of claim 1, wherein the detached Ill-nitride layers contain GaN, InGaN, AlGaN and / or AHnGaN.

15. The method of claim 1 , wherein the detached IIT-nitride layers are used as a substrate for a device such as a light emitting diode (LED), a laser diode (LD), apower electronic devices, a radio frequency (RF) device, or other optoelectronic device.

16. The method of claim 1. wherein the sacrificial layer has an electron carrier concentration of more than l x 1019cm-3.

17. A method for fabricating Ill-nitride layers, comprising: epitaxially growing first Ill-nitride layers including a sacrificial layer on or above a substrate, wherein the sacrificial layer has an electron carrier concentration between I xlO19cm’3and l x lO21cm'J; exposing a portion of the sacrificial layer to an electrolyte for electrochemical etching; using the electrochemical etching to partially etch away the sacrificial layer so that a portion of the first Ill-nitride layers are partially-relaxed Ill-nitride layers that are at least 20% biaxially relaxed; epitaxially depositing second Ill-nitride layers on or above the partially relaxed Ill-nitride layers; detaching the first and second Ill-nitride layers from the substrate, so that the substrate is a recycled substrate; and epitaxially growing additional III -nitride layers on the recycled substrate.

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