Sub-sampling duty cycle corrector and clock generator
The subsampling duty cycle corrector addresses the challenge of high-frequency duty cycle adjustment by detecting voltage through a subsampling process, ensuring precise edge alignment and low jitter in clock signals.
WO2026121465A1 Publication Date: 2026-06-11KUMOH NAT INST OF TECH IND ACADEMIC COOPERATION FOUND
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Patent Information
- Application Number
- PCT/KR2025/012316
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-12-06
- Filing Date
- 2025-08-13
- Publication Date
- 2026-06-11
AI Technical Summary
Technical Problem
Conventional duty cycle correctors struggle to achieve high precision in adjusting duty cycle when the frequency of the clock signal is high, leading to misalignment of rising and falling edges in clock signals.
Method used
A subsampling duty cycle corrector that detects duty cycle information as voltage through a subsampling process, utilizing an inverter, pulse generation unit, frequency tracking & rising edge alignment unit, and falling edge alignment unit to generate phase-corrected output signals.
Benefits of technology
Secures high precision and low jitter characteristics by precisely adjusting the duty cycle, aligning edges, and reducing phase noise in clock signals.
✦ Generated by Eureka AI based on patent content.
Abstract
Proposed are a sub-sampling duty cycle corrector and a clock generator capable of securing high precision low-jitter characteristics by detecting duty cycle information as a voltage through a sub-sampling process and processing the duty cycle information. The sub-sampling duty cycle corrector generates an output signal by correcting the phase of an input signal, and comprises an inverter, a pulse generation unit, a frequency tracking and rising edge alignment unit, and a falling edge alignment unit.
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