A frequency mixer arrangement

Abstract

A frequency mixer arrangement (300, 400, 500, 600) for receiving a first input signal (LOin) and a second input signal (IFin; RFin), for mixing the first and the second input signals to provide a frequency mixed signal (RFout; IFout), and for providing the frequency mixed signal as an output signal. The frequency mixer arrangement (300, 400, 500, 600) comprises: a first transistor (210), wherein the first transistor (210) is configured to receive the first and the second input signals at a control terminal (211) of the first transistor (210) and to mix the first and the second input signals to provide the frequency mixed signal from a current-sourcing terminal (213) of the first transistor (210), and wherein the first transistor (210) is configured to receive a first bias voltage (Vb1) at the control terminal (211) of the first transistor (210) and to receive a first supply voltage (Vcc1) at a current-collecting terminal (212) of the first transistor (210); and a diode (250), wherein an anode (251) of the diode (250) is galvanically connected to the current-sourcing terminal (213) of the first transistor (210) and a cathode (252) of the diode (250) is galvanically connected to ground, wherein the frequency mixer arrangement (300, 400, 500, 600) further comprises an inductive component (380) connected in series between the anode (251) of the diode (250) and the current-sourcing terminal (213) of the first transistor (210).

Description

[0001] A FREQUENCY MIXER ARRANGEMENT

[0002] TECHNICAL FIELD

[0003] The present disclosure relates generally to the field of wireless communications. More particularly, it relates to a frequency mixer arrangement for receiving a first input signal and a second input signal, for mixing the first and the second input signals to provide a frequency mixed signal, and for providing the frequency mixed signal as an output signal. The present disclosure also relates to an apparatus, for a wireless communications network, comprising said frequency mixer arrangement.

[0004] BACKGROUND

[0005] An up-conversion mixer converts an incoming intermediate frequency (IF) signal into a radio frequency (RF) signal by frequency mixing the IF signal with a local oscillator (LO) signal. Similarly, a modulator (which may also be called an up-conversion mixer) converts an incoming baseband (BB) signal into an RF signal by mixing the BB signal with an LO signal.

[0006] A down-conversion mixer converts an incoming RF signal into an IF signal by frequency mixing the RF signal with an LO signal. Similarly, a de-modulator (which may also be called a down-conversion mixer) converts an incoming RF signal into a BB signal by mixing the RF signal with an LO signal.

[0007] For frequencies beyond 100 GHz (sub-terahertz), a mixer (which may be called a power mixer) delivering a large RF output power is desired. However, the output power is limited by available power from semiconductor solid- state devices. High output power may be desired for lower frequencies as well, and for down-conversion mixers (where the output power is of the IF signal or BB signal).

[0008] A. Bilato et al. discloses a Gilbert mixer merged with a power amplifier in "SiGe BiCMOS D-Band Heterodyne Power Mixer with Back-Off Efficiency Enhanced by Current Clamping," in IEEE Solid-State Circuits Letters, vol. 7, pp. 2-5, 2024. The mixer of said document utilizes cascoded transistors to increase the RF output power. However, the cascoded transistors have an amplification function only and no function of re-mixing, due to a cancellation LO and IF signals at the source / emitter of the differential cascoded transistors.

[0009] Besides the Gilbert-type mixer, the transconductance mixer type is a promising candidate for high-frequency (e.g., above 100 GHz) mixers providing high power. In some transconductance up-conversion mixers, the LO signal and the IF signal are applied at the transistor's base / gate, and the RF signal is obtained at the transistor's collector / drain. Since the LO signal is applied at the base / gate, this kind of mixer may be called a base / gate pumped mixer. M. Bao et al. discloses a single-ended up-conversion mixer comprising an individual transconductance mixer in "A 31 ~61 GHz linear transconductance up-conversion mixer with 15 GHz IF-bandwidth," 2013 IEEE MTT-S International Microwave Symposium Digest (MTT), Seattle, WA, USA, 2013, pp. 1-3.

[0010] Y. Li et al. discloses a single-ended up-conversion mixer comprising a transconductance mixer and cascaded amplification / re-mixing stage in "A High Conversion Gain 210-GHz InP DHBT Sub-Harmonic Mixer Using Gain- Enhanced Structure," in IEEE Access, vol. 7, pp. 101453-101458, 2019. Said document utilizes subharmonic mixing, where the single tone input has a frequency that is half an intended LO signal frequency (i.e. , said single tone has a frequency of fLo / 2). Furthermore, a cascaded common emitter configured transistor amplifies the RF signal at frequency of (fRF=f o±fiF). Simultaneously, the signal at frequency of fRF=fLo / 2±fiF and the leakage of the input signal at frequency of fFo / 2 are re-mixed by the cascaded transistor to increase RF output power / conversion gain.

[0011] To improve conversion gain, lower LO power, and lower the direct current (DC) power consumption, a transconductance mixer based on a Darlington-cell may be implemented. K. -C. Lin et al. discloses an example of a Darlington-cell-based mixer in "A 4.2-mW 6-dB Gain 5-65-GHz Gate-Pumped Down-Conversion Mixer Using Darlington Cell for 60-GHz CMOS Receiver," in IEEE Transactions on Microwave Theory and Techniques, vol.

[0012] 61 , no. 4, pp. 1516-1522, April 2013. In said document, a diode (implemented as a diode-connected transistor) is connected to the emitter / source of a first transistor and the base / gate of a second transistor, where the first and second transistors are connected in a Darlington configuration.

[0013] W. -C. Wang et al. discloses a Darlington-type transconductance mixer with an extend RF bandwidth and lower requirements of LO input power in "A 25-to-70 GHz and low LO power mixer using modified SiGe NMOS-HBT Darlington cell for Gigabit BPSK demodulation," 2013 IEEE MTT-S International Microwave Symposium Digest (MTT), Seattle, WA, USA, 2013, pp. 1-3. In said document, a diode (implemented as a diode-connected transistor) is connected to the emitter / source of a first transistor and the base / gate of a second transistor. The first transistor is arranged in a common collector / source configuration and the second transistor is connected in a common emitter / drain configuration, which may be called a modified Darlington configuration.

[0014] While the published documents mentioned above provide some improvements in terms of output power and conversions gains at high frequency applications (e.g., above 100 GHz), further improvements are still desired. Thus, there is a need for improved frequency mixers for up-conversion and / or down-conversion, particularly for high-frequency applications (such as, e.g., above 100 GHz).

[0015] SUMMARY

[0016] It is an object of the present disclosure to mitigate, alleviate or eliminate one or more of the above-identified deficiencies and disadvantages in the prior art and solve at least the above-mentioned problem. In particular, an object is to provide improved frequency mixer arrangements, particularly for high-frequency applications (such as, e.g., above 100 GHz). This object is attained at least in part by a frequency mixer arrangement for receiving a first input signal and a second input signal, for mixing the first and the second input signals to provide a frequency mixed signal, and for providing the frequency mixed signal as an output signal. The frequency mixer arrangement comprises a first transistor. The first transistor is configured to receive the first and the second input signals at a control terminal of the first transistor and to mix the first and the second input signals to provide the frequency mixed signal from a current-sourcing terminal of the first transistor. The first transistor is configured to receive a first bias voltage at the control terminal of the first transistor and to receive a first supply voltage at a currentcollecting terminal of the first transistor. The frequency mixer arrangement also comprises a diode. An anode of the diode is galvanically connected to the current-sourcing terminal of the first transistor and a cathode of the diode is galvanically connected to ground. The frequency mixer arrangement further comprises an inductive component connected in series between the anode of the diode and the current-sourcing terminal of the first transistor.

[0017] The inductive component improves performance of the frequency mixer arrangement, such as increased conversion gain, higher output power (of the frequency mixed signal), and reduced DC power. The frequency mixer arrangement may be considered as having two cascaded mixing stages, where the first transistor constitutes the first stage, and the diode constitutes the second stage. Without the inductive component, there may be significant leakage of the frequency mixed signal into ground. Such leakage is undesired since it lowers the output power of the frequency mixed signal. Furthermore, in some cases, it may be desired that the first transistor outputs parts of the first and the second input signals at the current-sourcing terminal of the first transistor (e.g., for re-mixing purposes). Without the inductive component, there may be significant leakage of the parts of the first and the second input signals. The leakage due to the diode may be mitigated by using a small diode relative to the size of the first transistor. However, a smaller diode reduces the mixing contribution of the diode, and thus reduces the conversion gain and output power of the frequency mixer arrangement. The inductive component enables using a larger diode compared to the case without the inductive component. A larger diode is advantageous since that increases the mixing contribution of the diode, and thus increases the conversion gain and output power of the frequency mixer arrangement.

[0018] Furthermore, the inductive component increases the power of the parts of the first and the second input signal at the current-sourcing terminal of the first transistor, which is an advantage when further transistor stages are cascaded with the first transistor and the diode. This increases the performance (such as conversion gain) of the whole cascaded arrangement.

[0019] In some embodiments, the first transistor is a first bipolar junction transistor (BJT), where a base terminal of the first BJT is the control terminal of the first transistor, a collector terminal of the first BJT is the current-collecting terminal of the first transistor, and an emitter terminal of the first BJT is the current-sourcing terminal of the first transistor.

[0020] In some embodiments, the first transistor is a first field effect transistor (FET), where a gate terminal of the first FET is the control terminal of the first transistor, a drain terminal of the first FET is the current-collecting terminal of the first transistor, and a source terminal of the first FET is the current-sourcing terminal of the first transistor. In some embodiments, the first input signal comprises a fundamental tone.

[0021] In some embodiments, the frequency mixer arrangement is an up-conversion frequency mixer arrangement. In that case, the first input signal may be a local oscillator (LO) signal or a frequency divided LO signal. If, e.g., the up-conversion frequency mixer arrangement utilizes sub-harmonic mixing, the first input signal may be the frequency divided LO signal, which comprises a fraction of a desired harmonic. Furthermore, in these cases, the second input signal may be an intermediate frequency (IF) signal or a baseband (BB) signal. Also, the output signal may be a radio frequency (RF) signal. When the second input signal a BB signal, the up-conversion frequency mixer arrangement may also be called a modulator arrangement. In some embodiments, the frequency of the RF signal of the up-conversion frequency mixer arrangement is at least 100 GHz.

[0022] In some embodiments, the frequency mixer arrangement is a down-conversion frequency mixer arrangement. In that case, the first input signal may be an LO signal or a frequency divided LO signal, the second input signal may be an RF signal, and the output signal may be an IF signal or a BB signal. When the second input signal is a BB signal, the down-conversion frequency mixer arrangement may also be called a de-modulator arrangement. In some embodiments, the frequency of the RF signal of the down-conversion frequency mixer arrangement is at least 100 GHz.

[0023] In some embodiments, the inductive component comprises a transmission line. A transmission line is easy to implement on a planar substrate.

[0024] In some embodiments, the transmission line has an electrical length of at least A / 16, and preferably at least A / 12, where A is the wavelength of the fundamental tone or of a higher harmonic of the fundamental tone. These values have shown to be suitable for improving performance of the frequency mixer arrangement.

[0025] In some embodiments, the transmission line has an electrical length of at most A / 6, and preferably at most A / 8, where A is the wavelength of the fundamental tone or of a higher harmonic of the fundamental tone. These values have shown to be suitable for improving performance of the frequency mixer arrangement.

[0026] In some embodiments, frequency mixer arrangement is configured to receive the fundamental tone with a frequency in a span of different frequencies. Furthermore, the inductive component is configured to present an inductive reactance for each frequency in the span of different frequencies or in a span of different harmonic frequencies of the fundamental tone. In this way, inductive component enables improved performance of the frequency mixer arrangement across a large bandwidth.

[0027] In some embodiments, the inductive reactance for each frequency in the span of different frequencies is between 18 and 35 Ohm. These values have shown to be suitable for improving performance of the frequency mixer arrangement. Other values are also possible.

[0028] In some embodiments, the frequency mixer arrangement comprises a first resistive component. A first terminal of the first resistive component is galvanically connected to ground and a second terminal of the first resistive component is galvanically connected to the current-sourcing terminal of the first transistor. The first resistive component may, e.g., comprises a resistor. The second terminal of the first resistive component may directly be connected to the anode of the diode (which forms a galvanic connection to the current-sourcing terminal of the first transistor via the inductive component). Alternatively, the second terminal of the first resistive component may directly be connected to the current-sourcing terminal of the first transistor. A direct connection to the anode has shown to provide better performance of the frequency mixer arrangement compared to a direct connection to the current-sourcing terminal of the first transistor.

[0029] The first resistive component may improve linearity of the frequency mixer arrangement. For example, the 1-dB compression point of the output power may be increased, which is an advantage. Furthermore, the resistive value of the first resistive component may be selected to achieve a particular characteristic of the conversion gain of the frequency mixer arrangement. In some cases, it may be desired that the gain characteristics is linear. In other cases, it may be desired that the gain characteristics presents a gain expansion, which may, e.g., be used to compensate gain compression of other non-linear components cascaded with the frequency mixer arrangement, such as, e.g., a power amplifier.

[0030] It should be noted that, for an up-conversion mixer, the 1-dB compression point of the output power is a normally an important parameter, especially at sub-terahertz, where the power of the frequency mixed signal is limited by the devices' performance.

[0031] In some embodiments, the first resistive component is configured to present a resistance in the range of 80 to 1200 Ohm. These values have shown to be suitable for improving performance of the frequency mixer arrangement. Other values are also possible.

[0032] In some embodiments, the diode is based on a third BJT or a third FET.

[0033] In some embodiments, a size of the diode is at least 0.5 times the size of the first transistor, preferable equal or larger than the size of the first transistor, and more preferably at least 2.5 times the size of the first transistor. These values have shown to be suitable for improving performance of the frequency mixer arrangement. Other values are also possible.

[0034] In some embodiments, the frequency mixer arrangement comprises a first bias feed network for receiving the first bias voltage and for providing the first bias voltage to the first transistor, and a first supply feed network for receiving the first supply voltage and for providing the first supply voltage to the first transistor.

[0035] In some embodiments, the frequency mixer arrangement comprises a second transistor. A control terminal of the second transistor is galvanically connected to the current-sourcing terminal of the first transistor. The second transistor is configured to mix signals received at the control terminal of the second transistor to provide the frequency mixed signal from a current-collecting terminal of the second transistor. The second transistor is configured to receive a second supply voltage at the current-collecting terminal of the second transistor. A current-sourcing terminal of the second transistor is galvanically connected to ground. The inductive component improves performance of the frequency mixer arrangement (including the first and the second transistors), such as increased conversion gain, higher output power (of the frequency mixed signal), and reduced DC power. The frequency mixer arrangement may be considered as having three cascaded mixing stages, where the first transistor constitutes the first stage, the diode constitutes the second stage, and the second transistor constitutes the third mixing stage. The inductive component enables using a larger diode compared to the case without the inductive component. A larger diode is advantageous since that increases the mixing contribution of the diode, and thus increases the conversion gain and output power of the frequency mixer arrangement.

[0036] In embodiments including the first resistive component, the first resistive component may improve linearity of the frequency mixer arrangement. For example, the 1-dB compression point of the output power may be increased, which is an advantage. Furthermore, the resistive value of the first resistive component may be selected to achieve a particular characteristic of the conversion gain of the frequency mixer arrangement. In some cases, it may be desired that the gain characteristics is linear. In other cases, it may be desired that the gain characteristics presents a gain expansion, which may, e.g., be used to compensate gain compression of other non-linear components, like a power amplifier, cascaded with the frequency mixer arrangement.

[0037] The gain characteristics of the frequency mixer arrangement can be selectively controlled by the particular resistive value of the first resistive component. In addition, the gain characteristics of the frequency mixer arrangement can be selectively controlled by the particular power level of the first input signal. Thus, the disclosed frequency mixer arrangement presents an increased control of the gain characteristics (e.g., in terms of gain compression or gain expansion). In some embodiments, the resistive value of the first resistive component can be selected as fixed value, and the power of the first input signal can be controlled during operation (e.g., to control gain characteristics and compensate for temperature and process variations). Alternatively, power of the first input signal can be fixed, and the resistive value could be controlled during operation. This type of control may, e.g., be implemented by an automatic control system.

[0038] In some embodiments, a current mirror may be used to provide the bias voltage to the first transistor. In this way, the sensitivity of gain characteristics of the frequency mixer arrangement with respect to the ratio of power of the first input signal over the resistive value is decreased.

[0039] In some embodiments the second transistor is a second BJT, where a base terminal of the second BJT is the control terminal of the second transistor, a collector terminal of the second BJT is the current-collecting terminal of the second transistor, and an emitter terminal of the second BJT is the current-sourcing terminal of the second transistor.

[0040] In some embodiments, the second transistor is a second FET, where a gate terminal of the second FET is the control terminal of the second transistor, a drain terminal of the second FET is the current-collecting terminal of the second transistor, and a source terminal of the second FET is the current-sourcing terminal of the second transistor. In some embodiments, a size of the second transistor is at least 0.3 times the size of the first transistor, preferable at least 0.4 times the size of the first transistor, and more preferably at least 0.6 times the size of the first transistor. These values have shown to be suitable for improving performance of the frequency mixer arrangement.

[0041] In some embodiments, the first transistor is configured to provide respective parts of the first and the second input signals from the current-sourcing terminal of the first transistor. Furthermore, the second transistor is configured to mix the respective parts to provide the frequency mixed signal from the current-collecting terminal of the second transistor. In this way, the diode and the second transistor will re-mix the signals, which increases the overall conversion gain of the frequency mixer arrangement. Furthermore, in some embodiments, the second transistor is configured to amplify the frequency mixed signal provided from the current-sourcing terminal of the first transistor.

[0042] In some embodiments, the frequency mixer arrangement comprises a second supply feed network for receiving the second supply voltage and for providing the second supply voltage to the second transistor.

[0043] In some embodiments, the frequency mixer arrangement is configured such that a second bias voltage is provided to the control terminal of the second transistor via the current-sourcing terminal of the first transistor. Such DC coupling improves the performance of the frequency mixer arrangement compared to when using a separate bias feed for the second transistor. With a separate bias feed for the second transistor, a DC blocking capacitor is needed between the current-sourcing terminal of the first transistor and the control terminal of the second transistor. Such a DC blocking capacitor may attenuate (or block) low-frequency signals (such as an IF signal), and thereby reduce the mixing contribution of the second transistor.

[0044] In some embodiments, the frequency mixer arrangement is configured to provide the frequency mixed signal, provided by the current-collecting terminal of the second transistor, as the output signal.

[0045] In some embodiments, the first transistor is a primary first transistor, the second transistor is a primary second transistor, the diode is a primary diode, and the inductive component is a primary inductive component. In that case, frequency mixer arrangement may further comprise a secondary first transistor, a secondary second transistor, a secondary diode, and a secondary inductive component. The primary first transistor, the primary second transistor, the primary diode, and the primary inductive component are connected in a balanced configuration with the secondary first transistor, the secondary second transistor, the secondary diode, and the secondary inductive component. The balanced configuration may configured such that the frequency mixed signal is added constructively at an output port, such that any leakage of the second input signals (that is provided to the primary and the secondary first transistors, and leaked from the primary and the secondary second transistors), is added destructively at the output port, and such that any leakage of the first input signals (that is provided to the primary and the secondary first transistors, and leaked from the primary and the secondary second transistors) is added destructively at the output port. In particular, the respective currentcollecting terminals of the primary second transistor and the secondary second transistor may be connected to an output port of the frequency mixer arrangement. Furthermore, the primary first transistor and the secondary first transistor may be driven by a respective differential first input signals and respective differential second input signals. Differential signals refer to two signals with the same magnitude but opposite phases (180° degrees phase difference).

[0046] In some embodiments, the frequency mixer arrangement comprises a second resistive component, where a first terminal of the second resistive component is galvanically connected to the current-sourcing terminal of the primary first transistor and second terminal of the second resistive component is galvanically connected to the current-sourcing terminal of the secondary first transistor. The first terminal of the second resistive component may directly be connected to the anode of the primary diode and the second terminal of the second resistive component may directly be connected to the anode of the secondary diode.

[0047] There is also disclosed herein an apparatus for a wireless communications network, the apparatus comprising the frequency mixer arrangement according to the discussions above. The apparatus is associated with the abovediscussed advantages. The apparatus may, e.g., be a network node or a wireless device.

[0048] BRIEF DESCRIPTION OF THE DRAWINGS

[0049] With reference to the appended drawings, below follows a more detailed description of embodiments of the present disclosure cited as examples. In the drawings:

[0050] Figure 1 is a schematic illustration of a wireless communications network according to embodiments;

[0051] Figure 2a-2b illustrate respective non-published internal reference examples of frequency mixer arrangements;

[0052] Figures 3-6 illustrate examples of frequency mixer arrangements according to embodiments;

[0053] Figures 7 and 8 illustrate examples of respective filters according to embodiments;

[0054] Figures 9a-9b show plots of conversion gain and DC power, respectively, versus output power for the example arrangements of Figure 2a, 2b, and 3;

[0055] Figures 10a-1 Ob show plots of conversion gain and DC power, respectively, versus output power for example arrangements of Figure 3;

[0056] Figures 11 a-11c show plots of conversion gain, phase, and DC power, respectively, versus output power for example arrangements of Figure 4;

[0057] Figures 12a-12b show plots of conversion DC voltage and power injected into a second transistor, respectively, versus output power for example arrangements of Figure 4;

[0058] Figures 13a- 13b show plots of conversion gain and DC power, respectively, versus output power for example arrangements of Figure 4; Figures 14a- 14b show plots of conversion gain and DC power, respectively, versus output power for example arrangements of Figure 6;

[0059] Figures 15a- 15b show plots of conversion gain and DC power, respectively, versus output power for example arrangements of Figure 6; and

[0060] Figures 16a- 16b show plots of conversion gain versus frequency for example arrangements of Figure 6.

[0061] DETAILED DESCRIPTION

[0062] The present disclosure is described below with reference to the accompanying drawings, in which certain aspects of the present disclosure are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments and aspects set forth herein; rather, these embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. The same features are denoted by the same reference signs throughout the description.

[0063] It is to be understood that the present disclosure is not limited to the embodiments described herein and illustrated in the drawings; rather, the skilled person will recognize that many changes and modifications may be made within the scope of the appended claims.

[0064] Figure 1 - Wireless communications network

[0065] Figure 1 depicts a wireless communications network 100 in which embodiments herein may operate. In some embodiments, the wireless communications network 100 may be a radio communications network, such as, sixth generation (6G), New Radio (NR), or NR+ telecommunications network. However, the wireless communications network 100 may also employ technology of any one of third / fourth / fifth generation, Long Term Evolution (LTE), LTE-Advanced, Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Ultra Mobile Broadband (UMB), or any other similar network or system. The wireless communications network 100 may also employ technology transmitting on millimeter-waves (mmW), such as, e.g., an ultra-dense network (UDN). In some embodiments, the wireless communications network 100 may also employ transmissions supporting WiFi transmissions, e.g., the wireless communications standard IEEE 802.11 ad or similar, or other non-cellular wireless transmissions.

[0066] The wireless communications network 100 comprises a network node 110. The network node 110 may serve wireless devices in at least one cell 115, or coverage area. The network node 110 may correspond to any type of network node or radio network node capable of communicating with a wireless device and / or with another network node, such as, a base station (BS), a radio base station, gNB, eNB, eNodeB, a Home NodeB, a Home eNodeB, a femto BS, or a pico BS in the wireless communications network 100. Further examples of the network node 110 may be a repeater, multi-standard radio (MSR) radio node such as MSR BS, network controller, radio network controller (RNC), base station controller (BSC), relay, donor node controlling relay, base transceiver station (BTS), access point (AP), transmission points, transmission nodes, a remote radio unit (RRU), a remote radio head (RRH), nodes in distributed antenna system (DAS), or core network node. The network node 110 may be arranged to communicate with a remote data processing unit 140, e.g., via a core network 150 of the wireless communications network 100. The remote data processing unit 140 may, for example, be a remote standalone server, a cloud-implemented server, a distributed server, dedicated data processing resources in a server farm, or similar.

[0067] As is also shown in Figure 1, a wireless device 121 is located within the cell 115. The wireless device 121 is configured to communicate within the wireless communications network 100 via the network node 110 over a radio link served by the network node 110. The wireless device 121 may transmit data over an air or radio interface to the network node 110 in uplink (UL), transmissions 132 and the radio base station may transmit data over an air or radio interface to the wireless device 121 in downlink (DL) transmissions 131. The wireless device 121 may refer to any type of wireless devices or user equipment (UE) communicating with a network node and / or with another wireless device in a cellular, mobile or radio communication network or system. Examples of such wireless devices are mobile phones, cellular phones, personal digital assistants (PDAs), smart phones, tablets, sensors equipped with a UE, laptop mounted equipment (LME) (e.g. universal serial bus, USB), laptop embedded equipment (LEE), machine type communication (MTC) devices, or machine to machine (M2M) device, customer premises equipment (CPE), target device, device-to-device (D2D) wireless device, wireless device capable of machine to machine (M2M) communication.

[0068] As part of the developing of the embodiments described herein, it has been realized that the output power (of, e.g., RF for up-conversion or IF for down-conversion) and conversion gain of a frequency mixer arrangement (comprising a first transistor and a diode arranged connected to the emitter / source of the first transistor) can be improved when an inductive component is connected in series between the diode and the emitter / source of the transistor.

[0069] Figures 2a-2b

[0070] Figures 2a-2b constitute respective non-published internal reference examples of frequency mixer arrangements 200a, 200b. The transistors of Figures 2a-2b are HBTs but could equivalently be FETs.

[0071] Figure 2a shows a frequency mixer arrangement 200a, which is single-ended and comprises a single first transistor 210. The first transistor is configured to receive a first input signal, which is an LO signal (LOin), and a second input signal, which is an IF signal (I Fin), for mixing the first and the second input signals to provide a frequency mixed signal, namely an RF signal (RF0Ut). The first transistor 210 is arranged in a common collector configuration. Thus, the first transistor 210 is configured to receive the first (LOjn) and the second (I Fin) input signals at the base 211 of the first transistor 210 and to mix the first and the second input signals to provide the frequency mixed signal (RF0Ut) from the emitter 213 of the first transistor 210.

[0072] The first transistor 210 is configured to receive a first bias voltage Vbiat the base 211 of the first transistor 210 and to receive a first supply voltage Vcciat the emitter 212 of the first transistor 210. The first bias voltage Vbiis provided via a resistor 220. The first supply voltage Vcciis provided directly to the collector 212 and an alternating current (AC) choke 240 is arranged at the emitter 213 of the first transistor 210. The AC choke blocks LO / RF signals to ground and provides a DC path to ground. A capacitor 260 constitutes a DC block before an output port 293.

[0073] The frequency mixer arrangement 200a is configured to receive the first input signal (LOjn) at a first input port

[0074] 291, to receive the second input signal (I Fin) input signal at a second input port 292, and to provide the frequency mixed signal (RF0Ut) as an output signal from the output port 293. Note that the first transistor 210 itself may output a signal which comprises energy at several frequencies and harmonics, and that it may be desired to filter the output of the first transistor 210 such that the frequency mixer arrangement 200a only outputs energy (of a significant level) at a single (desired) frequency span at the output port 293. Different filtering arrangements and techniques for such purposes are possible. In Figure 2a, there is bandpass filter 231 arranged at the first input port 291 and a bandpass filter 232 arranged at the second input port 292, with respective frequency characteristics matching the second and the first input signals, respectively. Note that there may be one or more DC blocks arranged such that the first bias voltage Vbiis blocked from the first and the second input ports 291,

[0075] 292.

[0076] Figure 2b shows a frequency mixer arrangement 200b which is single-ended and comprises the first transistor 210 and a diode 250. The frequency mixer arrangement 200b shares the same components and configuration as the frequency mixer arrangement 200a, except that the AC choke 240 has been replaced with the diode 250. An anode 251 of the diode 250 is galvanically connected to the current-sourcing terminal 213 of the first transistor 210 and a cathode 252 of the diode 250 is galvanically connected to ground.

[0077] Figures 3-8

[0078] Figures 3-6 show respective examples of frequency mixer arrangements 300, 400, 500, 600 according to embodiments.

[0079] Figure 3 shows an example frequency mixer arrangement 300, which is single-ended and comprises a single first transistor 210 and a diode 250. Figure 4 shows an example of a frequency mixer arrangement 400, which is single-ended and comprises the first transistor 210, the diode 250, and a second transistor 470. Figure 5 shows an example of a frequency mixer arrangement 500, which is single-ended and comprises the first transistor 210, the diode 250, and the second transistor 470. Figure 6 shows an example of a frequency mixer arrangement 600, which is similar to frequency mixer arrangement 400, but is arranged in a balanced configuration. In general, the frequency mixer arrangement 300, 400, 500, 600 is suitable for receiving a first input signal (LOjn) and a second input signal (I Fin, RFin), for mixing the first and the second input signals to provide a frequency mixed signal (RF0Ut, IF0Ut), and for providing the frequency mixed signal as an output signal.

[0080] In general, the first input signal (LOjn), may comprise a fundamental tone. Furthermore, the frequency mixer arrangement may be an up-conversion frequency mixer arrangement. The examples frequency mixer arrangement 300, 400, 600 of Figures 3, 4, and 6 are respective up-conversion frequency mixer arrangements. In the up-conversion frequency mixer arrangement, the first input signal may be an LO signal (LOjn). In some embodiments, however, the frequency mixer arrangement is a subharmonic mixer, where the first input signal may be a frequency divided LO signal. In subharmonic mixing, a single tone input has a frequency that is a fraction of an intended LO signal frequency. For example, said single tone may have a frequency of fio / n, where n is a natural number larger than one and fLo is the intended LO signal frequency. Furthermore, in the up- conversion frequency mixer arrangement, the second input signal may be an IF signal (IFin). Alternatively, the second input signal may be a BB signal. In addition, in the up-conversion frequency mixer arrangement, the output signal may be an RF signal (RF0Ut). When the second input signal is a BB signal, the up-conversion frequency mixer arrangement may also be called a modulator.

[0081] In some embodiments, the frequency mixer arrangement is a down-conversion frequency mixer arrangement. The example frequency mixer arrangement 500 of Figure 5 is a down-conversion frequency mixer arrangement. In the down-conversion frequency mixer arrangement, the first input signal is an LO signal or a frequency divided LO signal, the second input signal is an RF signal (RFin), and the output signal is an IF signal (I Fout) or a BB signal. When the output signal is a BB signal, the down-conversion frequency mixer arrangement may also be called a de-modulator.

[0082] The frequency mixer arrangement 300, 400, 500, 600 is configured to receive the first input signal (LOjn) at a first input port 291, to receive the second input signal (I Fjn; RFjn) at a second input port 292, and to provide the frequency mixed signal (RF0Ut; I Fout) as an output signal from the output port 293. Note that different filtering arrangements and techniques for filtering such that the frequency mixer arrangements 300, 400, 500, 600 only outputs energy (of a significant level) at a single (desired) frequency span at the output port 293 may be implemented.

[0083] As is shown in Figures 3, 4, and 6, the frequency mixer arrangement 300, 400, 600 may comprise a bandpass filter 231 arranged at the first input port 291 when the frequency mixer arrangement is an up-conversion frequency mixer arrangement. Furthermore, the frequency mixer arrangement 300, 400, 600 may comprise a bandpass filter 232 (or alternatively a lowpass filter) arranged at the second input port 292 when the frequency mixer arrangement is an up-conversion frequency mixer arrangement. The bandpass filter 231 and the bandpass filter 232 have respective frequency characteristics matching the first and the second input signals, respectively.

[0084] As is shown in Figure 5, the frequency mixer arrangement 500 may comprise a lowpass filter 534 (or alternatively a bandpass filter) arranged at the output port 293 when the frequency mixer arrangement is a down-conversion frequency mixer arrangement. Furthermore, the frequency mixer arrangement 500 may comprise a combiner network 533 arranged to combine the inputs at the first 291 and the second 292 input ports when the frequency mixer arrangement is an up-conversion frequency mixer arrangement. The combiner network 533 may, e.g., comprise a Wilkinson power combiner or a 90° hybrid. The lowpass filter 534 has frequency characteristics matching the output signal.

[0085] In general, the frequency mixer arrangement 300, 400, 500, 600 comprises a first transistor 210. The first transistor 210 is configured to receive the first (LOjn) and the second (I Fin, RFjn) input signals at a control terminal

[0086] 211 of the first transistor 210 and to mix the first and the second input signals to provide the frequency mixed signal (RF0Ut, IF0Ut) from a current-sourcing terminal 213 of the first transistor 210.

[0087] The first transistor 210 may be a first BJT, where a base terminal of the first BJT is the control terminal 211 of the first transistor 210, a collector terminal of the first BJT is the current-collecting terminal 212 of the first transistor 210, and an emitter terminal of the first BJT is the current-sourcing terminal 213 of the first transistor 210. Alternatively, wherein the first transistor 210 may be a first FET, where a gate terminal of the first FET is the control terminal 211 of the first transistor 210, a drain terminal of the first FET is the current-collecting terminal

[0088] 212 of the first transistor 210, and a source terminal of the first FET is the current-sourcing terminal 213 of the first transistor 210.

[0089] The first transistor 210 is configured to receive a first bias voltage Vbi at the control terminal 211 of the first transistor 210 and to receive a first supply voltage Vcciat a current-collecting terminal 212 of the first transistor 210. In the examples of Figures 3-6, the first bias voltage Vbi is provided via a resistor 220. However, other ways of providing the first bias voltage are possible. In general, the frequency mixer arrangement 300, 400, 500, 600 may comprise a first bias feed network for receiving the first bias voltage Vbiand for providing the first bias voltage Vbito the first transistor 210. In the examples of Figures 3-6, the first supply voltage Vcciis provided directly to the emitter 212 of the first transistor 210. However, other ways of providing the first supply voltage are possible. In general, the frequency mixer arrangement 300, 400, 500, 600 may comprise a first supply feed network for receiving the first supply voltage Vcciand for providing the first supply voltage Vccito the first transistor 210.

[0090] As is shown the examples of Figures 3,4, and 6, the frequency mixer arrangement 300, 400, 600 may comprise a capacitor 260 arranged at the output port 293, which constitutes a DC block. As is shown the example of Figure 5, the frequency mixer arrangement 500 may comprise a DC block integrated in the filter 534. Note that there may be one or more DC blocks arranged such that the first bias voltage Vbiis blocked from the first and the second input ports 291, 292. For example, such DC blocks could be integrated in any of the filters 231 , 232, and combiner 533.

[0091] The frequency mixer arrangement 300, 400, 500, 600 comprises a diode 250. An anode 251 of the diode 250 is galvanically connected to the current-sourcing terminal 213 of the first transistor 210 and a cathode 252 of the diode 250 is galvanically connected to ground. A diode is a two-port electronic component that presents an asymmetric conductance, i.e. , it conducts current primarily in one direction. A presents low (zero in the ideal case) resistance in one direction and high (infinite in the ideal case) resistance in the other direction. A diode may be implemented in various ways. In particular, the diode 250 may be based on a third BJT or a third FET. Furthermore, the diode may be implemented using the same semiconductor technology as the first transistor 210. The diode 250 may, e.g., be formed by a BJT where the base is connected to the collector, which forms the anode, and where the emitter forms the cathode. The diode 250 may, e.g., be formed by a BJT where the emitter is connected to the collector, which forms the cathode, and where the base forms the anode. The diode 250 may, e.g., be formed by a FET where the gate is connected to the drain, which forms the anode, and where the source forms the cathode. The diode 250 may, e.g., be formed by a FET where the source is connected to the drain, which forms the cathode, and where the gate forms the anode.

[0092] The first transistor 210, the second transistor 470, and the diode 250 are associated with respective sizes. The size of a FET transistor or diode is the total gate width. For example, the number of fingers multiplied by width of each finger. For a BJT transistor or diode, the size is the total emitter length. For example, the number of fingers multiplied by the length of each finger.

[0093] In some embodiments, the size of the diode 250 is at least 0.5 times the size of the first transistor 210, preferable equal or larger than the size of the first transistor 210, and more preferably at least 2.5 times the size of the first transistor 210. In this way, the mixing contribution of the diode 250 is substantial relative to the mixing contribution of the first transistor 210. Thus, the conversion gain and output power of the frequency mixer arrangement 300 is improved.

[0094] The frequency mixer arrangement 300, 400, 500, 600 comprises an inductive component 380 connected in series between the anode 251 of the diode 250 and the current-sourcing terminal 213 of the first transistor 210. The inductive component 380 is two-port component. The inductive component 380 may also be called a two-port network. The inductive component 380 is configured to present an inductive (also called positive) reactance. According to some aspects, the inductive component 380 may be represented by a two-port network presenting the impedance Z=R+jX, where R is a resistance, X is a reactance, and X is positive.

[0095] In some embodiments, the frequency mixer arrangement 300, 400, 500, 600 may be configured to receive the fundamental tone with a frequency in a span of different frequencies. In that case, the inductive component 380 may be configured to present an inductive reactance for each frequency in the span of different frequencies. For example, the frequency mixer arrangement 300, 400, 500, 600 may be configured to receive the fundamental tone with a frequency in a span of 140 to 170 GHz, where the inductive component 380 is configured to present an inductive reactance for each frequency in the span 140-170 GHz. When the frequency mixer arrangement 300, 400, 500, 600 is a subharmonic mixer, the inductive component 380 may be configured to present an inductive reactance for each frequency in a span of different harmonic frequencies of the fundamental tone. For example, the frequency mixer arrangement 300, 400, 500, 600 may be configured to receive the fundamental tone with a frequency in a span of 70 to 85 GHz, where the inductive component 380 is configured to present an inductive reactance for each frequency in the span 140-170 GHz. In some embodiments, the inductive reactance for each frequency in the span of different frequencies or in the span of different harmonic frequencies of the fundamental tone may be between 18 and 35 Ohm.

[0096] As is shown in the examples of Figures 3-6, the inductive component 380 may comprise a transmission line. However, other ways of implementing the inductive component 380 are also possible. A transmission line is easy to implement on a planar substrate. The transmission line may have an electrical length of at least A / 16, and preferably at least A / 12, where A is the wavelength of the fundamental tone or of a higher harmonic of the fundamental tone. When the frequency mixer arrangement 300, 400, 500, 600 is configured to receive the fundamental tone with a frequency in a span of different frequencies, the electrical length of the transmission line may be for the center frequency in the span of different frequencies or the center frequency in the span of different harmonic frequencies of the fundamental tone. The transmission line may have an electrical length of at most A / 6, and preferably at most A / 8, where A is the wavelength of the fundamental tone or of a higher harmonic of the fundamental tone. Furthermore, the characteristic impedance of the transmission line may, e.g., be a value above 50 Ohm. Other values are also possible.

[0097] The frequency mixer arrangement 300 may be considered as having two cascaded mixing stages, where the first transistor 210 constitutes the first stage, and the diode 250 constitutes the second stage. According to some aspects, the cathode-grounded diode 250 functions a varactor with one terminal grounded. If the inductive component 380 would not be present, there may significant leakage of the frequency mixed signal into ground. Such leakage is undesired since it lowers the output power of the frequency mixed signal at the output port 293. Furthermore, in some cases, it may be desired that the first transistor 210 outputs parts of the first (LOjn) and the second (IFin; RFin) input signals at the current-sourcing terminal 213 of the first transistor 210 (e.g., for re-mixing purposes). If the inductive component 380 would not be present, there may significant leakage of the parts of the first and the second input signals, which is undesired. The leakage due to the diode may be mitigated by using a small diode relative to the size of the first transistor 210. However, a smaller diode reduces the mixing contribution of the diode, and thus reduces the conversion gain and output power of a frequency mixer arrangement. The inductive component 380 increases the magnitude of the impedance, presented to the currentsourcing terminal 213 of the first transistor 210, of the combination of diode 250 and inductive component 380 (i.e., the impedance when looking into node 381 in Figures 3-6). This enables using a larger diode compared to the case without the inductive component 380. A larger diode is advantageous since that increases the mixing contribution of the diode, and thus increases the conversion gain and output power of the frequency mixer arrangement 300.

[0098] As is shown in the example the frequency mixer arrangements 300, 400, 500 of Figure 3-5, the frequency mixer arrangement may further comprise a first resistive component 390. A first terminal 392 of the first resistive component 390 is galvanically connected to ground and a second terminal 391 of the first resistive component 390 is galvanically connected to the current-sourcing terminal 213 of the first transistor 210. As is shown in the examples of Figures 3-5, the second terminal 391 of the first resistive component 390 may directly be connected to the anode 251 of the diode 250 (which forms a galvanic connection to the current-sourcing terminal 213 of the first transistor 210 via the inductive component 380). Alternatively, the second terminal 391 of the first resistive component 390 may directly be connected to the current-sourcing terminal 213 of the first transistor 210. A direct connection to the anode 251 has shown to provide better performance of the frequency mixer arrangement compared to a direct connection to the current-sourcing terminal 213 of the first transistor 210.

[0099] As is shown in the example frequency mixer arrangement 600 of Figure 6, the frequency mixer arrangement may further comprise a second resistive component 690. In general, a first terminal 691 of the second resistive component 690 is galvanically connected to the current-sourcing terminal 213 of one of the first transistors 210 and a second terminal 692 of the second resistive component 690 is galvanically connected to the currentsourcing terminal 213 of the other of the first transistors 210.

[0100] The resistive component 390, 690 may comprise a resistor. A resistor is a passive two-terminal electrical component that presents electrical resistance. A resistor may be implemented in various ways. In particular, a resistor may be implemented using the same semiconductor technology as the first transistor 210. In some embodiments, the resistive component 390, 690 may be configured to present a resistance in the range of 80 to 1200 Ohm.

[0101] As is shown in the examples of Figures 4-6, the frequency mixer arrangement may further comprise a second transistor 470. A control terminal 471 of the second transistor 470 is galvanically connected to the currentsourcing terminal 213 of the first transistor 210. The second transistor 470 is configured to mix signals received at the control terminal 471 of the second transistor 470 to provide the frequency mixed signal (RF0Ut, I Fout), from a current-collecting terminal 472 of the second transistor 470.

[0102] The second transistor 470 may be a second BJT, where a base terminal of the second BJT is the control terminal

[0103] 471 of the second transistor 470, a collector terminal of the second BJT is the current-collecting terminal 472 of the second transistor 470, and an emitter terminal of the second BJT is the current-sourcing terminal 473 of the second transistor 470. Alternatively, the second transistor 470 may be a second FET, where a gate terminal of the second FET is the control terminal 471 of the second transistor 470, a drain terminal of the second FET is the current-collecting terminal 472 of the second transistor 470, and a source terminal of the second FET is the current-sourcing terminal 473 of the second transistor 470.

[0104] The second transistor 470 is configured to receive a second supply voltage Vcc2 at the current-collecting terminal

[0105] 472 of the second transistor 470. A current-sourcing terminal 473 of the second transistor 470 is galvanically connected to ground. In the examples of Figures 4 and 5, the second supply voltage Vcc2 is provided by an AC choke 461. In the example of Figure 6, the second supply voltage Vcc2 is provided by transmission lines 662 and 663. In general, however, the frequency mixer arrangement 400, 500, 600 may comprise a second supply feed network 461 for receiving the second supply voltage Vcc2 and for providing the second supply voltage Vcc2 to the second transistor 470. Furthermore, the frequency mixer arrangement 400, 500, 600 may be configured such that a second bias voltage is provided to the control terminal 471 of the second transistor 470 via the currentsourcing terminal 213 of the first transistor 210. In other words, a DC voltage outputted by the current-sourcing terminal 213 of the first transistor 210 is provided to the control terminal 471 of the second transistor 470 via a galvanic connection, where said DC voltage constitutes the second bias voltage. Such DC coupling increases the performance of the frequency mixer arrangement 400, 500, 600 compared to when using a separate bias feed for the second transistor 470. With a separate bias feed for the second transistor 470, a DC blocking capacitor is needed between the current-sourcing terminal of the first transistor 210 and the control terminal 471 of the second transistor 470. Such a DC blocking capacitor may attenuate (or block) low-frequency signals (such as an IF signal), and thereby reduce the mixing contribution of the second transistor 470.

[0106] The first transistor 210 may be configured to provide respective parts of the first (LOjn) and the second input signals (I Fin, RFjn) from the current-sourcing terminal 213 of the first transistor 210. In that case, the second transistor 470 may be configured to mix the respective parts to provide the frequency mixed signal (RF0Ut, IF0Ut) from the current-collecting terminal 472 of the second transistor 470. Furthermore, the second transistor 470 may be configured to amplify the frequency mixed signal (RF0Ut, I Fout) provided from the current-sourcing terminal 213 of the first transistor 210.

[0107] As mentioned, the frequency mixer arrangement 300, 400, 500, 600 is configured to provide the frequency mixed signal (RF0Ut; IF0Ut) as an output signal from the output port 293. Thus, the frequency mixer arrangement 400, 500, 600 may be configured to provide the frequency mixed signal (RF0Ut, I Fout), provided by the current-collecting terminal 472 of the second transistor 470, as the output signal.

[0108] In some embodiments, a size of the second transistor 470 is at least 0.3 times the size of the first transistor 210, preferable at least 0.4 times the size of the first transistor 210, and more preferably at least 0.6 times the size of the first transistor 210.

[0109] The frequency mixer arrangement 400, 500, 600 may be considered as having three cascaded mixing stages, where the first transistor 210 constitutes the first stage, the diode 250 constitutes the second stage, and the second transistor 470 constitutes the third mixing stage. The inductive component 380 increases the magnitude of the impedance, presented to the current-sourcing terminal 213 of the first transistor 210, of the combination of diode 250 and inductive component 380 (i.e., the impedance when looking into node 381 in Figures 3-6). This enables using a larger diode compared to the case without the inductive component 380. A larger diode is advantageous since that increases the mixing contribution of the diode, and thus increases the conversion gain and output power of the frequency mixer arrangement 400, 500, 600.

[0110] For embodiments with the resistive component 390, 690, the resistive value of the resistive component 390, 690 and the diode 250 together affect base / gate voltage provided to the second transistor 470. The resistive value of the resistive component 390, 690 and the diode 250 also affect the parts of the first input signal (LOjn) that is provided by the current-sourcing terminal 213 of the first transistor that is injected into the base terminal of the second transistor. In particular, the resistive value of the resistive component 390, 690 affects gain compression / expansion characteristics of said parts of the first input signal (LOjn). The characteristics may, e.g., be used to mitigate gain compression of the second transistor 470, which is an advantage. The power level of the first input signal (LOin) injected at the first input port 291 also affects the behavior of the mixing stages, and consequently also the characteristics of the whole frequency mixer arrangement 400, 500, 600. Thus, both the power level of the first input signal (LOin) injected at the first input port 291 as well as the resistive value of the resistive component 390, 690 may be selected to obtain a desired characteristic of the whole frequency mixer arrangement 400, 500, 600.

[0111] The resistive value of the resistive component 390, 690 influences the base / gate voltage bias provided to the second transistor 470. When the second transistor is a silicon germanium (SiGe) HBT device, the resistive value is advantageously selected such that the base / gate voltage bias provided to the second transistor 470 is in the range of 0.68 to 0.76 V.

[0112] The disclosed frequency mixer arrangement presents an increased control of the gain characteristics (e.g., in terms of gain compression or gain expansion). In some embodiments, the resistive value of the resistive component 390, 690 can be selected as fixed value, and the power of the first input signal can be controlled during operation (e.g., to control gain characteristics and compensate for temperature and process variations). Alternatively, power of the first input signal can be fixed, and the resistive value could be controlled during operation. This type of control may, e.g., be implemented by an automatic control system.

[0113] In some embodiments, a current mirror may be used to provide the bias voltage to the first transistor. In this way, the sensitivity of gain characteristics of the frequency mixer arrangement with respect to the ratio of power of the first input signal over the resistive value is decreased.

[0114] As mentioned, Figure 6 shows an example of a frequency mixer arrangement 600, which is similar to frequency mixer arrangement 400, but is arranged in a balanced configuration. Thus, in some embodiments, the first transistor 210 is a primary first transistor, the second transistor 470 is a primary second transistor, the diode 250 is a primary diode, and the inductive component 380 is a primary inductive component. In that case, the frequency mixer arrangement 600 may further comprises a secondary first transistor 210, a secondary second transistor 470, a secondary diode 250, and a secondary inductive component. The primary first transistor 210, the primary second transistor 470, the primary diode 250, and the primary inductive component 380 are connected in a balanced configuration with the secondary first transistor 210, the secondary second transistor 470, the secondary diode 250, and the secondary inductive component 380.

[0115] The frequency mixer arrangement with a balanced configuration may comprise any of the features of the single- ended frequency mixer arrangements discussed above.

[0116] In the example of Figure 6, the first input signal is differential and comprises two parts, namely, LOitl+and LOin., which are provided to respective first input ports 291. Similarly, the second input signal is differential and comprises two parts, namely, I Fin+and I Fin., which are provided to respective second input ports 292. The differential signals may, e.g., be provided a balun (not shown). In other words, the primary first transistor and the secondary first transistor may be driven by respective differential first input signals and respective differential second input signals. Each of the first and second input ports 291, 292 are provided with a respective filter (see 231 and 232 in Figure 6). The filter 232 is implemented as a lowpass filter. The filters also act as respective impedance matching networks.

[0117] As mentioned, in the example of Figure 6, the frequency mixer arrangement comprises a second resistive component 690. The first terminal 691 of the second resistive component 690 is galvanically connected to the current-sourcing terminal 213 of one of the first transistors 210 and a second terminal 692 of the second resistive component 690 is galvanically connected to the current-sourcing terminal 213 of the other of the first transistors 210. In particular, the first terminal 691 of the second resistive component 690 may directly be connected to the anode of the primary diode and the second terminal 690 of the second resistive 690 component may directly be connected to the anode of the secondary diode. The cathodes of both the primary and secondary diodes are connected to ground. In Figure 6, the resistive component 690 replaces two resistors 390 of Figure 4.

[0118] The respective current-collecting terminals of the primary second transistor and the secondary second transistor may be connected to an output port of the frequency mixer arrangement. In the example of Figure 6, the frequency mixer arrangement comprises an output combiner, which is formed by two transmission lines 662, a transmission line 663, a transmission line 664, as well as a capacitor 260. The output combiner is configured to combine the output of the respective second transistors 470 into a single-ended output. Furthermore, in the example of Figure 6, the balanced configuration is configured such that the frequency mixed signal (RF0Ut) is added constructively at the output port 293, and such that any leakage of the second input signals (I Fjn+and IFjn-) is added destructively at the output port 293, and such that any leakage of the first input signals (LOjn+and LOjn-) is added destructively at the output port 293. The second supply voltage VCC2 is provided via transmission lines 662 and 663.

[0119] Figure 7 shows an example of filter 232 and Figure 8 shows an example of filter 291 . In Figure 7, the filter 232 comprises transmission lines TLn, TL12, TL13, TL14, and capacitors On, C12, C13. In Figure 8, the filter 231 comprises transmission lines TL21, TL22, TL23, TL24, and capacitors C21 , C22.

[0120] There is also disclosed herein an apparatus 110, 121 for a wireless communications network 100. The apparatus comprises the frequency mixer arrangement 300, 400, 500, 600 according to the discussions above. The apparatus is associated with the above-discussed advantages. The apparatus may, e.g., be a network node 110 or a wireless device 121 , as discussed in connection to Figure 1.

[0121] Figures 9-16

[0122] Figures 9-16 show simulations example up-conversion frequency mixer arrangements. In the simulations, a 90 nm SiGe HBT process is used (for the first transistor 210, the second transistor 470, and the diode 250 and all other circuit components). For Figures 9-15, the frequencies of the first input signal (LOjn), the second input signal (IFin), and the output signal (RF0Ut) are 160 GHz, 1 GHz, and 161 GHz, respectively. Figures 9a and 9b show conversion gain and DC power, respectively, versus output power for each of the frequency mixer arrangements 200a, 200b, 300 of Figures 2A, 2B, and 3. In the figures, the frequency mixer arrangement 200a of Figure 2A is called "Single-stage”, the frequency mixer arrangement 200b of Figure 2B is called "With diode only Two-stage”, and the frequency mixer arrangement 300 of Figure 3 is called "With diode+TL Two-stage”. For the frequency mixer arrangement of Figure 3, the resistance of the resistor 390 is set to infinity, which is the same as omitting the resistor 390. For each frequency mixer arrangement, the source / load impedance for all frequencies are equal. Each input is provided with ideal band-pass filters, which has zero impedance at desired frequencies and a very large impedance at other (undesired) frequencies. Furthermore, the power of the second input signal (IFjn) is swept from -29 dBm to -11 dBm, and the first input signal (LOjn) is fixed at 3 dBm.

[0123] In Figure 9a, it can be seen that the small IF input signal gains are 5.0 dB, 5.6 dB, and 7.1 dB for the frequency mixer arrangements 200a, 200b, and 300, respectively. The 1-dB output compression (OPidB) is -10.0 dBm, -10.4 dBm, and -8.7 dBm for the frequency mixer arrangements 200a, 200b, and 300, respectively.

[0124] Compared to the frequency mixer arrangement 200a, the frequency mixer arrangement 200b has somewhat higher small signal gain but a similar OPidB. However, by including the inductive component 380 in the frequency mixer arrangement 300, the small signal gain increases by 1.5 dB and the OPidB increases by 1.7 dB relative to the frequency mixer arrangement 200b.

[0125] The frequency mixer arrangements 200a and 200b consume the same DC power approximately. However, the frequency mixer arrangement 300 consumes about a half of the DC power compared to the frequency mixer arrangements 200a and 200b. At OPidB, the frequency mixer arrangements 200b and 300 consume 12 mW and 18.5 mW, respectively. Thus, by including the inductive component 380 in the frequency mixer arrangement 300, the efficiency is improved.

[0126] In some embodiments, which include the second transistor, another benefit of including the inductive component is that the power of the parts of the first input signal (LOjn) that is provided by the current sourcing terminal of the first transistor is also increased. This increases the conversion gain of the whole frequency mixer arrangement with the second transistor.

[0127] Figures 10a and 10b conversion gain and DC power, respectively, versus output power for the frequency mixer arrangement 300 of Figure 3 for different values of the resistance of the resistive component 390, in particular for 60 Ohm, 80 Ohm, and infinity. Port termination impedances, filters, power levels etc. are the same as for Figures 9a and 9b. In Table 1 below shows conversion gain (C. Gain), OPidB, DC power at OPidB (PDC @ OPidB) and PDC @ low Pout for 60 Ohm, 80 Ohm, and infinity of the resistive component (Re).

[0128] Table 1 . Performance of the frequency mixer arrangement 300.

[0129] It can be seen that, as the resistive value equals 80 Ohm, the OPidB increases by 1.3 dB, compared to omitting the resistive component, at a cost of a reduced small signal gain by 0.4 dB, and an increased DC power consumption from 12 mW to 19 mW (2 dB) at OPidB.

[0130] Figures 11-14 show simulations for frequency mixer arrangement 400 of Figure 4. Compared to the frequency mixer arrangement 300 of Figure 3, the transistor and diode sizes, as well as the base bias voltage are redesigned, and the source / load impedances are also re-selected, to maximize the RF output power.

[0131] Figures 11 a and 11 b show conversion gain, phase of the frequency mixed signal (RF0Ut), and DC power, respectively, versus output power or different values of the resistance of the resistive component 390, in particular for 70 Ohm, 100 Ohm, 150 Ohm, and infinity. The power of the first input signal (LOjn) is 2 dBm, which is 1 dB lower than that for Figures 10a-10b, due to an increased conversion gain. The power of the second input signal (IFin) is swept from -38 dBm to -12 dBm. Similar to Figures 9-10, the source / load impedance for all frequencies are equal. Each input is provided with ideal band-pass filters, which has zero impedance at desired frequencies and a very large impedance at other (undesired) frequencies. From the simulations, it can be seen that

[0132] 1) The resistive value can improve the linearity. For example, OPidB increases from -7dBm (without the resistive component 390) to -3.2 dBm (when the resistive value is 100 Ohm).

[0133] 2) Compared to the frequency mixer arrangement 300, OPidB increases from -7.4 dBm (when the resistive value is 80 Ohm) to -3.2 dBm (when the resistive value is 100 Ohm).

[0134] It should be noted that, for an up-conversion mixer, OPidB is a normally an important parameter for an up- conversion mixer, especially at sub-terahertz, where the power of the frequency mixed signal (RF0Ut) is limited by the devices' performance. In some cases, there may be room for sacrificing some gain and / or some DC power consumption (efficiency) for improved OPidB.

[0135] Table 2 below shows conversion gain (C. Gain), OPidB, DC power at OPidB (PDC @ OPidB) and PDC @ low Pout for 70 Ohm, 100 Ohm, 150 Ohm, and infinity of the resistive component (Re). Table 2. Performance of the frequency mixer arrangement 400.

[0136] In Figure 11b, it can be seen that the phase decreases with increasing power of the second input signal (IFjn), and that no expansion of the phase is present.

[0137] For a given power of 2 dBm of the first input signal (LOn), when the resistive value is 100 Ohm, a conversion gain expansion appears around output power of -9 dBm. When the resistive value is 70 Ohm, the conversion gain expands around output power of -6 dBm.

[0138] Figures 12a and 12b show the DC voltage at the base terminal 471 of the second transistor 470 and LO power injected into the second transistor 470 (i.e., parts of the first input signal provided from the current-sourcing terminal 213 of the first transistor 210), respectively, versus output power or different values of the resistance of the resistive component 390, in particular for 70 Ohm, 100 Ohm, 150 Ohm, and infinity. It can be seen that said DC voltage is unchanged around the gain expansion region, as shown in Figure 12a. However, the smaller the value of the resistance, the more quickly the LO power injected into the second transistor 470 increases with increasing power of the second input signal (I Fin), as shown in Figure 12b.

[0139] The conversion gain increases with increasing LO power to a certain extension. The proposed arrangement of the first transistor 210 and the diode 250 (i.e., the two stages) in front of the second transistor 470 provides a possibility of LO power expansion with respect to increasing power of the second input signal (I Fin). Furthermore, the rate of increasing LO power can be controlled by the resistive value.

[0140] It should be noted that the power of the first input signal (LOin), injected at the first input port 291, may influence on the conversion gain of the whole frequency mixer arrangement 400. Figures 13a and 13b are similar to Figures 11a and 11c, respectively. However, Figures 13a and 13b show conversion gain and DC power, respectively, versus output power for the frequency mixer arrangement 400 of Figure 4 for different values of the power of the first input signal (LOin), namely 0, 1, 2, and 3 dBm, when the resistance of the resistive component 390 is 150 Ohm. It can be seen that the conversion gain increases with increasing power of the first input signal (LOin). When the power of the first input signal (LOin) is reduced from 1 dBm to 0 dBm, the conversion gain expansion becomes increasingly noticeable. It can be noted that both the resistive value and the power of the first input signal (LOin), may influence the linearity and conversion gain of the frequency mixer arrangement 400.

[0141] Figures 14-16 show simulations for frequency mixer arrangement 600 of Figure 6.

[0142] Figures 14a and 14b show conversion gain and DC power, respectively, versus output power or different values of the resistance of the resistive component 390. The total power of the second input signal (IFjn+plus I Fin-) is swept from -30 dBm to -4 dBm. The frequency of the second input signal (I Fjn+plus IFjn-) is 1 GHz. The frequency of the frequency mixed signal (RF0Ut) is 161 GHz.

[0143] Figures 15a and 15b are similar to Figures 14a and 14b, respectively. However, in Figures 14a and 14b the power of the first input signal is in total 7 dBm (i.e., 4 dBm for each of LOjn+and LOjn-), and in Figures 15a and 15b the power of the first input signal is in total 6 dBm. Furthermore, Figures 14a and 14b show simulations for 50 Ohm, 100 Ohm, 200 Ohm, and infinity for the resistive value, and Figures 15a and 15b show simulations for 350 Ohm, 800 Ohm, 1200 Ohm, and infinity for the resistive value. Note that the larger resistive values of Figures 15a and 15b are due to the lower power of 6 dBm results in a smaller DC current through the resistive component. Thus, a larger resistive value should be selected to such that a large enough DC bias voltage is provided to the second transistor 470, and such that the conversion gain expansion is not too large.

[0144] Table 3 below shows conversion gain (C. Gain), OPidB, DC power at OPidB (PDC @ OPidB) and PDC @ low Pout for 50 Ohm, 100 Ohm, 200 Ohm, and infinity of the resistive component (Re) corresponding to Figures 14a and 14b.

[0145] Table 3. Performance of the frequency mixer arrangement 600 when the power of the first input signal is in total 7 dBm.

[0146] With a resistive value of infinity and 200 Ohm, the OPidB are 6.5 dBm and 4.0 dBm, respectively, the conversion gain are 14.8 dB and 16.5 dB, respectively, and DC power consumption at OPidB are 98 mW and 77 mW, respectively. Thus, with a resistive value of 200 Ohm, the OPidB can be increased by 1 .5 dB at the cost of lower conversion gain, as well as higher DC power consumption. Reducing the resistive value to 100 Ohm or 50 Ohm, makes the conversion gain expansion more apparent.

[0147] Table 4 below shows conversion gain (C. Gain), OPidB, DC power at OPidB (PDC @ OPidB) and PDc @ low Pout for 350 Ohm, 800 Ohm, 1200 Ohm, and infinity of the resistive component (Re) corresponding to Figures 15a and 15b.

[0148] Table 4. Performance of the frequency mixer arrangement 600 when the power of the first input signal is in total 6 dBm.

[0149] When the resistive value is 1200 Ohm, the conversion gain presents a slight expansion. When the resistive value is reduced to 350 Ohm, the conversion gain presents more expansion. Compared to when the power of the first input signal is in total 7 dBm (when the resistive value is infinity), the conversion gain at small values of the power of the second input signal (I Fjn+plus I Fin-) is 14.3 dB which has been reduced by 2.2 dB. However, OPidB has been increased by 2.1 dB.

[0150] Figures 16a and 16b show the conversion gain at frequency of the frequency mixed signal versus frequency of the second input signal (IFjn+and IFjn-) and versus frequency of the first input signal (LOjn+and LOjn-), respectively. The power of the first input signal (LOjn+plus LOjn-) is in total 7 dBm and the power of the second input signal (IFjn+ plus IFin-) is in total -15 dBm. The figures show simulations for a resistive value of 150 Ohm and infinity. In Figure 16a, the frequency of the second input signal (IFjn+and I Fin-) is swept from 10 MHz to 20 GHz. The frequency of the first input signal (LOjn+and LOjn-) is 160 GHz. The 3-dB bandwidths are 8.5 GHz and 7.5 GHz for a resistive value of infinity and 150 O, respectively. In Figure 16b, the frequency of the first input signal (LOjn+and LOin-) is swept from 140 GHz to 170 GHz. The frequency of the second input signal (I Fjn+and IFin-) is 1 GHz. The 3-dB bandwidth is 17 GHz (from 150 GHz to 167 GHz) for a resistive value of infinity, and 14 GHz (from 153 GHz to 167 GHz) for a resistive value of 150 Ohm. The 3-dB bandwidths are determined mainly by filter characteristics, as well as the impedance matching networks. The description of the example embodiments provided herein have been presented for purposes of illustration. The description is not intended to be exhaustive or to limit example embodiments to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of various alternatives to the provided embodiments. The examples discussed herein were chosen and described to explain the principles and the nature of various example embodiments and its practical application to enable one skilled in the art to utilize the example embodiments in various manners and with various modifications as are suited to the particular use contemplated. It should be appreciated that the example embodiments presented herein may be practiced in any combination with each other. It should be noted that the word "comprising” does not necessarily exclude the presence of other elements or steps than those listed and the words "a” or "an” preceding an element do not exclude the presence of a plurality of such elements. It should further be noted that any reference signs do not limit the scope of the claims, that the example embodiments may be implemented at least in part by means of both hardware and software, and that several "means”, "units” or "devices” may be represented by the same item of hardware. The embodiments herein are not limited to the above-described preferred embodiments. Various alternatives, modifications and equivalents may be used. Therefore, the above embodiments should not be construed as limiting.

Claims

1. 26CLAIMS1. A frequency mixer arrangement (300, 400, 500, 600) for receiving a first input signal (LOin) and a second input signal (IFin; RFin), for mixing the first and the second input signals to provide a frequency mixed signal (RFout; IFout), and for providing the frequency mixed signal as an output signal, the frequency mixer arrangement (300, 400, 500, 600) comprising: a first transistor (210), wherein the first transistor (210) is configured to receive the first (LOin) and the second (IFin; RFin) input signals at a control terminal (211) of the first transistor (210) and to mix the first and the second input signals to provide the frequency mixed signal (RF0Ut; IF0Ut) from a current-sourcing terminal (213) of the first transistor (210), and wherein the first transistor (210) is configured to receive a first bias voltage (Vbi) at the control terminal (211) of the first transistor (210) and to receive a first supply voltage (Vcci) at a current-collecting terminal (212) of the first transistor (210); and a diode (250), wherein an anode (251) of the diode (250) is galvanically connected to the current-sourcing terminal (213) of the first transistor (210) and a cathode (252) of the diode (250) is galvanically connected to ground, wherein the frequency mixer arrangement (300, 400, 500, 600) further comprises an inductive component (380) connected in series between the anode (251) of the diode (250) and the current-sourcing terminal (213) of the first transistor (210).

2. The frequency mixer arrangement (300, 400, 500, 600) according to claim 1 , wherein the first transistor (210) is a first bipolar junction transistor, BJT, wherein a base terminal of the first BJT is the control terminal (211) of the first transistor (210), a collector terminal of the first BJT is the current-collecting terminal (212) of the first transistor (210), and an emitter terminal of the first BJT is the current-sourcing terminal (213) of the first transistor (210), or wherein the first transistor (210) is a first field effect transistor, FET, wherein a gate terminal of the first FET is the control terminal (211) of the first transistor (210), a drain terminal of the first FET is the currentcollecting terminal (212) of the first transistor (210), and a source terminal of the first FET is the current-sourcing terminal (213) of the first transistor (210).

3. The frequency mixer arrangement (300, 400, 500, 600) according to claim 1 or 2, wherein the first input signal (LOin) comprises a fundamental tone.

4. The frequency mixer arrangement (300, 400, 500, 600) according to any previous claim, wherein the inductive component (380) comprises a transmission line.

5. The frequency mixer arrangement (300, 400, 500, 600) according to claim 4 when dependent on claim 3, wherein the transmission line has an electrical length of at least A / 16, and preferably at least A / 12, where A is the wavelength of the fundamental tone or of a higher harmonic of the fundamental tone.

6. The frequency mixer arrangement (300, 400, 500, 600) according to claim 5 or claim 4 when dependent on claim 3, wherein the transmission line has an electrical length of at most A / 6, and preferably at most A / 8, where A is the wavelength of the fundamental tone or of a higher harmonic of the fundamental tone.

7. The frequency mixer arrangement (300, 400, 500, 600) according to any previous claim when dependent on claim 3, wherein frequency mixer arrangement (300, 400, 500, 600) is configured to receive the fundamental tone with a frequency in a span of different frequencies, and wherein the inductive component (380) is configured to present an inductive reactance for each frequency in the span of different frequencies or in a span of different harmonic frequencies of the fundamental tone.

8. The frequency mixer arrangement (300, 400, 500, 600) according to claim 7, wherein the inductive reactance for each frequency in the span of different frequencies or in the span of different harmonic frequencies of the fundamental tone is between 18 and 35 Ohm.

9. The frequency mixer arrangement (300, 400, 500) according to any previous claim, further comprising a first resistive component (390), wherein a first terminal (392) of the first resistive component (390) is galvanically connected to ground and a second terminal (391) of the first resistive component (390) is galvanically connected to the current-sourcing terminal (213) of the first transistor (210).

10. The frequency mixer arrangement (300, 400, 500) according to claim 9, wherein the second terminal (391) of the first resistive component (390) is directly connected to the anode (251) of the diode (250).11 . The frequency mixer arrangement (300, 400, 500, 600) according to claim 9 or 10, wherein the first resistive component (390) comprises a resistor.

12. The frequency mixer arrangement (300, 400, 500, 600) according to any of claims 9-11 , wherein the first resistive component (390) is configured to present a resistance in the range of 80 to 1200 Ohm.

13. The frequency mixer arrangement (300, 400, 600) according to any previous claim, wherein the frequency mixer arrangement (300, 400, 600) is an up-conversion frequency mixer arrangement, wherein the first input signal (LOjn) is a local oscillator, LO, signal or a frequency divided LO signal, the second input signal (I Fin) is an intermediate frequency, IF, signal or a baseband, BB, signal, and the output signal (RF0Ut) is a radio frequency, RF, signal.

14. The frequency mixer arrangement (500) according to any of claims 1 -12, wherein the frequency mixer arrangement (500) is a down-conversion frequency mixer arrangement, wherein the first input signal (LOjn) is an LO signal or a frequency divided LO signal, the second input signal (RFin) is an RF signal, and the output signal (IFout) is an IF signal or a BB signal.

15. The frequency mixer arrangement (300, 400, 500, 600) according to any previous claim, wherein the diode (250) is based on a third BJT or a third FET.

16. The frequency mixer arrangement (300, 400, 500, 600) according to claim 15, wherein a size of the diode (250) is at least 0.5 times the size of the first transistor (210), preferable equal or larger than the size of the first transistor (210), and more preferably at least 2.5 times the size of the first transistor (210).

17. The frequency mixer arrangement (300, 400, 500, 600) according to any previous claim, comprising a first bias feed network for receiving the first bias voltage (Vbi) and for providing the first bias voltage (Vbi) to the first transistor (210), and a first supply feed network for receiving the first supply voltage (Vcci) and for providing the first supply voltage (Vcci) to the first transistor (210).

18. The frequency mixer arrangement (400, 500, 600) according to any previous claim, further comprising a second transistor (470), wherein a control terminal (471) of the second transistor (470) is galvanically connected to the current-sourcing terminal (213) of the first transistor (210), and wherein the second transistor (470) is configured to mix signals received at the control terminal of the second transistor (470) to provide the frequency mixed signal (RF0Ut; IF0Ut) from a current-collecting terminal (472) of the second transistor (470), and wherein the second transistor (470) is configured to receive a second supply voltage (VCC2) at the current-collecting terminal (472) of the second transistor (470), and wherein a current-sourcing terminal (473) of the second transistor (470) is galvanically connected to ground.

19. The frequency mixer arrangement (400, 500, 600) according to claim 18, wherein the second transistor (470) is a second BJT, wherein a base terminal of the second BJT is the control terminal (471) of the second transistor (470), a collector terminal of the second BJT is the current-collecting terminal (472) of the second transistor (470), and an emitter terminal of the second BJT is the current-sourcing terminal (473) of the second transistor (470), or wherein the second transistor (470) is a second FET, wherein a gate terminal of the second FET is the control terminal (471) of the second transistor (470), a drain terminal of the second FET is the currentcollecting terminal (472) of the second transistor (470), and a source terminal of the second FET is the currentsourcing terminal (473) of the second transistor (470).

20. The frequency mixer arrangement (400, 500, 600) according to any of claims 18-19, wherein a size of the second transistor (470) is at least 0.3 times the size of the first transistor (210), preferable at least 0.4 times the size of the first transistor (210), and more preferably at least 0.6 times the size of the first transistor (210).21 . The frequency mixer arrangement (400, 500, 600) according to any of claims 18-20, wherein the first transistor (210) is configured to provide respective parts of the first (LOjn) and the second (I Fjn; RFjn) input signals from the current-sourcing terminal (213) of the first transistor (210), and wherein the second transistor (470) is configured to mix the respective parts to provide the frequency mixed signal (RF0Ut; IF0Ut) from the currentcollecting terminal (472) of the second transistor (470).

22. The frequency mixer arrangement (400, 500, 600) according to any of claims 18-21 , wherein the second transistor (470) is configured to amplify the frequency mixed signal (RF0Ut; IF0Ut) provided from the currentsourcing terminal (213) of the first transistor (210).2923. The frequency mixer arrangement (400, 500, 600) according to any of claims 18-22, comprising a second supply feed network (461) for receiving the second supply voltage (VCC2) and for providing the second supply voltage (VCC2) to the second transistor (470).

24. The frequency mixer arrangement (400, 500, 600) according to any of claims 18-23, wherein the frequency mixer arrangement (400, 500, 600) is configured such that a second bias voltage is provided to the control terminal (471) of the second transistor (470) via the current-sourcing terminal (213) of the first transistor (210).

25. The frequency mixer arrangement (400, 500, 600) according to any of claims 18-24, wherein the frequency mixer arrangement (400, 500, 600) is configured to provide the frequency mixed signal (RF0Ut; IF0Ut), provided by the current-collecting terminal (472) of the second transistor (470), as the output signal.

26. The frequency mixer arrangement (600) according to any of claims 18-25, wherein the first transistor (210) is a primary first transistor, the second transistor (470) is a primary second transistor, the diode (250) is a primary diode, and the inductive component (380) is a primary inductive component, and wherein the frequency mixer arrangement (600) further comprises a secondary first transistor (210), a secondary second transistor (470), a secondary diode (250), and a secondary inductive component (380), and wherein the primary first transistor, the primary second transistor, the primary diode, and the primary inductive component are connected in a balanced configuration with the secondary first transistor, the secondary second transistor, the secondary diode, and the secondary inductive component.

27. The frequency mixer arrangement (600) according to claim 26, comprising a second resistive component (690), wherein a first terminal (691) of the second resistive component (690) is galvanically connected to the current-sourcing terminal (213) of the primary first transistor (210) and second terminal (692) of the second resistive component (690) is galvanically connected to the current-sourcing terminal (213) of the secondary first transistor (210).

28. The frequency mixer arrangement (600) according to claim 27, wherein the first terminal (691) of the second resistive component (690) is directly connected to the anode (251) of the primary diode (250) and the second terminal (692) of the second resistive component (690) is directly connected to the anode (251) of the secondary diode (250).

29. An apparatus (110, 121) for a wireless communications network (100), the apparatus comprising the frequency mixer arrangement (300, 400, 500, 600) according to any of claims 1-28.

30. The apparatus (110, 121) according to claim 29, wherein the apparatus is a network node (110) or a wireless device (121).

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