Multi-core processor shared cache task scheduling method

Abstract

The invention discloses a method for task scheduling of a shared cache of a multi-core processor. The method includes: firstly, dividing the shared Cache of the multi-core processor into a plurality of blocks, and initializing processing core correlation parameters; secondly, for each task in a task queue of the multi-core processor and different shared Cache blocks needed by the tasks, computing earliest task execution completion time corresponding to all processing cores and the task shared Cache blocks; thirdly, judging whether or not task processing core pairs capable of satisfying conditions of the shared Cache blocks needed by the tasks are available; fourthly, searching for the optimum schedulable task processing core pair, scheduling the tasks onto the corresponding processing cores to the executed, and updating the correlation parameter of the multi-core processor parameters; fifthly, judging whether all the tasks in the task queue are scheduled or not, if yes, outputting a task processing core pair sequence, and otherwise, executing the second, third and fourth steps circularly. Compared with an existing multi-core processor oriented task scheduling theory, the method has the performance advantages of short scheduling length and average response time and the like.

Description

technical field

[0001] The invention belongs to the technical field of computer software and on-chip multi-core processor resource management and task scheduling, and relates to a task scheduling method considering a shared high-speed cache cache. Background technique

[0002] In recent years, with the continuous improvement of VLSI integration and main frequency, integrated circuit technology has encountered insurmountable physical problems such as interconnection delay, short channel effect, drift velocity saturation, hot carrier degradation effect, etc. Extreme challenge. This challenge has brought problems such as manufacturing cost, power consumption, and heat dissipation to single-core processor technology, prompting chip manufacturers to turn to multi-core processors that integrate multiple processor cores on the chip. At present, commercial multi-core U processors integrating dozens of cores, such as twelve-core Intel Xeon E5 and AMD Opteron, have been widely used i...

Examples

Embodiment Construction

[0025] The method of the present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

[0026] The present invention proposes a multi-core processor shared Cache-driven task scheduling method, the flow chart of which is as follows figure 1 shown. The method can make full use of the multi-core processor Cache to implement an efficient task scheduling mechanism, thereby improving the concurrent processing performance of the multi-core processor.

[0027] The present invention realizes through following technical scheme:

[0028] This embodiment is aimed at independent parallel application tasks, these tasks do not have dependencies such as data and control, and can run independently on their data sets. However, due to competition among multi-core processors sharing the Cache, the task data cannot be effectively loaded into the Cache and the performance of the processor is reduced. In the present invention, the execution ti...

technical field

[0001] The invention belongs to the technical field of computer software and on-chip multi-core processor resource management and task scheduling, and relates to a task scheduling method considering a shared high-speed cache cache. Background technique

[0002] In recent years, with the continuous improvement of VLSI integration and main frequency, integrated circuit technology has encountered insurmountable physical problems such as interconnection delay, short channel effect, drift velocity saturation, hot carrier degradation effect, etc. Extreme challenge. This challenge has brought problems such as manufacturing cost, power consumption, and heat dissipation to single-core processor technology, prompting chip manufacturers to turn to multi-core processors that integrate multiple processor cores on the chip. At present, commercial multi-core U processors integrating dozens of cores, such as twelve-core Intel Xeon E5 and AMD Opteron, have been widely used i...

Examples

Embodiment Construction

[0025] The method of the present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

[0026] The present invention proposes a multi-core processor shared Cache-driven task scheduling method, the flow chart of which is as follows figure 1 shown. The method can make full use of the multi-core processor Cache to implement an efficient task scheduling mechanism, thereby improving the concurrent processing performance of the multi-core processor.

[0027] The present invention realizes through following technical scheme:

[0028] This embodiment is aimed at independent parallel application tasks, these tasks do not have dependencies such as data and control, and can run independently on their data sets. However, due to competition among multi-core processors sharing the Cache, the task data cannot be effectively loaded into the Cache and the performance of the processor is reduced. In the present invention, the execution ti...

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