AI computing acceleration board with configurable hardware computing power, processing method thereof, and server

Abstract

The embodiments of the present invention disclose an AI computing acceleration board with configurable hardware computing power, a processing method thereof, and a server, which include a PCIE interface, an interface bridge circuit, at least one AI acceleration processing chip, and at least one power management chip, wherein the number of the AI ​​acceleration processing chips is configurable. The embodiments of the present invention make the number of processing chips fixed on the traditional acceleration board configurable through the interface design of the customized AI acceleration processing chip and the system architecture innovation of the AI ​​computing acceleration board, so that the computing power of each AI computing acceleration board is configurable. Users can select the board with corresponding computing power according to actual computing needs, which greatly improves the flexibility of the use of the AI ​​computing acceleration board, reduces hardware costs, and improves device utilization.

Description

Technical Field

[0001] The present invention relates to the field of computer integrated circuit technology, and in particular to an AI computing acceleration board with configurable hardware computing power, a processing method thereof, and a server. Background Art

[0002] With the rapid development of the Internet and information industry, various sound, image and video data have experienced explosive growth. Big data processing has gradually replaced traditional manual data processing, and the application of artificial intelligence (AI) technology has enabled big data analysis and processing capabilities to take another leap forward.

[0003] Deep learning technology has triggered the rapid development of artificial intelligence applications, leading humanity from the information age into the intelligent age. Deep learning is essentially a machine learning technology that requires powerful hardware computing capabilities to complete complex data processing and calculations. For such large amounts of data processing and calculations, existing artificial intelligence solutions use dedicated AI acceleration processing chips to perform deep learning operations. However, even a single ultra-high-performance AI acceleration processing chip has a processing power far from meeting the computing requirements. In order to meet the processing needs of large-scale data, technicians began to use multiple AI acceleration processing chips to form a computing cluster to build AI computing acceleration boards, and communicate with the host CPU through high-speed interfaces (such as the PCIE interface for peripheral component interconnection), thereby forming a deep learning server system, which greatly improved the computing processing capabilities of deep learning.

[0004] In the existing solution, the number of AI acceleration processing chips carried by the AI ​​computing acceleration board is fixed, which results in the computing power of an AI computing acceleration board being fixed. If the computing power of the server needs to be configured, multiple boards need to be plugged into the server motherboard, such as the Chinese invention patent application with publication number CN107329926A. However, when general users configure a PC or server, the number of high-speed interface slots (PCIE interfaces) on the motherboard is limited, resulting in the user being unable to flexibly configure the computing power of the server system according to the actual usage scenario, thereby resulting in a waste of server hardware resources or insufficient system computing power, which cannot meet the actual computing and processing needs. Summary of the Invention

[0005] To solve the above problems, according to one aspect of the present invention, an AI computing accelerator card with configurable hardware computing power is proposed. The AI ​​computing accelerator card includes:

[0006] PCIE interface, used to connect to the PCIE slot of the host;

[0007] Interface bridge circuit, used to convert the PCIE interface into a SerDes interface compatible with the AI ​​acceleration processing chip;

[0008] At least one AI acceleration processing chip, configured to perform AI computing acceleration processing, the AI ​​acceleration processing chip comprising a first SerDes interface and a second SerDes interface;

[0009] At least one power management chip, configured to supply power to the at least one AI acceleration processing chip;

[0010] The number of the AI ​​acceleration processing chips is configurable. When there are multiple AI acceleration processing chips, the multiple AI acceleration processing chips are cascaded in sequence through the first SerDes interface and the second SerDes interface.

[0011] In some implementations, when there is one AI acceleration processing chip, the AI ​​acceleration processing chip is communicatively connected to the interface bridge circuit via a first SerDes interface.

[0012] In some embodiments, when there are multiple AI acceleration processing chips, the AI ​​acceleration processing chip is communicatively connected to the next-level AI acceleration processing chip via a second SerDes interface.

[0013] In some embodiments, the components of the AI ​​computing acceleration board are carried on a PCB carrier board.

[0014] In some implementations, the PCIE interface is further configured to receive data sent by the host CPU and forward the data to the interface bridge circuit.

[0015] In some embodiments, the interface bridge circuit is further used to convert the data to be calculated in the data sent by the host CPU and send it to the AI ​​acceleration processing chip via a Serdes interface for processing.

[0016] In some embodiments, the AI ​​acceleration processing chip processes the data to be calculated, including performing deep learning calculations on the data to be calculated.

[0017] In some embodiments, the AI ​​acceleration processing chip includes an ASIC processing chip.

[0018] In some embodiments, the AI ​​acceleration processing chip includes a tensor processing unit TPU.

[0019] In some embodiments, the interface bridge circuit includes:

[0020] The PCIE interface module is used to receive data sent by the host CPU and convert the data into parallel data;

[0021] An AXI bus module is used to distribute the data to be calculated in the parallel data to the chip link module, and distribute the control commands in the parallel data to the control module;

[0022] A chip link module, used for accessing the data to be calculated;

[0023] A conversion module, used to convert the parallel data to be calculated accessed by the chip link module into serial data;

[0024] A Serdes interface module is used to send the converted serial data to the AI ​​acceleration processing chip for processing;

[0025] The control module is used to receive the control commands distributed by the AXI bus module and control and schedule the AI ​​acceleration processing chip according to the control commands.

[0026] In some embodiments, the interface bridge circuit is further used to receive the calculation result data of the AI ​​acceleration processing chip and send it to the host CPU via the PCIE interface.

[0027] In some embodiments, the number of the at least one power management chip is configured according to the number of the at least one AI acceleration processing chip.

[0028] In some embodiments, the at least one power management chip is connected to the interface bridge circuit, and the interface bridge circuit is further used to control the at least one power management chip to power the corresponding AI acceleration processing chip.

[0029] In some embodiments, the interface bridge circuit is further configured to detect a faulty chip in the at least one power management chip.

[0030] In some embodiments, the at least one AI acceleration processing chip is directly soldered to the PCB carrier board.

[0031] In some embodiments, the at least one AI acceleration processing chip is fixed to the PCB carrier board via a clip of a dedicated socket.

[0032] According to another aspect of the present invention, a method for accelerating the AI ​​computing acceleration board described in any of the aforementioned embodiments is provided, comprising:

[0033] Receive data sent by the host CPU through the PCIE interface;

[0034] Converting the data to be calculated in the data sent by the host CPU through an interface bridge circuit and sending the data to be calculated to at least one AI acceleration processing chip via a Serdes interface for accelerated processing;

[0035] The operation result data of the at least one AI acceleration processing chip is returned to the host CPU through the interface bridge circuit.

[0036] According to another aspect of the present invention, a server is provided, comprising:

[0037] A host computer including a PCIE slot; and

[0038] An AI computing acceleration board as described in any of the aforementioned embodiments connected to a PCIE slot of the host.

[0039] The embodiments of the present invention, through the interface design of customized AI acceleration processing chips and the system architecture innovation of AI computing acceleration boards, make the fixed number of processing chips on traditional acceleration boards configurable, so that the computing power of each AI computing acceleration board is configurable. Users can select boards with corresponding computing power according to actual computing needs, greatly improving the flexibility of using AI computing acceleration boards, reducing hardware costs, and improving device utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 2. This is a schematic diagram of the structure of an AI computing acceleration board with configurable hardware computing power according to an embodiment of the present invention;

[0041] Figure 2 is a schematic structural diagram of an interface bridge circuit according to an embodiment of the present invention;

[0042] Figure 3 1 is a flow chart of a method for accelerating a computation of an AI computation acceleration board according to any embodiment of the present invention;

[0043] Figure 4 2 is a schematic diagram of the structure of a server with configurable hardware computing power according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0045] Figure 1 FIG is a structural diagram of an AI computing acceleration board 100 with configurable hardware computing power according to an embodiment of the present invention. Figure 1 As shown, the AI ​​computing acceleration board 100 includes a PCIE interface 10, an interface bridge circuit 20, N AI acceleration processing chips 30, and N power management chips (PMICs) 40 corresponding to the N AI acceleration processing chips, where N is an integer greater than or equal to 1, wherein:

[0046] The PCIE interface 10 is used to connect to the PCIE slot of the host, receive data sent by the host CPU, and send the data sent by the host CPU to the interface bridge circuit 20. At the same time, the PCIE interface 10 is also used to return the calculation result data of the AI ​​acceleration processing chip 30 to the host CPU.

[0047] The interface bridge circuit 20 is used to convert the PCIE interface into a SerDes interface compatible with the AI ​​accelerator processing chip 30. The data sent by the host is converted and sent to the AI ​​accelerator processing chip 30 via the SerDes interface for processing. The interface bridge circuit 20 is also used to receive the calculation result data returned by the AI ​​accelerator processing chip 30 and transmit it to the host CPU via the PCIE interface 10.

[0048] In some embodiments, the interface bridge circuit 20 also includes control functions for the AI ​​computing acceleration board, such as power-on timing control of the power management chip, control and scheduling of the AI ​​acceleration processing chip, etc.

[0049] The AI ​​acceleration processing chip 30 is used to perform AI computing acceleration processing based on the data to be calculated sent by the host CPU and return the calculation result data to the interface bridge circuit 20. The AI ​​acceleration processing chip 30 is configured with two SerDes interfaces: one SerDes interface is used for data communication with the previous-level AI acceleration processing chip or interface bridge circuit, and the other SerDes interface is used for data communication with the next-level AI acceleration processing chip.

[0050] In some embodiments, the AI ​​acceleration processing chip is implemented using an ASIC processing chip, and the AI ​​operation includes deep learning calculation.

[0051] In some embodiments, the AI ​​acceleration processing chip can also be implemented using Google's Tensor Processing Unit (TPU).

[0052] The power management chip 40 is used to supply power to the AI ​​acceleration processing chip and implement the power management function.

[0053] In some embodiments, the power management chip 40 is connected to the interface bridge circuit 20 via a low-speed serial bus. The interface bridge circuit is also used to control the power management chip to power the corresponding AI acceleration processing chip.

[0054] In an embodiment of the present invention, on the one hand, since a large amount of data is exchanged between the AI ​​acceleration processing chip and other AI acceleration processing chips, a special data interface is required. The embodiment of the present invention adopts a serial / deserialization (Serdes) interface. The Serdes interface is a time division multiplexing (TDM) and point-to-point (P2P) serial communication technology, that is, at the transmitting end, multiple low-speed parallel signals are converted into high-speed serial signals for transmission via the transmission medium, and at the receiving end, the high-speed serial signals are converted back into low-speed parallel signals. This point-to-point serial communication technology makes full use of the channel capacity of the transmission medium, can reduce the required number of transmission channels and device pins, improve the signal transmission speed, and greatly reduce the communication cost. Specifically, the AI ​​acceleration processing chip is configured with two Serdes interfaces, one Serdes interface is used for data communication with the upper-level AI acceleration processing chip or interface bridge circuit, and the other Serdes interface is used for data communication with the next-level AI acceleration processing chip. The AI ​​acceleration processing chip serializes the large amount of parallel data that needs to be transmitted through the Serdes interface, and then transmits the data between chips through the fewer serial traces on the PCB carrier board of the AI ​​computing acceleration board.

[0055] Furthermore, since the CPU of a host (such as a PC or server) typically has a standard PCIE interface but is generally not equipped with a SerDes interface, in order to adapt to the SerDes interface of the AI ​​acceleration processing chip, an interface bridge circuit is configured on the AI ​​computing acceleration board in this embodiment to convert the PCIE interface into a SerDes interface.

[0056] Through such a configuration combination, the number of AI acceleration processing chips carried by the AI ​​computing acceleration board in the embodiment of the present invention is configurable. Figure 1 The AI ​​acceleration processing chips (30-2, ..., 30-N) in the dotted box can be installed in full, in part, or not at all, depending on actual computing needs. This allows for flexible configuration of the hardware computing power of the AI ​​computing acceleration board.

[0057] On the other hand, since the AI ​​acceleration processing chip that performs AI computing acceleration processing has very high power supply requirements, it usually requires a low voltage below 1V and a high current of more than 50A, and both voltage and current need to be adjusted in real time according to the load. Therefore, the AI ​​computing acceleration board of the embodiment of the present invention does not adopt the centralized power supply method used by the traditional PCIE board, but adopts a distributed power supply layout, that is, each AI acceleration processing chip is equipped with an independent power supply, and each power supply has an independent power management chip 40 (40-1, ..., 40-N). All power management chips 40 are connected to the interface bridge circuit 20 via a low-speed serial bus. The interface bridge circuit 20 dynamically adjusts the power supply of each group of AI acceleration processing chips according to the PC or server's demand for AI computing power and workload. This architecture improves system reliability. If a power management chip fails, it does not affect the normal operation of other power management chips, and the fault point can be quickly located through communication with the interface bridge circuit 20. Secondly, according to different computing power configurations, the number of power management chips PMIC can be configured accordingly according to the number of configured AI acceleration processing chips, reducing hardware costs and improving device utilization.

[0058] In the embodiment of the present invention, the various component chips included in the AI ​​computing acceleration board are carried on a PCB carrier board. There are two optional ways to load the AI ​​acceleration processing chip:

[0059] Method 1: Directly solder the AI ​​acceleration processing chip to the PCB carrier. This method has the advantage of strong contact, but the disadvantage is that the hardware computing power of the AI ​​computing acceleration board cannot be configured in real time. Once the board is produced, the computing power is fixed.

[0060] Method 2: Use a dedicated socket, secured to the PCB carrier using the socket's clips. This method offers the advantage of flexible, on-demand computing power configuration, but comes at a slightly higher cost. Both mounting methods offer flexible configurations tailored to different usage scenarios.

[0061] Figure 2 FIG. 2 is a schematic diagram of the structure of the interface bridge circuit 20 according to an embodiment of the present invention. Figure 2 As shown, the interface bridge circuit 20 is implemented using a programmable logic device FPGA, which includes a PCIE interface module 201, an AXI bus module 202, a chip link module 203, a conversion module 204, a Serdes interface module 205 and a control module 206.

[0062] The PCIE interface module 201 is used to receive data sent by the host CPU and convert the data into parallel data.

[0063] The AXI bus module 202 is used to distribute and transmit the parallel data converted by the PCIE interface module 201, wherein the data to be calculated is distributed to the chip link module 203, and the control commands are distributed to the control module 206. The AXI (Advanced Xtensible Interface) bus is an on-chip bus oriented towards high performance, high bandwidth, and low latency.

[0064] The chip link module 203 is used to access the distributed data to be operated. In the entire system, the chip link module 203 is equivalent to a global DMA, which can directly access data without processor intervention, and includes an asynchronous first-in first-out queue FIFO.

[0065] The conversion module 204 is used to convert the parallel data to be operated accessed by the chip link module into serial data.

[0066] The Serdes interface module 205 is used to send the converted serial data to the AI ​​acceleration processing chip 30 for processing.

[0067] The control module 206 is used to receive control commands distributed by the AXI bus module 202 and control and schedule the AI ​​acceleration processing chip according to the control commands.

[0068] In some embodiments, the Serdes interface module 205 is also used to receive the calculation result data returned by the AI ​​acceleration processing chip 30; the conversion module 204 is also used to convert the calculation result data returned by the AI ​​acceleration processing chip received by the Serdes interface module 205 into parallel data; the chip link module 203 is also used to access the calculation result data returned by the AI ​​acceleration processing chip; the AXI bus module 202 is also used to transmit the calculation result data returned by the AI ​​acceleration processing chip to the PCIE interface module 201; the PCIE interface module 201 is also used to transmit the calculation result data returned by the AI ​​acceleration processing chip to the host.

[0069] In some embodiments, the control module 206 includes an AXI-to-APB bridge module and a control port. The AXI bus module 202 distributes control commands contained in data sent by the host to the AXI-to-APB bridge module. The AXI-to-APB bridge module is configured to logically convert control commands received from the AXI bus module 202 into the Advanced Peripheral Bus (APB) protocol format and send the commands to the corresponding control port.

[0070] In some implementations, the control port may include, but is not limited to, an I2C control port and a PWM control port.

[0071] The I2C control port connects to the I2C ports of the AI ​​accelerator processing chip and the temperature sensor, and is used to control and schedule each AI accelerator processing chip and monitor its temperature. In some embodiments, the I2C control port is also used to adjust the power management chip to implement power-on and power-off sequencing and dynamic frequency and voltage regulation functions of the AI ​​accelerator processing chip.

[0072] The PWM control port is used to control the fan speed of the AI ​​accelerator board. Combined with the temperature sensor connected to the I2C port, it enables dynamic adjustment of the AI ​​accelerator chip temperature and fan speed.

[0073] The embodiment of the present invention uses a programmable logic device FPGA to implement bridging conversion from a PCIE interface to a Serdes interface, making the design and use of the AI ​​computing acceleration board more flexible, and can realize peripheral management and logic control of the AI ​​computing acceleration board with multiple AI acceleration processing chips cascaded.

[0074] Figure 3 This is a flow chart of a method for accelerating the processing of an AI computing acceleration board applied to any embodiment of the present invention. Figure 3 As shown, the method includes:

[0075] Step S1, receiving data sent by the host CPU through the PCIE interface;

[0076] Step S2: converting the data to be calculated in the data sent by the host CPU through the interface bridge circuit and sending it to at least one AI acceleration processing chip via the SerDes interface for accelerated processing;

[0077] Step S3: Return the calculation result data of the at least one AI acceleration processing chip to the host CPU through the interface bridge circuit.

[0078] Figure 4 FIG. 2 is a schematic diagram of a server 200 with configurable hardware computing power according to an embodiment of the present invention. Figure 4 As shown, the server 200 of the embodiment of the present invention includes:

[0079] A host computer including a PCIE slot;

[0080] And the AI ​​computing acceleration board 100 with configurable hardware computing power of any of the aforementioned embodiments connected to the host PCIE slot.

[0081] The embodiments of the present invention, through the customized interface design of the AI ​​acceleration processing chip and the system architecture innovation of the AI ​​computing acceleration board, make the fixed number of processing chips on the traditional acceleration board configurable, making the computing power of the AI ​​computing acceleration board configurable, greatly improving the flexibility of use of the AI ​​computing acceleration board, reducing hardware costs, and improving device utilization.

[0082] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An AI computing acceleration board with configurable hardware computing power, characterized by: include: PCIE interface, used to connect to the PCIE slot of the host; An interface bridge circuit, used to convert the PCIE interface into a SerDes interface compatible with the AI ​​acceleration processing chip, serialize the parallel data required to be transmitted by the AI ​​acceleration processing chip through the SerDes interface, and then transmit the data between the AI ​​acceleration processing chips through the serial traces on the PCB carrier board of the AI ​​computing acceleration board; At least one AI acceleration processing chip, configured to perform AI computing acceleration processing, wherein the AI ​​acceleration processing chip includes a first SerDes interface and a second SerDes interface; At least one power management chip, configured to supply power to the at least one AI acceleration processing chip; Wherein, the interface bridge circuit includes: The PCIE interface module is used to receive data sent by the host CPU, convert the data into parallel data, and transmit the calculation result data returned by the AI ​​acceleration processing chip to the host; An AXI bus module is configured to distribute the data to be calculated in the parallel data to the chip link module, distribute the control commands in the parallel data to the control module, and transmit the calculation result data returned by the AI ​​acceleration processing chip to the PCIE interface module; A chip link module, used to access the data to be calculated and the calculation result data returned by the AI ​​acceleration processing chip; A conversion module, configured to convert the parallel data to be calculated accessed by the chip link module into serial data, and to convert the calculation result data returned by the AI ​​acceleration processing chip and received by the SerDes interface module into parallel data; A Serdes interface module is used to send the converted serial data to the AI ​​acceleration processing chip for processing, and receive the calculation result data returned by the AI ​​acceleration processing chip; A control module, configured to receive control commands distributed by the AXI bus module and control and schedule the AI ​​acceleration processing chip according to the control commands; Wherein, the control module includes an AXI to APB bridge module and a control port; The AXI to APB bridge module is used to perform logic conversion on the control commands received from the AXI bus module, convert them into APB peripheral bus protocol format, and send them to the corresponding control port; The control port includes an I2C control port and a PWM control port; wherein, the I2C control port is connected to the I2C ports of the AI ​​acceleration processing chip and the temperature sensor, and is used to control and schedule each AI acceleration processing chip, monitor the temperature of the AI ​​acceleration processing chip, and adjust the power management chip; the PWM control port is used to control the fan speed of the AI ​​computing acceleration board, in combination with the temperature sensor connected to the I2C port. The number of AI acceleration processing chips is configurable. When there are multiple AI acceleration processing chips, the multiple AI acceleration processing chips are cascaded in sequence through the first SerDes interface and the second SerDes interface. The AI ​​acceleration processing chip communicates with the next-level AI acceleration processing chip through the second SerDes interface. The number of the at least one power management chip is configured according to the number of the at least one AI acceleration processing chip; the at least one power management chip is connected to the interface bridge circuit, and the interface bridge circuit is also used to control the at least one power management chip to supply power to the corresponding AI acceleration processing chip, and to detect a faulty chip in the at least one power management chip.

2. The AI ​​computing acceleration board according to claim 1, characterized in that: When there is one AI acceleration processing chip, the AI ​​acceleration processing chip is communicatively connected to the interface bridge circuit via a first SerDes interface.

3. The AI ​​computing acceleration board according to claim 1, wherein: The components of the AI ​​computing acceleration board are carried on a PCB carrier board.

4. The AI ​​computing acceleration board according to claim 1, wherein: The PCIE interface is also used to receive data sent by the host CPU and forward it to the interface bridge circuit.

5. The AI ​​computing acceleration board according to claim 4, characterized in that: The interface bridge circuit is used to convert the data to be calculated in the data sent by the host CPU and send it to the AI ​​acceleration processing chip via the Serdes interface for processing.

6. The AI ​​computing acceleration board according to claim 5, characterized in that: The AI ​​acceleration processing chip processes the data to be calculated, including performing deep learning calculations on the data to be calculated.

7. The AI ​​computing acceleration board according to claim 6, characterized in that: The AI ​​acceleration processing chip includes an ASIC processing chip.

8. The AI ​​computing acceleration board according to claim 6, wherein: The AI ​​acceleration processing chip includes a tensor processing unit TPU.

9. The AI ​​computing acceleration board according to claim 3, characterized in that: The at least one AI acceleration processing chip is directly soldered to the PCB carrier board.

10. The AI ​​computing acceleration board according to claim 3, characterized in that: The at least one AI acceleration processing chip is fixed to the PCB carrier board via a clip of a dedicated socket.

11. A computing acceleration processing method applied to the AI ​​computing acceleration board according to any one of claims 1 to 10, characterized in that: include: Receive data sent by the host CPU through the PCIE interface; Converting the data to be calculated in the data sent by the host CPU through an interface bridge circuit and sending the data to be calculated to at least one AI acceleration processing chip via a Serdes interface for accelerated processing; The operation result data of the at least one AI acceleration processing chip is returned to the host CPU through the interface bridge circuit.

12. A server, characterized in that: include: A host computer including a PCIE slot; and An AI computing acceleration board as described in any one of claims 1 to 10 connected to a PCIE slot of the host.

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