Bypass Error Correction Code (ECC) processing based on software hints

Abstract

Methods and apparatus relate to techniques for avoiding cache lookups for cold caches. In an example, an apparatus includes logic, including at least in part hardware logic, to: receive metadata from an application, wherein the metadata indicates one or more processing operations that can comply with a predetermined level of bit errors in a read operation from a memory; determine acceptable error correction code bypassed pixel data from the metadata; and generate one or more error correction code bypass hints for subsequent cache accesses of the acceptable error correction code bypassed pixel data; and transmit the one or more error correction code bypass hints to a graphics processing pipeline. Other embodiments are also disclosed and claimed.

Description

Technical Field

[0001] The present disclosure relates generally to the field of electronic devices. More specifically, some embodiments relate to techniques for bypassing error correction code (ECC) processing based on software hints. Background Art

[0002] As integrated circuit manufacturing technology improves, manufacturers are able to integrate additional functionality onto a single silicon substrate. As the number of functions increases, the number of components on a single integrated circuit (IC) chip also increases. The additional components add additional signal switching, thereby generating more heat and / or consuming more power. The additional heat can damage the components on the chip through, for example, thermal expansion. Moreover, the additional power consumption can limit the use location and / or use model of such devices (e.g., especially for devices that rely on battery power to function). Therefore, efficient power management can have a direct impact on the efficiency, lifespan, and use model of electronic devices.

[0003] In addition, current parallel graphics data processing includes the development of systems and methods for performing specific operations on graphics data, such as linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function compute units to process graphics data. However, recently, portions of graphics processors have been made programmable, enabling these processors to support a wider range of operations to process vertex and fragment data.

[0004] To further improve performance, graphics processors typically implement processing techniques such as pipelining, which attempt to process as much graphics data as possible in parallel throughout different parts of the graphics pipeline. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, groups of parallel threads attempt to execute program instructions synchronously as often as possible to improve processing efficiency. A general overview of software and hardware for the SIMT architecture can be found in Shane Cook, CUDA Programming, Chapter 3, pages 37-51 (2013) and / or Nicholas Wilt, CUDA Handbook, A Comprehensive Guide to GPU Programming, Sections 2.6.2 to 3.1.2 (June 2013). BRIEF DESCRIPTION OF THE DRAWINGS

[0005] In order to understand the above-described features of the present embodiment in detail, the above briefly summarized embodiments may be described in more detail by reference to the embodiments, some of which are shown in the attached drawings. However, it should be noted that the attached drawings only show typical embodiments and therefore should not be considered as limiting the scope thereof.

[0006] Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0007] FIG. 2A to FIG. 2D A parallel processor component according to an embodiment is shown;

[0008] FIG. 3A to FIG. 3B is a block diagram of a graphics multiprocessor according to an embodiment;

[0009] 4A to 4F An exemplary architecture is presented in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0010] Figure 5 A graphics processing pipeline according to an embodiment is shown;

[0011] Figures 6 to 7A is a flow chart illustrating operations in a method for bypassing error correction code (ECC) processing based on software hints in accordance with an embodiment.

[0012] Figure 7B is a schematic block diagram of data flow in a method for bypassing error correction code (ECC) processing based on software hints according to an embodiment.

[0013] Figure 8 A block diagram of a switching regulator according to an embodiment is shown.

[0014] Fig. 9 is a block diagram of a system including a streaming multiprocessor according to one or more embodiments.

[0015] Fig.10 A block diagram of a parallel processing system according to one embodiment is shown.

[0016] Fig.11 is a block diagram of a processing system according to an embodiment.

[0017] Fig.12 is a block diagram of a processor according to an embodiment;

[0018] Fig.13 is a block diagram of a graphics processor according to an embodiment;

[0019] Fig.14is a block diagram of a graphics processing engine of a graphics processor according to some embodiments;

[0020] Fig.15 is a block diagram of a graphics processor provided by an additional embodiment;

[0021] Fig.16 Thread execution logic is shown, the thread execution logic including an array of processing elements employed in some embodiments;

[0022] Fig.17 is a block diagram illustrating a graphics processor instruction format according to some embodiments;

[0023] Fig.18 is a block diagram of a graphics processor according to another embodiment;

[0024] FIG. 19A to FIG. 19B A graphics processor command format and command sequence according to some embodiments are presented;

[0025] Fig. 20 An exemplary graphics software architecture for a data processing system according to some embodiments is presented;

[0026] Fig.21 is a block diagram showing an IP core development system according to an embodiment;

[0027] Fig. 22 is a block diagram illustrating an exemplary system-on-chip integrated circuit according to an embodiment;

[0028] Fig.23 is a block diagram illustrating additional exemplary graphics processors; and

[0029] Fig.24 is a block diagram illustrating an additional exemplary graphics processor of a system-on-chip integrated circuit according to an embodiment. DETAILED DESCRIPTION

[0030] In the following description, many specific details are set forth to provide a comprehensive understanding of the various embodiments. However, the various embodiments may be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits are not described in detail so as not to obscure the particular embodiments. In addition, various aspects of the embodiments may be performed using various means, such as integrated semiconductor circuits ("hardware"), computer-readable instructions organized into one or more programs ("software"), or some combination of hardware and software. For the purposes of this disclosure, references to "logic" shall mean hardware, software, firmware, or some combination thereof.

[0031] Some embodiments discussed herein may be applied in any processor (e.g., GPCPU, CPU, GPU, etc.), graphics controller, etc. Other embodiments are also disclosed and claimed. Further, some embodiments may be applied in computing systems including one or more processors (e.g., having one or more processor cores), such as those discussed herein, including, for example, mobile computing devices, such as smartphones, tablets, UMPCs (Ultra Mobile Personal Computers), laptops, Ultrabook™ computing devices, wearable devices (such as smart watches, smart glasses), and the like.

[0032] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to a host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuits / logic for efficiently processing these commands / instructions.

[0033] In the following description, many specific details are set forth to provide a more comprehensive understanding. However, it will be apparent to those skilled in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the present embodiment.

[0034] System Overview

[0035] Figure 11 is a block diagram illustrating a computer system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104, the one or more processors and the system memory communicating via an interconnect path, which may include a memory hub 105. The memory hub 105 may be a separate component within a chipset component or may be integrated within one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107, which may enable the computing system 100 to receive input from one or more input devices 108. In addition, the I / O hub 107 may enable a display controller (which may be included in one or more processors 102) to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include a local display device, an internal display device, or an embedded display device.

[0036] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112, which are coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols (such as but not limited to PCI Express), or it can be a vendor-specific communication interface or communication structure. In one embodiment, the one or more parallel processors 112 form a computing-centric parallel or vector processing system that includes a large number of processing cores and / or processing clusters such as integrated many-core (MIC) processors. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 110B.

[0037] Within the I / O subsystem 111, a system storage unit 114 may be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. The I / O switch 116 may be used to provide an interface mechanism to enable connection between the I / O hub 107 and other components that may be integrated into the platform, such as a network adapter 118 and / or a wireless network adapter 119, as well as various other devices that may be added via one or more plug-in devices 120. The network adapter 118 may be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0038] Computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 107. Figure 1 The communication paths interconnecting the various components may be implemented using any suitable protocol such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express), or any other bus or point-to-point communication interface(s) and / or protocol such as the NV-Link high-speed interconnect or an interconnect protocol known in the art.

[0039] In one embodiment, one or more parallel processors 112 incorporate circuits optimized for graphics and video processing, including, for example, video output circuits, and the circuits constitute a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 incorporate circuits optimized for general-purpose processing while retaining the basic computing architecture described in more detail herein. In yet another embodiment, the components of the computing system 100 can be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 112, a memory hub 105, (multiple) processors 102, and an I / O hub 107 can be integrated into a system on a chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a system in package (SIP) configuration. In other embodiments, at least a portion of the components of the computing system 100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computing system.

[0040] It should be understood that the computing system 100 shown herein is illustrative and variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of (multiple) processors 102, and the number of (multiple) parallel processors 112, can be modified as needed. For example, in some embodiments, the system memory 104 is directly connected to the (multiple) processors 102 rather than through a bridge, and other devices communicate with the system memory 104 via the memory hub 105 and the (multiple) processors 102. In other alternative topologies, the (multiple) parallel processors 112 are connected to the I / O hub 107 or directly to one of the one or more processors 102, rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 can be integrated into a single chip. Some embodiments may include two or more groups of (multiple) processors 102 attached via multiple sockets, which can be coupled to two or more instances of (multiple) parallel processors 112.

[0041] Some specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be omitted. In addition, some architectures may use different terminology to describe components related to the computing system 100. Figure 1 For example, in some architectures, memory hub 105 may be referred to as a north bridge, while I / O hub 107 may be referred to as a south bridge.

[0042] Figure 2A A parallel processor 200 according to an embodiment is shown. Various components of the parallel processor 200 may be implemented using one or more integrated circuit devices such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). According to an embodiment, the parallel processor 200 shown is Figure 1 A variation of one or more parallel processors 112 is shown.

[0043] In one embodiment, parallel processor 200 includes parallel processing unit 202. The parallel processing unit includes an I / O unit 204, which enables communication with other devices including other instances of parallel processing unit 202. I / O unit 204 can be directly connected to other devices. In one embodiment, I / O unit 204 is connected to other devices via the use of a hub or switch interface such as memory hub 105. The connection between memory hub 105 and I / O unit 204 forms communication link 113. Within parallel processing unit 202, I / O unit 204 is connected to host interface 206 and memory cross switch 216, wherein host interface 206 receives commands related to performing processing operations and memory cross switch 216 receives commands related to performing memory operations.

[0044] When host interface 206 receives command buffers via I / O unit 204, host interface 206 may direct work operations for executing the commands to front end 208. In one embodiment, front end 208 is coupled to scheduler 210, which is configured to dispatch commands or other work items to processing cluster array 212. In one embodiment, scheduler 210 ensures that processing cluster array 212 is properly configured and in a valid state before dispatching tasks to processing clusters of processing cluster array 212.

[0045] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, up to cluster 214N). Each cluster 214A to 214N of the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may use various scheduling and / or work distribution algorithms to allocate work to the clusters 214A to 214N of the processing cluster array 212, which may vary depending on the workload caused by each type of program or calculation. Scheduling may be handled dynamically by the scheduler 210, or may be partially assisted by compiler logic in the process of compiling program logic configured to be executed by the processing cluster array 212. In one embodiment, different clusters 214A to 214N of the processing cluster array 212 may be allocated to process different types of programs or to perform different types of calculations.

[0046] Processing cluster array 212 may be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 may include logic for performing processing tasks including filtering of video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0047] In one embodiment, processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where parallel processor 200 is configured to perform graphics processing operations, processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations and tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute shader programs associated with graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 202 may transfer data from system memory via I / O unit 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing and then written back to system memory.

[0048] In one embodiment, when parallel processing unit 202 is used to perform graphics processing, scheduler 210 can be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to multiple clusters 214A to 214N of processing cluster array 212. In some embodiments, portions of processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to generate a rendered image for display. Intermediate data generated by one or more of clusters 214A to 214N can be stored in a buffer to allow the intermediate data to be transferred between clusters 214A to 214N for further processing.

[0049] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, a processing task may include data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands (e.g., which program to execute) that define how the data is to be processed. The scheduler 210 may be configured to obtain an index corresponding to a task or may receive an index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0050] Each of the one or more instances of the parallel processing unit 202 may be coupled to a parallel processor memory 222. The parallel processor memory 222 may be accessed via a memory crossbar switch 216, which may receive memory requests from the processing cluster array 212 and the I / O unit 204. The memory crossbar switch 216 may access the parallel processor memory 222 via a memory interface 218. The memory interface 218 may include a plurality of partition units (e.g., partition unit 220A, partition unit 220B, up to partition unit 220N), which may each be coupled to a portion (e.g., memory unit) of the parallel processor memory 222. In one implementation, the number of partition units 220A to 220N is configured to be equal to the number of memory units, such that the first partition unit 220A has a corresponding first memory unit 224A, the second partition unit 220B has a corresponding memory unit 224B, and the Nth partition unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partition units 220A to 220N may not be equal to the number of memory devices.

[0051] In various embodiments, the memory units 224A to 224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A to 224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of the memory units 224A to 224N may vary and may be selected from one of a variety of conventional designs. Rendering targets such as frame buffers or texture maps may be stored on the memory units 224A to 224N, allowing the partition units 220A to 220N to write to portions of each rendering target in parallel to efficiently use the available bandwidth of the parallel processor memory 222. In some embodiments, in order to support a unified memory design that utilizes system memory together with local cache memory, the local instance of the parallel processor memory 222 may be excluded.

[0052] In one embodiment, any of the clusters 214A to 214N of the processing cluster array 212 can process data to be written to any of the memory units 224A to 224N within the parallel processor memory 222. The memory crossbar 216 can be configured to pass the output of each cluster 214A to 214N to any partition unit 220A to 220N or another cluster 214A to 214N, which can perform additional processing operations on the output. Each cluster 214A to 214N can communicate with the memory interface 218 through the memory crossbar 216 to perform read or write operations on various external memory devices. In one embodiment, the memory crossbar 216 can be connected to the memory interface 218 to communicate with the I / O unit 204, and can be connected to the local instance of the parallel processor memory 222, so that the processing units within different processing clusters 214A to 214N can communicate with the system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar switch 216 may use virtual channels to separate traffic flows between the clusters 214A to 214N and the partition units 220A to 220N.

[0053] Although a single instance of parallel processing unit 202 is shown as being within parallel processor 200, any number of instances of parallel processing unit 202 may also be included. For example, multiple instances of parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Even if different instances have different numbers of processing cores, different local parallel processor storage amounts, and / or other configuration differences, different instances of parallel processing unit 202 may also be configured to interoperate. For example, and in one embodiment, some instances of parallel processing unit 202 may include higher precision floating point units relative to other instances. Systems incorporating one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented in various configurations and form factors, including but not limited to desktop computers, laptop computers or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0054] Figure 2B is a block diagram of a partition system 220 according to an embodiment. In one embodiment, the partition system 220 is Figure 2A20A to 220N. As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and an ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 216 and the ROP 226. Read misses and urgent write-back requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Dirty updates can also be sent to the frame buffer via the frame buffer interface 225 for opportunistic processing. In one embodiment, the frame buffer interface 225 interacts with one of the memory units in the parallel processor memory, such as the memory units 224A to 224N of FIG. 2 (e.g., within the parallel processor memory 222).

[0055] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. ROP 226 then outputs processed graphics data stored in graphics memory. In some embodiments, ROP 226 includes compression logic that compresses z or color data written to memory and decompresses z or color data read from memory. In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A to 214N of FIG. 2) rather than within partition unit 220. In this embodiment, read and write requests for pixel data are transmitted through memory crossbar switch 216 rather than pixel fragment data. The processed graphics data can be displayed on a display device such as Figure 1 to one of the one or more display devices 110, routed by the processor(s) 102 for further processing, or by Figure 2A One of the processing entities within parallel processor 200 is routed for further processing.

[0056] Figure 2CIt is a block diagram of a processing cluster 214 in a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A to 214N of Figure 2. The processing cluster 214 can be configured to execute multiple threads in parallel, wherein the term "thread" refers to an instance of a specific program executed on a specific input data set. In some embodiments, a single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, a single instruction multiple thread (SIMT) technology is used to use a public instruction unit configured to issue instructions to a group of processing engines in each of the processing clusters to support the parallel execution of a large number of roughly synchronized threads. Different from the SIMD execution mechanism that all processing engines usually execute the same instruction, SIMT execution allows different threads to more easily follow the divergent execution path through a given thread program. It will be appreciated by those skilled in the art that the SIMD processing mechanism represents a functional subset of the SIMT processing mechanism.

[0057] The operation of the processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to the SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of Figure 2 and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The graphics multiprocessor 234 shown is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures can be included in the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included in the processing cluster 214. The graphics multiprocessor 234 can process data, and the data crossbar switch 240 can be used to distribute the processed data to one of multiple possible destinations including other shading units. The pipeline manager 232 can promote the distribution of processed data by specifying a destination for the data to be distributed via the data crossbar switch 240.

[0058] Each graphics multiprocessor 234 within a processing cluster 214 may include the same set of function execution logic (e.g., arithmetic logic units, load store units, etc.). The function execution logic may be configured in a pipelined manner, where a new instruction may be issued before a previous instruction is completed. The function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. In one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may exist.

[0059] The instructions transmitted to the processing cluster 214 constitute threads. A group of threads executed on a group of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread in a thread group can be assigned to a different processing engine in the graphics multiprocessor 234. A thread group can include fewer threads than the number of processing engines in the graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle of processing the thread group. A thread group can also include more threads than the number of processing engines in the graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines in the graphics multiprocessor 234, processing can be performed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 234.

[0060] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 234 can abandon the internal cache and use cache memory (e.g., L1 cache 308) within the processing cluster 214. Each graphics multiprocessor 234 can also access the L2 cache within the partition unit (e.g., partition unit 220A to 220N of Figure 2) shared between all processing clusters 214, and can be used to pass data between threads. The graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of the local parallel processor memory and / or system memory. Any memory outside the parallel processing unit 202 can be used as global memory. In which the processing cluster 214 includes multiple instances of the graphics multiprocessor 234, the embodiment can share common instructions and data that can be stored in the L1 cache 308.

[0061] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG. 2 . The MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more referred to as blocking) and optionally cache line indexes. The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality to achieve efficient request interleaving between partition units. The cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0062] In graphics and computing applications, the processing clusters 214 can be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or in some embodiments from an L1 cache within the graphics multiprocessor 234, and is retrieved from an L2 cache, local parallel processor memory, or system memory as needed. Each graphics multiprocessor 234 outputs processed tasks to a data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. A preROP 242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234, direct the data to ROP units, which can be located with partition units (e.g., partition units 220A to 220N of FIG. 2 ) as described herein. The preROP 242 unit optimizes color blending, organizes pixel color data, and performs address translation.

[0063] It should be understood that the core architecture described herein is illustrative and variations and modifications are possible. Any number of processing units, such as graphics multiprocessor 234, texture unit 236, preROP 242, etc., may be included in processing cluster 214. In addition, although only one processing cluster 214 is shown, the parallel processing unit described herein may include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0064] Figure 2D A graphics multiprocessor 234 is shown according to one embodiment. In such an embodiment, the graphics multiprocessor 234 is coupled to the pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0065] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. These instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 can dispatch instructions as thread groups (e.g., warps), each thread of the thread group is assigned to a different execution unit within the GPGPU core 262. Instructions can access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 266.

[0066] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 262, load / store unit 266) connected to the graphics multiprocessor 324. In one embodiment, the register file 258 is divided between each of the functional units so that each functional unit is allocated a dedicated portion of the register file 258. In one embodiment, the register file 258 is divided between the different warps being executed by the graphics multiprocessor 324.

[0067] The GPGPU cores 262 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 324. Depending on the embodiment, the architecture of the GPGPU cores 262 may be similar or different. For example, and in one embodiment, the first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 floating-point arithmetic standard or enable variable-precision floating-point arithmetic. In addition, the graphics multiprocessor 324 may also include one or more fixed-function or special-function units for performing specific functions such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0068] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 324 to the register file 258 and the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to implement load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so the data transfer between the GPGPU core 262 and the register file 258 has a very low latency. The shared memory 270 can be used to implement communication between threads executed on the functional units within the graphics multiprocessor 234. For example, the cache memory 272 can be used as a data cache to cache texture data communicated between the functional units and the texture unit 236. The shared memory 270 can also be used as a cached managed program. In addition to the automatically cached data stored in the cache memory 272, threads executing on the GPGPU core 262 can also programmatically store data in the shared memory.

[0069] FIG. 3A to FIG. 3B Additional graphics multiprocessors are shown according to embodiments. The graphics multiprocessors 325, 350 shown are Figure 2C The illustrated graphics multiprocessors 325, 350 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0070] Figure 3A A graphics multiprocessor 325 is shown according to an additional embodiment. The graphics multiprocessor 325 includes Figure 2D The graphics multiprocessor 325 may include multiple additional instances of the execution resource unit of the graphics multiprocessor 234. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A to 332B, register files 334A to 334B, and (multiple) texture units 344A to 344B. The graphics multiprocessor 325 also includes multiple groups of graphics or compute execution units (e.g., GPGPU cores 336A to 336B, GPGPU cores 337A to 337B, GPGPU cores 338A to 338B) and multiple groups of load / store units 340A to 340B. In one embodiment, the execution resource unit has a common instruction cache 330, texture and / or data cache memory 342, and shared memory 346. The various components can communicate via the interconnect structure 327. In one embodiment, the interconnect structure 327 includes one or more crossbar switches, which are used to enable communication between the various components of the graphics multiprocessor 325.

[0071] Figure 3BA graphics multiprocessor 350 is shown according to an additional embodiment. Figure 2D and Figure 3A As shown, the graphics processor includes multiple groups of execution resources 356A to 356D, each of which includes multiple instruction units, register files, GPGPU cores, and load storage units. The execution resources 356A to 356D can work with (multiple) texture units 360A to 360D to perform texture operations while sharing an instruction cache 354 and a shared memory 362. In one embodiment, the execution resources 356A to 356D can share multiple instances of the instruction cache 354 and the shared memory 362 as well as texture and / or data cache memories 358A to 358B. The various components can be connected via Figure 3A The interconnect structure 327 communicates with a similar interconnect structure 352 .

[0072] Those skilled in the art will understand that Figure 1 , FIG. 2A to FIG. 2D and FIG. 3A to FIG. 3B The architecture described in is illustrative and does not limit the scope of the embodiments of the present invention. Therefore, the techniques described herein can be implemented on any appropriately configured processing unit, including but not limited to: one or more mobile application processors; one or more desktop computer or server central processing units (CPUs), including multi-core CPUs; one or more parallel processing units such as parallel processing unit 202 of FIG. 2; and one or more graphics processors or special processing units, without departing from the scope of the embodiments described herein.

[0073] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside a package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0074] Technologies for GPU to host processor interconnect

[0075] Figure 4AAn exemplary architecture is shown in which multiple GPUs 410 to 413 are communicatively coupled to multiple multi-core processors 405 to 406 via high-speed links 440 to 443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, high-speed links 440 to 443 support 4GB / s, 30GB / s, 80GB / s, or higher communication throughput, depending on the implementation. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the invention are not limited to any particular communication protocol or throughput.

[0076] Furthermore, in one embodiment, two or more of the GPUs 410 to 413 are interconnected via high-speed links 444 to 445, which may be implemented using the same or different protocols / links as used for high-speed links 440 to 443. Similarly, two or more of the multi-core processors 405 to 406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus running at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4A All communications between the various system components shown in can be accomplished using the same protocol / links (eg, through a common interconnect structure). However, as mentioned, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0077] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memory 401-402 via memory interconnects 430-431, respectively, and each GPU 410-413 is communicatively coupled to GPU memory 420-423 via GPU memory interconnects 450-453, respectively. The memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. By way of example and not limitation, the processor memory 401-402 and the GPU memory 420-423 may be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0078] As described below, although the various processors 405-406 and GPUs 410-413 may each be physically coupled to a specific memory 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed among all the various physical memories. For example, the processor memories 401-402 may each include 64GB of system memory address space, and the GPU memories 420-423 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable storage space in the described example).

[0079] Figure 4B Additional details of the interconnection between the multi-core processor 407 and the graphics acceleration module 446 according to one embodiment are shown. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0080] The processor 407 shown includes a plurality of cores 460A to 460D, each of which has a translation lookaside buffer 461A to 461D and one or more caches 462A to 462D. These cores may include various other components (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.) for executing instructions and processing data not shown to avoid obscuring the basic principles of the present invention. Caches 462A to 462D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 426 may be included in the cache hierarchy and shared by each group of cores 460A to 460D. For example, one embodiment of the processor 407 includes 24 cores, each of which has its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 cache and the L3 cache is shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to the system memory 441 , which may include the processor memories 401 to 402 .

[0081] The data and instructions stored in the various caches 462A to 462D, 456, and the system memory 441 are maintained consistent via inter-core communication via the consistency bus 464. For example, each cache may have cache consistency logic / circuitry associated therewith to communicate via the consistency bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via the consistency bus 464 to snoop cache accesses. Cache snooping / consistency techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the basic principles of the present invention.

[0082] In one embodiment, the proxy circuit 425 communicatively couples the graphics acceleration module 446 to the coherence bus 464, thereby allowing the graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the core. Specifically, the interface 435 provides connectivity to the proxy circuit 425 via a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the link 440.

[0083] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 431, 432, 43N of the graphics acceleration module 446. The graphics processing engines 431, 432, 43N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, 43N may include different types of graphics processing engines such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and block image transfer engines within the GPU. In other words, the graphics acceleration module may be a GPU having multiple graphics processing engines 431, 432, 43N, or the graphics processing engines 431 to 432, 43N may be separate GPUs integrated on a common package, line card, or chip.

[0084] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions such as virtual to physical memory translation (also known as effective to real memory translation) and a memory access protocol for accessing the system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431 to 432, 43N. In one embodiment, the data stored in the cache 438 and the graphics memory 433 to 434, 43N is kept consistent with the core caches 462A to 462D, 456 and the system memory 411. As mentioned, this can be accomplished via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and memories 433 to 434, 43N (e.g., sending updates to cache 438 related to modifications / accesses of cache lines on processor caches 462A to 462D, 456 and receiving updates from cache 438).

[0085] A set of registers 445 stores context data for threads executed by the graphics processing engines 431 to 432, 43N, and a context management circuit 448 manages thread contexts. For example, the context management circuit 448 may perform save and restore operations to save and restore contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, upon context switching, the context management circuit 448 may store current register values ​​to a specified area in memory (e.g., identified by a context pointer). The context management circuit may restore register values ​​upon returning to context. In one embodiment, the interrupt management circuit 447 receives and processes interrupts received from system devices.

[0086] In one implementation, the virtual / effective address from the graphics processing engine 431 is converted to an actual / physical address in the system memory 411 by the MMU 439. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 can be dedicated to a single application executed on the processor 407, or can be shared between multiple applications. In one embodiment, a virtual graphics execution environment is presented in which the resources of the graphics processing engines 431 to 432, 43N are shared with multiple applications or virtual machines (VMs). Resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0087] Thus, the accelerator integrated circuit acts as a bridge to the system of graphics acceleration modules 446 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage virtualization of the graphics processing engine, interrupts, and memory management.

[0088] Since the hardware resources of the graphics processing engines 431-432, 43N are explicitly mapped to the actual address space seen by the host processor 407, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431-432, 43N so that they appear on the system as independent units.

[0089] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, 43M are coupled to each of the graphics processing engines 431-432, 43N, respectively. The graphics memories 433-434, 43M store instructions and data being processed by each of the graphics processing engines 431-432, 43N. The graphics memories 433-434, 43M may be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D XPoint or Nano-Ram.

[0090] In one embodiment, in order to reduce data traffic on link 440, biasing techniques are used to ensure that the data stored in graphics memory 433 to 434, 43M is the data most frequently used by graphics processing engines 431 to 432, 43N, and preferably not used (at least not frequently) by cores 460A to 460D. Similarly, the biasing mechanism attempts to keep data needed by the core (and preferably not the graphics processing engines 431 to 432, 43N) within caches 462A to 462D, 456 of the core and system memory 411.

[0091] Figure 4C Another embodiment is shown in which an accelerator integrated circuit 436 is integrated into the processor 407. In this embodiment, the graphics processing engines 431 to 432, 43N communicate directly with the accelerator integrated circuit 436 via the interface 437 and the interface 435 through the high-speed link 440 (which may also utilize any form of bus or interface protocol). The accelerator integrated circuit 436 can perform operations related to Figure 4B The same operations are described, but given their close proximity to the coherency bus 462 and caches 462A to 462D, 426, it is possible to operate at a higher throughput.

[0092] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The shared programming model may include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0093] In one embodiment of a dedicated process model, graphics processing engines 431 to 432, 43N are dedicated to a single application or process under a single operating system. A single application can funnel other application requests to graphics engines 431 to 432, 43N, thereby providing virtualization within a VM / partition.

[0094] In a dedicated process programming model, the graphics processing engines 431 to 432, 43N can be shared by multiple VM / application partitions. The shared model requires a hypervisor that virtualizes the graphics processing engines 431 to 432, 43N to allow access by each operating system. For a single partition system without a hypervisor, the graphics processing engines 431 to 432, 43N are owned by the operating system. In both cases, the operating system can virtualize the graphics processing engines 431 to 432, 43N to provide access to each process or application.

[0095] For the shared programming model, the graphics acceleration module 446 or the individual graphics processing engines 431 to 432, 43N use a process handle to select a process element. In one embodiment, the process elements are stored in the system memory 411 and can be addressed using the effective address to real address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431 to 432, 43N (i.e., calling the system software to add a process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0096] Figure 4D An exemplary accelerator integrated slice 490 is shown. As used herein, a "slice" includes a specified portion of the processing resources of the accelerator integrated circuit 436. The application effective address space 482 within the system memory 411 stores process elements 483. In one embodiment, the process element 483 is stored in response to a GPU call 481 from an application 480 executed on the processor 407. The process element 483 contains the processing state of the corresponding application 480. The work descriptor (WD) 484 contained in the process element 483 can be a single job requested by the application, or can contain a pointer to a job queue. In the latter case, the WD 484 is a pointer to a job request queue in the application address space 482.

[0097] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, 43N may be shared by all or some processes in the system. Embodiments of the present invention include an infrastructure for establishing a processing state and sending a WD 484 to the graphics acceleration module 446 to start a job in a virtual environment.

[0098] In one implementation, the dedicated process programming model is specific to a specific implementation. In this model, a single process owns the graphics acceleration module 446 or a separate graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 to obtain the owned partition, and the operating system initializes the accelerator integrated circuit 436 to obtain the owned process when the graphics acceleration module 446 is allocated.

[0099] In operation, the WD acquisition unit 491 in the accelerator integrated slice 490 acquires the next WD 484, which includes an indication of the work to be performed by one of the graphics processing engines of the graphics acceleration module 446. As shown, the data from the WD 484 can be stored in the register 445 and used by the MMU 439, the interrupt management circuit 447 and / or the context management circuit 446. For example, one embodiment of the MMU 439 includes a segment / page walk circuit for accessing the segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can process the interrupt event 492 received from the graphics acceleration module 446. When performing graphics operations, the effective address 493 generated by the graphics processing engine 431 to 432, 43N is converted to an actual address by the MMU 439.

[0100] In one embodiment, the same set of registers 445 is replicated for each graphics processing engine 431 to 432, 43N and / or graphics acceleration module 446, and this set of registers can be initialized by a hypervisor or an operating system. Each of these replicated registers can be included in an accelerator integrated slice 490. Table 1 shows exemplary registers that can be initialized by a hypervisor.

[0101] Table 1 - Hypervisor Initialization Registers

[0102] 1 Slice Control Register 2 Real Address (RA) Dispatch Process Area Pointer 3 Authorization mask override register 4 Interrupt vector table entry offset 5 Interrupt vector table entry limit 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Manager Accelerator Utilizes Record Pointers 9 Storage Description Register

[0103] Example registers that may be initialized by the operating system are shown in Table 2.

[0104] Table 2 - Operating System Initialization Registers

[0105] 1 Process and thread identities 2 Effective Address (EA) context save / restore pointer 3 Virtual Address (RA) Accelerator Utilizes Record Pointers 4 Virtual Address (RA) storage segment table pointer 5 Authorization Mask 6 Job Descriptor

[0106] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431 to 432, 43N. The WD contains all the information needed by the graphics processing engine 431 to 432, 43N to complete its work, or the WD can be a pointer to a memory location where the application has established a command queue for work to be completed.

[0107] Figure 4E Additional details of one embodiment of the sharing model are shown. The embodiment includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes a graphics acceleration module engine of an operating system 495.

[0108] The shared programming model allows all or some processes from all or some partitions in the system to use the graphics acceleration module 446. There are two programming models where the graphics acceleration module 446 is shared by multiple processes and partitions: time-sliced ​​sharing and graphics direct sharing.

[0109] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. In order for the graphics acceleration module 446 to support virtualization of the hypervisor 496, the graphics acceleration module 446 may comply with the following requirements: 1) Application job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The graphics acceleration module 446 guarantees that application job requests are completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 446 provides the ability to preempt job processing. 3) When operating in a direct sharing programming model, fairness of the graphics acceleration module 446 in the process must be guaranteed.

[0110] In one embodiment, for the shared model, an application 480 is required to make an operating system 495 system call using a graphics acceleration module 446 type, a work descriptor (WD), an authorization mask register (AMR) value, and a context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function of the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can be in the following form: a graphics acceleration module 446 command; an effective address pointer to a user-defined structure; an effective address pointer to a command queue; or any other data structure used to describe the work to be performed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application that sets the AMR. If the implementation of the accelerator integrated circuit 436 and the graphics acceleration module 446 does not support the user authorization mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 496 may optionally apply the current authorization mask override register (AMOR) value before placing the AMR into the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains the effective address of an area in the application address space 482 for the graphics acceleration module 446 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. The context save / restore area may be a plugged in system memory.

[0111] Upon receiving the system call, the operating system 495 can verify that the application 480 is registered and authorized to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 with the information shown in Table 3.

[0112] Table 3 - Parameters of the operating system calling the hypervisor

[0113] 1 Work Descriptor (WD) 2 Authorization Mask Register (AMR) value (may be masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0114] Upon receiving the hypervisor call, the hypervisor 496 may verify that the operating system 495 has registered and is authorized to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into the process element linked list for the corresponding graphics acceleration module 446 type. The process element may contain the information shown in Table 4.

[0115] Table 4 - Process element information

[0116]

[0117]

[0118] In one embodiment, the hypervisor initializes the plurality of accelerator integrated slices 490 of registers 445 .

[0119] like Figure 4F As shown, one embodiment of the present invention employs a unified memory addressable via a common virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations executed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 401-402 and GPU memories 420-423, thereby allowing any processor or GPU to access any physical memory having a virtual address mapped to that memory.

[0120] In one embodiment, bias / coherency management circuits 494A-494E within one or more of MMUs 439A-439E ensure cache coherency between caches of a host processor (e.g., 405) and GPUs 410-413 and implement biasing techniques that indicate physical memory where certain types of data should be stored. Figure 4F 4. Although multiple instances of bias / consistency management circuits 494A to 494E are shown in FIG. 4, bias / consistency circuits may also be implemented within an MMU of one or more host processors 405 and / or within an accelerator integrated circuit 436.

[0121] One embodiment allows the GPU-attached memory 420 to 423 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology, but without suffering from the typical performance defects associated with full system cache coherence. The ability to access the GPU-attached memory 420 to 423 as system memory does not cause heavy cache coherence overhead, which provides a favorable operating environment for GPU offloading. This arrangement allows the host processor 405 software to set operands and access calculation results without the overhead of traditional I / O DMA data copying. These traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are inefficient relative to simple memory accesses. At the same time, the ability to access the GPU-attached memory 420 to 423 without cache coherence overhead may be critical to the execution time of the offloaded calculation. For example, in the case of a large number of streaming write memory services, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 410 to 413. The efficiency of operand setting, the efficiency of result access, and the efficiency of GPU calculation all play an important role in determining the effectiveness of GPU offloading.

[0122] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table may be used, which may be a page granular structure including 1 or 2 bits per GPU attached memory page (i.e., controlled at the granularity of a memory page). The bias table may be implemented in the stolen memory range of one or more GPU attached memories 420 to 423, with or without a bias cache in GPUs 410 to 413 (e.g., to cache frequently / recently used entries of the bias table). Alternatively, the entire bias table may be maintained within the GPU.

[0123] In one implementation, the bias table entry associated with each access to the GPU attached memory 420 to 423 is accessed before the GPU memory is actually accessed, so that the following operations are performed. First, local requests from GPUs 410 to 413 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 420 to 423. Local requests from the GPUs whose pages are found in the host bias are forwarded to the processor 405 (e.g., over a high-speed link as described above). In one embodiment, the request from the processor 405 to find the requested page in the host processor bias completes the request like a normal memory read. Alternatively, the request for the GPU bias page can be forwarded to the GPUs 410 to 413. If the GPU is not currently using the page, the GPU can convert the page to the host processor bias.

[0124] The bias state of a page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a hardware-only based mechanism.

[0125] One mechanism for changing the bias state employs an API call (e.g., OpenCL) which in turn calls a GPU device driver which in turn sends a message (or queues a command descriptor) to the GPU, thereby directing the GPU to change the bias state and, for certain transitions, perform a cache flush operation in the host. The cache flush operation is required for a transition from host processor 405 bias to GPU bias, but not for the reverse transition.

[0126] In one embodiment, cache coherency is maintained by temporarily presenting GPU bias pages that are non-cacheable to host processor 405. To access these pages, processor 405 may request access from GPU 410, which may or may not grant access immediately, depending on the implementation. Therefore, to reduce communication between processor 405 and GPU 410, it is advantageous to ensure that GPU bias pages are pages that are needed by the GPU but not by the host processor 405, and vice versa.

[0127] Graphics processing pipeline

[0128] Figure 5 2. A graphics processing pipeline 500 according to an embodiment is shown. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem as described herein, such as the parallel processor 200 of FIG. 2. In one embodiment, the parallel processor is Figure 12 . As described herein, various parallel processing systems may implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., parallel processing unit 202 of FIG. 2 ). For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3 ) may be configured to perform the functions of one or more of a vertex processing unit 504, a tessellation control processing unit 508, a tessellation evaluation processing unit 512, a geometry processing unit 516, and a fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 may also be performed by other processing engines within a processing cluster (e.g., processing cluster 214 of FIG. 3 ) and corresponding partition units (e.g., partition units 220A to 220N of FIG. 2 ). The graphics processing pipeline 500 may also be implemented using one or more dedicated processing units for the functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be executed by parallel processing logic within a general purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., parallel processor memory 222 as shown in FIG. 2 ) via a memory interface 528, which may be an example of the memory interface 218 of FIG. 2 .

[0129] In one embodiment, data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. Data assembler 502 then outputs vertex data including vertex attributes to vertex processing unit 504. Vertex processing unit 504 is a programmable execution unit that executes vertex shader programs to illuminate and transform vertex data as specified by the vertex shader programs. Vertex processing unit 504 reads data stored in cache, local or system memory for processing vertex data, and can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0130] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 50. Primitive assembler 506 reads the stored vertex attributes and constructs graphics primitives as needed for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0131] The tessellation control processing unit 508 treats the input vertices as control points of a geometric patch. These control points are transformed from an input representation from the patch (e.g., a basis for the patch) to a representation suitable for surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometric patch. The tessellation factors apply to individual edges and quantify the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and divide the patch into a plurality of geometric primitives such as lines, triangles, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the tessellated patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0132] A second instance of primitive assembler 514 receives vertex attributes from tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by geometry processing unit 516. Geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform graphics primitives received from primitive assembler 514 as specified by the geometry shader programs. In one embodiment, geometry processing unit 516 is programmed to tessellate the graphics primitives into one or more new graphics primitives and to compute parameters for rasterizing the new graphics primitives.

[0133] In some embodiments, the geometry processing unit 516 can add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs the graphics primitives for processing by the viewport scaling, picking, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or the system memory for processing the geometry data. The viewport scaling, picking, and clipping unit 520 performs clipping, picking, and viewport scaling, and outputs the processed graphics primitives to the rasterizer 522.

[0134] The rasterizer 522 can perform depth picking and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate segments and outputs these segments and associated coverage data to the segment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to generate shaded fragments or pixels output to the raster operation unit 526. The fragment / pixel processing unit 524 can read data stored in a parallel processor memory or system memory to use when processing fragment data. The fragment or pixel shader program can be configured to color with samples, pixels, tiles, or other granularity according to the sampling rate configured for the processing unit.

[0135] The raster operation unit 526 is a processing unit that performs raster operations including, but not limited to, stenciling, z-testing, blending, etc., and outputs pixel data as processed graphics data for storage in a graphics memory (e.g., parallel processor memory 222 in FIG. 2 , and / or as shown in FIG. Figure 1 The raster operation unit 526 may be configured to compress the z or color data written to the memory and to decompress the z or color data read from the memory.

[0136] Many existing processing systems (such as, for example, graphics systems) implement error correction code (ECC) processing for each transaction in cache (including L3 cache) in order to provide error-free data. ECC processing consumes a large amount of computing resources and power resources.

[0137] The subject matter described herein solves these and other problems by providing a technique for bypassing ECC processing for some cache access operations. For example, for some applications (e.g., texture sampling or shading), only red, green, blue, alpha (RGBA) texture / color data is needed. In such applications, it is acceptable for the RGBA values ​​retrieved from the cache to have smaller bit errors, because small errors will not degrade the image quality beyond acceptable limits. As described herein, in some examples, the application may pass information indicating which data sets can tolerate small errors in the data retrieved from the cache. The data may be used to provide a hint to a controller (such as, for example, a cache controller in a graphics processing system) to indicate whether a specific cache access operation can bypass ECC processing.

[0138] The technology described herein solves these and other problems by enabling one or more controllers in a processing system (e.g., a graphics processing system) to receive metadata from an application, wherein the metadata indicates one or more processing operations that can accommodate a predetermined level of bit errors when performing read operations from a memory. The controller(s) can determine acceptable error correction code bypassed pixel data from the metadata and generate one or more error correction code bypass hints for subsequent cache accesses of the acceptable error correction code bypassed pixel data. The one or more error correction code bypass hints can be transmitted to a graphics processing pipeline.

[0139] The graphics processing pipeline may receive the one or more error correction code bypass hints and use the hint(s) to bypass the error correction code logic when the error correction code bypass hint indicates that bypassing the error correction code logic is acceptable for graphics processing data retrieved from the cache memory.

[0140] Figure 6 7 is a flow chart illustrating operations in a method for bypassing error correction code (ECC) processing based on software hints according to an embodiment. In some examples, Figure 6 The operations depicted in FIG. 7 are implemented as logic that can be executed in one or more controllers. In various examples, the logic can be implemented as logic instructions (i.e., software) stored in a memory and executable on a processor. In other examples, the logic can be reduced to programmable circuitry (e.g., in a field programmable gate array (FPGA)), or to fixed circuitry in hardware, or a combination thereof.

[0141] refer to Figure 67 , at operation 610, metadata is received from an application in a controller (e.g., in a processor executing a user-mode graphics driver). At operation 615, the controller determines from the metadata whether there is any pixel data associated with the graphics of the application and for which error correction code (ECC) bypass is acceptable. For example, for an application such as texture sampling or shading that only reads RGBA texture / color data, it may be able to tolerate a certain degree of error in the RGBA values ​​read from the cache because it will not degrade the image quality to an unacceptable level.

[0142] At operation 620, the controller generates one or more error correction code (ECC) bypass hints for subsequent cache access. In some examples, the error correction code (ECC) bypass hint may identify a specific cache location associated with the data. In other examples, the error correction code (ECC) bypass hint may identify a graphics processing operation (e.g., texture sampling or shading) that can accept error correction code (ECC) bypass. At operation 625, the one or more error correction code (ECC) bypass hints are transmitted to the graphics processing pipeline.

[0143] Fig. 7A An example of an operation for using an error correction code (ECC) hint to bypass error correction code (ECC) processing is depicted in FIG. FIG. 7A to FIG. 7B At operation 710 , a frame is received in a graphics processing pipeline for processing. At operation 715 , the graphics processing pipeline initiates a graphics processing operation on the frame received in operation 710 .

[0144] At operation 720, a graphics processing pipeline receives a Figure 6 The error correction code(s) (ECC) bypass hints generated in operation 720 are bypassed, and at operation 725, the pixel data is retrieved from a cache (eg, an L3 cache) for processing.

[0145] At operation 730, if the error correction code (ECC) bypass hint(s) received in operation 720 for the pixel data retrieved from the cache in operation 725 indicates that the pixel data retrieved in operation 725 may not bypass error correction code (ECC) processing, then control passes to operation 735 and error correction code (ECC) processing is applied to the pixel data retrieved from the cache in operation 725. In contrast, at operation 735, if the error correction code (ECC) bypass hint(s) received in operation 720 for the pixel data retrieved from the cache in operation 725 indicates that the pixel data retrieved in operation 725 may bypass error correction code (ECC) processing, then control passes to operation 735 and error correction code (ECC) processing is bypassed for the pixel data retrieved from the cache in operation 725.

[0146] After completing operation 735 or 740, control passes back to operation 720 and receives bypass hint(s) for the next set of pixel data. Fig. 7A The operation of the cache memory allows error correction code (ECC) processing to be selectively applied to pixel data retrieved from the cache memory. This reduces the computational cost, memory latency and power consumption of the graphics system.

[0147] Figure 7B is a schematic block diagram of data flow in a method for bypassing error correction code (ECC) processing based on software hints according to an embodiment. Figure 7B As shown in , input data from the cache is input to multiplexer 770 via line 752, and one or more error correction code (ECC) hints are input to multiplexer 770 via line 754 as a control.

[0148] If the ECC hint(s) indicate that the input data from the cache requires ECC processing, the input data from the cache is input to the ECC block 1320, which may include one or more Fast Fourier Transform modules 760, 762, 764. In contrast, if the ECC hint(s) indicate that the input data from the cache does not require ECC processing, the input data from the cache is not input to the ECC block 1320.

[0149] Multiplexer 770 receives as data inputs the output of ECC block 1320 and input data from the cache via line 752. If one or more error correction code (ECC) hints input as controls via line 754 indicate that the input data from the cache requires error correction code (ECC) processing, multiplexer 770 selects as output the output of ECC block 1320. In contrast, if one or more error correction code (ECC) hints input as controls via line 754 indicate that the input data from the cache does not require error correction code (ECC) processing, multiplexer 770 selects as output the input data from the cache.

[0150] Power components

[0151] Figure 8 1 shows a block diagram of a switching regulator according to an embodiment. Figure 8 One or more switching regulators shown in FIG. 1 may be incorporated into various systems discussed herein to provide power to one or more integrated circuit (IC) chips. Figure 8 A single phase of a current-parking switching regulator with a single inductor is discussed, but one or more of the multiple phases of the current-parking switching regulator may be implemented with a split inductor. In addition, a combination of one or more current-parking switching regulators (with or without a split inductor) may be used with one or more conventional power conversion devices to provide power to a load (e.g., logic circuit 814).

[0152] More specifically, Figure 8A system 800 is shown, which includes a switching regulator (sometimes referred to as a current parking switching regulator). In various embodiments, the current parking switching regulator can be a multi-phase switching regulator. A multi-phase control unit 802 is coupled to a plurality of phases, wherein each phase may include one or more upstream phases 804 and one or more downstream phases 806. As shown, a power supply 808 is coupled to an upstream control logic 810 (which provides a current control mechanism in each upstream phase). More than one upstream control logic may be used in various implementations. Each upstream phase may include an inductor (not shown) that is coupled to a corresponding downstream phase. In an embodiment, the upstream phases may each include one or more inductors. The multi-phase control unit 802 may configure any active upstream control logic 810 to generate current, for example, by an inductor coupled between an upstream phase and a downstream phase. The downstream control logic 812 may be configured by the multi-phase control unit 802 to be on, off, or switched to adjust the voltage level at the load (e.g., logic circuit 814). In turn, downstream control logic 812 may be configured by multi-phase control unit 802 to maintain the voltage level at the load within a range based at least in part on the Vmin (minimum voltage) and Vmax (maximum voltage) values.

[0153] In one embodiment, an inductor (coupled between a downstream phase and a corresponding upstream phase) may be positioned external to a semiconductor package 816 including a load 814. Another inductor (not shown) may be positioned internal to the package 816, for example, to reduce parasitic capacitance. In one embodiment, the inductor internal to the package 816 may be an air core inductor coupled to the logic circuit 814 via one or more switching logic including planar metal-oxide semiconductor field effect transistors (MOSFETs). Additionally, in various embodiments, one or more of the components discussed herein (e.g., reference 814) may be coupled to the logic circuit 814. Figure 8 , 9 and / or 10, including, for example, an L3 cache, upstream control logic, and / or downstream control logic) may be provided in a substrate(s) layer(s) (e.g., between semiconductor packages), on an integrated circuit die, or external to a semiconductor package (e.g., on an integrated circuit board (PCB)).

[0154] Fig. 9is a block diagram of a system 900 including a streaming multiprocessor 902 according to one or more embodiments. The streaming multiprocessor may include 32 single instruction, multithread (SIMT) lanes 904 capable of collectively issuing up to 32 instructions per clock cycle, e.g., one instruction from each of the 32 threads. There may be more or fewer lanes, depending on the implementation, such as 64, 128, 256, etc. The SIMT lanes 904 may further include one or more of: an arithmetic logic unit (ALU) 906, a special function unit (SFU) 908, a memory unit (MEM) 910, and / or a texture unit (TEX) 912.

[0155] In some embodiments, one or more of the ALU(s) 906 and / or TEX unit(s) 912 may be low energy or high capacity, e.g., such as discussed with reference items 920 and 922. For example, the system may map 100% of the register addresses of threads 0-30 to the low energy portion, and 100% of the register addresses of threads 31-127 to the high capacity portion. As another example, the system may map 20% of the registers of each thread to the low energy portion, and 80% of the registers of each thread to the high capacity portion. In addition, the system may determine the number of entries to allocate per thread based on runtime information.

[0156] like Fig. 9 As shown in , the streaming multiprocessor 902 may also include a register file 914, a scheduler logic 916 (e.g., for scheduling threads or thread groups, or both), and a shared memory 918, such as a local scratch storage. As discussed herein, a "thread group" refers to a plurality of threads grouped together with an ordered (e.g., sequential or continuous) thread index. Typically, a register file refers to an array of registers accessed by a component of a processor such as the processor discussed herein (including a graphics processor). The register file 914 includes a low-energy portion or structure 920 and a high-capacity portion or structure 922. The streaming multiprocessor 902 may be configured to address the register file 914 using a single logical namespace for both the low-energy portion and the high-capacity portion.

[0157] In some embodiments, the system may include several physical registers that can be shared by threads running simultaneously on the system. This allows the system to implement a flexible register mapping scheme using a single namespace. The compiler may then assign register live ranges to register addresses, and the compiler may use a register allocation mechanism to minimize or reduce the number of registers used per thread. In an embodiment, multiple live ranges may be assigned to the same register address as long as the live ranges do not overlap. This allows, for example, to determine at runtime and after the instruction has been compiled how many entries per thread will be allocated in the low energy portion and the high capacity portion relative thereto. For example, the system may map 100% of the register addresses of threads 0-30 to the low energy portion, and 100% of the register addresses of threads 31-127 to the high capacity portion. As another example, the system may map 20% of the registers of each thread to the low energy portion, and 80% of the registers of each thread to the high capacity portion. The system may determine the number of entries allocated per thread based on runtime information, for example, about the number of thread groups in execution, and the marginal benefits obtained from starting more thread groups or allocating more space in the low energy portion to a smaller number of thread groups.

[0158] Fig.10 A block diagram of a parallel processing system 1000 is shown according to one embodiment. System 1000 includes a parallel processing (previously presented) subsystem 1002, which in turn includes one or more parallel processing units (PPUs) PPU-0 through PPU-P. Each PPU is coupled to a local parallel processing (PP) memory (e.g., MEM-0 through MEM-P, respectively). In some embodiments, PP subsystem system 1002 may include P number of PPUs. PPU-0 1004 and parallel processing memory 1006 may be implemented using one or more integrated circuit devices such as a programmable processor, an application specific integrated circuit (ASIC), or a memory device.

[0159] See also Fig.10 , several optional switches or connections 1007 are shown that can be used in system 1000 to manage power. Although several switches 1007 are shown, embodiments are not limited to the specific switches shown, and more or fewer switches may be used depending on the implementation. These connections / switches 1007 can be used for clock gating or general power gating. Thus, item 1007 may include one or more of power transistors, on-die switches, power plane connections, etc. In an embodiment, before power is turned off to a portion of system 1000 via switch / connection 1007, logic (e.g., a microcontroller, a digital signal processor, firmware, etc.) can ensure that the results of the operation are committed (e.g., to memory) or completed to maintain correctness.

[0160] Further, in some embodiments, one or more of the PPUs in the parallel processing subsystem 1002 is a graphics processor with a rendering pipeline that can be configured to perform various tasks, such as those discussed herein with respect to other figures. Graphics information / data can be communicated with other components of the computing system (including components of the system 1000) via a memory bridge 1008. Data can be transmitted via a shared bus and / or one or more interconnects 1010 (including, for example, one or more direct or point-to-point links). PPU-0 1004 can access its local parallel processing memory 1014 (which can be used as a graphics memory including, for example, a frame buffer) to store and update pixel data, deliver pixel data to a display device (such as those discussed herein), etc. In some embodiments, the parallel processing subsystem 1002 may include one or more PPUs operating as graphics processors, and one or more other PPUs operating to perform general-purpose computations. The PPUs may be the same or different, and each PPU may access its own dedicated parallel processing memory device(s), non-dedicated parallel processing memory device(s), or a shared memory device or cache.

[0161] In an embodiment, the operations performed by the PPUs may be controlled by another processor (or one of the PPUs), which is often referred to as a main processor or processor core. In one embodiment, the main processor / core may write a command stream for each PPU to a push buffer in various locations (such as main system memory, cache, or other memory such as those discussed herein with reference to other figures). The written commands may then be read by each PPU and executed asynchronously with respect to the operations of the main processor / core.

[0162] In addition, if Fig.10 As shown in , PPU-0 includes front-end logic 1020, which may include an input / output (I / O or IO) unit (e.g., to communicate with other components of system 1000 through memory bridge 1008) and / or a host interface (e.g., which receives commands related to processing tasks). Front-end 1020 can receive commands read by the host interface (e.g., from a push buffer). Front-end 1020 in turn provides the command to a work scheduling unit 1022, which schedules and distributes the operation(s) / task(s) associated with the command to a processing cluster array or arithmetic subsystem 1024 for execution.

[0163] like Fig.10As shown in , the processing cluster array 1024 may include one or more general processing cluster (GPC) units (e.g., GPC-0 1026, GPC-1 1028 to GPC-M 1030). Each GPC may be capable of executing a large number (e.g., hundreds or thousands) of threads simultaneously, where each thread is an instance of a program. In various applications, different GPCs may be allocated for processing different types of programs or for performing different types of calculations. For example, in a graphics application, a first group of GPCs (e.g., including one or more GPC units) may be allocated to perform tessellation operations and generate primitive topology for a patch, and a second group of GPCs (e.g., including one or more GPC units) may be allocated to perform tessellation shading to evaluate patch parameters of the primitive topology and determine vertex positions and other per-vertex attributes. The allocation of GPCs may vary depending on the workload generated by each type of program or calculation.

[0164] In addition, the processing tasks assigned by the work scheduling unit 1022 may include an index of data to be processed, such as surface / patch data, primitive data, vertex data, pixel data, and / or state parameters and commands that define how the data is to be processed (e.g., what program to execute). The work scheduling unit 1022 may be configured to obtain an index corresponding to the task, or may receive the index from the front end 1020. The front end 1020 may also ensure that the GPC is configured to a valid state before starting the processing specified by the push buffer.

[0165] In one embodiment, communication path 1012 is a peripheral component interface (PCI) Express (or PCI-e) link in which a dedicated lane can be allocated to each PPU. Other communication paths may also be used. For example, commands related to processing tasks may be directed to host interface 1018, while commands related to memory operations (e.g., reading from or writing to parallel processing memory 1014) may be directed to memory crossbar unit 1032.

[0166] In some embodiments, parallel processing subsystem 1002 may be implemented as an add-in card that is inserted into an expansion slot of a computer system or server (such as a blade server). In other embodiments, the PPU may be integrated on a single chip with a bus bridge (such as memory bridge 1008, I / O bridge, etc.). In still other embodiments, some or all components of the PPU may be integrated on a single integrated circuit chip with one or more other processor cores, memory devices, caches, etc.

[0167] Furthermore, one of the main problems with modern processors today is that they have a clock rate limit at about 4GHz. At this point, they simply generate too much heat for current technology and require special and expensive cooling solutions. This is because as we increase the clock rate, the power consumption goes up. In fact, if you fix the voltage, the power consumption of the CPU is roughly the cube of the clock rate. To make this worse, as you increase the heat generated by the CPU, due to the properties of silicon, for the same clock rate, the power consumption is also increasing. Converting power into heat is a complete waste of energy. This increasingly inefficient use of power eventually means that you are not able to adequately power or cool the processor, and you reach the thermal limit of the device or its housing, the so-called power wall.

[0168] Faced with the problem of making ever-faster processors without being able to increase clock rates, processor manufacturers have had to come up with another countermeasure. Rather than continually trying to increase CPU clock rates and / or extract more instructions per clock, they have been forced to take the route of adding more cores to the processor via instruction-level parallelism.

[0169] Additionally, power usage is an important consideration when designing a machine that is constantly running. Often, the cost of operating a supercomputer in just a few years can equal the cost of installing it in the first place. Of course, the cost of running such a machine over its lifetime will easily exceed the original installation cost. Power usage comes from the components themselves, but also from the cooling that is necessary to allow such a computer to operate. Even a high-end workstation with four GPUs requires some planning on how to keep it cool. Unless you live in a cold climate and can move your computer out to the cold, it will do a pretty good job of heating up your office. Put a few of these machines in a room, and the air temperature in that room will very quickly start to rise to quite unacceptable levels.

[0170] Therefore, a lot of power is spent on installing air conditioning systems to ensure that the computers stay cool and can operate without generating errors. This is especially true in the summer when temperatures can reach 85℉ / 30℃ or higher. Air conditioning is expensive to operate. Deep thought should be given to how to best cool such a system and whether the heat energy can be reused in some way. Liquid cooling systems are very effective in this regard because the liquid can be circulated through the heat exchanger and into the conventional heating system without any chance of the two liquids mixing. With the ever-increasing cost of natural resources, and the increasing pressure on businesses to be seen as green businesses, it is no longer economically or socially acceptable to simply pump the heat out the window.

[0171] Liquid cooling systems offer interesting options in terms of recycling waste heat energy. While an air cooling system can only be used to heat the immediate area in which it is located, the heat from the liquid coolant can be pumped elsewhere. By using a heat exchanger, conventional water can be used to cool the coolant. This can then be pumped into a heating system or even used to heat an outdoor swimming pool or other large body of water. When several such systems are installed, such as in a corporate or university computer center, it makes sense to use this waste heat energy to reduce heating bills elsewhere in the organization.

[0172] Many supercomputer installations are sited next to major rivers precisely because they need a ready supply of chilled water. Others use large cooling towers to dissipate waste heat energy. Neither solution is particularly green. Having already paid for the energy, there is no point in simply throwing it away when it could just as easily be used for heating. When considering power usage, we must also remember that program design actually plays a very important role in power consumption. The most expensive operation in terms of power is moving data onto and off the chip. Therefore, simply making efficient use of registers and shared memory within the device greatly reduces power usage. If you also consider that the total execution time of a well-written program is much smaller than that of a poorly written program, then you can see that rewriting old programs to take advantage of new features such as larger shared memories can reduce the cost of running even large data centers.

[0173] See also Fig.10 , the memory interface 1014 includes N partition units (e.g., Unit-0 1034, Unit-1 1036 to Unit-N 1038), each of which is directly coupled to a corresponding portion of the parallel processing memory 1006 (e.g., Mem-0 1040, Mem-1 1042 to Mem-N 1044). The number of partition units can generally be equal to the number of previously presented memories (or N as shown). The previously presented memories can be implemented using volatile memories such as dynamic random access memories (DRAM) or other types of volatile memories such as those discussed herein. In other embodiments, the number of partition units may not be equal to the number of memory devices. Graphics data (such as render targets, frame buffers, or texture maps) can be stored throughout the previously presented memory devices, allowing the partition units to write portions of the graphics data in parallel to efficiently use the available bandwidth of the parallel processing memory 1006.

[0174] In addition, any of the GPCs can process data to be written to any of the partition units within the parallel processing memory. A crossbar unit 1032 can be implemented as an interconnect that is configured to route the output of each GPC to the input of any partition unit or to another GPC for further processing. Thus, GPCs 1026 to 1030 can communicate with the memory interface 1014 through the crossbar unit 1032 to read from or write to various other (or external) memory devices. As shown, the crossbar unit 1032 can communicate directly with the front end 1020 and has a coupling (direct or indirect) to the local memory 1006 to allow processing cores within different GPCs to communicate with system memory and / or other memories that are not local to the PPU. In addition, the crossbar unit 1032 can utilize virtual channels to organize information flows (traffic streams) between GPCs and partition units.

[0175] System Overview

[0176] Fig.11 1 is a block diagram of a processing system 1100 according to an embodiment. In various embodiments, the system 1100 includes one or more processors 1102 and one or more graphics processors 1108, and may be a single processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 1102 or processor cores 1107. In one embodiment, the system 1100 is a processing platform incorporated into a system on a chip (SoC) integrated circuit for use in a mobile device, handheld device, or embedded device.

[0177] Embodiments of system 1100 may include or incorporate a server-based game platform, a game console, including a game and media console, a mobile game console, a handheld game console, or an online game console. In some embodiments, system 1100 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. Data processing system 1100 may also include a wearable device (such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device), coupled to the wearable device, or integrated in the wearable device. In some embodiments, data processing system 1100 is a television or set-top box device having one or more processors 1102 and a graphical interface generated by one or more graphics processors 1108.

[0178] In some embodiments, one or more processors 1102 each include one or more processor cores 1107 for processing instructions, which perform the operation of the system and user software when executed. In some embodiments, each processor core in the one or more processor cores 1107 is configured to process a specific instruction set 1109. In some embodiments, the instruction set 1109 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 1107 can each process different instruction sets 1109, and the instruction set may include instructions for facilitating emulation of other instruction sets. The processor core 1107 may also include other processing devices, such as a digital signal processor (DSP).

[0179] In some embodiments, the processor 1102 includes a cache memory 1104. Depending on the architecture, the processor 1102 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among the components of the processor 1102. In some embodiments, the processor 1102 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), and known cache coherence techniques may be used to share the external cache among the processor cores 1107. Additionally, a register file 1106 is included in the processor 1102, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 1102.

[0180] In some embodiments, the processor 1102 is coupled to a processor bus 1110, which is used to transmit communication signals, such as address, data, or control signals, between the processor 1102 and other components within the system 1100. In one embodiment, the system 1100 uses an exemplary 'hub' system architecture, including a memory controller hub 1116 and an input-output (I / O) controller hub 1130. The memory controller hub 1116 facilitates communication between memory devices and other components of the system 1100, while the I / O controller hub (ICH) 1130 provides connections to I / O devices via a local I / O bus. In one embodiment, the logic of the memory controller hub 1116 is integrated within the processor.

[0181] The memory device 1120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable properties for use as processing memory. In one embodiment, the memory device 1120 may operate as system memory for the system 1100 to store data 1122 and instructions 1121 for use when one or more processors 1102 execute applications or processes. The memory controller hub 1116 is also coupled to an optional external graphics processor 1112, which may communicate with one or more graphics processors 1108 in the processor 1102 to perform graphics and media operations.

[0182] In some embodiments, the ICH 1130 enables peripheral components to be connected to the memory devices 1120 and the processor 1102 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 1146, a firmware interface 1128, a wireless transceiver 1126 (e.g., Wi-Fi, Bluetooth), a data storage device 1124 (e.g., a hard drive, flash memory, etc.), and a traditional I / O controller 1140 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1142 connect multiple input devices, such as a keyboard and mouse 1144 combination. A network controller 1134 may also be coupled to the ICH 1130. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 1110. It should be understood that the system 1100 shown is exemplary and not limiting, as other types of data processing systems configured in different ways may also be used. For example, I / O controller hub 1130 may be integrated within one or more processors 1102 , or memory controller hub 1116 and I / O controller hub 1130 may be integrated within a discrete external graphics processor, such as external graphics processor 1112 .

[0183] Fig.12 is a block diagram of an embodiment of a processor 1200 having one or more processor cores 1202A- 1202N, an integrated memory controller 1214 , and an integrated graphics processor 1208 . Fig.12Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Processor 1200 may include additional cores up to and including additional core 1202N represented by a dashed box. Processor cores 1202A to 1202N each include one or more internal cache units 1204A to 1204N. In some embodiments, each processor core may also access one or more shared cache units 1206.

[0184] Internal cache units 1204A to 1204N and shared cache unit 1206 represent a cache memory hierarchy within processor 1200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache is classified as LLC before external memory. In some embodiments, cache coherence logic maintains coherence between each cache unit 1206 and 1204A to 1204N.

[0185] In some embodiments, the processor 1200 may further include a set of one or more bus controller units 1216 and a system agent core 1210. The one or more bus controller units 1216 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 1210 provides management functions for each processor component. In some embodiments, the system agent core 1210 includes one or more integrated memory controllers 1214 for managing access to each external memory device (not shown).

[0186] In some embodiments, one or more of the processor cores 1202A to 1202N include support for simultaneous multithreading. In such embodiments, the system agent core 1210 includes components for coordinating and operating the cores 1202A to 1202N during multithreaded processing. In addition, the system agent core 1210 may also include a power control unit (PCU) including logic and components for regulating the power state of the processor cores 1202A to 1202N and the graphics processor 1208.

[0187] In some embodiments, in addition, the processor 1200 further includes a graphics processor 1208 for performing graphics processing operations. In some embodiments, the graphics processor 1208 is coupled to a set of shared cache units 1206 and a system agent core 1210, which includes one or more integrated memory controllers 1214. In some embodiments, a display controller 1211 is coupled to the graphics processor 1208 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 1211 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within the graphics processor 1208 or the system agent core 1210.

[0188] In some embodiments, a ring-based interconnect unit 1212 is used to couple the internal components of the processor 1200. However, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those well known in the art. In some embodiments, the graphics processor 1208 is coupled to the ring interconnect 1212 via an I / O link 1213.

[0189] Exemplary I / O links 1213 represent at least one of a plurality of varieties of I / O interconnects, including package I / O interconnects that facilitate communication between various processor components and high-performance embedded memory modules 1218 (such as eDRAM modules). In some embodiments, each of processor cores 1202A to 1202N and graphics processor 1208 use embedded memory modules 1218 as a shared last-level cache.

[0190] In some embodiments, processor cores 1202A to 1202N are homogeneous cores that execute the same instruction set architecture. In another embodiment, processor cores 1202A to 1202N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of processor cores 1202A to 1202N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 1202A to 1202N are homogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In addition, processor 1200 may be implemented on one or more chips or as a SoC integrated circuit having the components shown in addition to other components.

[0191] Fig.131 is a block diagram of a graphics processor 1300, which may be a discrete graphics processing unit or may be a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates with memory via a mapped I / O interface to registers on the graphics processor and using commands placed in processor memory. In some embodiments, the graphics processor 1300 includes a memory interface 1314 for accessing memory. The memory interface 1314 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0192] In some embodiments, the graphics processor 1300 also includes a display controller 1302 for driving display output data to a display device 1320. The display controller 1302 includes hardware for one or more overlapping planes of the display and a composition of multiple layers of video or user interface elements. In some embodiments, the graphics processor 1300 includes a video codec engine 1306 for encoding, decoding, or media transcoding to, from, or between one or more media encoding formats, including but not limited to: Moving Picture Experts Group (MPEG) (such as MPEG-2), Advanced Video Coding (AVC) format (such as H.264 / MPEG-4 AVC), and Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) format (such as JPEG, and Motion JPEG (MJPEG) format).

[0193] In some embodiments, graphics processor 1300 includes a block image transfer (BLIT) engine 1304 for performing two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 1310. In some embodiments, GPE 1310 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0194] In some embodiments, GPE 1310 includes a 3D pipeline 1312 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 1312 includes programmable and fixed functional elements that perform various tasks within the elements and / or generated execution threads to 3D / media subsystem 1315. Although 3D pipeline 1312 can be used to perform media operations, embodiments of GPE 1310 also include a media pipeline 1316 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0195] In some embodiments, the media pipeline 1316 includes fixed-function or programmable logic units to replace or perform one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, on behalf of the video codec engine 1306. In some embodiments, in addition, the media pipeline 1316 also includes a thread generation unit to generate threads for execution on the 3D / media subsystem 1315. The generated threads perform calculations for media operations on one or more graphics execution units included in the 3D / media subsystem 1315.

[0196] In some embodiments, the 3D / media subsystem 1315 includes logic for executing threads generated by the 3D pipeline 1312 and the media pipeline 1316. In one embodiment, the pipeline sends thread execution requests to the 3D / media subsystem 1315, which includes thread dispatch logic for arbitrating and dispatching each request to available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 1315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and for storing output data.

[0197] Graphics processing engine

[0198] Fig.14 is a block diagram of a graphics processing engine 1410 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 1410 is Fig.13 A version of the GPE 1810 is shown. Fig.14 Those elements having the same reference number (or name) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Fig.13 1410. The 3D pipeline 1312 and the media pipeline 1316 of the GPE 1410. The media pipeline 1316 is optional in some embodiments of the GPE 1410 and may not be explicitly included in the GPE 1410. For example and in at least one embodiment, separate media and / or image processors are coupled to the GPE 1410.

[0199] In some embodiments, GPE 1410 is coupled to or includes a command stream converter 1403, which provides a command stream to 3D pipeline 1312 and / or media pipeline 1316. In some embodiments, command stream converter 1403 is coupled to a memory, which may be a system memory, or one or more cache memories of an internal cache memory and a shared cache memory. In some embodiments, command stream converter 1403 receives commands from the memory and sends these commands to 3D pipeline 1312 and / or media pipeline 1316. The commands are instructions obtained from a ring buffer storing commands for 3D pipeline 1312 and media pipeline 1316. In one embodiment, in addition, the ring buffer may also include a batch command buffer storing multiple batches of multiple commands. Commands for 3D pipeline 1312 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 1312 and / or image data and memory objects for media pipeline 1316. The 3D pipeline 1312 and the media pipeline 1316 process the commands by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the execution unit array 1414 .

[0200] In various embodiments, the 3D pipeline 1312 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 1414. The graphics core array 1414 provides a unified execution resource block. The multi-purpose execution logic (e.g., execution unit) within the graphics core array 1414 includes support for various 3D API shader languages ​​and can execute multiple simultaneous execution threads associated with multiple shaders.

[0201] In some embodiments, graphics core array 1414 also includes execution logic for performing media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution unit also includes general logic that can be programmed to perform parallel general computing operations. The general logic can be connected to Figure 1 (multiple) processor cores 107 or Fig.12 The general logic within cores 1202A to 1202N in the process performs processing operations in parallel or in combination.

[0202] Output data generated by threads executing on graphics core array 1414 can output data to memory in unified return buffer (URB) 1418. URB 1418 can store data for multiple threads. In some embodiments, URB 1418 can be used to send data between different threads executing on graphics core array 1414. In some embodiments, URB 1418 can also be used for synchronization between threads on the graphics core array and fixed function logic within shared function logic 1420.

[0203] In some embodiments, graphics core array 1414 is scalable such that the array includes a variable number of graphics cores each having a variable number of execution units based on the target power and performance level of GPE 1410. In one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0204] The graphics core array 1414 is coupled to a shared function logic 1420, which includes a plurality of resources shared between the graphics cores in the graphics core array. The shared functions within the shared function logic 1420 are hardware logic units that provide specialized supplementary functions to the graphics core array 1414. In various embodiments, the shared function logic 1420 includes, but is not limited to, a sampler 1421, math 1422, and inter-thread communication (ITC) 1423 logic. In addition, some embodiments implement one or more caches 1425 within the shared function logic 1420. The shared functions are implemented in situations where the demand for a given specialized function is insufficient to be included in the graphics core array 1414. Instead, a single instance of the specialized function is implemented as an independent entity in the shared function logic 1420 and shared between execution resources within the graphics core array 1414. The exact set of functions shared between and included within the graphics core array 1414 varies between embodiments.

[0205] Fig.15 is a block diagram of another embodiment of a graphics processor 1500 . Fig.15 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0206] In some embodiments, graphics processor 1500 includes ring interconnect 1502, pipeline front end 1504, media engine 1537, and graphics cores 1580A to 1580N. In some embodiments, ring interconnect 1502 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of multiple processors integrated into a multi-core processing system.

[0207] In some embodiments, the graphics processor 1500 receives batches of commands via a ring interconnect 1502. The incoming commands are interpreted by a command stream converter 1503 in a pipeline front end 1504. In some embodiments, the graphics processor 1500 includes scalable execution logic for performing 3D geometry processing and media processing via (multiple) graphics cores 1580A to 1580N. For 3D geometry processing commands, the command stream converter 1503 supplies the commands to a geometry pipeline 1536. For at least some media processing commands, the command stream converter 1503 supplies the commands to a video front end 1534, which is coupled to a media engine 1537. In some embodiments, the media engine 1537 includes a video quality engine (VQE) 1530 for video and image post-processing and a multi-format encoding / decoding (MFX) 1533 engine for providing hardware accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 1536 and the media engine 1537 each generate an execution thread, which is used for thread execution resources provided by at least one graphics core 1580A.

[0208] In some embodiments, the graphics processor 1500 includes an extensible thread execution resource characterization module core 1580A to 1580N (sometimes referred to as a core slice), each of which has a plurality of sub-cores 1550A to 550N, 1560A to 1560N (sometimes referred to as a core sub-slice). In some embodiments, the graphics processor 1500 may have any number of graphics cores 1580A to 1580N. In some embodiments, the graphics processor 1500 includes a graphics core 1580A, which has at least a first sub-core 1550A and a second sub-core 1560A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 1550A). In some embodiments, the graphics processor 1500 includes a plurality of graphics cores 1580A to 1580N, each of which includes a group of first sub-cores 1550A to 1550N and a group of second sub-cores 1560A to 1560N. Each of the group of first sub-cores 1550A to 1550N includes at least a first group of execution units 1552A to 1552N and media / texture samplers 1554A to 1554N. Each of the group of second sub-cores 1560A to 1560N includes at least a second group of execution units 1562A to 1562N and samplers 1564A to 1564N. In some embodiments, each sub-core 1550A to 1550N, 1560A to 1560N shares a group of shared resources 1570A to 1570N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0209] Execution Unit

[0210] Fig.16 Thread execution logic 1600 is shown, comprising an array of processing elements employed in some embodiments of a GPE. Fig.16 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0211] In some embodiments, thread execution logic 1600 includes a shader processor 1602, a thread dispatcher 1604, an instruction cache 1606, a scalable execution unit array including a plurality of execution units 1608A to 1608N, a sampler 1610, a data cache 1612, and a data port 1614. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any one of execution units 1608A, 1608B, 1608C, 1608D, up to 1608N-1 and 1608N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, thread execution logic 1600 includes one or more connections to a memory (e.g., system memory or cache memory) through one or more of the instruction cache 1606, the data port 1614, the sampler 1610, and the execution unit array 1608A to 1608N. In some embodiments, each execution unit (e.g., 1608A) is an independently programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 1608A to 1608N is scalable to include any number of separate execution units.

[0212] In some embodiments, execution units 1608A to 1608N are primarily used to execute shader programs. Shader processor 1602 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 1604. In one embodiment, thread dispatcher includes logic for arbitrating thread initiation requests from graphics and media pipelines and instantiating the requested threads on one or more execution units 1608A to 1608N. For example, the geometry pipeline (e.g., Fig.15 1536) can dispatch vertex processing, tessellation or geometry processing threads to thread execution logic 1600 ( Fig.16) for processing. In some embodiments, thread dispatcher 1604 can also process runtime thread generation requests from executing shader programs.

[0213] In some embodiments, execution units 1608A to 1608N support instruction sets (including native support for many standard 3D graphics shader instructions) so that shader programs from graphics libraries (e.g., Direct3D and OpenGL) are executed with minimal conversion. These execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., compute and media shaders). Each of execution units 1608A to 1608N is capable of performing multi-issue single instruction multiple data (SIMD), and multi-threaded operations can achieve an efficient execution environment in the face of high latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. For pipelines with integer, single-precision floating-point operations and double-precision floating-point operations, SIMD branch functions, logical operations, transcendental operations, and other miscellaneous operations, execution is multiple issues per clock. While waiting for data from memory or one of the shared functions, dependency logic within execution units 1608A to 1608N puts the waiting thread to sleep until the requested data has returned. While the waiting thread is sleeping, hardware resources may be dedicated to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit may execute operations of a pixel shader, a fragment shader, or another type of shader program including a different vertex shader.

[0214] Each of the execution units 1608A to 1608N operates on an array of data elements. The number of data elements is the "execution size," or number of channels of an instruction. An execution channel is a logical unit that performs data element access, masking, and flow control within an instruction. The number of channels may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In some embodiments, the execution units 1608A to 1608N support integer and floating point data types.

[0215] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compressed data types, and the execution unit will process various elements based on the data size of the element. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four separate 64-bit compressed data elements (data elements of quadruple word length (QW) size), eight separate 32-bit compressed data elements (data elements of double word length (DW) size), sixteen separate 16-bit compressed data elements (data elements of word length (W) size), or thirty-two separate 8-bit data elements (data elements of byte (B) size). However, different vector widths and register sizes are possible.

[0216] One or more internal instruction caches (e.g., 1606) are included in the thread execution logic 1600 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 1612) are included to cache thread data during thread execution. In some embodiments, a sampler 1610 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 1610 includes a specialized texture or media sampling function to process texture or media data during the sampling process before providing the sampled data to the execution unit.

[0217] During execution, the graphics and media pipeline sends a thread initiation request to the thread execution logic 1600 via the thread generation and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 1602 is called to further calculate output information and cause the result to be written to the output surface (e.g., color buffer, depth buffer, stencil printing buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates the value of each vertex attribute, which is interpolated across the rasterized object. In some embodiments, the pixel processor logic within the shader processor 1602 then executes the pixel or fragment shader program supplied by the application programming interface (API). In order to execute the shader program, the shader processor 1602 dispatches the thread to the execution unit (e.g., 1608A) via the thread dispatcher 1604. In some embodiments, the pixel shader 1602 uses the texture sampling logic in the sampler 1610 to access the texture data in the texture map stored in the memory. Arithmetic operations on texture data and input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels without further processing.

[0218] In some embodiments, data port 1614 provides a memory access mechanism for thread execution logic 1600 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 1614 includes or is coupled to one or more cache memories (e.g., data cache 1612) to cache data via the data port for memory access.

[0219] Fig.17 1 is a block diagram illustrating a graphics processor instruction format 1700 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid line boxes illustrate components that are typically included in execution unit instructions, while dashed lines include optional components or components that are only included in a subset of instructions. In some embodiments, the instruction format 1700 described and illustrated are macroinstructions because they are instructions supplied to the execution unit, as opposed to micro-operations generated from instruction decoding (once the instruction is processed).

[0220] In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit instruction format 1710. A 64-bit compact instruction format 1730 may be used for some instructions based on the selected instruction, multiple instruction options, and the number of operands. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are limited to 64-bit format 1730. The native instructions available in 64-bit format 1730 vary according to the embodiment. In some embodiments, the instructions are partially compressed using a set of index values ​​in index field 1713. The execution unit hardware references a set of compression tables based on the index values ​​and uses the compression table output to reconstruct the native instructions in 128-bit instruction format 1710.

[0221] For each format, the instruction opcode 1712 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a synchronous add operation across each color channel, and the color channel represents a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 1714 enables control of certain execution options, such as channel selection (e.g., prediction) and data channel sorting (e.g., mixing). For instructions using the 128-bit instruction format 1710, the execution size field 1716 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 1716 is not available for the 64-bit compact instruction format 1730.

[0222] Some execution unit instructions have up to three operands, including two source operands (src0 1720, src1 1722) and a destination 1718. In some embodiments, the execution unit supports dual destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 1724), where the instruction opcode 1712 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0223] In some embodiments, the 128-bit instruction format 1710 includes an access / address mode field 1726, which defines, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction.

[0224] In some embodiments, the 128-bit instruction format 1710 includes an access / address mode field 1726 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes, including 16-byte aligned access modes and 1-byte aligned access modes, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction can use byte-aligned addressing for source operands and destination operands, and when in a second mode, the instruction can use 16-byte aligned addressing for all source operands and destination operands.

[0225] In one embodiment, the address mode portion of the access / address mode field 1726 determines whether the instruction uses direct addressing or indirect addressing. When direct register addressing mode is used, the bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0226] In some embodiments, instructions are grouped based on the opcode 1712 bit field to simplify opcode decoding 1740. For 8-bit opcodes, the 4th, 5th, and 6th bits allow the execution unit to determine the type of opcode. The precise opcode grouping shown is exemplary only. In some embodiments, the move and logic opcode group 1742 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 1742 shares five most significant bits (MSBs), wherein the move (mov) instruction adopts the form of 0000xxxxb, and the logic instruction adopts the form of 0001xxxxb. The flow control instruction group 1744 (e.g., call (call), jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 1746 includes a mixture of instructions, including synchronization instructions (e.g., wait (wait), send (send)) in the form of 0011xxxxb (e.g., 0x30). The parallel math instruction group 1748 includes component-wise arithmetic instructions (e.g., add, mul) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 1748 performs arithmetic operations in parallel across data lanes. The vector math group 1750 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic operations on vector operands, such as dot product operations.

[0227] Graphics Pipeline

[0228] Fig.18 is a block diagram of another embodiment of a graphics processor 1800 . Fig.18 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0229] In some embodiments, graphics processor 1800 includes graphics pipeline 1820, media pipeline 1830, display engine 1840, thread execution logic 1850, and rendering output pipeline 1870. In some embodiments, graphics processor 1800 is a graphics processor within a multi-core processing system including one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to graphics processor 1800 via ring interconnect 1802. In some embodiments, ring interconnect 1802 couples graphics processor 1800 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 1802 are interpreted by command stream converter 1803, which supplies instructions to individual components of graphics pipeline 1820 or media pipeline 1830.

[0230] In some embodiments, command stream converter 1803 directs the operation of vertex fetcher 1805, which reads vertex data from memory and executes vertex processing commands provided by command stream converter 1803. In some embodiments, vertex fetcher 1805 provides vertex data to vertex shader 1807, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex fetcher 1805 and vertex shader 1807 execute vertex processing instructions by dispatching execution threads to execution units 1852A to 1852B via thread dispatcher 1831.

[0231] In some embodiments, execution units 1852A-1852B are vector processor arrays with instruction sets for performing graphics and media operations. In some embodiments, execution units 1852A-1852B have an attached L1 cache 1851 that is dedicated to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0232] In some embodiments, the graphics pipeline 1820 includes a tessellation component for performing hardware accelerated tessellation of 3D objects. In some embodiments, the programmable hull shader 811 configures the tessellation operation. The programmable domain shader 817 provides back-end evaluation of the tessellation output. The tessellation 1813 operates at the direction of the hull shader 1811 and contains dedicated logic for generating a detailed set of geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline 1820. In some embodiments, if tessellation is not used, the tessellation components (e.g., hull shader 1811, tessellation 1813, domain shader 1817) can be bypassed.

[0233] In some embodiments, the complete geometric object may be processed by the geometry shader 1819 via one or more threads dispatched to the execution units 1852A-1852B, or may proceed directly to the clipper 1829. In some embodiments, the geometry shader operates on entire geometric objects (rather than vertices or vertex patches as in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 1819 receives input from the vertex shader 1807. In some embodiments, the geometry shader 1819 may be programmed by a geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0234] Before rasterization, the clipper 1829 processes the vertex data. The clipper 1829 can be a fixed function clipper or a programmable clipper with clipping and geometry shader functions. In some embodiments, the rasterizer and depth test component 1873 in the render output pipeline 1870 dispatches a pixel shader to convert the geometric object into its per-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 1850. In some embodiments, the application can bypass the rasterizer and depth test component 1873 and access the unrasterized vertex data via the outflow unit 1823.

[0235] The graphics processor 1800 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed among the main components of the graphics processor. In some embodiments, execution units 1852A-1852B and associated cache(s) 1851, texture and media samplers 1854, and texture / sampler cache 1858 are interconnected via data ports 1856 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, samplers 1854, caches 1851, 1858, and execution units 1852A-1852B each have separate memory access paths.

[0236] In some embodiments, the rendering output pipeline 1870 includes a rasterizer and a depth test component 1873, which converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a window device / masker unit for performing fixed-function triangle and line rasterization. An associated rendering cache 1878 and a depth cache 1879 are also available in some embodiments. A pixel operation component 1877 performs pixel-based operations on data, but in some instances, pixel operations associated with 2D operations (e.g., using mixed bit block image transfer) are performed by the 2D engine 1841, or replaced by an overlapping display plane by a display controller 1843 at display time. In some embodiments, a shared L3 cache 1875 can be used for all graphics components, thereby allowing data to be shared without using the main system memory.

[0237] In some embodiments, the graphics processor media pipeline 1830 includes a media engine 1837 and a video front end 1834. In some embodiments, the video front end 1834 receives pipeline commands from the command stream converter 1803. In some embodiments, the media pipeline 1830 includes a separate command stream converter. In some embodiments, the video front end 1834 processes the media commands before sending the commands to the media engine 1837. In some embodiments, the media engine 1837 includes a thread generation function for generating threads for dispatching to the thread execution logic 1850 via the thread dispatcher 1831.

[0238] In some embodiments, the graphics processor 1800 includes a display engine 1840. In some embodiments, the display engine 1840 is external to the processor 1800 and is coupled to the graphics processor via a ring interconnect 1802, or some other interconnect bus or mechanism. In some embodiments, the display engine 1840 includes a 2D engine 1841 and a display controller 1843. In some embodiments, the display engine 1840 includes dedicated logic that can operate independently of the 3D pipeline. In some embodiments, the display controller 1843 is coupled to a display device (not shown), which can be a system integrated display device (such as in a laptop computer), or an external display device attached via a display device connector.

[0239] In some embodiments, graphics pipeline 1820 and media pipeline 1830 can be configured to perform operations based on multiple graphics and media programming interfaces and are not dedicated to any application programming interface (API). In some embodiments, the driver software of the graphics processor converts the API dispatch dedicated to a specific graphics or media library into a command that can be processed by the graphics processor. In some embodiments, support is provided for all open graphics libraries (OpenGL), open computing language (OpenCL) and / or Vulkan graphics and computing APIs from Khronos Group. In some embodiments, support can also be provided for the Direct3D library of Microsoft Corporation. In some embodiments, the combination of these libraries can be supported. Support can also be provided for the open source computer vision library (OpenCV). If a mapping from the pipeline of future API to the pipeline of graphics processor can be made, the future API with compatible 3D pipelines will also be supported.

[0240] Graphics Pipeline Programming

[0241] Fig.19A is a block diagram illustrating a graphics processor command format 1900 according to some embodiments. Fig.19B is a block diagram illustrating a graphics processor command sequence 1910 according to an embodiment. Fig.19A The solid-line boxes in show components that are typically included in a graphics command, while the dashed lines include components that are optional or included only in a subset of the graphics commands. Fig.19A The exemplary graphics processor command format 1900 includes a data field for identifying the target client 1902 of the command, a command operation code (opcode) 1904, and associated data 1906 for the command. Some commands also include a sub-opcode 1905 and a command size 1908.

[0242] In some embodiments, client 1902 defines a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser checks the client field of each command to adjust further processing of the command and routes the command data to a suitable client unit. In some embodiments, a graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing the command. Once the command is received by the client unit, the client unit reads the opcode 1904 and the sub-opcode 1905 (if present) to determine the operation to be performed. The client unit uses the information in the data field 1906 to execute the command. For some commands, it is expected that the command size 1908 explicitly defines the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands in the command based on the command opcode. In some embodiments, the command is aligned via multiples of the double word length.

[0243] Fig.19B An exemplary graphics processor command sequence 1910 is shown in the flowchart in FIG. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses the version of the command sequence shown to initiate, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for exemplary purposes only, as the embodiments are not limited to these specific commands or this command sequence. Moreover, the commands may be issued as a batch of commands in a command sequence so that the graphics processor will process the command sequence in an at least partially simultaneous manner.

[0244] In some embodiments, the graphics processor command sequence 1910 may begin with a pipeline flush command 1912 to cause any active graphics pipeline to complete currently pending commands for that pipeline. In some embodiments, the 3D pipeline 1922 and the media pipeline 1924 are not operating simultaneously. The pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to the pipeline flush, the command parser for the graphics processor will stop command processing until the active drawing engine completes pending operations and invalidates the associated read cache. Optionally, any data marked as 'dirty' in the render cache may be flushed to memory. In some embodiments, the pipeline flush command 1912 may be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0245] In some embodiments, pipeline select command 1913 is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, pipeline select command 1913 is only required once in an execution context before issuing pipeline commands, unless the context is to issue commands for two pipelines. In some embodiments, pipeline flush command 1912 is required just before a pipeline switch via pipeline select command 1913.

[0246] In some embodiments, pipeline control commands 1914 configure the graphics pipeline for operation and are used to program the 3D pipeline 1922 and the media pipeline 124. In some embodiments, pipeline control commands 1914 configure the pipeline state of the active pipeline. In one embodiment, pipeline control commands 1914 are used for pipeline synchronization and for clearing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0247] In some embodiments, return buffer state command 1916 is used to configure a set of return buffers for corresponding pipelines to write data. Some pipeline operations require allocating, selecting, or configuring one or more return buffers into which the operation writes intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, return buffer state 1916 includes selecting the size and number of return buffers to use for the set of pipeline operations.

[0248] The remaining commands in the command sequence differ based on the active pipeline for operation. Based on pipeline decision 1920 , the command sequence is tailored for either the 3D pipeline 1922 starting at 3D pipeline state 1930 , or the media pipeline 1924 starting at media pipeline state 1940 .

[0249] Commands for 3D pipeline state 1930 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, 3D pipeline state 1930 commands can also selectively disable or bypass specific pipeline elements if those elements are not to be used.

[0250] In some embodiments, 3D primitive 1932 commands are used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 1932 commands will be forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 1932 command data to generate multiple vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, 3D primitive 1932 commands are used to perform vertex operations on 3D primitives via vertex shaders. In order to process vertex shaders, the 3D pipeline 1922 dispatches the shader execution thread to the graphics processor execution unit.

[0251] In some embodiments, the 3D pipeline 1922 is triggered via an execute 1934 command or event. In some embodiments, a register write triggers the command execution. In some embodiments, the execution is triggered via a 'go' or 'kick' command in the command sequence. In one embodiment, the command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for the 3D primitives. Once the operation is completed, the generated geometric objects are rasterized and the pixel engine shades the generated pixels. For these operations, additional commands for controlling pixel shading and pixel backend operations may also be included.

[0252] In some embodiments, when performing media operations, the graphics processor command sequence 1910 follows the media pipeline 1924 path. Generally, the specific purpose and manner of programming the media pipeline 1924 depends on the media or computing operation to be performed. During the media decoding process, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed, and the media decoding can be performed in whole or in part using resources provided by one or more general processing cores. In one embodiment, the media pipeline also includes elements for general purpose graphics processor unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using compute shader programs, and the compute shader programs are not explicitly related to rendering graphics primitives.

[0253] In some embodiments, the media pipeline 1924 is configured in a similar manner to the 3D pipeline 1922. A set of commands for configuring the media pipeline state 1940 are dispatched or placed into the command queue, before the media object commands 1942. In some embodiments, the media pipeline state commands 1940 include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the media pipeline state commands 1940 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0254] In some embodiments, media object commands 1942 supply pointers to media objects for processing by the media pipeline. The media object includes a memory buffer that contains video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object commands 1942. Once the pipeline states are configured and media object commands 1942 are queued, media pipeline 1924 is triggered via an execute 1944 command or an equivalent execution event (e.g., a register write). The output from media pipeline 1924 can then be post-processed by operations provided by 3D pipeline 1922 or media pipeline 1924. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0255] Graphics software architecture

[0256] Fig. 20 An exemplary graphics software architecture of a data processing system 2000 according to some embodiments is shown. In some embodiments, the software architecture includes a 3D graphics application 2010, an operating system 2020, and at least one processor 2030. In some embodiments, processor 2030 includes a graphics processor 2032 and one or more general purpose processor cores 2034. Graphics application 2010 and operating system 2020 are each executed in a system memory 2050 of the data processing system.

[0257] In some embodiments, the 3D graphics application 2010 includes one or more shader programs, which include shader instructions 2012. The shader language instructions can be in a high-level shader language, such as a high-level shader language (HLSL) or an OpenGL shader language (GLSL). The application also includes executable instructions 2014, which are in a machine language suitable for execution by a general-purpose processor core 2034. The application also includes a graphics object 2016 defined by vertex data.

[0258] In some embodiments, operating system 2020 is from Microsoft Corporation Operating system, dedicated UNIX operating system, or open source UNIX operating system using Linux kernel variant. Operating system 2020 can support graphics API 2022, such as Direct3D API, OpenGL API or Vulkan API. When Direct3D API is in use, operating system 2020 uses front-end shader compiler 2024 to compile any shader instruction 2012 in HLSL into a lower-level shader language. The compilation can be just-in-time (JIT) compilation, or the application can execute shader pre-compilation. In some embodiments, in the process of compiling 3D graphics application 2010, high-level shaders are compiled into low-level shaders. In some embodiments, shader instructions 2012 are provided in an intermediate form, such as a version of the standard portable intermediate representation (SPIR) used by Vulkan API.

[0259] In some embodiments, the user mode graphics driver 2026 includes a backend shader compiler 2027 that converts shader instructions 2012 into hardware-specific representations. When using the OpenGL API, shader instructions 2012 in the GLSL high-level language are passed to the user mode graphics driver 2026 for compilation. In some embodiments, the user mode graphics driver 2026 uses the operating system kernel mode function 2028 to communicate with the kernel mode graphics driver 2029. In some embodiments, the kernel mode graphics driver 2029 communicates with the graphics processor 2032 to dispatch commands and instructions.

[0260] IP Core Implementation

[0261] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium, which represents and / or defines logic within an integrated circuit such as a processor. For example, a machine-readable medium may include instructions representing the various logics within a processor. When read by a machine, the instructions may enable the machine to manufacture logic for performing the techniques described herein. This type of representation (referred to as an "IP core") is a reusable unit of logic for an integrated circuit, which may be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to each consumer or manufacturing facility that loads the hardware model on a manufacturing machine that manufactures the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any of the embodiments described herein.

[0262] Fig.212 is a block diagram showing an IP core development system 2100 that can be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system 2100 can be used to generate a modular, reusable design that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). The design facility 2130 can use a high-level programming language (e.g., C / C++) to generate a software simulation 2110 for the IP core design. The software simulation 2110 can be used to design, test and verify the behavior of the IP core using a simulation model 2112. The simulation model 2112 can include functional, behavioral and / or timing simulations. Then the register transfer level (RTL) design 2115 can be created or synthesized by the simulation model 2112. The RTL design 2115 is an abstraction of the behavior of an integrated circuit (including associated logic executed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 2115, a lower level design at a logic level or transistor level can also be created, designed or synthesized. Thus, the specific details of the initial design and simulation can change.

[0263] The RTL design 2115 or equivalent can be further synthesized into a hardware model 2120 by the design facility, which can adopt a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. Non-volatile memory 2140 (e.g., hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to a third-party manufacturing facility 2165. Alternatively, the IP core design can be transmitted (e.g., via the Internet) via a wired connection 2150 or a wireless connection 2160. The manufacturing facility 2165 can then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0264] Exemplary System-on-Chip Integrated Circuit

[0265] Figure 22 to Figure 24 An exemplary integrated circuit and related graphics processor that can be manufactured using one or more IP cores according to various embodiments described herein are shown. In addition to what is shown, other logic and circuits may also be included, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0266] Fig. 222200, which may be manufactured using one or more IP cores according to an embodiment. The exemplary integrated circuit 2200 includes one or more application processors 2205 (e.g., CPUs), at least one graphics processor 2210, and may also include an image processor 2215 and / or a video processor 2220, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 2200 includes peripheral or bus logic, including a USB controller 2225, a UART controller 2230, an SPI / SDIO controller 2235, and an I 2 S / I 2 The integrated circuit may include a display device 2245 coupled to one or more of a high-definition multimedia interface (HDMI) controller 2250 and a mobile industry processor interface (MIPI) display interface 2255. Storage may be provided by a flash memory subsystem 2260 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 2265 to access SDRAM or SRAM memory devices. In addition, some integrated circuits also include an embedded security engine 2270.

[0267] Fig.23 23 is a block diagram illustrating an exemplary graphics processor 2310 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores according to an embodiment. The graphics processor 2310 may be Fig. 22 A variation of the graphics processor 2210 of FIG. The graphics processor 2310 includes a vertex processor 2305 and one or more fragment processors 2315A to 2315N (e.g., 2315A, 2315B, 2315C, 2315D, all the way to 2315N-1 and 2315N). The graphics processor 2310 can execute different shader programs via separate logic, so that the vertex processor 2305 is optimized to perform operations of the vertex shader program, while one or more fragment processors 2315A to 2315N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor 2305 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. (Multiple) fragment processors 2315A to 2315N use the primitives and vertex data generated by the vertex processor 2305 to generate a frame buffer displayed on a display device. In one embodiment, the fragment processor(s) 2315A to 2315N are optimized to execute fragment shader programs provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0268] In addition, graphics processor 2310 also includes one or more memory management units (MMUs) 2320A-2320B, one or more caches 2325A-2325B, and (multiple) circuit interconnects 2330A-2330B. One or more MMUs 2320A-2320B provide virtual to physical address mappings for integrated circuit 2310, including for vertex processor 2305 and / or one or more fragment processors 2315A-2315N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 2325A-2325B. In one embodiment, one or more MMUs 2325A-2325B may communicate with other MMUs within the system, including with Fig. 22 The graphics processor 2310 may be synchronized with one or more MMUs associated with one or more application processors 2205, image processor 2215, and / or video processor 2220 so that each processor 2205 to 2220 may participate in a shared or unified virtual memory system. According to an embodiment, one or more circuit interconnects 2330A to 2330B may enable the graphics processor 2310 to interact with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0269] Fig.24 24 is a block diagram illustrating an additional exemplary graphics processor 2410 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores in accordance with an embodiment. The graphics processor 2410 may be Fig. 22 A variation of the graphics processor 2210 of FIG. The graphics processor 2410 includes Fig.23 One or more MMUs 2320A-2320B, caches 2325A-2325B, and circuit interconnects 2330A-2330B of the integrated circuit 2300.

[0270] The graphics processor 2410 includes one or more shader cores 2415A to 2415N (e.g., 2415A, 2415B, 2415C, 2415D, 2415E, 2415F, all the way to 2415N-1 and 2415N), which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code including shader program code to implement vertex shaders, fragment shaders and / or compute shaders. The exact number of shader cores present may vary in embodiments and implementations. In addition, the graphics processor 2410 also includes an inter-core task manager 2405, which acts as a thread dispatcher for dispatching execution threads to one or more shader cores 2415A to 2415N and a tiling unit 2418 for accelerating tiling operations for tile-based rendering, wherein the rendering operations of a scene are subdivided in image space, for example to exploit local spatial consistency within a scene or to optimize the use of internal caches.

[0271] The following items relate to further examples.

[0272] Example 1 may optionally include a device comprising logic, at least in part including hardware logic, to: receive metadata from an application, wherein the metadata indicates one or more processing operations that can comply with a predetermined level of bit errors when performing a read operation from a memory; determine pixel data that is acceptable for error correction code bypassing from the metadata; and generate one or more error correction code bypass hints for subsequent cache accesses to the pixel data that is acceptable for error correction code bypassing; and transmit the one or more error correction code bypass hints to a graphics processing pipeline.

[0273] Example 2 may optionally include the subject matter of Example 1, wherein the processing operation includes at least one of a texturing operation or a shading operation.

[0274] Example 3 may optionally include the subject matter of any of Examples 1 to 2, further comprising logic, at least in part including hardware logic, for: receiving a frame in the graphics processing pipeline; and initiating a graphics processing operation on the frame.

[0275] Example 4 may optionally include the subject matter of any of Examples 1 to 3, further comprising logic comprising at least in part hardware logic to: receive the one or more error correction code bypass hints in the graphics processing pipeline.

[0276] Example 5 may optionally include the subject matter of any of Examples 1 to 4, further comprising logic comprising at least in part hardware logic to retrieve graphics processing data from a cache memory.

[0277] Example 6 may optionally include the subject matter of any one of Examples 1 to 5, further comprising logic, at least in part including hardware logic, for bypassing the error correction code logic when the error correction code bypass hint indicates that bypassing the error correction code logic is acceptable for the graphics processing data retrieved from the cache memory.

[0278] Example 7 may optionally include the subject matter of any one of Examples 1 to 6, further comprising logic, at least in part including hardware logic, for applying the error correction code logic when the error correction code bypass hint indicates that bypassing the error correction code logic is unacceptable for the graphics processing data retrieved from the cache memory.

[0279] Example 8 may optionally include an electronic device comprising: a processor having one or more processor cores; logic comprising at least in part hardware logic, the logic being configured to: receive metadata from an application, wherein the metadata indicates one or more processing operations that may comply with a predetermined level of bit errors when performing a read operation from a memory; determine acceptable error correction code bypassed pixel data from the metadata; and generate one or more error correction code bypass hints for subsequent cache accesses to the acceptable error correction code bypassed pixel data; and transmit the one or more error correction code bypass hints to a graphics processing pipeline.

[0280] Example 9 may optionally include the subject matter of Example 8, wherein the processing operation includes at least one of a texturing operation or a shading operation.

[0281] Example 10 may optionally include the subject matter of any of Examples 8 to 9, further comprising logic, at least in part including hardware logic, for: receiving a frame in the graphics processing pipeline; and initiating a graphics processing operation on the frame.

[0282] Example 11 may optionally include the subject matter of any of Examples 8 to 10, further comprising logic comprising at least in part hardware logic to: receive the one or more error correction code bypass hints in the graphics processing pipeline.

[0283] Example 12 may optionally include the subject matter of any of Examples 8 to 11, further comprising logic comprising at least in part hardware logic to: retrieve graphics processing data from a cache memory.

[0284] Example 13 may optionally include the subject matter of any one of Examples 8 to 12, further comprising logic, at least in part including hardware logic, for bypassing the error correction code logic when the error correction code bypass hint indicates that bypassing the error correction code logic is acceptable for the graphics processing data retrieved from the cache memory.

[0285] Example 14 may optionally include the subject matter of any one of Examples 8 to 13, further comprising logic, at least in part including hardware logic, for applying the error correction code logic when the error correction code bypass hint indicates that bypassing the error correction code logic is unacceptable for the graphics processing data retrieved from the cache memory.

[0286] Example 15 is a method comprising: receiving metadata from an application, wherein the metadata indicates one or more processing operations that can comply with a predetermined level of bit errors when performing a read operation from a memory; determining pixel data for which error correction codes are acceptable to be bypassed from the metadata; and generating one or more error correction code bypass hints for subsequent cache accesses to the pixel data for which error correction codes are acceptable to be bypassed; and transmitting the one or more error correction code bypass hints to a graphics processing pipeline.

[0287] Example 16 may optionally include the subject matter of Example 15, wherein the processing operation includes at least one of a texturing operation or a shading operation.

[0288] Example 17 may optionally include the subject matter of any of Examples 15 to 16, further comprising: receiving a frame in the graphics processing pipeline; and initiating a graphics processing operation on the frame.

[0289] Example 18 may optionally include the subject matter of any of Examples 15 to 17, further comprising: receiving the one or more error correction code bypass hints in the graphics processing pipeline.

[0290] Example 19 may optionally include the subject matter of any of Examples 15 to 18, further comprising: retrieving graphics processing data from the cache memory.

[0291] Example 20 may optionally include the subject matter of any one of Examples 15 to 19, further comprising bypassing the error correction code logic when the error correction code bypass hint indicates that bypassing the error correction code logic is acceptable for the graphics processing data retrieved from the cache memory.

[0292] Example 21 may optionally include the subject matter of any one of Examples 15 to 20, further comprising bypassing the error correction code logic when the error correction code bypass hint indicates that bypassing the error correction code logic is acceptable for the graphics processing data retrieved from the cache memory.

[0293] Example 22 is one or more computer-readable media, comprising one or more instructions that, when executed on at least one processor, configure the at least one processor to perform one or more operations, the operations being to: receive metadata from an application, wherein the metadata indicates one or more processing operations that can comply with a predetermined level of bit errors when performing a read operation from a memory; determine acceptable error correction code bypassed pixel data from the metadata; and generate one or more error correction code bypass hints for subsequent cache accesses to the acceptable error correction code bypassed pixel data; and transmit the one or more error correction code bypass hints to a graphics processing pipeline.

[0294] Example 23 may optionally include the subject matter of Example 22, wherein the processing operation includes at least one of a texturing operation or a shading operation.

[0295] Example 24 may optionally include the subject matter of any of Examples 22 to 23, further comprising one or more instructions that, when executed on the at least one processor, configure the at least one processor to: receive a frame in the graphics processing pipeline; and initiate a graphics processing operation on the frame.

[0296] Example 25 may optionally include the subject matter of any one of Examples 22 to 24, further comprising one or more instructions that, when executed on the at least one processor, configure the at least one processor to: receive the one or more error correction code bypass hints in the graphics processing pipeline.

[0297] Example 26 may optionally include the subject matter of any of Examples 22 to 25, further comprising one or more instructions that, when executed on the at least one processor, configure the at least one processor to: retrieve graphics processing data from a cache memory.

[0298] Example 27 may optionally include the subject matter of any one of Examples 22 to 26, further comprising one or more instructions that, when executed on the at least one processor, configure the at least one processor to: bypass the error correction code logic when the error correction code bypass hint indicates that bypassing the error correction code logic is acceptable for the graphics processing data retrieved from the cache memory.

[0299] Example 28 may optionally include the subject matter of any one of Examples 22 to 27, further comprising one or more instructions that, when executed on the at least one processor, configure the at least one processor to: apply the error correction code logic when the error correction code bypass hint indicates that bypassing the error correction code logic is unacceptable for the graphics processing data retrieved from the cache memory.

[0300] In various embodiments, the operations discussed herein may be implemented as hardware (e.g., logic circuits), software, firmware, or a combination thereof, which may be provided as a computer program product, such as a tangible (e.g., non-transitory) machine-readable or computer-readable medium having stored thereon instructions (or software programs) for programming a computer to perform the processes discussed herein. The machine-readable medium may include an information storage device.

[0301] In addition, such computer-readable media may be downloaded as a computer program product, wherein the program may be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communication link (e.g., a bus, a modem, or a network connection) in the form of a data signal provided in a carrier wave or other propagation medium.

[0302] References in this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, and / or characteristic described in connection with the embodiment may be included in at least one implementation. The various appearances of the phrase "in one embodiment" in this specification may or may not all refer to the same embodiment.

[0303] Likewise, in the specification and claims, the terms "coupled" and "connected" and their derivatives may be used. In some embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements may not be in direct contact with each other, but may still cooperate or interact with each other.

[0304] Thus, although embodiments have been described using language specific to structural features and / or methodological acts, it will be understood that the claimed subject matter may not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claimed subject matter.

Claims

1. A device comprising: Logic comprising, at least in part, hardware logic, the logic being configured to: receiving metadata from an application, wherein the metadata indicates one or more processing operations that are compliant with a predetermined level of bit errors in read operations from the cache memory; determining pixel data of an image from the metadata for which bypassing an error correction code operation does not degrade the image to an unacceptable level when reading the pixel data from the cache memory; and generating one or more error correction code bypass hints for subsequent cache accesses of the pixel data for which bypassing error correction code operations does not degrade the image to an unacceptable level when the pixel data is read from the cache memory; and The one or more error correction code bypass hints are transmitted to a graphics processing pipeline.

2. The device according to claim 1, wherein: The processing operation includes at least one of a texturing operation or a shading operation.

3. The apparatus of claim 1 , further comprising logic, at least in part comprising hardware logic, for: receiving a frame in the graphics processing pipeline; and A graphics processing operation is initiated for the frame.

4. The apparatus of claim 3, further comprising logic, at least in part comprising hardware logic, for: The one or more error correction code bypass hints are received in the graphics processing pipeline.

5. The apparatus of claim 4, further comprising logic, at least in part comprising hardware logic, for: Graphics processing data is retrieved from cache memory.

6. The apparatus of claim 5, further comprising logic, at least in part comprising hardware logic, for: The error correction code logic is bypassed when the error correction code bypass hint indicates that bypassing error correction code logic is acceptable for the graphics processing data retrieved from the cache memory.

7. The apparatus of claim 5, further comprising logic, at least in part comprising hardware logic, for: The error correction code logic is applied when the error correction code bypass hint indicates that bypassing error correction code logic is not acceptable for the graphics processing data retrieved from the cache memory.

8. An electronic device comprising: a processor having one or more processor cores; Logic comprising, at least in part, hardware logic, the logic being configured to: receiving metadata from an application, wherein the metadata indicates one or more processing operations that are compliant with a predetermined level of bit errors in read operations from the cache memory; determining pixel data of an image from the metadata for which bypassing an error correction code operation does not degrade the image to an unacceptable level when reading the pixel data from the cache memory; and generating one or more error correction code bypass hints for subsequent cache accesses of the pixel data for which bypassing error correction code operations does not degrade the image to an unacceptable level when the pixel data is read from the cache memory; and The one or more error correction code bypass hints are transmitted to a graphics processing pipeline.

9. The electronic device as claimed in claim 8, wherein: The processing operation includes at least one of a texturing operation or a shading operation.

10. The electronic device of claim 9, further comprising logic comprising at least in part hardware logic, the logic being configured to: receiving a frame in the graphics processing pipeline; and A graphics processing operation is initiated for the frame.

11. The electronic device of claim 10, further comprising logic comprising at least in part hardware logic, the logic being configured to: The one or more error correction code bypass hints are received in the graphics processing pipeline.

12. The electronic device of claim 10, further comprising logic comprising at least in part hardware logic, the logic being configured to: Graphics processing data is retrieved from cache memory.

13. The electronic device of claim 12, further comprising logic comprising at least in part hardware logic, the logic being configured to: The error correction code logic is bypassed when the error correction code bypass hint indicates that bypassing error correction code logic is acceptable for the graphics processing data retrieved from the cache memory.

14. The electronic device according to claim 12, wherein: The one or more operating conditions include at least one of the following: The error correction code logic is applied when the error correction code bypass hint indicates that bypassing error correction code logic is not acceptable for the graphics processing data retrieved from the cache memory.

15. A method comprising: receiving metadata from an application, wherein the metadata indicates one or more processing operations that are compliant with a predetermined level of bit errors in read operations from the cache memory; determining pixel data of an image from the metadata for which bypassing an error correction code operation does not degrade the image to an unacceptable level when reading the pixel data from the cache memory; and generating one or more error correction code bypass hints for subsequent cache accesses of the pixel data for which bypassing error correction code operations does not degrade the image to an unacceptable level when the pixel data is read from the cache memory; and The one or more error correction code bypass hints are transmitted to a graphics processing pipeline.

16. The method of claim 15, wherein: The processing operation includes at least one of a texturing operation or a shading operation.

17. The method of claim 16, further comprising: receiving a frame in the graphics processing pipeline; as well as A graphics processing operation is initiated for the frame.

18. The method of claim 17, further comprising: The one or more error correction code bypass hints are received in the graphics processing pipeline.

19. The method of claim 18, further comprising: Graphics processing data is retrieved from cache memory.

20. The method of claim 19, further comprising: The error correction code logic is bypassed when the error correction code bypass hint indicates that bypassing error correction code logic is acceptable for the graphics processing data retrieved from the cache memory.

Images