Barrier and synchronization for machine learning at autonomous machines

Abstract

This application discloses barriering and synchronizing machine learning at an autonomous machine. A mechanism for facilitating barriering and synchronizing machine learning at an autonomous machine is described. One method, as described herein, includes detecting a group of threads associated with machine learning on one or more processing devices. The method may further include facilitating barrier synchronization of the thread group across a plurality of dies, such that each thread in the thread group is scheduled across a set of computing elements associated with the plurality of dies, wherein each die represents a processing device in the one or more processing devices, the processing device including a graphics processor.

Description

Technical Field

[0001] The embodiments described herein generally relate to data processing, and more specifically to facilitating barriers and synchronization of machine learning at autonomous machines. Background Technology

[0002] Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data, such as linear interpolation, tessellation, rasterization, texture mapping, and depth testing. Traditionally, graphics processing units (GPUs) use fixed-function computing units to process graphics data; however, recently, some GPUs have been made programmable, enabling them to support a wider range of operations to process vertex and fragment data.

[0003] To further improve performance, graphics processing units (GPUs) typically implement processing techniques such as pipelined processing, which attempt to process as much graphics data as possible in parallel across different parts of the graphics pipeline. Parallel GPUs with a Single Instruction Multithreaded (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, multiple sets of parallel threads attempt to synchronize the execution of program instructions as often as possible to improve processing efficiency. A general overview of the software and hardware of the SIMT architecture can be found in Chapter 3, pages 37–51 of Shane Cook’s *CUDA Programming* (2013) and / or in Sections 2.6.2–3.1.2 of Nicholas Wilt’s *CUDA Handbook, A Comprehensive Guide to GPU Programming* (June 2013).

[0004] Machine learning has successfully solved a wide variety of tasks. The computations generated during the training and use of machine learning algorithms (e.g., neural networks) are naturally suited for efficient parallel implementation. Therefore, parallel processors such as general-purpose graphics processing units (GPGPUs) have played a crucial role in the practical implementation of deep neural networks. Parallel graphics processors with a single-instruction, multi-threaded (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, multiple sets of parallel threads attempt to synchronize the execution of program instructions as often as possible to improve processing efficiency. The efficiency provided by parallel machine learning algorithm implementations allows for the use of large-capacity networks and enables those networks to be trained on large datasets.

[0005] Conventional barrier and synchronization techniques are severely limited for a number of reasons, such as being entirely software-dependent, inaccessible to multiple thread groups, and lacking general functionality. Consequently, these techniques are inefficient in terms of system resources such as time, memory, power, and bandwidth. Attached Figure Description

[0006] The embodiments are illustrated in the accompanying drawings by way of example rather than limitation, and in which the same reference numerals refer to similar elements. A more specific description of the foregoing summary can be obtained by referring to the embodiments, some of which are illustrated in the drawings, to provide a more detailed understanding of the features described above. However, it should be noted that the drawings merely illustrate exemplary embodiments and should therefore not be considered as limiting the scope of the invention, as other equivalent embodiments may be shown in the drawings.

[0007] Figure 1 This is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein.

[0008] Figures 2A to 2D A parallel processor component according to an embodiment is shown.

[0009] Figure 3A and Figure 3B This is a block diagram of a graphics multiprocessor according to an embodiment.

[0010] Figures 4A to 4F An exemplary architecture in which multiple graphics processing units are communicatively coupled to multiple multi-core processors is shown.

[0011] Figure 5 This is a conceptual diagram of a graphics processing pipeline according to an embodiment.

[0012] Figure 6 A computing device is shown that employs a managed barrier and a synchronization mechanism according to one embodiment.

[0013] Figure 7 A barrier and synchronization mechanism according to one embodiment is shown.

[0014] Figure 8A An architectural setup for adopting and using a multi-core barrier for machine learning is shown according to one embodiment.

[0015] Figure 8B A framework for facilitating the synchronization of thread groups in machine learning is shown according to one embodiment.

[0016] Figure 8C A framework for facilitating data sharing across graphics processors using surface libraries in machine learning is demonstrated according to one embodiment.

[0017] Figure 9A A graphics processor according to one embodiment is shown for facilitating optimized scheduling of thread groups in machine learning in the presence of barriers or shared local memory.

[0018] Figure 9B A framework for facilitating thread group preemption based on barriers in machine learning is shown according to one embodiment.

[0019] Figure 10 A machine learning software stack according to an embodiment is shown.

[0020] Figure 11 A highly parallel general-purpose graphics processing unit according to an embodiment is shown.

[0021] Figure 12 A multi-GPU computing system according to an embodiment is shown.

[0022] Figure 13A and Figure 13B The layers of an exemplary deep neural network are shown.

[0023] Figure 14 It demonstrates the training and deployment of deep neural networks.

[0024] Figure 15 Demonstrates the training and deployment of deep neural networks.

[0025] Figure 16 This is a diagram illustrating distributed learning.

[0026] Figure 17 An exemplary inference system-on-a-chip (SOC) suitable for performing inference using a trained model is demonstrated.

[0027] Figure 18 This is a block diagram of an embodiment of a computer system having a processor having one or more processor cores and a graphics processor.

[0028] Figure 19 This is a block diagram of one embodiment of a processor, which has one or more processor cores, an integrated memory controller, and an integrated graphics processor.

[0029] Figure 20 This is a block diagram of one embodiment of a graphics processor, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores.

[0030] Figure 21 This is a block diagram of an embodiment of a graphics processing engine for a graphics processor.

[0031] Figure 22This is a block diagram of another embodiment of a graphics processor.

[0032] Figure 23 It is a block diagram that includes the thread execution logic for processing the array of elements.

[0033] Figure 24 The instruction format of the graphics processor execution unit according to an embodiment is shown.

[0034] Figure 25 This is a block diagram of another embodiment of a graphics processor, which includes a graphics pipeline, a media pipeline, a display engine, thread execution logic, and a rendering output pipeline.

[0035] Figure 26A This is a block diagram illustrating the graphics processor command format according to an embodiment.

[0036] Figure 26B This is a block diagram illustrating a sequence of graphics processor commands according to an embodiment.

[0037] Figure 27 An exemplary graphical software architecture of a data processing system according to an embodiment is shown.

[0038] Figure 28 This is a block diagram illustrating an IP core development system, according to an embodiment, that can be used to manufacture integrated circuits for performing operations.

[0039] Figure 29 This is a block diagram illustrating an exemplary system-on-a-chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment.

[0040] Figure 30 This is a block diagram illustrating an exemplary graphics processor for a system-on-a-chip integrated circuit.

[0041] Figure 31 This is a block diagram illustrating an additional exemplary graphics processor for a system-on-a-chip integrated circuit. Detailed Implementation

[0042] The embodiments provide a novel technique for providing multi-core barriers for machine learning and having pre-threaded synchronization within thread groups. The embodiments further provide for using barriers to facilitate synchronization across thread groups, wherein, for those thread groups that do not have shared local memory (SLM) or barriers used, they are scheduled across streaming multiprocessors (SM) and / or graphics processors. The embodiments further provide for barrier-based preemption of threads.

[0043] It should be noted that throughout this document, terms or abbreviations such as "convolutional neural network," "CNN," "neural network," "NN," "deep neural network," "DNN," "recurrent neural network," and "RNN" can be used interchangeably. Additionally, throughout this document, terms such as "autonomous machine" or simply "machine," "autonomous vehicle" or simply "vehicle," "autonomous agent" or simply "agent," "autonomous device," or "computing device," and "robot" can be used interchangeably.

[0044] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses a dedicated circuitry / logic to efficiently process these commands / instructions.

[0045] Numerous specific details are set forth in the following description. However, as described herein, embodiments can be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the understanding of this specification.

[0046] System Overview I

[0047] Figure 1This is a block diagram illustrating a computer system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104, the one or more processors and the system memory communicating via an interconnect path, the interconnect path including a memory hub 105. The memory hub 105 may be a separate component within a chipset assembly or integrated within one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that enables the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 enables a display controller (which may be included in one or more processors 102) to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include a local display device, an internal display device, or an embedded display device.

[0048] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 coupled to a memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standards-based communication link technologies or protocols (such as, but not limited to, PCI Express), or a vendor-specific communication interface or communication architecture. In one embodiment, the one or more parallel processors 112 form a computation-centric parallel or vector processing system including a large number of processing cores and / or processing clusters such as integrated many-core (MIC) processors. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of one or more display devices 110A coupled via an I / O hub 107. The one or more parallel processors 112 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 110B.

[0049] Within the I / O subsystem 111, system storage unit 114 can be connected to I / O hub 107 to provide storage for computing system 100. I / O switch 116 can be used to provide an interface mechanism to enable connections between I / O hub 107 and other components that can be integrated into the platform, such as network adapter 118 and / or wireless network adapter 119, as well as various other devices that can be added via one or more plug-in devices 120. Network adapter 118 can be an Ethernet adapter or another wired network adapter. Wireless network adapter 119 can include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more radio devices.

[0050] The computing system 100 may include other components not explicitly shown, such as USB or other port connectors, optical storage drives, video capture devices, etc., and may also be connected to the I / O hub 107. Figure 1 The communication paths for interconnecting various components can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express), or (multiple) other bus or point-to-point communication interfaces and / or protocols such as NV-Link high-speed interconnect or interconnect protocols known in the art.

[0051] In one embodiment, one or more parallel processors 112 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and said circuitry constitutes a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 incorporate circuitry optimized for general-purpose processing while retaining the underlying computing architecture described in more detail herein. In yet another embodiment, components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 112, memory hub 105, processor(s)102, and I / O hub 107 may be integrated into a system-on-a-chip (SoC) integrated circuit. Alternatively, components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In other embodiments, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM) that may interconnect with other MCMs to form a modular computing system.

[0052] It should be understood that the computing system 100 shown herein is exemplary and variations and modifications are possible. The connectivity topology can be modified as needed, including the number and arrangement of bridges, the number of processors(102), and the number of parallel processors(112). For example, in some embodiments, system memory 104 is connected directly to processors(102) instead of via bridges, while other devices communicate with system memory 104 via memory hub 105 and processors(102). In other alternative topologies, parallel processors(112) are connected to I / O hub 107 or directly to one or more processors(102), instead of to memory hub 105. In other embodiments, I / O hub 107 and memory hub 105 may be integrated into a single chip. Some embodiments may include two or more groups of processors(102) attached via multiple sockets, which may be coupled to two or more instances of parallel processors(112).

[0053] Some specific components shown in this document are optional and may not be included in all implementations of the computing system 100. For example, any number of plug-in cards or peripheral devices may be supported, or some components may be omitted. Furthermore, some architectures may be described using different terminology. Figure 1 Similar components are shown. For example, in some architectures, the memory hub 105 may be referred to as the Northbridge, while the I / O hub 107 may be referred to as the Southbridge.

[0054] Figure 2A A parallel processor 200 according to an embodiment is illustrated. Various components of the parallel processor 200 can be implemented using one or more integrated circuit devices such as a programmable processor, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). According to the embodiment, the illustrated parallel processor 200 is... Figure 1 The one or more variants of the parallel processor 112 shown.

[0055] In one embodiment, the parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204 that enables communication with other devices, including other instances of the parallel processing unit 202. The I / O unit 204 may be directly connected to other devices. In one embodiment, the I / O unit 204 is connected to other devices via a hub or switch interface, such as a memory hub 105. The connection between the memory hub 105 and the I / O unit 204 forms a communication link 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar switch 216, wherein the host interface 206 receives commands relating to performing processing operations, and the memory crossbar switch 216 receives commands relating to performing memory operations.

[0056] When host interface 206 receives a command buffer via I / O unit 204, host interface 206 can route work operations for executing those commands to front end 208. In one embodiment, front end 208 is coupled to scheduler 210, which is configured to distribute commands or other work items to processing cluster array 212. In one embodiment, scheduler 210 ensures that processing cluster array 212 is correctly configured and active before distributing tasks to processing clusters within processing cluster array 212.

[0057] Processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, up to cluster 214N). Each cluster 214A through 214N of processing cluster array 212 can execute a large number of concurrent threads. Scheduler 210 may use various scheduling and / or work distribution algorithms to allocate work to clusters 214A through 214N of processing cluster array 212, and these algorithms may vary depending on the workload caused by each type of program or computation. Scheduling may be handled dynamically by scheduler 210, or it may be partially assisted by compiler logic during the compilation of program logic configured to be executed by processing cluster array 212.

[0058] In one embodiment, different clusters 214A to 214N of the processing cluster array 212 can be assigned to process different types of programs or to perform different types of computations.

[0059] The processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, the processing cluster array 212 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0060] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic, tessellation logic, and other vertex processing logic for performing texture operations. Additionally, the processing cluster array 212 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 may transfer data from system memory via I / O unit 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) and then written back to system memory.

[0061] In one embodiment, when the parallel processing unit 202 is used to perform graphics processing, the scheduler 210 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations across multiple clusters 214A to 214N of the processing cluster array 212. In some embodiments, portions of the processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more of the clusters 214A to 214N can be stored in a buffer to allow intermediate data to be transferred between the clusters 214A to 214N for further processing.

[0062] During operation, the processing cluster array 212 may receive processing tasks to be executed via scheduler 210, which receives commands defining the processing tasks from front-end 208. For graphics processing operations, processing tasks may include data to be processed, such as surface (patch) data, graph data, vertex data, and / or pixel data, as well as state parameters defining how the data is processed and indices of commands (e.g., which program to execute). Scheduler 210 may be configured to retrieve indices corresponding to tasks or may receive indices from front-end 208. Front-end 208 may be configured to ensure that the processing cluster array 212 is configured to be active before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0063] Each of one or more instances of parallel processing unit 202 may be coupled to parallel processor memory 222. Parallel processor memory 222 may be accessed via memory crossbar switch 216, which receives memory requests from processing cluster array 212 and I / O unit 204. Memory crossbar switch 216 may access parallel processor memory 222 via memory interface 218. Memory interface 218 may include multiple partition units (e.g., partition units 220A, 220B, up to partition units 220N), each of which may be coupled to a portion (e.g., memory cell) of parallel processor memory 222. In one implementation, the number of partition units 220A to 220N is configured to be equal to the number of memory cells, such that a first partition unit 220A has a corresponding first memory cell 224A, a second partition unit 220B has a corresponding memory cell 224B, and the Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A to 220N may not be equal to the number of memory devices.

[0064] In various embodiments, memory cells 224A to 224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory cells 224A to 224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will understand that the specific implementation of memory cells 224A to 224N can vary and can be selected from one of a variety of conventional designs. Render targets, such as frame buffers or texture maps, may be stored on memory cells 224A to 224N, thereby allowing partitioning cells 220A to 220N to write portions of each render target in parallel to efficiently utilize the available bandwidth of parallel processor memory 222. In some embodiments, to support a unified memory design utilizing system memory along with local cache memory, local instances of parallel processor memory 222 may be excluded.

[0065] In one embodiment, any of clusters 214A to 214N of the processing cluster array 212 can process data to be written to any of the memory cells 224A to 224N within the parallel processor memory 222. A memory crossbar switch 216 can be configured to pass the output of each cluster 214A to 214N to any partition cell 220A to 220N or another cluster 214A to 214N, which can perform additional processing operations on the output. Each cluster 214A to 214N can communicate with the memory interface 218 via the memory crossbar switch 216 to perform read or write operations for various external memory devices. In one embodiment, the memory crossbar switch 216 can be connected to the memory interface 218 to communicate with the I / O unit 204 and can be connected to a local instance of the parallel processor memory 222, thereby enabling processing units within different processing clusters 214A to 214N to communicate with system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar switch 216 can use virtual channels to separate traffic flows between clusters 214A to 214N and partition units 220A to 220N.

[0066] While a single instance of the parallel processing unit 202 is shown within the parallel processor 200, any number of instances of the parallel processing unit 202 can also be included. For example, multiple instances of the parallel processing unit 202 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. Different instances of the parallel processing unit 202 can be configured to interact even if the different instances have different numbers of processing cores, different amounts of local parallel processor storage, and / or other configuration differences. For example, and in one embodiment, some instances of the parallel processing unit 202 may include higher precision floating-point units relative to other instances. Systems incorporating one or more instances of the parallel processing unit 202 or the parallel processor 200 can be implemented in various configurations and form factors, including but not limited to desktop computers, laptop or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0067] Figure 2B This is a block diagram of partitioning unit 220 according to an embodiment. In one embodiment, partitioning unit 220 is... Figure 2AAn example of one of partition units 220A to 220N. As shown, partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from memory crossbar switch 216 and ROP 226. Read misses and urgent write-back requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Dirty updates can also be sent to the frame buffer via the frame buffer interface 225 for opportunistic processing. In one embodiment, the frame buffer interface 225 communicates with memory cells in the parallel processor memory (e.g., ...). Figure 2A One of the interactions of memory cells 224A to 224N (e.g., within parallel processor memory 222).

[0068] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stencil printing, z-testing, and blending. ROP 226 then outputs processed graphics data, which is stored in graphics memory. In some embodiments, ROP 226 includes compression logic for compressing z- or color data written to memory and decompressing z- or color data read from memory. In some embodiments, ROP 226 is included in each processing cluster (e.g., Figure 2A The data is contained within clusters 214A to 214N, rather than within partition unit 220. In such an embodiment, read and write requests for pixel data are transmitted via memory crossbar switch 216 instead of pixel fragment data.

[0069] Processed graphic data can be displayed on display devices such as Figure 1 On one or more display devices 110, routed by processor(s) 102 for further processing, or by... Figure 2A One of the processing entities within the parallel processor 200 is routed for further processing.

[0070] Figure 2C This is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is... Figure 2AAn instance of one of the processing clusters 214A to 214N. Processing cluster 214 can be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a specific program executing on a specific input dataset. In some embodiments, Single Instruction Multiple Data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, Single Instruction Multiple Threading (SIMT) technology is used to support the parallel execution of a large number of substantially synchronous threads using a common instruction unit configured to issue instructions to a set of processing engines within each of the processing cluster. Unlike SIMD execution mechanisms, where all processing engines typically execute the same instructions, SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that SIMD processing mechanisms represent a subset of the functionality of SIMT processing mechanisms.

[0071] The operation of cluster 214 can be controlled via pipeline manager 232, which distributes processing tasks to the SIMT parallel processors. Pipeline manager 232... Figure 2A The scheduler 210 receives instructions and manages the execution of those instructions via the graphics multiprocessor 234 and / or texture unit 236. The graphics multiprocessor 234 shown is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures can be included within the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included within the processing cluster 214. The graphics multiprocessor 234 can process data, and the data crossover switch 240 can be used to distribute the processed data to one of a plurality of possible destinations, including other shading units. The pipeline manager 232 can facilitate the distribution of processed data by specifying a destination for the data to be distributed via the data crossover switch 240.

[0072] Each graphics multiprocessor 234 within the processing cluster 214 may include the same group of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). The functional execution logic can be configured in a pipelined manner, where new instructions can be issued before completing previous instructions. Functional execution logic can be provided. The functional logic supports various operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and calculations of various algebraic functions. In one embodiment, the same functional unit hardware can be used to perform different operations, and any combination of functional units can exist.

[0073] Instructions transmitted to processing cluster 214 constitute threads. A group of threads executing on a set of parallel processing engines is a thread group. Thread groups execute the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 234. A thread group may include fewer threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle of processing the thread group. A thread group may also include more threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing can be performed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 234.

[0074] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 234 may forgo the internal cache and instead use a cache memory (e.g., L1 cache 308) within the processing cluster 214. Each graphics multiprocessor 234 may also access partition units shared across all processing clusters 214 (e.g., ...). Figure 2A The graphics multiprocessor 234 has an L2 cache within partition units 220A to 220N, which can be used to transfer data between threads. The graphics multiprocessor 234 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. Any memory outside of the parallel processing unit 202 can be used as global memory. Embodiments where the processing cluster 214 includes multiple instances of the graphics multiprocessor 234 can share common instructions and data that can be stored in the L1 cache 308.

[0075] Each processing cluster 214 may include an MMU 245 (Memory Management Unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside in Figure 2A The memory interface 218 is located within the MMU 245. The MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to tiles (more specifically, chunks) and optionally cache line indices. The MMU 245 may include an address translation lookahead buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or the L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality to achieve efficient request interleaving between partition units. Cache line indices can be used to determine whether a request for a cache line is a hit or a miss.

[0076] In graphics and computing applications, processing cluster 214 can be configured such that each graphics multiprocessor 234 is coupled to texture unit 236 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within the graphics multiprocessor 234, and is retrieved as needed from an L2 cache, local parallel processor memory, or system memory. Each graphics multiprocessor 234 outputs a processed task to data crossover switch 240 to provide the processed task to another processing cluster 214 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via memory crossover switch 216. Pre-ROP 242 (Pre-Raster Operation Unit) is configured to receive data from graphics multiprocessors 234 and direct the data to ROP units, which can be partitioned as described herein (e.g., Figure 2A The preROP 242 unit is located in partition units 220A to 220N. It can optimize color mixing, organize pixel color data, and perform address translation.

[0077] It should be understood that the core architecture described herein is exemplary and variations and modifications are possible. For example, any number of processing units such as graphics multiprocessors 234, texture units 236, preROP 242, etc., can be included within processing cluster 214. Furthermore, although only one processing cluster 214 is shown, the parallel processing units as described herein can include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 can be configured to operate independently of other processing clusters 214 using separate and different processing units, L1 caches, etc.

[0078] Figure 2D A graphics multiprocessor 234 according to one embodiment is illustrated. In such an embodiment, the graphics multiprocessor 234 is coupled to a pipeline manager 232 of a processing cluster 214. The graphics multiprocessor 234 has an execution pipeline including, but not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0079] In one embodiment, instruction cache 252 receives a stream of instructions to be executed from pipeline manager 232. These instructions are cached in instruction cache 252 and dispatched for execution by instruction unit 254. Instruction unit 254 can dispatch instructions as thread groups (e.g., threads), with each thread in the thread group assigned to a different execution unit within GPGPU core 262. Instructions can access any of the local, shared, or global address spaces by specifying an address within a unified address space. Address mapping unit 256 can be used to translate addresses in the unified address space into different memory addresses accessible by load / store unit 266.

[0080] Register file 258 provides a set of registers for the functional units of graphics multiprocessor 324. Register file 258 provides temporary storage for operands on data paths connected to functional units of graphics multiprocessor 324 (e.g., GPGPU core 262, load / store unit 266). In one embodiment, register file 258 is partitioned among each of the functional units such that each functional unit is allocated a dedicated portion of register file 258. In one embodiment, register file 258 is partitioned between different meridians being executed by graphics multiprocessor 324.

[0081] Each GPGPU core 262 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 324. According to embodiments, the architecture of the GPGPU core 262 may be similar or different. For example, in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 floating-point arithmetic standard or enable variable-precision floating-point arithmetic. Additionally, the graphics multiprocessor 324 may also include one or more fixed-function or special-function units for performing specific functions such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also contain fixed-function or special-function logic.

[0082] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 324 to the register file 258 and the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a cross-switch interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, thus data transfer between the GPGPU core 262 and the register file 258 has very low latency. The shared memory 270 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 234. For example, the cache memory 272 can be used as a data cache to cache texture data communicated between functional units and texture units 236. The shared memory 270 can also be used as a cached, managed program. In addition to the automatically cached data stored in the cache memory 272, threads executing on the GPGPU core 262 can also programmatically store data in the shared memory.

[0083] Figures 3A to 3B An additional graphics multiprocessor according to an embodiment is shown. The graphics multiprocessors 325 and 350 shown are... Figure 2C Variants of the graphics multiprocessor 234. The graphics multiprocessors 325 and 350 shown can be configured as streaming multiprocessors (SM) capable of executing a large number of execution threads simultaneously.

[0084] Figure 3A A graphics multiprocessor 325 according to an additional embodiment is shown. The graphics multiprocessor 325 includes, relative to... Figure 2D The graphics multiprocessor 234 includes multiple additional instances of execution resource units. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A to 332B, register files 334A to 334B, and texture units(s) 344A to 344B. The graphics multiprocessor 325 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A to 336B, GPGPU cores 337A to 337B, GPGPU cores 338A to 338B) and multiple sets of load / memory units 340A to 340B. In one embodiment, the execution resource units have a common instruction cache 330, a texture and / or data cache memory 342, and a shared memory 346. The various components can communicate via interconnect architecture 327. In one embodiment, interconnect architecture 327 includes one or more cross switches to enable communication between the components of the graphics multiprocessor 325.

[0085] Figure 3B A graphics multiprocessor 350 according to an additional embodiment is shown. Figure 2D and Figure 3A As shown, the graphics processor includes multiple sets of execution resources 356A to 356D, each set of execution resources including multiple instruction units, register files, GPGPU cores, and load memory units. Execution resources 356A to 356D can work with (multiple) texture units 360A to 360D to perform texture operations, while sharing instruction cache 354 and shared memory 362. In one embodiment, execution resources 356A to 356D can share instruction cache 354, shared memory 362, and multiple instances of texture and / or data cache memories 358A to 358B. Various components can be connected via... Figure 3A The interconnect structure 327 communicates with the similar interconnect structure 352.

[0086] Those skilled in the art will understand that Figure 1 , Figures 2A to 2D and Figures 3A to 3B The architecture described herein is descriptive and does not limit the scope of embodiments of the invention. Therefore, the techniques described herein can be implemented on any suitably configured processing unit, including but not limited to: one or more mobile application processors; one or more desktop computer or server central processing units (CPUs), including multi-core CPUs; one or more parallel processing units such as… Figure 2A The parallel processing unit 202; and one or more graphics processors or dedicated processing units, without departing from the scope of the embodiments described herein.

[0087] In some embodiments, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0088] Technologies for GPU-to-host processor interconnects

[0089] Figure 4AAn exemplary architecture is shown in which multiple GPUs 410 to 413 are communicatively coupled to multiple multi-core processors 405 to 406 via high-speed links 440 to 443 (e.g., bus, point-to-point interconnect, etc.). In one embodiment, high-speed links 440 to 443 support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher, depending on the implementation. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the basic principles of the invention are not limited to any particular communication protocol or throughput.

[0090] Furthermore, in one embodiment, two or more of GPUs 410 to 413 are interconnected via high-speed links 444 to 445, which can be implemented using the same or different protocols / links as those used for high-speed links 440 to 443. Similarly, two or more of multi-core processors 405 to 406 can be connected via high-speed link 433, which can be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, Figure 4A All communication between the various system components shown can be accomplished using the same protocol / link (e.g., via a common interconnect structure). However, as mentioned, the basic principles of the invention are not limited to any particular type of interconnect technology.

[0091] In one embodiment, each multi-core processor 405 to 406 is communicatively coupled to processor memories 401 to 402 via memory interconnects 430 to 431, and each GPU 410 to 413 is communicatively coupled to GPU memories 420 to 423 via GPU memory interconnects 450 to 453. Memory interconnects 430 to 431 and 450 to 453 may utilize the same or different memory access technologies. By way of example and not limitation, processor memories 401 to 402 and GPU memories 420 to 423 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memories such as 3D XPoint or Nano-RAM. In one embodiment, one portion of the memory may be volatile memory, while another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0092] As described below, although the various processors 405 to 406 and GPUs 410 to 413 can each be physically coupled to specific memories 401 to 402 and 420 to 423 respectively, a unified memory architecture can be implemented, in which the same virtual system address space (also known as the “effective address” space) is distributed across all the various physical memories. For example, processor memories 401 to 402 can each include 64 GB of system memory address space, and GPU memories 420 to 423 can each include 32 GB of system memory address space (resulting in a total of 256 GB of addressable memory space in the example described).

[0093] Figure 4B Additional details are shown regarding the interconnection between a multi-core processor 407 and a graphics acceleration module 446 according to one embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0094] The processor 407 shown includes multiple cores 460A to 460D, each having a translation backstop buffer 461A to 461D and one or more caches 462A to 462D. These cores may include various other components (e.g., instruction fetch units, branch prediction units, decoders, execution units, reordering buffers, etc.) for executing instructions and processing data not shown to avoid obscuring the basic principles of the invention. Caches 462A to 462D may include Level 1 (L1) and Level 2 (L2) caches. Furthermore, one or more shared caches 426 may be included in the cache hierarchy and shared by the respective groups of cores 460A to 460D. For example, one embodiment of the processor 407 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 407 and graphics accelerator integration module 446 are connected to the system memory 441, which may include processor memories 401 to 402.

[0095] Consistency is maintained for data and instructions stored in various caches 462A to 462D, 456 and system memory 441 via inter-core communication through a coherence bus 464. For example, each cache may have associated cache coherence logic / circuit to communicate via the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via the coherence bus 464 to snoop on cache accesses. Cache snooping / coherence techniques will be well understood by those skilled in the art, and to avoid obscuring the basic principles of the invention, they will not be described in detail here.

[0096] In one embodiment, proxy circuitry 425 communicatively couples graphics acceleration module 446 to coherence bus 464, thereby allowing graphics acceleration module 446 to participate in cache coherence protocols as a peer of the core. Specifically, interface 435 provides connectivity to proxy circuitry 425 via high-speed link 440 (e.g., PCIe bus, NVLink, etc.), and interface 437 connects graphics acceleration module 446 to link 440.

[0097] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services for multiple graphics processing engines 431, 432, and 43N representing the graphics acceleration module 446. The graphics processing engines 431, 432, and 43N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, and 43N may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and block image transfer engines. In other words, the graphics acceleration module may be a GPU with multiple graphics processing engines 431, 432, and 43N, or the graphics processing engines 431 to 432, 43N may be separate GPUs integrated into a common package, line card, or chip.

[0098] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and memory access protocols for accessing system memory 441. The MMU 439 may also include a translation back buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 438 stores commands and data for efficient access by graphics processing engines 431 to 432, 43N. In one embodiment, the data stored in cache 438 and graphics memories 433 to 434, 43N is kept consistent with core caches 462A to 462D, 456 and system memory 411. As mentioned, this can be accomplished via proxy circuitry 425, which participates in cache coherency mechanisms on behalf of cache 438 and memories 433 to 434, 43N (e.g., sending updates to cache 438 related to modifications / accesses to cache lines on processor caches 462A to 462D, 456 and receiving updates from cache 438).

[0099] A set of registers 445 stores context data for threads executed by graphics processing engines 431 to 432, 43N, and context management circuitry 448 manages the thread context. For example, context management circuitry 448 can perform save and restore operations to save and restore the context of various threads during context switching (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 448 can store the current register value to a designated area in memory (e.g., identified by a context pointer). The context management circuitry can restore the register value upon returning to the context. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from system devices.

[0100] In one implementation, the MMU 439 translates the virtual / effective address from the graphics processing engine 431 into a physical / actual address in system memory 411. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 may be dedicated to a single application executing on processor 407, or it may be shared among multiple applications. In one embodiment, a virtual graphics execution environment is presented, where the resources of graphics processing engines 431 to 432, 43N are shared with multiple applications or virtual machines (VMs). Resources may be subdivided into “shards” allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0101] Therefore, the accelerator integrated circuit acts as a bridge for the system of the graphics acceleration module 446, and provides address translation and system memory caching services. Furthermore, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage the virtualization of the graphics processing engine, interrupts, and memory management.

[0102] Because the hardware resources of the graphics processing engines 431 to 432, 43N are explicitly mapped to the actual address space seen by the host processor 407, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431 to 432, 43N, allowing them to appear as independent units on the system.

[0103] As mentioned, in the illustrated embodiment, one or more graphics memories 433 to 434, 43M are coupled to each of the graphics processing engines 431 to 432, 43N, respectively. Graphics memories 433 to 434, 43M store instructions and data being processed by each of the graphics processing engines 431 to 432, 43N. Graphics memories 433 to 434, 43M can be volatile memories such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories such as 3D XPoint or Nano-RAM.

[0104] In one embodiment, to reduce data traffic on link 440, a biasing technique is used to ensure that the data stored in graphics memories 433 to 434, 43M is the data most frequently used by graphics processing engines 431 to 432, 43N, and preferably not used (or at least infrequently used) by cores 460A to 460D. Similarly, the biasing mechanism attempts to keep the data required by the cores (and preferably not graphics processing engines 431 to 432, 43N) within the caches 462A to 462D, 456 of the cores and system memory 411.

[0105] Figure 4C Another embodiment in which the accelerator integrated circuit 436 is integrated within the processor 407 is shown. In this embodiment, the graphics processing engines 431 to 432, 43N communicate directly with the accelerator integrated circuit 436 via high-speed link 440 through interfaces 437 and 435 (this can also utilize any form of bus or interface protocol). The accelerator integrated circuit 436 can perform operations related to... Figure 4B The operation described is the same, but given its close proximity to the coherence bus 462 and caches 462A to 462D, 426, it may operate at a higher throughput.

[0106] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The shared programming model may include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0107] In one embodiment of the dedicated process model, graphics processing engines 431 to 432, 43N are dedicated to a single application or process within a single operating system. A single application can centralize requests from other applications to graphics engines 431 to 432, 43N, thereby providing virtualization within a VM / partition.

[0108] In a dedicated process programming model, graphics processing engines 431 to 432, 43N can be shared by multiple VM / application partitions. This shared model requires a hypervisor to virtualize the graphics processing engines 431 to 432, 43N, allowing access by each operating system. For single-partition systems without a hypervisor, the graphics processing engines 431 to 432, 43N are owned by the operating system. In both cases, the operating system can virtualize the graphics processing engines 431 to 432, 43N to provide access to each process or application.

[0109] For a shared programming model, the graphics acceleration module 446 or the individual graphics processing engines 431 to 432, 43N use a process handle to select process elements. In one embodiment, the process elements are stored in system memory 411 and can be addressed using the effective address to physical address translation techniques described herein. The process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engines 431 to 432, 43N (i.e., invoking system software to add a process element to the process element list). The lower 16 bits of the process handle may be the offset of the process element within the process element list.

[0110] Figure 4D An exemplary accelerator integration slice 490 is shown. As used herein, a “slice” refers to a designated portion of the processing resources of the accelerator integrated circuit 436. The application-effective address space 482 within system memory 411 stores process elements 483. In one embodiment, process element 483 is stored in response to a GPU call 481 from an application 480 executing on processor 407. Process element 483 contains the processing state of the corresponding application 480. The job descriptor (WD) 484 contained in process element 483 may be a single job requested by the application, or it may contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the application address space 482.

[0111] The graphics acceleration module 446 and / or individual graphics processing engines 431 to 432, 43N can be shared by all or some processes in the system. Embodiments of the invention include infrastructure for establishing a processing state and sending a WD 484 to the graphics acceleration module 446 to begin work in a virtual environment.

[0112] In one implementation, the dedicated process programming model is implementation-specific. In this model, a single process owns either the graphics acceleration module 446 or a separate graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 to obtain its assigned partition, and the operating system initializes the accelerator integrated circuit 436 to obtain its assigned process when the graphics acceleration module 446 is allocated.

[0113] In operation, the WD acquisition unit 491 in the accelerator integration slice 490 acquires the next WD 484, which includes instructions for work to be performed by one of the graphics processing engines of the graphics acceleration module 446. As shown, data from the WD 484 can be stored in register 445 and used by the MMU 439, interrupt management circuitry 447, and / or context management circuitry 446. For example, one embodiment of the MMU 439 includes segment / page walk circuitry for accessing segment / page tables 486 within the OS virtual address space 485. The interrupt management circuitry 447 can handle interrupt events 492 received from the graphics acceleration module 446. When performing graphics operations, the effective address 493 generated by the graphics processing engines 431 to 432, 43N is translated into an actual address by the MMU 439.

[0114] In one embodiment, the same set of registers 445 is copied for each graphics processing engine 431 to 432, 43N and / or graphics acceleration module 446, and this set of registers can be initialized by a hypervisor or operating system. Each of these copied registers can be included in the accelerator integration slice 490. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0115] Table 1 - Supervisor Initialization Registers

[0116] 1 Slice Control Register 2 Real Address (RA) Scheduler Region Pointer 3 Authorization mask override register 4 Interruption vector table entry offset 5 Interruption vector table entry limit 6 Status Register 7 Logical partition ID 8 The Real Address (RA) management accelerator utilizes record pointers 9 Storage description register

[0117] Table 2 shows exemplary registers that can be initialized by the operating system.

[0118] Table 2 - Operating System Initialization Registers

[0119] 1 Process and thread identifiers 2 Valid Address (EA) Context Save / Restore Pointer 3 Virtual Address (RA) accelerators utilize record pointers 4 Virtual Address (RA) segment table pointer 5 Authorization mask 6 Job descriptor

[0120] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engines 431 to 432, 43N. The WD contains all the information required for the graphics processing engines 431 to 432, 43N to complete their work, or the WD may be a pointer to a memory location where the application has established a queue of work commands to be completed.

[0121] Figure 4E Additional details of one embodiment of the shared model are shown. This embodiment includes a hypervisor physical address space 498 in which a list of process elements 499 is stored. The hypervisor physical address space 498 is accessible via a hypervisor 496 that virtualizes the graphics acceleration module engine of operating system 495.

[0122] The shared programming model allows all or some processes from all or some partitions of the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time-sliced ​​sharing and direct graphics sharing.

[0123] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. For the graphics acceleration module 446 to support the virtualization of the hypervisor 496, the graphics acceleration module 446 must meet the following requirements: 1) Application job requests must be autonomous (i.e., no need to maintain state between jobs), or the graphics acceleration module 446 must provide context saving and restoration mechanisms. 2) The graphics acceleration module 446 guarantees completion of application job requests within a specified time, including any translation errors, or the graphics acceleration module 446 provides the ability to preempt job processing. 3) When operating in a direct shared programming model, fairness of the graphics acceleration module 446 within the process must be guaranteed.

[0124] In one embodiment, for the shared model, application 480 is required to make an operating system system call 495 using the graphics acceleration module 446 type, working descriptor (WD), authorization mask register (AMR) value, and context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function of the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is specifically formatted for the graphics acceleration module 446 and can be in the following forms: graphics acceleration module 446 command; valid address pointer to a user-defined structure; valid address pointer to a command queue; or any other data structure describing the work to be performed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to that of the application setting the AMR. If the implementation of the accelerator integrated circuit 436 and the graphics acceleration module 446 does not support the User Authorization Mask Override Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Before placing the AMR in process element 483, hypervisor 496 may optionally apply the Current Authorization Mask Override Register (AMOR) value. In one embodiment, CSRP is one of the registers 445 containing the effective addresses of regions in application address space 482 for the graphics acceleration module 446 to save and restore context state. This pointer is optional if saving state between jobs is not required or when a job is preempted. The context save / restore region may be plugged-in system memory.

[0125] Upon receiving a system call, the operating system 495 can verify that the application 480 has been registered and authorized to use the graphics acceleration module 446. The operating system 495 then uses the information shown in Table 3 to invoke the hypervisor 496.

[0126] Table 3 - Operating System Call Parameters for the Hypervisor

[0127] 1 Working Descriptor (WD) 2 Authorization Mask Register (AMR) value (may be masked) 3 Valid Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual address (VA) accelerators utilize record pointers (AURP). 6 Virtual address of the Memory Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0128] Upon receiving a call from the management program, the management program 496 can verify that the operating system 495 has been registered and authorized to use the graphics acceleration module 446. The management program 496 then places the process element 483 into a process element linked list corresponding to the graphics acceleration module 446 type. The process element may contain the information shown in Table 4.

[0129] Table 4 - Process Element Information

[0130] 1 Working Descriptor (WD) 2 Authorization Mask Register (AMR) value (may be masked) 3 Valid Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual address (VA) accelerators utilize record pointers (AURP). 6 Virtual address of the Memory Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table, exported from hypervisor call parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 The Real Address (RA) management accelerator utilizes record pointers 12 Storage Descriptor Register (SDR)

[0131] In one embodiment, the hypervisor initializes the multiple accelerator integration slice 490 of register 445.

[0132] like Figure 4F As shown, one embodiment of the invention employs a unified memory addressable via a common virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations performed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion to second processor memory 402, a third portion to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 401-402 and GPU memories 420-423, thereby allowing any processor or GPU to access any physical memory having a virtual address mapped to said memory.

[0133] In one embodiment, the bias / coherence management circuitry 494A to 494E within one or more of the MMUs 439A to 439E ensures cache coherence between the host processor (e.g., 405) and the caches of the GPUs 410 to 413, and implements biasing techniques that indicate the physical memory where certain types of data should be stored. Although in Figure 4F Several instances of bias / coherence management circuitry 494A to 494E are shown, but bias / coherence circuitry can also be implemented within the MMU of one or more host processors 405 and / or within the accelerator integrated circuit 436.

[0134] One embodiment allows GPU-attached memories 420-423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the typical performance drawbacks associated with system-wide cache coherence. The ability to access GPU-attached memories 420-423 as system memory avoids heavy cache coherence overhead, providing a favorable operating environment for GPU offloading. This arrangement allows host processor 405 software to set operands and access computation results without the overhead of traditional I / O DMA data copies. These traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient compared to simple memory accesses. Furthermore, the ability to access GPU-attached memories 420-423 without cache coherence overhead can be critical to the execution time of offloading computations. For example, in scenarios with heavy streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410-413. The efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation all play a significant role in determining the effectiveness of GPU offloading.

[0135] In one implementation, the choice between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which may be a page-granular structure comprising 1 or 2 bits per GPU-attached memory page (i.e., controlled at the memory page level). The bias table can be implemented within the stolen memory range of one or more GPU-attached memories 420-423, with or without a bias cache in GPUs 410-413 (e.g., caching frequently / recently used entries of the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0136] In one implementation, the bias table entries associated with each access to GPU-attached memories 420-423 are accessed before the actual access to GPU memory, such that: First, local requests from GPUs 410-413 that find their pages in the GPU bias are directly forwarded to the corresponding GPU memories 420-423. Local requests from GPUs that find their pages in the host bias are forwarded to processor 405 (e.g., via a high-speed link as described above). In one embodiment, a request from processor 405 that finds the requested page in the host processor bias completes the request like a normal memory read. Alternatively, requests for GPU-biased pages can be forwarded to GPUs 410-413. If the GPU is not currently using the page, the GPU can convert the page to host processor bias.

[0137] The page bias state can be changed through software-based mechanisms, hardware-assisted software mechanisms, or, for a finite set of cases, hardware-only mechanisms.

[0138] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn invokes the GPU device driver, which then sends a message to the GPU (or enqueues a command descriptor), thereby instructing the GPU to change the bias state. For certain transitions, a cache dump clearing operation is performed on the host machine. This cache dump clearing operation is necessary for transitions from host processor 405 bias to GPU bias, but not necessary for the reverse transition.

[0139] In one embodiment, cache coherence is maintained by temporarily presenting GPU bias pages that the host processor 405 cannot cache. To access these pages, the processor 405 can request access from the GPU 410, which may grant access immediately or not, depending on its implementation. Therefore, to reduce communication between the processor 405 and the GPU 410, it is advantageous to ensure that the GPU bias pages are pages needed by the GPU but not by the host processor 405, and vice versa.

[0140] Graphics processing pipeline

[0141] Figure 5 A graphics processing pipeline 500 according to an embodiment is illustrated. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem such as those described herein. Figure 2A Within the parallel processor 200, in one embodiment, the parallel processor is Figure 1 Variations of the (multiple) parallel processors 112. As described herein, various parallel processing systems can be implemented via parallel processing units (e.g., Figure 2A One or more instances of parallel processing units 202) implement the graphics processing pipeline 500. For example, shader units (e.g., Figure 2D The graphics multiprocessor 234 can be configured to perform the functions of one or more of the vertex processing unit 504, tessellation control processing unit 508, tessellation evaluation processing unit 512, geometry processing unit 516, and fragment / pixel processing unit 524. The functions of the data assembler 502, primitive assemblers 506, 514, 518, tessellation unit 510, rasterizer 522, and raster operation unit 526 can also be handled by a processing cluster (e.g., Figure 3A Other processing engines and corresponding partition units (e.g., within the processing cluster 214) Figure 2CThe graphics processing pipeline 500 is executed by partitioning units 220A to 220N. The graphics processing pipeline 500 can also be implemented using one or more dedicated processing units. In one embodiment, one or more portions of the graphics processing pipeline 500 can be executed by parallel processing logic within a general-purpose processor (e.g., CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 can access on-chip memory (e.g., such as memory interface 528) via memory interface 528. Figure 2A The parallel processor memory 222 shown can be a memory interface. Figure 2A An example of memory interface 218.

[0142] In one embodiment, the data assembler 502 is a processing unit that collects vertex data of surfaces and primitives. The data assembler 502 then outputs vertex data, including vertex attributes, to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes a vertex shader program to illuminate and transform vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in a cache, local, or system memory for processing vertex data and can be programmed to transform vertex data from an object-based coordinate representation to world space coordinate space or normalized device coordinate space.

[0143] The first instance of the primitive assembler 506 receives vertex attributes from the vertex processing unit 504. The primitive assembler 506 reads the stored vertex attributes as needed and constructs graphic primitives for processing by the tessellation control processing unit 508. Graphic primitives include triangles, line segments, points, patches, etc., supported by various graphics processing application programming interfaces (APIs).

[0144] The tessellation control processing unit 508 treats input vertices as control points for a geometric patch. These control points are transformed from an input representation of the patch (e.g., the patch's basis) into a representation suitable for surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 can also calculate tessellation factors for the edges of the geometric patch. The tessellation factor is applied to a single edge and quantifies the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and subdivide the patch into multiple geometric primitives, such as lines, triangles, or quadrilaterals, which are then transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate a surface representation and vertex attributes associated with each vertex of the geometric primitive.

[0145] A second instance of the primitive assembler 514 receives vertex attributes from the tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphic primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphic primitives received from the primitive assembler 514 as specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to subdivide the graphic primitives into one or more new graphic primitives and calculate parameters for rasterizing the new graphic primitives.

[0146] In some embodiments, the geometry processing unit 516 may add or delete elements in the geometry flow. The geometry processing unit 516 outputs parameters and vertices specifying new graphic primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphic primitives for processing by the viewport scaling, picking, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for processing geometric data. The viewport scaling, picking, and clipping unit 520 performs clipping, picking, and viewport scaling, and outputs the processed graphic primitives to the rasterizer 522.

[0147] Rasterizer 522 can perform depth picking and other depth-based optimizations. Rasterizer 522 also performs scan transformations on new graphic primitives to generate fragments and outputs these fragments and associated overlay data to fragment / pixel processing unit 524.

[0148] Fragment / pixel processing unit 524 is a programmable execution unit configured to execute fragment shader or pixel shader programs. Fragment / pixel processing unit 524 transforms fragments or pixels received from rasterizer 522 as specified by the fragment or pixel shader program. For example, fragment / pixel processing unit 524 can be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels output to raster operation unit 526. Fragment / pixel processing unit 524 can read data stored in parallel processor memory or system memory for use when processing fragment data. Fragment or pixel shader programs can be configured to shade at sample, pixel, tile, or other granularities according to a sampling rate configured for the processing unit.

[0149] The raster operation unit 526 is a processing unit that performs raster operations including but not limited to stencil printing, z-testing, and blending, and outputs pixel data as processed graphic data for storage in a graphics memory, for example, as... Figure 2A Parallel processor memory 222 in the memory, and / or such as Figure 1The system memory 104 is used for display on one or more display devices 110 or for further processing by one or more processors 102 or one or more parallel processors 112. In some embodiments, the raster operation unit 526 is configured to compress z-or color data written to memory and decompress z-or color data read from memory.

[0150] Figure 6 A computing device 600 is shown, illustrating a managed barrier and synchronization mechanism 610 according to one embodiment. The computing device 600 represents a communication and data processing device, including (but not limited to) smart wearable devices, smartphones, virtual reality (VR) devices, head-mounted displays (HMDs), mobile computers, Internet of Things (IoT) devices, laptop computers, desktop computers, server computers, etc., and is compatible with… Figure 1 The computing device 100 is similar to or the same as that described above; therefore, for the sake of brevity, clarity and ease of understanding, the above references will not be discussed or repeated further hereafter. Figures 1 to 5 The many details mentioned.

[0151] The computing device 600 may further include (but is not limited to) autonomous machines or artificial intelligence agents, such as mechanical agents or machines, electronic agents or machines, virtual agents or machines, electromechanical agents or machines, etc. Examples of autonomous machines or artificial intelligence agents may include (but are not limited to) robots, autonomous vehicles (e.g., self-driving cars, autonomous flying aircraft, autonomous navigation ships, etc.), autonomous equipment (autonomous construction vehicles, autonomous medical equipment, etc.), and so on. Throughout this document, "computing device" may be interchangeably referred to as "autonomous machine" or "artificial intelligence agent" or simply "robot".

[0152] It is envisioned that, although the terms "autonomous vehicle" and "autonomous driving" are used throughout this document, the embodiments are not limited thereto. For example, "autonomous vehicle" is not limited to automobiles, but can include any number and type of autonomous machines, such as robots, autonomous devices, home autonomous devices, etc., and any one or more tasks or operations associated with such autonomous machines can be used interchangeably with autonomous driving.

[0153] The computing device 600 may further include (but is not limited to) mainframe computers, such as server computers, desktop computers, etc., and may further include set-top boxes (e.g., internet-based cable TV set-top boxes, etc.), GPS-based devices, etc. The computing device 600 may include mobile computing devices used as communication devices, such as cellular phones including smartphones, personal digital assistants (PDAs), tablet computers, laptop computers, e-readers, smart TVs, television platforms, wearable devices (e.g., glasses, watches, bracelets, smart cards, jewelry, clothing, etc.), media players, etc. For example, in one embodiment, the computing device 600 may include a mobile computing device employing a computer platform that hosts integrated circuits (“ICs”) such as systems-on-a-chip (“SoCs” or “SOCs”) that integrate various hardware and / or software components of the computing device 600 onto a single chip.

[0154] As shown, in one embodiment, computing device 600 may include any number and type of hardware and / or software components, such as (but not limited to) a graphics processing unit (“GPU” or “graphics processor” for short) 614, a graphics driver (also referred to as a “GPU driver,” “graphics driver logic,” “driver logic,” user-mode driver (UMD), UMD, user-mode driver framework (UMDF), UMDF, or simply “driver”) 616, a central processing unit (“CPU” or “application processor” for short) 612, memory 608, network devices, drivers, etc., and input / output (I / O) sources 604, such as a touchscreen, touch panel, touchpad, virtual or conventional keyboard, virtual or conventional mouse, ports, connectors, etc. Computing device 600 may include an operating system (OS) 606 that serves as an interface between the hardware and / or physical resources of computing device 600 and the user. It is contemplated that the graphics processor 614 and application processor 612 may be… Figure 1 One or more of the processors 102.

[0155] It should be understood that, for some implementations, systems equipped with fewer or more features than those described above may be preferred. Therefore, the configuration of the computing device 600 may vary depending on the implementation, depending on numerous factors (such as price constraints, performance requirements, technological improvements, or other circumstances).

[0156] The embodiment may be implemented as any one or a combination of the following: one or more microchips or integrated circuits interconnected using a motherboard, hard-wired logic, software stored in a memory device and executed by a microprocessor, firmware, application-specific integrated circuits (ASICs) and / or field-programmable gate arrays (FPGAs). By way of example, the terms “logic,” “module,” “component,” “engine,” and “mechanism” may include software or hardware and / or a combination of software and hardware.

[0157] In one embodiment, the barrier and synchronization mechanism 610 may be managed or facilitated by the operating system 606 of the computing device 600. In another embodiment, the barrier and synchronization mechanism 610 may be managed by or part of the graphics processing unit (“GPU” or simply “graphics processor”) 614 or the firmware of the graphics processor 614. For example, the barrier and synchronization mechanism 610 may be embedded in the processing hardware of the graphics processor 614 or may be implemented as part of it. Similarly, in yet another embodiment, the storage mechanism 610 may be managed by or part of the central processing unit (“CPU” or simply “application processor”) 612. For example, the barrier and synchronization mechanism 610 may be embedded in the processing hardware of the application processor 612 or may be implemented as part of it. In yet another embodiment, the barrier and synchronization mechanism 610 may be hosted or be part of any number and type of components of the computing device 600. For example, one part of the barrier and synchronization mechanism 610 may be hosted or be part of the operating system 606, another part may be hosted or be part of the graphics processor 614, another part may be hosted or be part of the application processor 612, and one or more parts of the barrier and synchronization mechanism 610 may be hosted or be part of any number and type of devices of the operating system 606 and / or the computing device 600. It is contemplated that one or more parts or components of the barrier and synchronization mechanism 610 may be used as hardware, software, and / or firmware.

[0158] It is conceivable that the embodiments are not limited to any particular implementation or hosting of the barrier and synchronization mechanism 610, and the barrier and synchronization mechanism 610 and one or more of its components may be implemented as hardware, software, firmware or any combination thereof.

[0159] The computing device 600 can host multiple network interfaces to provide access to networks such as LANs, wide area networks (WANs), metropolitan area networks (MANs), personal area networks (PANs), Bluetooth, cloud networks, mobile networks (e.g., 3G, 4G, etc.), intranets, the Internet, etc. The multiple network interfaces may include, for example, a wireless network interface with an antenna, which may represent one or more antennas. The multiple network interfaces may also include, for example, a wired network interface for communicating with a remote device via a network cable, which may be, for example, an Ethernet cable, coaxial cable, optical fiber, serial cable, or parallel cable.

[0160] Embodiments may be provided, for example, as a computer program product, which may include one or more machine-readable media having machine-executable instructions stored thereon, which, when executed by one or more machines (such as a computer, a network of computers, or other electronic devices), cause one or more machines to perform operations according to the embodiments described herein. Machine-readable media may include, but are not limited to: floppy disks, optical disks, CD-ROMs (CD-ROMs) and magneto-optical disks, ROMs, RAMs, EPROMs (erasable programmable read-only memory), EEPROMs (electrically erasable programmable read-only memory), magnetic cards or optical cards, flash memory, or other types of media / machine-readable media suitable for storing machine-executable instructions.

[0161] Furthermore, the embodiments can be downloaded as a computer program product, wherein the program can be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communication link (e.g., a modem and / or a network connection) by means of one or more data signals embodied in and / or modulated by a carrier or other propagation medium.

[0162] Throughout this document, the term "user" may be used interchangeably with "viewer," "observer," "person," "individual," "end-user," etc. It should be noted that throughout this document, terms like "graphics domain" may be used interchangeably with "graphics processing unit," "graphics processor," or simply "GPU," and similarly, "CPU domain" or "host domain" may be used interchangeably with "computer processing unit," "application processor," or simply "CPU."

[0163] It should be noted that throughout this document, terms such as "node," "computing node," "server," "server device," "cloud computer," "cloud server," "cloud server computer," "machine," "host," "device," "computing device," "computer," and "computer system" can be used interchangeably. It should further be noted that throughout this document, terms such as "application," "software application," "program," "software program," "package," and "software package" can be used interchangeably. Furthermore, throughout this document, terms such as "job," "input," "request," and "message" can be used interchangeably.

[0164] Figure 7 An example of one embodiment is shown. Figure 6 The barriers and synchronization mechanisms 610. For the sake of brevity, those already referenced will not be repeated or discussed hereafter. Figures 1 to 6 Many details are discussed. In one embodiment, the barrier and synchronization mechanism 610 may include any number and type of components, such as (but not limited to): detection / observation logic 701; barrier logic 703; synchronization logic 705; communication / compatibility logic 707; and preemption and scheduling logic 709.

[0165] Conventional techniques for barriers are severely limited because they primarily focus on software-based synchronization, which is inherently limited and inefficient in terms of cost and resources, such as power, time, and storage. Furthermore, these techniques do not provide a global approach across all processors, such as GPUs.

[0166] The embodiments provide novel techniques for employing multi-die barriers for machine learning, wherein synchronization is provided across GPUs, such as providing hardware acceleration for barriers across GPU dies.

[0167] It's conceivable that barriers are typically used to synchronize threads within a thread group. However, any thread in the thread group executing a barrier instruction will be stalled until all threads in the group reach the same point, signaled by the execution of the barrier instruction through them. In other words, barrier instructions make signaling and synchronization hardware necessary, which restricts these barrier instructions to a cluster or block of compute elements, as any thread group needs to be scheduled within its corresponding compute element block / cluster. Since machine learning can have a considerable number of threads, this restriction of threads to a smaller cluster / block of compute resources limits overall throughput.

[0168] In one embodiment, barrier logic 703 is used to provide a novel multi-die barrier to threads in a thread group, thereby enabling... Figure 8AThese threads can be scheduled across a larger group of computing elements, as shown. For example, the detection / observation logic 701 can be used to detect any number and type of threads and thread groups that require scheduling or dispatching that can be accomplished through multi-die barriers.

[0169] In one embodiment, barrier logic 703 is used to employ a multi-die barrier to facilitate scheduling of threads and / or thread groups across all computing elements, without being tied to a specific block of computing elements. Furthermore, to ensure proper operation of this technique, barrier logic 703 facilitates the necessary control and synchronization to allow seamless communication of data / information across all dies associated with the multi-die barrier, thereby enabling the maintenance of synchronization and ordering between multi-stage GPUs such as the graphics processor 614.

[0170] The embodiments further provide a novel technique for pre-thread synchronization within and across thread groups, facilitated by synchronization logic 705. In one embodiment, synchronization logic 705 can be used to maintain synchronization not only within a thread group but also across multiple thread groups by extending a fence across those multiple thread groups without any barriers.

[0171] Current application programming interfaces (APIs) only allow synchronization within a thread group (such as through the use of thread group barriers). In one embodiment, synchronization logic 705 adds a new barrier command for cross-thread group synchronization, enabling multiple thread groups to be synchronized. For example, the X-thread barrier command can be associated with a list of thread group identifiers (IDs) as part of an argument, where the thread groups listed in the argument and identified by their IDs can then be synchronized. Furthermore, since different thread groups can run in different streaming multiprocessors (SMs), GPU hardware such as the graphics processor 614 can add cross switches or DSS structures to communicate barrier synchronization across these SMs. Figure 8B This was demonstrated in China.

[0172] The embodiments further provide the use of barriers, such as the synchronization logic 705, and thread group synchronization, such as using global barriers to synchronize across thread groups. For example, as per [reference to...] Figure 8C As demonstrated, surface libraries, such as those working on GPUs (e.g., Convolutional Neural Networks, CNNs), can be used to perform data sharing across GPUs like the Graphics Processing Unit 614. These surface libraries can store intermediate NN data as data surfaces in a cloud database. Other deep learning systems aiming to solve the same or similar problems can use side-by-side intermediate NN data (e.g., autonomous vehicles, such as Autonomous Machine 600) to obtain similar views and can share NN data.

[0173] Furthermore, in one embodiment, using synchronization logic 705, any surface generated in this way can be optionally compressed for faster transmission times, wherein the shared surface can be used to cross-reference results between two or more deep learning systems, such as autonomous machine 600. This can result in higher fault tolerance, such as two vehicles side-by-side potentially cross-reference their intermediate NN surfaces to be close enough.

[0174] The embodiments further provide a novel technique for scheduling thread groups across SM (or DSS) or GPUs, wherein these thread groups cannot access shared local memory (SLM).

[0175] In current GPU implementations, all threads in a thread group run in the same SM (or DSS) because they share the same SLM and / or use barriers for synchronization. For example, each SM implements both an SLM and hardware barriers, and therefore, in order for the barriers and SLM to work, all threads in the thread group are assigned to the same SM.

[0176] In one embodiment, a stop in the dispatch is used such that, assuming the GPU then has two SMs at any given time, SM0 with 10 idle threads and SM1 with 6 idle threads, a new thread group can then be ready to be scheduled using 16 threads. In this case, neither of the two SMs can currently coordinate the thread gap because they do not have 16 idle threads. However, there are a sufficient number of idle threads between the two SMs to schedule the new thread group.

[0177] In one embodiment, using preemption and scheduling logic 709, the thread scheduler policy can be modified to allow for, for example, Figure 6 The compiler and / or driver of driver 616 can continue and determine whether the thread group is using any barriers, while detecting the SLM size being used by the thread group. Now, if the thread group is not using any barriers or SLM, the thread scheduler can be facilitated by preemption and scheduling logic 709 to schedule the thread group across multiple SMs.

[0178] However, if the thread group uses a small amount of SLM space that the preemption and scheduling logic 709 deems not critical to system performance, the thread scheduler can be facilitated by the preemption and scheduling logic 709 to map this SLM space to global memory and subsequently schedule the thread group across multiple SMs. In some embodiments, the compiler can be facilitated by the preemption and scheduling logic 709 to estimate whether mapping the SLM space to global memory is acceptable (e.g., in terms of performance) and pass this hint to the thread scheduler. These hints can then become part of the thread group state in memory. (See also...) Figure 9AThis was presented and further discussed.

[0179] The embodiments further provide a novel technique for barrier-based thread group preemption, facilitated by the preemption and scheduling logic 709.

[0180] Imagine a barrier used to synchronize threads within a thread group. Any thread in a given thread group executing a barrier instruction might be stopped until all threads in the group have reached the point signaled by the thread group executing the barrier instruction. This barrier instruction may require signaling and synchronization hardware, where threads in the thread group execute the barrier that all other threads are waiting for. Although most threads may have completed execution by reaching the barrier, the process might still be stopped until all other threads or the thread group has reached that point. The need for synchronization can lead to suboptimal utilization of hardware resources and decreased workload throughput.

[0181] In one embodiment, preemption and scheduling logic 703 can be used to allow a thread group to be preempted while allowing other thread groups to continue running. For example, the first thread group might switch to execution when a second thread group completes execution or enters a similar barrier-stopped state. In one embodiment, preemption and scheduling logic 703 can allow the thread scheduler to maintain a list and state of preemptible thread groups, while having a maximum limit on how many of these thread groups might be preempted at a given time in order to maintain and sustain trace control to a manageable size. Figure 9B This was demonstrated.

[0182] Furthermore, communication / compatibility logic 707 can be used to facilitate the desired communication and compatibility between any number of devices of computing device 600 and the various components of barrier and synchronization mechanism 610.

[0183] Communication / compatibility logic 707 can be used to facilitate dynamic communication and compatibility between computing device 600 and the following: any number and type of other computing devices (such as mobile computing devices, desktop computers, server computing devices, etc.); processing devices or components (such as CPUs, GPUs, etc.); acquisition / sensing / detection devices (such as acquisition / sensing components including cameras, depth-sensing cameras, camera sensors, red-green-blue (“RGB” or “rgb”) sensors, microphones, etc.); display devices (such as output components, including displays, display areas, display projectors, etc.); user / context-aware components and / or identification / authentication sensors. Devices / appliances (such as biosensors / detectors, scanners, etc.); databases 730, such as memory or storage devices, databases and / or data sources (such as data storage devices, hard disk drives, solid-state drives, hard disks, memory cards or devices, memory circuits, etc.); communication media 725, such as one or more communication channels or networks (e.g., cloud networks, the Internet, intranets, cellular networks, proximity networks such as Bluetooth, Bluetooth Low Energy (BLE), Bluetooth Smart, Wi-Fi proximity, radio frequency identification (RFID), near field communication (NFC), body area networks (BAN), etc.); wireless or wired communication and related protocols (e.g., WiMAX, Ethernet, etc.); connectivity and location management technologies; software applications / websites (e.g., social and / or business networking websites, business applications, games and other entertainment applications); and programming languages, while ensuring compatibility with constantly changing technologies, parameters, protocols, standards, etc.

[0184] In addition, specific brands, words, terms, phrases, names, and / or acronyms (such as "detection," "observation," "thread," "thread group," "memory," "computing resource," "scheduling," "synchronization," "preemption," "streaming multiprocessor," "barrier," "multi-chip barrier," "training set," "autonomous machine," "agent," "machine," "vehicle," "robot," "driving," "CNN," "DNN," "NN," "execution unit," "EU," "shared local memory," "SLM," "graphics streaming," "cache," "graphics cache," "GPU," "graphics processor," "GPU domain," "GPGPU," "CPU," "application processor," "CPU domain," "graphics driver," "workload," "application," "graphics pipeline," "pipeline process," "API," "3D API"), Any use of terms such as “hardware,” “software,” “agent,” “graphics driver,” “kernel-mode graphics driver,” “user-mode driver,” “user-mode driver framework,” “buffer,” “graphics buffer,” “task,” “process,” “operation,” “software application,” “game,” etc., should not be read as limiting the embodiments to software or devices labeled in the product or literature outside of this document.

[0185] It is conceivable that any number and type of components can be added to or removed from the barrier and synchronization mechanism 610 to facilitate various embodiments, including the addition, removal, and / or enhancement of certain features. For the sake of simplicity, clarity, and ease of understanding, many of the standard and / or known components, such as those in computing devices, are not shown or discussed herein. It is conceivable that the embodiments described herein are not limited to any particular technology, topology, system, architecture, and / or standard, and are sufficiently dynamic to be adopted and adapted to any future changes.

[0186] Figure 8A An architectural setup 800 for adopting and using machine learning, according to one embodiment, is illustrated. For the sake of brevity, references to previous sections may be omitted or repeated thereafter. Figures 1 to 7 And many details within the discussion. Furthermore, the embodiments are not limited to any particular architectural layout, framework, setup, or structure of processes and / or components, such as setup 800.

[0187] As discussed earlier, conventional techniques are inefficient and unsuitable for machine learning because they typically cause threads or thread groups to halt until all threads or thread groups have reached the same point, signaled by those threads or thread groups executing the same barrier instruction. In other words, in conventional techniques, threads / thread groups are restricted to being dispatched or scheduled through specific blocks of computational elements, rather than exceeding them, which is particularly problematic for machine learning, as it often involves a large number of threads.

[0188] As shown in the figure, in one embodiment, barrier logic 703 is used in autonomous machines (such as...) Figure 6The autonomous machine 600 employs a multi-die barrier to allow threads in a thread group to be scheduled across all computing elements, rather than being limited to a specific group or cluster of computing elements. Furthermore, in one embodiment, as shown, barrier logic 703 provides communication with any number and type of processors (e.g., GPU0 801, GPU1 803, GPU2 805, GPU3 807, etc.) while facilitating barrier synchronization between GPUs 801-807, such that control and synchronization of information can be maintained across all processing devices (e.g., GPUs 801-807) associated with multiple dies. In one embodiment, the multi-die barrier may be a hardware barrier used to provide the hardware acceleration required for the barrier to operate across GPU dies 801-807. However, embodiments are not limited to this.

[0189] Figure 8B A framework 820 for facilitating the synchronization of thread groups in machine learning, according to one embodiment, is shown. For the sake of brevity, references to previous sections may be omitted or repeated thereafter. Figures 1 to 8A And many details within the discussion. Furthermore, the embodiments are not limited to any particular architectural layout, frame, setup, or structure of processes and / or components, such as frame 820.

[0190] As previously referred to Figure 7 The barrier command 831, discussed and shown herein, with argument 833, can be used to facilitate synchronization between multiple thread groups (such as TG0 821, TG1 823, TG2 825, and TGN 827) that can run on multiple different SMs. For example, it can be used... Figure 7 Synchronization logic 705 facilitates X-thread barrier commands, such as barrier command 831 with an argument 833 listing thread group IDs. In one embodiment, barrier command 831 is executed to facilitate and maintain data synchronization and communication between multiple thread groups 821-827 corresponding to the thread group IDs of the argument 833. Thus, thread groups 821-827 are synchronized even if they run on different SMs; the GPU hardware can add a cross-SM (or DSS) structure to enable cross-SM communication barrier synchronization.

[0191] Figure 8C A framework 840 for facilitating data sharing across GPUs using surface libraries in machine learning, according to one embodiment, is shown. For the sake of brevity, references to previous sections may be omitted or repeated thereafter. Figures 1 to 8B And many details within the discussion. Furthermore, the embodiments are not limited to any particular architectural layout, frame, setup, or structure of processes and / or components, such as frame 840.

[0192] For reference Figure 7As shown and discussed herein, each DL system 841, 843, 845 can store any intermediate NN data as surface data at one or more databases 730 (such as cloud databases) on (multiple) communication media 725 (such as cloud networks). It is conceivable that DL systems 841, 843, 845 can each represent an autonomous machine, such as an autonomous vehicle, and can be very close to or near each other, such as multiple autonomous vehicles traveling together on the same road.

[0193] In some embodiments, any surface data generated by DL systems 841, 843, 845 can be compressed to enable faster transmission between DL systems 841, 843, 845 and any other DL system or entity that is or is part of the frame 840. Thus, any number of DL systems 841, 843, 845 can communicate data / information with each other over multiple communication media 725, such that they are sufficiently close to each other's intermediate NN surfaces.

[0194] Figure 9A A graphics processor 614, according to one embodiment, is shown for facilitating optimized scheduling of thread groups in machine learning in a barrier-free or shared local memory context. For the sake of brevity, references to previous documentation may be omitted or repeated herein. Figures 1 to 8C And many details within the details of the discussion.

[0195] This place shows and previously about Figure 7 The graphics processor 614 discussed is shown as having multiple SMs, SMMs, or DSSs, such as SMM0 905 and SMM1 907. The illustrated embodiment further illustrates [the following description is missing from the original text]. Figure 7 The preemption and scheduling logic 709 facilitates communication between the thread scheduler 901 and the SMM 905 and 907, which is capable of receiving information or hints 903 from the compiler and / or driver regarding SLM, barriers, etc.

[0196] For example, in one embodiment, EU0 911A, EU1 911B, EU2 913A, and EU3 913B are shown as coming from the same thread group and being scheduled across SMs (such as SMMs 907, 907) because this particular thread group may not use any barriers 915, 917 or SLMs 921, 923. For example, if a thread group uses a small number of SLMs or is not determined to be performance-critical, the thread scheduler 901 can simply map this SLM space to global memory, thereby allowing it to schedule thread groups across multiple SMs, such as SMMs 907, 907.

[0197] Figure 9BA framework 950 for facilitating thread group preemption based on barriers in machine learning, according to one embodiment, is shown. For the sake of brevity, subsequent discussions or repeated references to previous documents may be omitted. Figures 1 to 9A And many details within the details of the discussion.

[0198] For reference Figure 7 In this paper and in the preceding discussion, a number of thread groups (such as TG0 951, TG1953, and TG2 955) are shown as associated with computing resources (such as computing elements, computing blocks, etc.) and as provided by Figure 7 The preemption and scheduling logic 709 facilitates communication with the thread scheduler 959 (such as a hardware thread scheduler).

[0199] As mentioned above, for example, using Figure 7 The preemption and scheduling logic 709 allows for the dispatching and execution of three threads, TG 951, 953, and 955. If TG1 953 either completes execution or enters a similar barrier-stall state, then TG0 951 can be switched to execution by the thread scheduler 959 without having to halt the entire process using computational resources 957. Similarly, using this novel technique and the availability of computational resources, when a thread in a thread group executes a barrier, it does not need to enter a stop state and wait for all other threads to reach that barrier point. This is achieved through the use of... Figure 7 The preemption and scheduling logic 709 is facilitated by the thread scheduler 959.

[0200] Machine Learning Overview

[0201] Machine learning algorithms are algorithms that can learn from a set of data. Implementations of machine learning algorithms can be designed to model high-level abstractions within a dataset. For example, image recognition algorithms can be used to determine which of several categories a given input belongs to; regression algorithms can output numerical values ​​given input; and pattern recognition algorithms can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0202] One example type of machine learning algorithm is a neural network. Many types of neural networks exist; a simple type is the feedforward network. A feedforward network can be implemented as an acyclic graph, where nodes are arranged in layers. Typically, a feedforward network topology consists of an input layer and an output layer, separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating the output in the output layer. Network nodes are fully connected to nodes in adjacent layers via edges, but there are no edges between nodes within a single layer. Data received at the nodes in the input layer of the feedforward network is propagated (i.e., “feedforward”) to the nodes in the output layer via activation functions that compute the state of nodes in each consecutive layer of the network based on coefficients (“weights”) associated with each of the edges connecting these layers. Depending on the specific model represented by the algorithm being executed, the output from a neural network algorithm can take various forms.

[0203] Before a machine learning algorithm can be used to model a specific problem, it is trained using a training dataset. Training a neural network involves: selecting a network topology; using a set of training data representing the problem being modeled by the network; and adjusting the weights until the network model exhibits minimum error for all instances in the training dataset. For example, during supervised learning training for a neural network, the output generated by the network in response to inputs representing instances in the training dataset is compared to the “correct” labeled output of those instances; an error signal representing the difference between the output and the labeled output is calculated; and the weights associated with the connections are adjusted to minimize the error as the error signal is backpropagated through the layers of the network. The network is considered “trained” when the error of each output generated from the instances in the training dataset is minimized.

[0204] The accuracy of machine learning algorithms is greatly affected by the quality of the dataset used to train the algorithm. The training process can be computationally intensive and may require a significant amount of time on a conventional general-purpose processor. Therefore, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, as the computations performed when adjusting the coefficients in a neural network are naturally suited to parallel implementation. Specifically, many machine learning algorithms and software applications have been adapted to use parallel processing hardware within general-purpose graphics processing devices.

[0205] Figure 10This is a generalized graph of 1000 stacks of machine learning software. Machine learning application 1002 can be configured to train a neural network using a training dataset or to achieve machine intelligence using a trained deep neural network. Machine learning application 1002 may include training and inference capabilities for the neural network and / or dedicated software, which can be used to train the neural network prior to deployment. Machine learning application 1002 can achieve any type of machine intelligence, including but not limited to: image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0206] Hardware acceleration for machine learning applications 1002 can be achieved via machine learning framework 1004. Machine learning framework 1004 provides a library of machine learning primitives. Machine learning primitives are the fundamental operations typically performed by machine learning algorithms. Without machine learning framework 1004, developers of machine learning algorithms would need to create and optimize the main computational logic associated with their algorithms, and then re-optimize that computational logic when a new parallel processor is developed. Instead, machine learning applications can be configured to use primitives provided by machine learning framework 1004 to perform the necessary computations. Exemplary primitives include tensor convolution, activation functions, and pooling, which are computational operations performed when training convolutional neural networks (CNNs). Machine learning framework 1004 can also provide primitives for implementing basic linear algebra subroutines performed by many machine learning algorithms, such as matrix and vector operations.

[0207] The machine learning framework 1004 can process input data received from the machine learning application 1002 and generate appropriate input for the computing framework 1006. The computing framework 1006 can abstract the low-level instructions provided to the GPGPU driver 1008, enabling the machine learning framework 1004 to utilize hardware acceleration via the GPGPU hardware 1010 without the machine learning framework 1004 being very familiar with the architecture of the GPGPU hardware 1010. Furthermore, the computing framework 1006 can implement hardware acceleration for the machine learning framework 1004 across various types and generations of GPGPU hardware 1010.

[0208] GPGPU Machine Learning Acceleration

[0209] Figure 11 A highly parallel general-purpose graphics processing unit 1100 is illustrated according to an embodiment. In one embodiment, the general-purpose processing unit (GPGPU) 1100 can be configured to be particularly efficient in handling the type of computational workload associated with training deep neural networks. Additionally, the GPGPU 1100 can be directly linked to other instances of GPGPUs to create multi-GPU clusters, thereby improving the training speed of particularly deep neural networks.

[0210] The GPGPU 1100 includes a host interface 1102 for connecting to a host processor. In one embodiment, the host interface 1102 is a PCI Express interface. However, the host interface can also be a vendor-specific communication interface or communication architecture. The GPGPU 1100 receives commands from the host processor and uses a global scheduler 1104 to distribute the execution threads associated with those commands to a group of compute clusters 1106A to 1106H. Compute clusters 1106A to 1106H share a cache memory 1108. The cache memory 1108 can act as a high-level cache within the cache memory of the compute clusters 1106A to 1106H.

[0211] The GPGPU 1100 includes memories 1114A to 1114B, which are coupled to computing clusters 1106A to 1106H via a set of memory controllers 1112A to 1112B. In various embodiments, memories 1114A to 1114B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory (e.g., synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory). In one embodiment, memory cells 224A to 224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM).

[0212] In one embodiment, each computing cluster GPLAB06A-H includes a set of graphics multiprocessors, such as Figure 4A The graphics multiprocessor 400 of the computing cluster includes various types of integer and floating-point logic units that can perform computational operations at a range of precisions, including precision suitable for machine learning computations. For example, in one embodiment, at least a subset of the floating-point units of each of the computing clusters 1106A to 1106H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0213] Multiple instances of GPGPU 1100 can be configured to operate as a computing cluster. The communication mechanisms used by the computing cluster for synchronization and data exchange vary across embodiments. In one embodiment, multiple instances of GPGPU 1100 communicate via host interface 1102. In one embodiment, GPGPU 1100 includes an I / O hub 1108 that couples GPGPU 1100 to GPU link 1110, which enables direct connections to other instances of GPGPU. In one embodiment, GPU link 1110 is coupled to a dedicated GPU-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1100. In one embodiment, GPU link 1110 is coupled to a high-speed interconnect for transmitting and receiving data to other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 1100 reside in a separate data processing system and communicate via a network device accessible via host interface 1102. In one embodiment, in addition to host interface 1102 or as an alternative to host interface 1102, GPU link 1110 may also be configured to connect to a host processor.

[0214] While the illustrated configuration of the GPGPU 1100 can be configured to train neural networks, one embodiment provides an alternative configuration of the GPGPU 1100 that can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, the GPGPU 1100 includes fewer compute clusters 1106A to 1106H compared to the training configuration. Additionally, the memory technology associated with memories 1114A to 1114B may differ between the inference and training configurations. In one embodiment, the inference configuration of the GPGPU 1100 may support inference-specific instructions. For example, the inference configuration may provide support for one or more 8-bit integer dot product instructions, which are typically used during inference operations for deployed neural networks.

[0215] Figure 12 A multi-GPU computing system 1200 according to an embodiment is illustrated. The multi-GPU computing system 1200 may include a processor 1202 coupled to a plurality of GPGPUs 1206A to D via a host interface switch 1204. In one embodiment, the host interface switch 1204 is a PCI Express switch device that couples the processor 1202 to a PCI Express bus through which the processor 1202 can communicate with the group of GPGPUs 1206A to D. Each of the plurality of GPGPUs 1206A to 1206D may be... Figure 11Examples of GPGPU 1100. GPGPU 1206A to D can be interconnected via a set of high-speed point-to-point GPU-GPU links 1216. High-speed GPU-GPU links can be via dedicated GPU links (e.g., such as...). Figure 11 The P2P GPU link 1216 connects to each of the GPGPUs 1206A through 1206D. The P2P GPU link 1216 enables direct communication between each of the GPGPUs 1206A through D without requiring communication via the host interface bus (to which the processor 1202 is connected). In the case of GPU-GPU traffic targeting the P2P GPU link, the host interface bus can still be used for system memory access or communication with other instances of the multi-GPU computing system 1200 (e.g., via one or more network devices). While in the illustrated embodiment the GPGPUs 1206A through D are connected to the processor 1202 via the host interface switch 1204, in one embodiment, the processor 1202 includes direct support for the P2P GPU link 1216 and can be directly connected to the GPGPUs 1206A through 1206D.

[0216] Machine learning neural network implementation methods

[0217] The computational architectures provided by the embodiments described herein can be configured to perform these types of parallel processing, which are particularly well-suited for training and deploying neural networks for machine learning. Neural networks can be generalized as networks of functions with graph relationships. As is well known in the art, there are various types of neural network implementations used in machine learning. One exemplary type of neural network is the feedforward network as previously described.

[0218] The second exemplary type of neural network is the Convolutional Neural Network (CNN). A CNN is a specialized feedforward neural network designed for processing data with a known, grid-like topology (e.g., image data). Therefore, CNNs are commonly used in computer vision and image recognition applications, but they can also be used in other types of pattern recognition, such as speech and language processing. Nodes in the input layer of a CNN are organized as a set of “filters” (feature detectors inspired by receptive fields found in the retina), and the output of each set of filters is propagated to nodes in successive layers of the network. The computation for a CNN involves applying convolutional mathematics to each filter to produce the output of that filter. Convolution is a specialized mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function related to convolution can be referred to as the input, and the second function can be referred to as the convolution kernel. The output can be referred to as a feature map. For example, the input to a convolutional layer can be a multidimensional array of data that defines various color components of the input image. The convolution kernel can be a multidimensional array of parameters, which are adapted through a training process for the neural network.

[0219] Recurrent Neural Networks (RNNs) are a type of feedforward neural network that includes feedback connections between layers. RNNs enable the modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture of an RNN includes loops. These loops represent the effect of the current value of a variable on its own value at future times, because at least a portion of the output data from the RNN is used as feedback to process subsequent inputs in the sequence. This variable nature of language data makes RNNs particularly useful for language processing.

[0220] The diagrams described below illustrate exemplary feedforward, CNN, and RNN networks, and describe the general process for training and deploying each of those types of networks respectively. It will be understood that these descriptions are exemplary and non-limiting with respect to any particular embodiment described herein, and that the concepts shown can generally be applied to deep neural networks and machine learning techniques.

[0221] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning performed using deep neural networks. In contrast to shallow neural networks that contain only a single hidden layer, the deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layers of the network enable multi-step pattern recognition, which results in reduced output error compared to shallow machine learning techniques.

[0222] Deep neural networks used in deep learning typically include a front-end network for performing feature recognition coupled to a back-end network representing a mathematical model, which can then perform operations (e.g., object classification, speech recognition, etc.) based on the feature representations provided to the model. Deep learning enables machine learning to be performed without requiring manual feature engineering on the model. Instead, deep neural networks can learn features based on statistical structure or correlations within the input data. The learned features can be provided to a mathematical model, which can then map the detected features to the output. The mathematical model used by the network is typically specialized for a specific task to be performed, and different models will be used to perform different tasks.

[0223] Once a neural network is structured, a learning model can be applied to it to train it to perform a specific task. The learning model describes how weights are adjusted within the model to reduce the network's output error. Backpropagation of error is a common method used to train neural networks. An input vector is presented to the network for processing. The network's output is compared to the expected output using a loss function, and an error value is calculated for each neuron in the output layer. These error values ​​are then backpropagated until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm (e.g., stochastic gradient descent) to update the neural network's weights.

[0224] Figures 13A-13B This demonstrates an exemplary convolutional neural network. Figure 13A Show the individual layers within a CNN. For example... Figure 13A As shown, an exemplary CNN for modeling image processing can receive input 1302, which describes the red, green, and blue (RGB) components of an input image. Input 1302 can be processed by multiple convolutional layers (e.g., convolutional layer 1304, convolutional layer 1306). Optionally, the output from the multiple convolutional layers can be processed by a set of fully connected layers 1308. Neurons in a fully connected layer have full connections to all activation functions in the previous layer, as previously described for feedforward networks. The output from the fully connected layer 1308 can be used to generate an output from the network. Matrix multiplication can be used instead of convolution to compute the activation functions within the fully connected layer 1308. Not all CNN implementations use fully connected layers 1308. For example, in some implementations, convolutional layers 1306 can generate the CNN output.

[0225] Convolutional layers are sparsely connected, unlike the traditional neural network configuration found in fully connected layers 1308. Traditional neural network layers are fully connected, such that each output unit interacts with each input unit. However, convolutional layers are sparsely connected because the output of the convolution of the receptive field (rather than the corresponding state value of each node in the receptive field) is fed to nodes in subsequent layers, as illustrated. The kernels associated with the convolutional layers perform convolution operations, the output of which is sent to the next layer. Dimensionality reduction performed within convolutional layers is one aspect that enables CNNs to scale to handle large images.

[0226] Figure 13B This illustrates an exemplary computational phase within a convolutional layer of a CNN. The input 1312 to the convolutional layer of the CNN can be processed in three phases within convolutional layer 1314. These three phases may include a convolution phase 1316, a detector phase 1318, and a pooling phase 1320. Convolutional layer 1314 can then output the data to successive convolutional layers. The last convolutional layer of the network can generate output feature map data or provide input to fully connected layers, for example, to generate classification values ​​for the input to the CNN.

[0227] Several convolutions are performed in parallel within convolutional stage 1316 to produce a set of linear activation functions. Convolutional stage 1316 may include affine transformations, which are any transformations that can be specified as a linear transformation plus a translation. Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolutional stage computes the output of a function (e.g., a neuron) connected to a specific region in the input, which can be determined as a local region associated with the neuron. The neuron computes the dot product between the neuron's weights and a region in the local input to which the neuron is connected. The output from convolutional stage 1316 defines a set of linear activation functions processed by successive stages of convolutional layer 1314.

[0228] Linear activation functions can be processed by detector stage 1318. In detector stage 1318, each linear activation function is processed by a nonlinear activation function. Nonlinear activation functions add nonlinearity to the overall network without affecting the receptive field of the convolutional layers. Several types of nonlinear activation functions can be used. One specific type is the Modified Linear Unit (ReLU), which uses an activation function defined as f(x) = max(0, x) such that the activation function is thresholded to zero.

[0229] Pooling stage 1320 uses a pooling function that replaces the output of convolutional layer 1306 with a generalized statistical value of the nearby output. The pooling function can be used to introduce translation invariance into the neural network, such that slight translations to the input do not change the pooling output. Local translation invariance can be useful when the presence of features in the input data is more important than the precise location of those features. Various types of pooling functions can be used during pooling stage 1320, including max pooling, average pooling, and L2-norm pooling. Additionally, some CNN implementations do not include a pooling stage. Instead, such implementations use an additional convolutional stage with a larger stride relative to the previous convolutional stage.

[0230] The output from convolutional layer 1314 can then be processed by the next layer 1322. The next layer 1322 can be either an additional convolutional layer or a fully connected layer 1308. For example, Figure 13A The first convolutional layer 1304 can output to the second convolutional layer 1306, and the second convolutional layer can output to the first layer in the fully connected layer 1308.

[0231] Figure 14 An exemplary recurrent neural network 1400 is shown. In a recurrent neural network (RNN), the previous state of the network influences the output of the current state. RNNs can be constructed in a variety of ways using a wide variety of functions. The use of RNNs typically revolves around using mathematical models to predict the future based on previous input sequences. For example, an RNN can be used to perform statistical language modeling to predict an upcoming word given a previous sequence of words. The shown RNN 1400 can be described as having the following components: an input layer 1402 that receives an input vector; a hidden layer 1404 for implementing the recurrent function; a feedback mechanism 1405 for implementing a 'memory' of previous states; and an output layer 1406 for outputting the result. The RNN 1400 operates based on time steps. The state of the RNN at a given time step is influenced by the feedback mechanism 1405 based on previous time steps. For a given time step, the state of the hidden layer 1404 is defined by the previous state and the input at the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1404. The second input (x2) can be processed by hidden layer 1404 using the state information determined during the processing of the initial input (x1). The given state can be computed as s. t =f(Ux t +Ws t-1), where U and W are parameter matrices. The function f is typically nonlinear, such as a variant of the hyperbolic tangent function (Tanh) or the correction function f(x) = max(0, x). However, the specific mathematical function used in hidden layer 1404 can vary depending on the specific implementation details of the RNN1400.

[0232] In addition to the basic CNN and RNN networks described, variations of those networks can be implemented. An example RNN variant is the Long Short-Term Memory (LSTM) RNN. LSTM RNNs are capable of learning long-term dependencies necessary for processing longer language sequences. A CNN variant is the Convolutional Deep Belief Network, which has a similar structure to a CNN and is trained in a similar manner to a deep belief network. A deep belief network (DBN) is a generative neural network consisting of multiple layers of stochastic (random) variables. A DBN can be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining an optimal set of initial weights for the neural network.

[0233] Figure 15 This demonstrates the training and deployment of deep neural networks. Once a given network has been structured for a task, it is trained using a training dataset. Various training frameworks have been developed to accelerate the training process. Figure 10 The machine learning framework 1004 can be configured as a training framework 1504. The training framework 1504 can be hooked up with an untrained neural network 1506 and enables the use of the parallel processing resources described herein to train the untrained neural network to generate a trained neural network 1508.

[0234] To begin the training process, initial weights can be selected randomly or by pre-training using a deep belief network. Training loops are then performed in a supervised or unsupervised manner.

[0235] Supervised learning is a learning method in which training is performed as an arbitration operation, such as when the training dataset 1502 includes inputs (which are paired with the expected outputs of said inputs), or when the training dataset includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the inputs and compares the resulting outputs with a set of expected or desired outputs. The error is then backpropagated through the system. The training framework 1504 can be tuned to adjust the weights controlling the untrained neural network 1506. The training framework 1504 can provide tools for monitoring the extent to which the untrained neural network 1506 converges to a model suitable for generating correct answers based on known input data. The training process occurs repeatedly as the network weights are adjusted to improve the outputs generated by the neural network. The training process can continue until the neural network reaches the statistically expected accuracy associated with the trained neural network 1508. The trained neural network 1508 can then be deployed to implement any number of machine learning operations.

[0236] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Therefore, for unsupervised learning, the training dataset 1502 would include input data without any associated output data. The untrained neural network 1506 can learn groupings within the unlabeled inputs and can determine how individual inputs relate to the overall dataset. Unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1507 capable of performing operations useful in data dimensionality reduction. Unsupervised training can also be used to perform anomaly detection, which allows the identification of data points in the input dataset that deviate from the normal pattern of the data.

[0237] Variations in supervised and unsupervised training can also be employed. Semi-supervised learning is a technique where the training dataset 1502 comprises a mixture of labeled and unlabeled data with the same distribution. Incremental learning is a variant of supervised learning where the input data is continuously used for further training of the model. Incremental learning enables the trained neural network 1508 to adapt to new data 1512 without forgetting the knowledge embedded within the network during the initial training.

[0238] Whether supervised or unsupervised, training very deep neural networks can be computationally too intensive for a single computing node. A distributed network of computing nodes can be used instead of a single node to accelerate the training process.

[0239] Figure 16This is a block diagram illustrating distributed learning. Distributed learning trains a model using multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. Each of these distributed computing nodes may include one or more host processors and general-purpose processing nodes, such as... Figure 11 The system features a highly parallel general-purpose graphics processing unit 1100. As shown, distributed learning can perform model parallelism 1602, data parallelism 1604, or a combination of model and data parallelism 1604.

[0240] In model parallelism 1602, different computing nodes in a distributed system can perform training computations on different parts of a single network. For example, each layer of a neural network can be trained by different processing nodes in a distributed system. Benefits of model parallelism include the ability to scale to exceptionally large models. Splitting the computations associated with different layers of a neural network makes it possible to train very large neural networks, where the weights of all layers are not fitted into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0241] In data parallelization 1604, different nodes in a distributed network have complete instances of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. While different approaches to data parallelization are possible, all data-parallel training methods require a technique for combining the results and synchronizing the model parameters across each node. Exemplary methods for combining data include parameter averaging and update-based data parallelization. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains the parameter data. Update-based data parallelization is similar to parameter averaging, except that model updates are passed instead of parameters from nodes to a parameter server. Additionally, update-based data parallelization can be performed in a distributed manner, where updates are compressed and passed between nodes.

[0242] For example, combined model and data parallelism can be implemented in a distributed system, where each compute node includes multiple GPUs. Each node can have a complete instance of the model, with individual GPUs within each node used to train different parts of the model.

[0243] Distributed training incurs increased overhead compared to training on a single machine. However, the parallel processors and GPGPUs described in this paper can each implement techniques to reduce the overhead of distributed training, including techniques for enabling high-bandwidth GPU-to-GPU data transfer and accelerating remote data synchronization.

[0244] Exemplary machine learning applications

[0245] Machine learning can be applied to solve a wide range of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range from reproducing human visual abilities (e.g., recognizing faces) to creating new categories of visual abilities. For example, a computer vision application can be configured to identify sound waves from vibrations induced in objects visible in a video. Parallel processor-accelerated machine learning enables the training of computer vision applications using training datasets significantly larger than previously feasible ones, and allows the deployment of inference systems using low-power parallel processors.

[0246] Parallel processor-accelerated machine learning has applications in autonomous driving, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on datasets that define appropriate responses to specific training inputs. The parallel processors described in this paper enable the rapid training of increasingly sophisticated neural networks for autonomous driving solutions and allow the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0247] Parallel processor-accelerated deep neural networks have been implemented as machine learning methods for Automatic Speech Recognition (ASR). ASR involves creating functions that compute the most probable language sequence given an input speech sequence. Accelerated machine learning using deep neural networks has replaced previous Hidden Markov Models (HMMs) and Gaussian Mixture Models (GMMs) used for ASR.

[0248] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. Automated learning programs can use statistical inference algorithms to generate models that are robust to errors or unfamiliar inputs. Exemplary natural language processor applications include automated machine translation between human languages.

[0249] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are typically highly parallel and include optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include... Figure 11The highly parallel general-purpose graphics processing unit 1100 and Figure 12 The multi-GPU computing system 1200. In contrast, deployed machine learning platforms typically include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0250] Figure 17 An exemplary System-on-Chip (SOC) 1700 for inference, suitable for performing inference using a trained model, is shown. The SOC 1700 may integrate multiple processing units, including a media processor 1702, a vision processor 1704, a GPGPU 1706, and a multi-core processor 1708. The SOC 1700 may additionally include on-chip memory 1705, which can implement a shared on-chip data pool accessible by each of the processing units. The processing units may be optimized for low-power operation to enable deployment to a wide variety of machine learning platforms, including autonomous vehicles and autonomous robots. For example, one implementation of the SOC 1700 can be used as part of a main control system for an autonomous vehicle. When the SOC 1700 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with the relevant functional safety standards of the deployment jurisdiction.

[0251] During operation, the media processor 1702 and the vision processor 1704 can work consistently to accelerate computer vision operations. The media processor 1702 enables low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in on-chip memory 1705. The vision processor 1704 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video to prepare them for processing using a trained image recognition model. For example, the vision processor 1704 can accelerate convolution operations for CNNs (for performing image recognition on high-resolution video data), while back-end model computation is performed by the GPGPU 1706.

[0252] The multi-core processor 1708 may include control logic for ordering and synchronization of data transfers and shared memory operations performed by the media processor 1702 and the vision processor 1704. The multi-core processor 1708 may also act as an application processor for executing software applications that can utilize the inference computing capabilities of the GPGPU 1706. For example, at least a portion of navigation and driving logic may be implemented in software executing on the multi-core processor 1708. Such software may directly offload computational workloads to the GPGPU 1706, or it may offload computational workloads to the multi-core processor 1708, which may offload at least a portion of those operations to the GPGPU 1706.

[0253] The GPGPU 1706 may include compute clusters, such as low-power configurations of compute clusters 1106A to 1106H within the highly parallel general-purpose graphics processing unit 1100. The compute clusters within the GPGPU 1706 can support instructions that are explicitly optimized for performing inference computations on trained neural networks. For example, the GPGPU 1706 can support instructions for performing low-precision computations (e.g., 8-bit and 4-bit integer vector operations).

[0254] System Overview II

[0255] Figure 18 This is a block diagram of a processing system 1800 according to an embodiment. In various embodiments, system 1800 includes one or more processors 1802 and one or more graphics processors 1808, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 1802 or processor cores 1807. In one embodiment, system 1800 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile devices, handheld devices, or embedded devices.

[0256] Embodiments of system 1800 may include or incorporate server-based gaming platforms, game consoles, including game and media consoles, mobile game consoles, handheld game consoles, or online game consoles. In some embodiments, system 1800 is a mobile phone, smartphone, tablet computing device, or mobile internet device. Data processing system 1800 may also include wearable devices (such as smartwatches, smart glasses, augmented reality devices, or virtual reality devices), coupled to said wearable device, or integrated into said wearable device. In some embodiments, data processing system 1800 is a television or set-top box device having one or more processors 1802 and a graphical interface generated by one or more graphics processors 1808.

[0257] In some embodiments, one or more processors 1802 each include one or more processor cores 1807 for processing instructions that, when executed, perform operations on the system and user software. In some embodiments, each of the one or more processor cores 1807 is configured to process a particular instruction set 1809. In some embodiments, the instruction set 1809 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). Multiple processor cores 1807 may each process different instruction sets 1809, which may include instructions for facilitating emulation of other instruction sets. Processor cores 1807 may also include other processing devices, such as digital signal processors (DSPs).

[0258] In some embodiments, processor 1802 includes cache memory 1804. Depending on the architecture, processor 1802 may have a single internal cache or multiple levels of internal caches. In some embodiments, cache memory is shared among components of processor 1802. In some embodiments, processor 1802 also uses an external cache (e.g., a Level 3 (L3) cache or a Last Level Cache (LLC)) (not shown), which can be shared among processor core 1807 using known cache coherence techniques. Additionally, register file 1806 is included in processor 1802, which may include different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers). Some registers may be general-purpose registers, while others may be specific to the design of processor 1802.

[0259] In some embodiments, processor 1802 is coupled to processor bus 1810, which is used to transmit communication signals, such as address, data, or control signals, between processor 1802 and other components within system 1800. In one embodiment, system 1800 uses an exemplary 'central' system architecture including a memory controller central hub 1816 and an input / output (I / O) controller central hub 1830. Memory controller central hub 1816 facilitates communication between memory devices and other components of system 1800, while I / O controller central hub (ICH) 1830 provides connectivity to I / O devices via a local I / O bus. In one embodiment, the logic of memory controller central hub 1816 is integrated within the processor.

[0260] Memory device 1820 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or some other memory device with suitable performance for use as processing memory. In one embodiment, memory device 1820 may operate as system memory of system 1800 to store data 1822 and instructions 1821 for use when one or more processors 1802 execute an application or process. Memory controller hub 1816 is also coupled to an optional external graphics processor 1812, which may communicate with one or more graphics processors 1808 in processor 1802 to perform graphics and media operations.

[0261] In some embodiments, ICH 1830 enables peripheral components to be connected to memory device 1820 and processor 1802 via a high-speed I / O bus. I / O peripherals include, but are not limited to: an audio controller 1846, a firmware interface 1828, a wireless transceiver 1826 (e.g., Wi-Fi, Bluetooth), a data storage device 1824 (e.g., hard disk drive, flash memory, etc.), and a conventional I / O controller 1840 for coupling conventional (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1842 connect multiple input devices, such as a keyboard and mouse combination 1844. A network controller 1834 may also be coupled to ICH 1830. In some embodiments, a high-performance network controller (not shown) is coupled to processor bus 1810. It should be understood that the illustrated system 1800 is exemplary and not limiting, as other types of data processing systems configured differently may also be used. For example, the I / O controller hub 1830 may be integrated within one or more processors 1802, or the memory controller hub 1816 and the I / O controller hub 1830 may be integrated within a discrete external graphics processor (such as external graphics processor 1812).

[0262] Figure 19 This is a block diagram of an embodiment of processor 1900, which has one or more processor cores 1902A to 1902N, an integrated memory controller 1914, and an integrated graphics processor 1908. Figure 19Those elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Processor 1900 may include, and include, an additional core 1902N, indicated by a dashed box. Processor cores 1902A to 1902N each include one or more internal cache units 1904A to 1904N. In some embodiments, each processor core may also access one or more shared cache units 1906.

[0263] Internal cache units 1904A to 1904N and shared cache unit 1906 represent the cache memory hierarchy within processor 1900. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared intermediate cache, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, wherein the highest-level cache is classified as LLC before external memory. In some embodiments, cache coherence logic maintains coherence between cache units 1906 and 1904A to 1904N.

[0264] In some embodiments, the processor 1900 may further include a set of one or more bus controller units 1916 and a system agent core 1910. The one or more bus controller units 1916 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 1910 provides management functions for each processor unit. In some embodiments, the system agent core 1910 includes one or more integrated memory controllers 1914 for managing access to various external memory devices (not shown).

[0265] In some embodiments, one or more of processor cores 1902A to 1902N include support for simultaneous multithreading. In this embodiment, system agent core 1910 includes components for coordinating and operating cores 1902A to 1902N during multithreaded processing. Additionally, system agent core 1910 may also include a power control unit (PCU) including logic and components for regulating the power states of processor cores 1902A to 1902N, and a graphics processor 1908.

[0266] In some embodiments, processor 1900 further includes a graphics processor 1908 for performing graphics processing operations. In some embodiments, graphics processor 1908 is coupled to a shared cache unit 1906 and a system proxy core 1910, the system proxy core including one or more integrated memory controllers 1914. In some embodiments, display controller 1911 is coupled to graphics processor 1908 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 1911 may be a separate module coupled to graphics processor via at least one interconnect, or it may be integrated within graphics processor 1908 or system proxy core 1910.

[0267] In some embodiments, ring-based interconnect units 1912 are used to couple internal components of processor 1900. However, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, including those well known in the art, may be used. In some embodiments, graphics processor 1908 is coupled to ring interconnect 1912 via I / O link 1913.

[0268] Exemplary I / O link 1913 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and a high-performance embedded memory module 1918 (such as an eDRAM module). In some embodiments, each of the processor cores 1902A to 1902N and the graphics processor 1908 uses the embedded memory module 1918 as a shared final-level cache.

[0269] In some embodiments, processor cores 1902A to 1902N are homogeneous cores executing the same instruction set architecture. In another embodiment, processor cores 1902A to 1902N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of processor cores 1902A to 1902N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 1902A to 1902N are homogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled to one or more power cores with lower power consumption. Additionally, processor 1900 can be implemented on one or more chips or implemented as a SoC integrated circuit having, among other components, the components shown.

[0270] Figure 20This is a block diagram of a graphics processing unit 2000, which may be a discrete graphics processing unit or a graphics processing unit integrated with multiple processing cores. In some embodiments, the graphics processing unit communicates with memory via a mapped I / O interface to registers on the graphics processing unit and using commands placed in processor memory. In some embodiments, the graphics processing unit 2000 includes a memory interface 2014 for accessing memory. The memory interface 2014 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0271] In some embodiments, the graphics processor 2000 further includes a display controller 2002 for driving display output data to a display device 2020. The display controller 2002 includes hardware for one or more overlapping planes of the display and a multi-layer video or user interface component. In some embodiments, the graphics processor 2000 includes a video codec engine 2006 for encoding, decoding, or converting media codes to, from, or between one or more media encoding formats, including but not limited to: Moving Picture Experts Group (MPEG) (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1, and Joint Group of Picture Experts Group (JPEG) formats (such as JPEG and Motion JPEG (MJPEG)).

[0272] In some embodiments, the graphics processor 2000 includes a block image transfer (BLIT) engine 2004 for performing two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfer. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 2010. In some embodiments, the graphics processing engine 2010 is a computational engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0273] In some embodiments, GPE 2010 includes a 3D pipeline 2012 for performing 3D operations, such as rendering 3D images and scenes using processing functions acting on 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 2012 includes programmable and fixed functional elements that perform various tasks within elements and / or generated execution threads of the 3D / media subsystem 2015. While the 3D pipeline 2012 can be used to perform media operations, embodiments of GPE 2010 also include a media pipeline 2016 specifically for performing media operations such as video post-processing and image enhancement.

[0274] In some embodiments, the media pipeline 2016 includes fixed-function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterleaving, and video encoding acceleration, in place of or on behalf of the video codec engine 2006. In some embodiments, the media pipeline 2016 further includes a thread generation unit to generate threads for execution on the 3D / media subsystem 2015. The generated threads perform calculations on media operations on one or more graphics execution units included in the 3D / media subsystem 2015.

[0275] In some embodiments, the 3D / media subsystem 2015 includes logic for executing threads generated by the 3D pipeline 2012 and the media pipeline 2016. In one embodiment, the pipelines send thread execution requests to the 3D / media subsystem 2015, the 3D / media subsystem including thread dispatch logic for arbitrating and dispatching requests to available thread execution resources. Execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 2015 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) for sharing data between threads and for storing output data.

[0276] 3D / Media Processing

[0277] Figure 21 This is a block diagram of a graphics processing engine 2110 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 2110 is... Figure 20 The image shows a version of GPE 2010. Figure 21 Those elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. For example, shown Figure 20 The 3D pipeline 2012 and the media pipeline 2016. The media pipeline 2016 is optional in some embodiments of the GPE 2110 and may not be explicitly included within the GPE 2110. For example, and in at least one embodiment, a separate media and / or image processor is coupled to the GPE 2110.

[0278] In some embodiments, GPE 2110 is coupled to or includes command stream converter 2103, which provides command streams to 3D pipeline 2012 and / or media pipeline 2016. In some embodiments, command stream converter 2103 is coupled to memory, which may be system memory, or one or more cache memories of internal cache memory and shared cache memory. In some embodiments, command stream converter 2103 receives commands from memory and sends these commands to 3D pipeline 2012 and / or media pipeline 2016. The commands are instructions obtained from a ring buffer storing instructions for 3D pipeline 2012 and media pipeline 2016. In one embodiment, the ring buffer may also include a batch command buffer storing multiple batches of commands. Commands for 3D pipeline 2012 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 2012 and / or image data and memory objects for media pipeline 2016. The 3D pipeline 2012 and the media pipeline 2016 process the commands by performing operations via logic within their respective pipelines or by dispatching one or more execution threads to the execution unit array 2114.

[0279] In various embodiments, the 3D pipeline 2012 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2114. The graphics core array 2114 provides a unified block of execution resources. The multipurpose execution logic (e.g., execution units) within the graphics core array 2114 includes support for various 3D API shader languages ​​and can execute multiple concurrent threads associated with multiple shaders.

[0280] In some embodiments, the graphics core array 2114 further includes execution logic for performing media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution unit also includes general-purpose logic programmable to perform parallel general-purpose computing operations. The general-purpose logic can be... Figure 18 (Multiple) processor cores 1807 or Figure 19 The general logic within the cores 1902A to 1902N performs processing operations in parallel or in combination.

[0281] Output data generated by threads executing on the graphics core array 2114 can be output to memory in a uniform return buffer (URB) 2118. URB 2118 can store data from multiple threads. In some embodiments, URB 2118 can be used to send data between different threads executing on the graphics core array 2114. In some embodiments, URB 2118 can also be used for synchronization between threads on the graphics core array and fixed-function logic within shared-function logic 2120.

[0282] In some embodiments, the graphics core array 2114 is scalable, such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of the GPE 2110. In one embodiment, the execution resources are dynamically scalable, allowing them to be enabled or disabled as needed.

[0283] The graphics core array 2114 is coupled to shared function logic 2120, which includes multiple resources shared among the graphics cores in the graphics core array. The shared functions within the shared function logic 2120 are hardware logic units that provide dedicated supplementary functions to the graphics core array 2114. In various embodiments, the shared function logic 2120 includes, but is not limited to, sampler 2121, math 2122, and inter-thread communication (ITC) 2123 logic. Additionally, some embodiments implement one or more caches 2125 within the shared function logic 2120. Shared functions are implemented when the demand for a given dedicated function is insufficient to be contained within the graphics core array 2114. Instead, a single instance of the dedicated function is implemented as a separate entity within the shared function logic 2120 and shared among execution resources within the graphics core array 2114. The exact set of functions shared and included within the graphics core array 2114 varies among embodiments.

[0284] Figure 22 This is a block diagram of another embodiment of the graphics processor 2200. Figure 22 Those elements having the same reference numerals (or names) as those in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0285] In some embodiments, the graphics processor 2200 includes a ring interconnect 2202, a pipeline front-end 2204, a media engine 2237, and graphics cores 2280A to 2280N. In some embodiments, the ring interconnect 2202 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of a plurality of processors integrated within a multi-core processing system.

[0286] In some embodiments, the graphics processor 2200 receives multiple batches of commands via a ring interconnect 2202. The incoming commands are interpreted by a command stream converter 2203 in the pipeline front-end 2204. In some embodiments, the graphics processor 2200 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores(a plurality of) 2280A to 2280N. For 3D geometry processing commands, the command stream converter 2203 supplies commands to the geometry pipeline 2236. For at least some media processing commands, the command stream converter 2203 supplies commands to a video front-end 2234, which is coupled to a media engine 2237. In some embodiments, the media engine 2237 includes a video quality engine (VQE) 2230 for video and image post-processing and a multi-format encoding / decoding (MFX) engine 2233 for providing hardware-accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2236 and the media engine 2237 each generate execution threads for thread execution resources provided by at least one graphics core 2280A.

[0287] In some embodiments, the graphics processor 2200 includes Scalable Thread Execution Resource Characteristic (SRM) cores 2280A to 2280N (sometimes referred to as core shards), each SRM core having multiple sub-cores 2250A to 2250N and 2260A to 2260N (sometimes referred to as core sub-shards). In some embodiments, the graphics processor 2200 may have any number of graphics cores 2280A to 2280N. In some embodiments, the graphics processor 2200 includes a graphics core 2280A, which has at least a first sub-core 2250A and a second sub-core 2260A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 2250A). In some embodiments, the graphics processor 2200 includes multiple graphics cores 2280A to 2280N, each graphics core including a set of first sub-cores 2250A to 2250N and a set of second sub-cores 2260A to 2260N. Each of the first set of sub-cores 2250A to 2250N includes at least a first set of execution units 2252A to 2252N and media / texture samplers 2254A to 2254N. Each of the second set of sub-cores 2260A to 2260N includes at least a second set of execution units 2262A to 2262N and samplers 2264A to 2264N. In some embodiments, each sub-core 2250A to 2250N and 2260A to 2260N shares a set of shared resources 2270A to 2270N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0288] Execution logic

[0289] Figure 23 The thread execution logic 2300 is shown, which includes an array of processing elements used in some embodiments of GPE. Figure 23 Elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0290] In some embodiments, thread execution logic 2300 includes a pixel shader 2302, a thread dispatcher 2304, an instruction cache 2306, a scalable array of execution units including multiple execution units 2308A to 2308N, a sampler 2310, a data cache 2312, and a data port 2314. In one embodiment, the included components are interconnected via an interconnect structure linking to each of these components. In some embodiments, thread execution logic 2300 includes one or more connections to memory (such as system memory or cache memory) via one or more of the instruction cache 2306, data port 2314, sampler 2310, and execution unit arrays 2308A to 2308N. In some embodiments, each execution unit (e.g., 2308A) is a separate vector processor capable of executing multiple synchronous threads and processing multiple data elements in parallel for each thread. In some embodiments, execution unit arrays 2308A to 2308N include any number of individual execution units.

[0291] In some embodiments, the execution unit arrays 2308A to 2308N are primarily used to execute "shader" programs. In some embodiments, the execution units 2308A to 2308N in the array execute an instruction set that includes native support for many standard 3D graphics shader instructions, enabling the execution of shader programs from graphics libraries (e.g., Direct3D and OpenGL) with minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., computation and media shaders).

[0292] Each execution unit 2308A to 2308N in the execution unit array operates on an array of data elements. The number of data elements is the "execution size," or the number of channels used for instructions. An execution channel is a logical unit that performs data element access, masking, and flow control within instructions. The number of channels may be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In some embodiments, execution units 2308A to 2308N support both integer and floating-point data types.

[0293] The execution unit instruction set includes Single Instruction Multiple Data (SIMD) instructions or Single Instruction Multiple Thread (SIMT) instructions. Individual data elements can be stored in registers as packed data types, and the execution unit processes each element based on its data size. For example, when operating on a 256-bit wide vector, all 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 64-bit packed data elements (four-word (QW) size data elements), eight separate 32-bit packed data elements (double-word (DW) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

[0294] One or more internal instruction caches (e.g., 2306) are included in the thread execution logic 2300 to cache thread instructions of the execution unit. In some embodiments, one or more data caches (e.g., 2312) are included to cache thread data during thread execution. In some embodiments, a sampler 2310 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2310 includes dedicated texture or media sampling functions to process texture or media data during the sampling process before providing sampled data to the execution unit.

[0295] During execution, the graphics and media pipeline sends thread initiation requests to thread execution logic 2300 via thread generation and dispatch logic. In some embodiments, thread execution logic 2300 includes a local thread dispatcher 2304 that arbitrates thread initiation requests from the graphics and media pipeline and instantiates the requested thread on one or more execution units 2308A to 2308N. For example, the geometry pipeline (e.g., Figure 22 2236) executes logic 2300 on thread 2300. Figure 23 The thread dispatcher 2304 can also handle runtime thread generation requests from the shader program.

[0296] Once a set of geometric objects has been processed and rasterized into pixel data, pixel shader 2302 is invoked to further compute output information and write the results to an output surface (e.g., a color buffer, depth buffer, stencil buffer, etc.). In some embodiments, pixel shader 2302 computes values ​​for each vertex attribute that will be interpolated across the rasterized objects. In some embodiments, pixel shader 2302 then executes a pixel shader program provided by an application programming interface (API). To execute the pixel shader program, pixel shader 2302 dispatches a thread to an execution unit (e.g., 2308A) via thread dispatcher 2304. In some embodiments, pixel shader 2302 uses texture sampling logic in sampler 2310 to access texture data in a texture map stored in memory. Arithmetic operations performed on the texture data and input geometry compute pixel color data for each geometric fragment, or discard one or more pixels without further processing.

[0297] In some embodiments, data port 2314 provides a memory access mechanism for thread execution logic 2300 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 2314 includes or is coupled to one or more cache memories (e.g., data cache 2312) to cache data via the data port for memory access.

[0298] Figure 24 This is a block diagram illustrating a graphics processor instruction format 2400 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having multiple instruction formats. Solid lines represent components typically included in the execution unit instructions, while dashed lines represent optional components or components included only in subsets of the instructions. In some embodiments, the instruction format 2400 described and illustrated are macro instructions, as they are instructions supplied to the execution unit, as opposed to micro-operations generated from instruction decoding (once the instruction is processed).

[0299] In some embodiments, the graphics processor execution unit natively supports instructions using the 128-bit instruction format 2410. A 64-bit compact instruction format 2430 can be used for some instructions based on the selected instruction, multiple instruction options, and the number of operands. The native 128-bit instruction format 2410 provides access to all instruction options, while some options and operations are limited to the 64-bit instruction format 2430. The native instructions available in the 64-bit instruction format 2430 vary depending on the embodiment. In some embodiments, instructions are partially compressed using a set of index values ​​in the index field 2413. The execution unit hardware references a set of compression tables based on the index values ​​and uses the output of the compression tables to reconstruct the native instructions using the 128-bit instruction format 2410.

[0300] For each format, instruction opcode 2412 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a synchronous add operation across each color channel, which represents a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, instruction control field 2414 enables control over certain execution options, such as channel selection (e.g., prediction) and data channel ordering (e.g., blending). For 128-bit instruction 2410, execution size field 2416 limits the number of data channels that will be executed in parallel. In some embodiments, execution size field 2416 is not available for 64-bit compact instruction format 2430.

[0301] Some execution unit instructions have up to three operands, including two source operands (src0 2420, src12 422) and a destination 2418. In some embodiments, the execution unit supports dual-destination instructions, where one of these destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2424), where the instruction opcode 2412 determines the number of source operands. The last source operand of the instruction may be an on-the-fly (e.g., hard-coded) value passed using the instruction.

[0302] In some embodiments, the 128-bit instruction format 2410 includes access / address mode information 2426, which, for example, specifies whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register addresses of one or more operands are provided directly by bits in the instruction 2410.

[0303] In some embodiments, the 128-bit instruction format 2410 includes an access / address mode field 2426 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction 2410 can use byte-aligned addressing for both source and destination operands, and when in a second mode, the instruction 2410 can use 16-byte aligned addressing for both source and destination operands.

[0304] In one embodiment, the address mode portion of the access / address mode field 2426 determines whether the instruction uses direct or indirect addressing. When using direct register addressing mode, the bits in instruction 2410 directly provide the register addresses of one or more operands. When using indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0305] In some embodiments, instructions are grouped based on the 2412-bit field of the opcode to simplify opcode decoding 2440. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely exemplary. In some embodiments, the move and logic opcode group 2442 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2442 shares five most significant bits (MSB), where move (mov) instructions are in the form of 0000xxxxb, and logic instructions are in the form of 0001xxxxb. The flow control instruction group 2444 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The mixed instruction group 2446 includes a mixture of instructions, including synchronous instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). Parallel math instruction group 2448 includes component-based arithmetic instructions (e.g., add, multiply) in the form 0100xxxxb (e.g., 0x40). Parallel math group 2448 performs arithmetic operations in parallel across data channels. Vector math group 2450 includes arithmetic instructions (e.g., dp4) in the form 0101xxxxb (e.g., 0x50). Vector math group performs arithmetic operations on vector operands, such as dot product.

[0306] Graphics Pipeline

[0307] Figure 25 This is a block diagram of another embodiment of the graphics processor 2500. Figure 25 Those elements having the same reference numerals (or names) as those in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0308] In some embodiments, the graphics processor 2500 includes a graphics pipeline 2520, a media pipeline 2530, a display engine 2540, thread execution logic 2550, and a rendering output pipeline 2570. In some embodiments, the graphics processor 2500 is a graphics processor within a multi-core processing system including one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to the graphics processor 2500 via a ring interconnect 2502. In some embodiments, the ring interconnect 2502 couples the graphics processor 2500 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 2502 are interpreted by a command stream converter 2503, which supplies instructions to individual components of the graphics pipeline 2520 or the media pipeline 2530.

[0309] In some embodiments, command stream converter 2503 directs the operation of vertex acquirer 2505, which reads vertex data from memory and executes vertex processing commands provided by command stream converter 2503. In some embodiments, vertex acquirer 2505 provides vertex data to vertex shader 2507, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex acquirer 2505 and vertex shader 2507 execute vertex processing instructions by dispatching execution threads to execution units 2552A to 2552B via thread dispatcher 2531.

[0310] In some embodiments, execution units 2552A to 2552B are vector processor arrays having an instruction set for performing graphics and media operations. In some embodiments, execution units 2552A to 2552B have an attached L1 cache 2551, which is dedicated to each array or shared between arrays. The cache may be configured as a data cache, an instruction cache, or a single cache partitioned to contain data and instructions in different partitions.

[0311] In some embodiments, the graphics pipeline 2520 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable shell shader 2511 configures the tessellation operation. A programmable domain shader 2517 provides back-end evaluation of the tessellation output. A tessellation unit 2513 operates in the direction of the shell shader 2511 and includes dedicated logic for generating a detailed set of geometric objects based on a rough geometry model that is provided as input to the graphics pipeline 2520. In some embodiments, the tessellation components 2511, 2513, and 2517 can be bypassed if tessellation is not used.

[0312] In some embodiments, the complete geometry object may be processed by the geometry shader 2519 via one or more threads dispatched to the execution units 2552A to 2552B, or it may proceed directly to the clipper 2529. In some embodiments, the geometry shader operates on the entire geometry object (rather than vertices or vertex patches in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 2519 receives input from the vertex shader 2507. In some embodiments, the geometry shader 2519 may be programmed by a geometry shader program to perform geometric tessellation when the tessellation unit is disabled.

[0313] Prior to rasterization, clipper 2529 processes vertex data. Clipper 2529 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader capabilities. In some embodiments, raster and depth testing unit 2573 in rendering output pipeline 2570 dispatches pixel shaders to convert geometry objects into their per-pixel representations. In some embodiments, pixel shader logic is included in thread execution logic 2550. In some embodiments, the application can bypass rasterization and access unrasterized vertex data via outflow unit 2523.

[0314] The graphics processor 2500 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be transferred among the main components of the graphics processor. In some embodiments, execution units 2552A to 2552B and(multiple) associated caches 2551, texture and media samplers 2554, and texture / sampler cache 2558 are interconnected via data port 2556 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, samplers 2554, caches 2551, 2558, and execution units 2552A to 2552B each have a separate memory access path.

[0315] In some embodiments, the rendering output pipeline 2570 includes a raster and depth testing unit 2573 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rendering output pipeline 2570 includes windower / mask units for performing fixed-function triangle and line rasterization. Associated rendering caches 2578 and depth caches 2579 are also available in some embodiments. Pixel manipulation unit 2577 performs pixel-based operations on the data; however, in some instances, pixel operations associated with 2D operations (e.g., using mixed bit-block image passing) are performed by the 2D engine 2541, or alternatively by the display controller 2543 using an overlay display plane at display time. In some embodiments, a shared L3 cache 2575 is available for all graphics components, allowing data to be shared without using main system memory.

[0316] In some embodiments, the graphics processor media pipeline 2530 includes a media engine 2537 and a video front-end 2534. In some embodiments, the video front-end 2534 receives pipeline commands from a command stream converter 2503. In some embodiments, the media pipeline 2530 includes a separate command stream converter. In some embodiments, the video front-end 2534 processes media commands before sending them to the media engine 2537. In some embodiments, the media engine 2537 includes a thread generation function for generating threads for dispatching to thread execution logic 2550 via a thread dispatcher 2531.

[0317] In some embodiments, the graphics processor 2500 includes a display engine 2540. In some embodiments, the display engine 2540 is external to the processor 2500 and coupled to the graphics processor via a ring interconnect 2502, or some other interconnect bus or mechanism. In some embodiments, the display engine 2540 includes a 2D engine 2541 and a display controller 2543. In some embodiments, the display engine 2540 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 2543 is coupled to a display device (not shown), which may be a system-integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0318] In some embodiments, the graphics pipeline 2520 and media pipeline 2530 may be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, the graphics processor's driver software translates API schedules specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL) and Open Computing Language (OpenCL) from the Khronos Group, and Microsoft's Direct3D library, or support may be provided for OpenGL and D3D. Support may also be provided for the open-source computer vision library (OpenCV). Future APIs with compatible 3D pipelines will also be supported if a pipeline mapping from future APIs to the graphics processor's pipeline can be made.

[0319] Graphical Pipeline Programming

[0320] Figure 26A This is a block diagram illustrating a graphics processor command format 2600 according to some embodiments. Figure 26B This is a block diagram illustrating a graphics processor command sequence 2610 according to an embodiment. Figure 26A Solid lines in the diagram represent components that are typically included in the drawing command, while dashed lines represent components that are optional or included only in a subset of the drawing command. Figure 26A An exemplary graphics processor command format 2600 includes a target client 2602 for identifying the command, a command operation code (opcode) 2604, and related data 2606 for the command. Some commands also include a sub-opcode 2605 and a command size 2608.

[0321] In some embodiments, client 2602 defines a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to adjust further processing of the command and route command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads opcode 2604 and sub-opcode 2605 (if present) to determine the operation to be performed. The client unit uses information within data field 2606 to execute the command. For some commands, an explicit command size 2608 is desired to define the size of the command. In some embodiments, the command parser automatically determines the size of at least some commands in the command based on the command opcode. In some embodiments, commands are aligned via multiples of double word length.

[0322] Figure 26B The flowchart illustrates an exemplary graphics processor command sequence 2610. In some embodiments, software or firmware of a data processing system characterized by an embodiment of a graphics processor uses a version of the illustrated command sequence to initiate, execute, and terminate a set of graphics operations. Sample command sequences are shown and described for illustrative purposes only, and embodiments are not limited to these specific commands or this command sequence. Moreover, the commands may be issued as a batch of commands in a command sequence, such that the graphics processor will process the command sequence in a manner that is at least partially simultaneous.

[0323] In some embodiments, the graphics processor command sequence 2610 may begin with a pipeline dump clearing command 2612 to cause any active graphics pipeline to complete its current pending commands. In some embodiments, the 3D pipeline 2622 and the media pipeline 2624 do not operate simultaneously. Pipeline dump clearing is performed to cause any pending commands to be completed by the active graphics pipeline. In response to pipeline dump clearing, the command parser for the graphics processor will stop command processing until the active rendering engine completes its pending operations and invalidates the associated read cache. Optionally, any data marked as 'dirty' in the render cache may be dumped and cleared into memory. In some embodiments, pipeline dump clearing command 2612 may be used for pipeline synchronization or before placing the graphics processor into a low-power state.

[0324] In some embodiments, pipeline selection command 2613 is used when a sequence of commands requires explicit switching of the graphics processor between pipelines. In some embodiments, pipeline selection command 2613 is only required once in an execution context before a pipeline command is issued, unless the context requires issuing commands for two pipelines. In some embodiments, pipeline dump clearing command 2612 is required exactly before the pipeline switch via pipeline selection command 2613.

[0325] In some embodiments, pipeline control command 2614 configures a graphics pipeline for operation and is used to program the 3D pipeline 2622 and the media pipeline 2624. In some embodiments, pipeline control command 2614 configures the pipeline state of an active pipeline. In one embodiment, pipeline control command 2614 is used for pipeline synchronization and for clearing data from one or more cache memories within an active pipeline before processing a batch of commands.

[0326] In some embodiments, the command for returning buffer state 2616 is used to configure a set of return buffers for corresponding pipelined write data. Some pipelined operations require allocating, selecting, or configuring one or more return buffers, in which intermediate data is written during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, configuring return buffer state 2616 includes selecting the size and number of return buffers for a set of pipelined operations.

[0327] The remaining commands in the command sequence differ based on the active pipeline used for the operation. Based on pipeline determination 2620, the command sequence is tailored for either the 3D pipeline 2622 starting at 3D pipeline state 2630, or the media pipeline 2624 starting at media pipeline state 2640.

[0328] Commands for 3D pipeline state 2630 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, 3D pipeline state 2630 commands can also selectively disable or bypass specific pipeline components (if those components will not be used).

[0329] In some embodiments, the 3D primitive 2632 command is used to submit 3D primitives to be processed by the 3D pipeline. The command and associated parameters passed to the graphics processor via the 3D primitive 2632 command are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 2632 command data to generate multiple vertex data structures. These vertex data structures are stored in one or more return buffers. In some embodiments, the 3D primitive 2632 command is used to perform vertex operations on the 3D primitives via a vertex shader. To process the vertex shader, the 3D pipeline 2622 dispatches shader execution threads to the graphics processor execution unit.

[0330] In some embodiments, the 3D pipeline 2622 is triggered by executing command 2634 or an event. In some embodiments, register writing triggers command execution. In some embodiments, execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, pipeline synchronization commands are used to trigger command execution so that the command sequence is cleared via a graphics pipeline dump. The 3D pipeline performs geometry processing on 3D primitives. Once the operation is complete, the resulting geometry is rasterized, and the pixel engine shades the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for these operations.

[0331] In some embodiments, when performing media operations, a sequence of graphics processor commands 2610 follows the media pipeline 2624 path. Generally, the specific purpose and manner of programming the media pipeline 2624 depends on the media or computational operation to be performed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed, and media decoding can be performed wholly or partially using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using computation shader programs that are not explicitly associated with rendering graphics primitives.

[0332] In some embodiments, the media pipeline 2624 is configured in a manner similar to that of the 3D pipeline 2622. A set of commands for configuring media pipeline state 2640 is dispatched or placed in a command queue before the media object command 2642. In some embodiments, the commands for media pipeline state 2640 include data for configuring media pipeline elements that will be used to process media objects. This includes data for configuring video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the commands for media pipeline state 2640 also support directing one or more pointers to "indirect" state elements that contain a batch of state settings.

[0333] In some embodiments, media object command 2642 supplies pointers to media objects for processing by the media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object command 2642. Once the pipeline states are configured and media object command 2642 is queued, media pipeline 2624 is triggered via execution of command 2644 or an equivalent execution event (e.g., register write). The output from media pipeline 2624 can then be post-processed by operations provided by 3D pipeline 2622 or media pipeline 2624. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0334] Graphical software architecture

[0335] Figure 27 An exemplary graphics software architecture of a data processing system 2700 according to some embodiments is illustrated. In some embodiments, the software architecture includes a 3D graphics application 2710, an operating system 2720, and at least one processor 2730. In some embodiments, the processor 2730 includes a graphics processor 2732 and one or more general-purpose processor cores 2734. The graphics application 2710 and the operating system 2720 each execute in the system memory 2750 of the data processing system.

[0336] In some embodiments, the 3D graphics application 2710 includes one or more shader programs, which include shader instructions 2712. The shader language instructions may employ a high-level shader language, such as High-Level Shading Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 2714, which employ a machine language suitable for execution by a general-purpose processor core 2734. The application also includes graphics objects 2716 defined by vertex data.

[0337] In some embodiments, the operating system 2720 is from Microsoft Corporation. The operating system 2720 may be a dedicated UNIX-like operating system or an open-source UNIX-like operating system using a variant of the Linux kernel. The operating system 2720 may support graphics APIs 2722, such as the Direct3D API or the OpenGL API. When the Direct3D API is in use, the operating system 2720 uses a front-end shader compiler 2724 to compile any shader instructions 2712 in HLSL into a lower-level shader language. This compilation may be just-in-time (JIT) compilation or pre-compilation of the application-executable shaders. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application 2710.

[0338] In some embodiments, the user-mode graphics driver 2726 includes a back-end shader compiler 2727 for translating shader instructions 2712 into a hardware-specific representation. When using the OpenGL API, shader instructions 2712 in the GLSL high-level language are passed to the user-mode graphics driver 2726 for compilation. In some embodiments, the user-mode graphics driver 2726 uses operating system kernel-mode functionality 2728 to communicate with the kernel-mode graphics driver 2729. In some embodiments, the kernel-mode graphics driver 2729 communicates with the graphics processor 2732 to dispatch commands and instructions.

[0339] IP core implementation

[0340] One or more aspects of at least one embodiment can be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions representing various logic within a processor. When read by a machine, these instructions can cause the machine to manufacture logic for performing the techniques described herein. Such representations (referred to as “IP cores”) are reusable units of logic for an integrated circuit, which can be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model can be supplied to various consumers or manufacturing facilities that load the hardware model onto manufacturing machines that manufacture integrated circuits. Integrated circuits can be manufactured such that the circuits perform the operations described in association with any of the embodiments described herein.

[0341] Figure 28This is a block diagram illustrating an IP core development system 2800 that can be used to manufacture integrated circuits to perform operations, according to an embodiment. The IP core development system 2800 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build entire integrated circuits (e.g., SOC integrated circuits). Design facility 2830 can generate software simulations 2810 of the IP core designs using a high-level programming language (e.g., C / C++). Software simulation 2810 can be used to design, test, and verify the behavior of the IP cores using simulation model 2812. Simulation model 2812 can include functional, behavioral, and / or timing simulations. Register transfer level (RTL) designs 2815 can then be created or synthesized from simulation model 2812. RTL design 2815 is an abstraction of the behavior of an integrated circuit (including associated logic performed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to RTL design 2815, lower-level designs at logic levels or transistor levels can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation can vary.

[0342] The RTL design 2815 or an equivalent can be further synthesized into a hardware model 2820 by the design facility. This hardware model may employ a hardware description language (HDL) or some other representation of the physical design data. The HDL can be further simulated or tested to validate the IP core design. The IP core design can be stored in non-volatile memory 2840 (e.g., hard disk, flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 2865. Alternatively, the IP core design can be transmitted (e.g., via the Internet) through a wired connection 2850 or a wireless connection 2860. The manufacturing facility 2865 can then manufacture an integrated circuit at least partially based on the IP core design. The manufactured integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0343] Exemplary System-on-Chip Integrated Circuit

[0344] Figures 29 to 31 Exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to various embodiments described herein are shown. In addition to those shown, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0345] Figure 29This is a block diagram illustrating an exemplary system-on-a-chip integrated circuit 2900 that can be fabricated using one or more IP cores according to an embodiment. The exemplary integrated circuit 2900 includes one or more application processors 2905 (e.g., CPU), at least one graphics processor 2910, and may additionally include an image processor 2915 and / or a video processor 2920, any of which can be modular IP cores from the same or multiple different design facilities. The integrated circuit 2900 includes peripheral or bus logic, including a USB controller 2925, a UART controller 2930, an SPI / SDIO controller 2935, and an I... 2 S / I 2 C controller 2940. Additionally, the integrated circuit may include a display device 2945, which is coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 2950 and a Mobile Industry Processor Interface (MIPI) display interface 2955. Storage may be provided by a flash memory subsystem 2960 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 2965 to access SDRAM or SRAM memory devices. Furthermore, some integrated circuits also include an embedded security engine 2970.

[0346] Figure 30 This is a block diagram illustrating an exemplary system-on-a-chip integrated circuit 3010 that can be fabricated using one or more IP cores according to an embodiment. The graphics processor 3010 may be... Figure 29 A variant of the graphics processor 2910. The graphics processor 3010 includes a vertex processor 3005 and one or more fragment processors 3015A to 3015N (e.g., 3015A, 3015B, 3015C, 3015D, up to 3015N-1 and 3015N). The graphics processor 3010 can execute different shader programs via separate logic, such that the vertex processor 3005 is optimized to perform vertex shader program operations, while one or more fragment processors 3015A to 3015N perform fragment (e.g., pixel) shading operations for use in fragment or pixel shader programs. The vertex processor 3005 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. The fragment processors (multiple) 3015A to 3015N use the primitive and vertex data generated by the vertex processor 3005 to produce frame buffers displayed on a display device. In one embodiment, fragment processors (multiple) 3015A to 3015N are optimized to execute fragment shader programs provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0347] Additionally, the graphics processor 3010 includes one or more memory management units (MMUs) 3020A to 3020B, one or more caches 3025A to 3025B, and (multiple) circuit interconnects 3030A to 3030B. The one or more MMUs 3020A to 3020B provide virtual-to-physical address mappings for the graphics processor 3010, including for vertex processors 3005 and / or one or more fragment processors 3015A to 3015N. These virtual-to-physical address mappings may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in the one or more caches 3025A to 3025B. In one embodiment, the one or more MMUs 3020A to 3020B may interact with other MMUs within the system, including those related to... Figure 29 One or more application processors 2905, image processor 2915, and / or video processor 2920 are associated with one or more MMUs for synchronization, enabling each processor 2905 to 2920 to participate in a shared or unified virtual memory system. According to an embodiment, one or more circuit interconnects 3030A to 3030B enable the graphics processor 3010 to interact with other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0348] Figure 31 This is a block diagram illustrating an additional exemplary graphics processor 3110 of a system-on-a-chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment. The graphics processor 3110 may be... Figure 29 A variant of the graphics processor 2910. The graphics processor 3110 includes... Figure 30 The integrated circuit 3000 includes one or more MMUs 3020A to 3020B, caches 3025A to 3025B, and circuit interconnects 3030A to 3030B.

[0349] The graphics processor 3110 includes one or more shader cores 3115A to 3115N (e.g., 3115A, 3115B, 3115C, 3115D, 3115E, 3115F, up to 3115N-1 and 3115N), which provide a unified shader core architecture, wherein a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary in embodiments and implementations. Additionally, the graphics processor 3110 includes an inter-core task manager 3105, which acts as a thread dispatcher for distributing execution threads to one or more shader cores 3115A to 3115N. The graphics processor 3110 further includes a tile unit 3118 for accelerating tile operations for tile-based rendering, wherein the rendering operations of the scene are subdivided in the image space. Tile-based rendering can be used to leverage local spatial consistency within a scene or optimize the use of internal caches.

[0350] References to "an embodiment," "an embodiment," "an example embodiment," "various embodiments," etc., indicate that the embodiments(s) thus described may include specific features, structures, or characteristics, but not every embodiment necessarily includes these specific features, structures, or characteristics. Furthermore, some embodiments may have some, all, or none of the features described with respect to other embodiments.

[0351] In the foregoing specification, embodiments have been described with reference to specific exemplary embodiments. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the specification and drawings are to be regarded in an illustrative rather than restrictive sense.

[0352] The term “coupling” and its derivatives may be used in the following specification and claims. “Coupling” is used to indicate that two or more elements cooperate or interact with each other, but they may or may not have an intermediate physical or electrical component between them.

[0353] As used in the claims, unless otherwise stated, the use of ordinal adjectives such as “first,” “second,” “third,” etc., to describe common elements merely indicates that different instances of similar elements are mentioned and is not intended to imply that elements so described must be in a given order, whether chronological, spatial, hierarchical, or in any other way.

[0354] The following terms and / or examples relate to further embodiments or examples. Details from the examples may be used anywhere in one or more embodiments. Various features of different embodiments or examples may be combined in various ways with some of the included features and others that have been excluded to suit a variety of different applications. Examples may include subjects, such as methods; means for performing actions of said methods; at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to perform the actions of said methods; or devices or systems for facilitating hybrid communication according to the embodiments and examples described herein.

[0355] Some embodiments relate to Example 1, which includes an apparatus for facilitating barriering and synchronization of machine learning at an autonomous machine, the apparatus comprising: detection / observation logic for detecting thread groups associated with machine learning on one or more processing devices; and barrier logic for facilitating barrier synchronization of the thread groups across a plurality of dies, such that each thread in the thread group is scheduled across a set of computing elements associated with the plurality of dies, wherein each die represents a processing device in the one or more processing devices, the processing device including a graphics processor.

[0356] Example 2 includes the subject matter as described in Example 1, and further includes: synchronization logic for facilitating the synchronization of the thread group using a barrier command based on a thread group identifier (ID) corresponding to the thread group, wherein the barrier command is executed to synchronize the thread group as identified by the thread group ID inserted into the barrier command as part of the argument.

[0357] Example 3 includes the subject matter as described in Examples 1 and 2, wherein one or more structural cross switches are used to synchronize the thread group across multiple graphics processors and multiple streaming multiprocessors (SMs).

[0358] Example 4 includes the subject matter as described in Examples 1 to 3, wherein the synchronization logic is further configured to facilitate the sharing of intermediate neural networks among multiple autonomous machines via a database over a communication network, wherein the intermediate neural network data is stored at the database by one or more of the multiple autonomous machines and compressed for faster transmission, wherein the database includes a cloud database and the communication network includes a cloud network.

[0359] Example 5 includes the subject matter as described in Examples 1 through 4, and further includes: preemption and scheduling logic for scheduling the one or more thread groups in the thread group across multiple graphics processors and multiple SMs by mapping one or more thread groups in the thread group to global memory, wherein the one or more thread groups in the thread group are not allocated with barriers or shared local memory (SLM).

[0360] Example 6 includes the subject matter as described in Examples 1 through 5, wherein the preemption and scheduling logic is further configured to preempt the one or more thread groups by switching to execution in order to prevent the one or more thread groups from entering a stopped state, wherein this preemption is based on a list and state of thread groups maintained by a thread scheduler, wherein the list of thread groups is used to indicate the number of thread groups that are allowed to be preempted over a period of time.

[0361] Example 7 includes the subject matter as described in Examples 1 through 6, wherein the graphics processor and the application processor are co-located on a common semiconductor package.

[0362] Some embodiments relate to Example 8, which includes a method for facilitating barriering and synchronization of machine learning at an autonomous machine, the method comprising: detecting a group of threads associated with machine learning and associated with one or more processing devices; and facilitating barrier synchronization of the thread group across a plurality of dies, such that each thread in the thread group is scheduled across a set of computing elements associated with the plurality of dies, wherein each die represents a processing device in the one or more processing devices, the processing device including a graphics processor.

[0363] Example 9 includes the subject matter as described in Example 8, and further includes: using a barrier command to facilitate the synchronization of the thread group based on a thread group identifier (ID) corresponding to the thread group, wherein the barrier command is executed to synchronize the thread group as identified by the thread group ID inserted into the barrier command as part of the argument.

[0364] Example 10 includes the subject matter as described in Examples 8 and 9, wherein one or more structural cross switches are used to synchronize the thread group across multiple graphics processors and multiple streaming multiprocessors (SMs).

[0365] Example 11 includes the subject matter as described in Examples 8 to 10, and further includes: facilitating the sharing of intermediate neural networks among multiple autonomous machines via a database over a communication network, wherein the intermediate neural network data is stored at the database by one or more of the multiple autonomous machines and compressed for faster transmission, wherein the database includes a cloud database and the communication network includes a cloud network.

[0366] Example 12 includes the subject matter as described in Examples 8 through 11, and further includes: scheduling the one or more thread groups in the thread group across multiple graphics processors and multiple SMs by mapping one or more thread groups in the thread group to global memory, wherein the one or more thread groups in the thread group are not allocated with barriers or shared local memory (SLM).

[0367] Example 13 includes the subject matter as described in Examples 8 through 12, further including: preempting the one or more thread groups by switching to execution to prevent the one or more thread groups from entering a stopped state, wherein this preemption is based on a list and state of thread groups maintained by a thread scheduler, wherein the list of thread groups is used to indicate the number of thread groups that are allowed to be preempted over a period of time.

[0368] Example 14 includes the subject matter as described in Examples 8 through 13, wherein the graphics processor and the application processor are co-located on a common semiconductor package.

[0369] Some embodiments relate to Example 15, which includes a graphics processing system comprising a computing device having memory coupled to a processor, the processor being configured to: detect thread groups related to machine learning associated with one or more processing devices; and facilitate barrier synchronization of the thread groups across a plurality of dies, such that each thread in the thread group is scheduled across a set of computing elements associated with the plurality of dies, wherein each die represents a processing device among the one or more processing devices, the processing device including a graphics processor.

[0370] Example 16 includes the subject matter as described in Example 15, wherein the processor is further configured to facilitate the synchronization of the thread group using a barrier command based on a thread group identifier (ID) corresponding to the thread group, wherein the barrier command is executed to synchronize the thread group as identified by the thread group ID inserted into the barrier command as part of the argument.

[0371] Example 17 includes the subject matter as described in Examples 15 and 16, wherein one or more structural cross switches are used to synchronize the thread group across multiple graphics processors and multiple streaming multiprocessors (SMs).

[0372] Example 18 includes the subject matter as described in Examples 15 to 17, wherein the operation further includes: facilitating the sharing of intermediate neural networks among multiple autonomous machines via a database over a communication network, wherein the intermediate neural network data is stored at the database by one or more of the multiple autonomous machines and compressed for faster transmission, wherein the database includes a cloud database and the communication network includes a cloud network.

[0373] Example 19 includes the subject matter as described in Examples 15 through 18, wherein the operation further includes scheduling the one or more thread groups in the thread group across multiple graphics processors and multiple SMs by mapping one or more thread groups in the thread group to global memory, wherein the one or more thread groups in the thread group are not allocated with barriers or shared local memory (SLM).

[0374] Example 20 includes the subject matter as described in Examples 15 through 19, wherein the operation further includes: preempting the one or more thread groups by switching to execution to prevent the one or more thread groups from entering a stopped state, wherein this preemption is based on a list and state of thread groups maintained by a thread scheduler.

[0375] Example 21 includes the subject matter as described in Examples 15 through 20, wherein the thread group list is used to indicate the number of thread groups that are allowed to be preempted over a period of time, wherein the graphics processor and the application processor are co-located on a common semiconductor package.

[0376] Example 22 includes at least one non-transitory or tangible machine-readable medium comprising a plurality of instructions which, when executed on a computing device, are used to implement or perform the method as claimed in any one of Examples 8-14.

[0377] Example 23 includes at least one machine-readable medium comprising a plurality of instructions which, when executed on a computing device, are used to implement or perform the method as claimed in any one of Examples 8-14.

[0378] Example 24 includes a system comprising a mechanism for implementing or performing the method as claimed in any one of Examples 8-14.

[0379] Example 25 includes an apparatus comprising means for performing the method as claimed in any one of Examples 8-14.

[0380] Example 26 includes a computing device arranged to implement or perform the method as claimed in any one of Examples 8-14.

[0381] Example 27 includes a communication device arranged to implement or perform the method as claimed in any one of claims 8-14.

[0382] Example 28 includes at least one machine-readable medium comprising a plurality of instructions which, when executed on a computing device, are used to implement or perform the method as described in any of the preceding claims or to implement the device as described in any of the preceding claims.

[0383] Example 29 includes at least one non-transitory or tangible machine-readable medium comprising a plurality of instructions which, when executed on a computing device, are used to implement or perform the method as described in any of the preceding claims or to implement the device as described in any of the preceding claims.

[0384] Example 30 includes a system comprising a mechanism for implementing or performing the method as described in any of the preceding claims or for implementing the device as described in any of the preceding claims.

[0385] Example 31 includes an apparatus comprising means for performing the method as described in any of the preceding claims.

[0386] Example 32 includes a computing device arranged for implementing or performing the method as described in any of the preceding claims or implementing the device as described in any of the preceding claims.

[0387] Example 33 includes a communication device arranged for implementing or performing the method as described in any of the preceding claims or implementing the device as described in any of the preceding claims.

[0388] The accompanying drawings and the foregoing description provide examples of embodiments. Those skilled in the art will understand that one or more of the described elements can be well combined into a single functional element. Alternatively, some elements may be divided into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, the order of processes described herein may be changed and is not limited to the manner described herein. Moreover, the actions described in any flowchart need not be performed in the order shown; nor is it necessary to perform all of the actions. Furthermore, those actions that do not depend on other actions may be performed in parallel with other actions. The scope of the embodiments is by no means limited to these specific examples. Many variations, such as differences in the structure, size, and use of materials, are possible, whether explicitly stated in the specification or not. The scope of the embodiments is at least as broad as that given by the following claims.

Claims

1. An apparatus for facilitating barriering and synchronization of machine learning at an autonomous machine, the apparatus comprising: Detection / observation logic is used to detect thread groups related to machine learning associated with one or more processing devices; as well as Barrier logic is provided to facilitate barrier synchronization of the thread group across multiple dies via multi-die barriers, such that each thread in the thread group is scheduled across a set of computing elements associated with the multiple dies, wherein each die represents a processing unit in one or more processing devices, the processing device including a graphics processor, and wherein the multi-die barriers include barrier instructions for synchronized execution.

2. The device as described in claim 1, characterized in that, Further includes: Synchronization logic is used to facilitate the synchronization of the thread group using a barrier command based on a thread group identifier (ID) corresponding to the thread group, wherein the barrier command is executed to synchronize the thread group identified by the thread group ID inserted into the barrier command as part of the argument.

3. The device as described in claim 2, characterized in that, Use one or more structured cross switches to synchronize the thread group across multiple stream multiprocessors (SMs) on multiple graphics processors.

4. The device as described in claim 2, characterized in that, The synchronization logic is further used to facilitate the sharing of intermediate neural networks among multiple autonomous machines via a database on a communication network, wherein the intermediate neural network data is stored in the database by one or more of the multiple autonomous machines and compressed for faster transmission, wherein the database includes a cloud database and the communication network includes a cloud network.

5. The device as described in claim 1, characterized in that, Further includes: Preemption and scheduling logic is used to schedule one or more thread groups in the thread group across multiple SMs on multiple graphics processors by mapping one or more thread groups in the thread group to global memory.

6. The device as described in claim 5, characterized in that, The preemption and scheduling logic is further used to preempt by switching to execution in order to prevent the one or more thread groups from entering a stopped state, wherein this preemption is based on a list and state of thread groups maintained by the thread scheduler, wherein the list of thread groups is used to indicate the number of thread groups that are allowed to be preempted during a period of time.

7. The device as described in claim 1, characterized in that, The graphics processor and application processor are located on a common semiconductor package.

8. A method for facilitating barriering and synchronization of machine learning at an autonomous machine, the method comprising: Detect and associate machine learning-related thread groups with one or more processing devices; as well as Facilitating barrier synchronization of the thread group across multiple dies via multi-die barriers, such that each thread in the thread group is scheduled across a set of computing elements associated with the multiple dies, wherein each die represents a processing unit in one or more processing devices, the processing device including a graphics processor, wherein the multi-die barrier includes barrier instructions for synchronized execution.

9. The method as described in claim 8, characterized in that, Further includes: A barrier command is used to facilitate the synchronization of the thread group based on a thread group identifier (ID) corresponding to the thread group, wherein the barrier command is executed to synchronize the thread group identified by the thread group ID inserted into the barrier command as part of the argument.

10. The method as described in claim 9, characterized in that, Use one or more structured cross switches to synchronize the thread group across multiple stream multiprocessors (SMs) on multiple graphics processors.

11. The method as described in claim 9, characterized in that, Further includes: Facilitating the sharing of intermediate neural networks among multiple autonomous machines via a database over a communication network, wherein the intermediate neural network data is stored in the database by one or more of the multiple autonomous machines and compressed for faster transmission, wherein the database includes a cloud database and the communication network includes a cloud network.

12. The method as described in claim 8, characterized in that, Further includes: The one or more thread groups in the thread group are scheduled across multiple SMs on multiple graphics processors by mapping one or more thread groups in the thread group to global memory.

13. The method as described in claim 8, characterized in that, Further includes: Preemption is performed by switching to execution to prevent one or more thread groups from entering a stopped state. This preemption is based on a list and state of thread groups maintained by the thread scheduler, wherein the list of thread groups indicates the number of thread groups that can be preempted over a period of time.

14. The method as described in claim 8, characterized in that, The graphics processor and application processor are located on a common semiconductor package.

15. At least one machine-readable medium comprising a plurality of instructions, which, when executed on a computing device, are used to implement or perform the method as claimed in any one of claims 8 to 14.

16. A system for facilitating barriering and synchronization of machine learning at an autonomous machine, comprising a mechanism for implementing or performing the method as described in any one of claims 8 to 14.

17. An apparatus for facilitating barriering and synchronization of machine learning at an autonomous machine, comprising means for performing the method as described in any one of claims 8 to 14.

18. A computing device arranged for implementing or performing the method as claimed in any one of claims 8 to 14.

19. A communication device arranged for implementing or performing the method as described in any one of claims 8 to 14.

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