All-Flash Server

Abstract

The present invention discloses an all-flash server, which includes a multi-core CPU, a memory controller, a memory module, a PCIe bus, a flash controller module plugged into the PCIe bus, and a flash module that can be plugged into the flash control module. The multi-core CPU is connected to the memory module through the memory controller. The multi-core CPU includes multiple CPU cores. The PCIe bus connects the memory controller to the multi-core CPU and the memory module. The flash controller module includes a flash controller, a first interface connected to the PCIe bus, and a second interface connected to the flash module. The flash module includes a number of flash memory chips and a third interface connected to the flash controller. The present invention increases the number of flash memory chips under the same circuit board area, and reduces power consumption. When a flash memory chip fails or reaches the end of its service life, only the faulty flash memory chip needs to be replaced, saving costs. At the same time, it can improve the utilization rate of the server CPU, reduce latency, and improve performance.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and particularly to an all-flash server. Background Art

[0002] For application scenarios with high requirements for IOPS and low latency requirements, a high-performance enterprise storage system is needed. Such high-performance enterprise storage systems were originally implemented using SAN storage systems constructed with disk arrays composed of a large number of 2.5-inch SAS interface, high-speed (10,000 or 15,000 revolutions per minute) HDDs and controllers. After the emergence of SSDs, especially SSDs using the NVMe interface, all-flash arrays or all-flash servers with all storage media being SSDs are replacing traditional SAN storage systems as enterprise-level high-performance storage systems.

[0003] An SSD consists of three parts: an SSD controller (main control) chip, a DRAM chip serving as a cache, and NAND flash memory particles (chips). NAND flash memory particles are a type of non-volatile (able to retain the stored data information even when power is off) semiconductor memory. All the data of SSD users is stored in the flash memory particles, which are the storage medium of the SSD and also the most easily damaged component in the SSD. In particular, the lifespan of TLC flash memory particles is much lower than that of the SSD controller chip and the cache chip.

[0004] As Figure 1 shown, the SSD is connected to the server. On the one hand, the server host itself has a CPU and DRAM serving as memory, and each SSD connected to the server host also has a CPU and DRAM serving as a cache. In the case where the number of CPU cores of the server is increasing and the number of SSDs connected to each server is also increasing, the CPUs and DRAMs inside the SSDs will not only cause the power consumption and cost of all-flash servers with a large number of SSDs to increase sharply, but also, since the controller chips and DRAM chips inside the SSDs occupy space on the circuit board, the number of flash memory particles that can be arranged in the same circuit board area is reduced, lowering the storage density of the SSD. At the same time, the lifespan of flash memory particles, especially the currently widely used TLC flash memory particles, is much lower than that of the controller chips and DRAM chips. In high-performance heavy-duty all-flash servers, the flash memory particles of the SSDs will quickly reach their service life, and the entire SSD including the controller and cache chips needs to be frequently replaced, greatly increasing the maintenance cost. These problems not only increase the user's TCO (Total Cost of Ownership), but also do not meet the requirements of green environmental protection.

[0005] On the other hand, the number of cores of server CPUs is increasing continuously. For example, the Intel Platinum 8180 CPU has 28 cores, the AMD EPYC 7601 has 32 cores, and the Qualcomm Centriq 2460 has 48 cores. Even the lowest-end server CPU, such as the Intel E3-1230, has 4 cores. In most cases, due to reasons such as uneven load, the inability of software and applications to achieve distributed processing, and blockages caused by hardware bottlenecks, many cores in multi-core server CPUs are inevitably idle and cannot be effectively utilized. Summary of the Invention

[0006] The main object of the present invention is to provide an all-flash server, which increases the number of flash memory particles under the same circuit board area, reduces power consumption, and when a flash memory particle fails or reaches the end of its service life, only the problematic flash memory particle needs to be replaced, saving costs. At the same time, it can improve the utilization rate of the server CPU, reduce latency, and improve performance.

[0007] The present invention provides an all-flash server, including a multi-core CPU, a memory controller, a memory module, a PCIe bus, a flash controller module plugged into the PCIe bus, and a flash module that can be plugged into the flash control module. The multi-core CPU is connected to the memory module through the memory controller. The multi-core CPU includes multiple CPU cores. The PCIe bus is connected to the multi-core CPU and the memory module through the memory controller. The flash controller module includes a flash controller, a first interface connected to the PCIe bus, and a second interface connected to the flash module. The flash module includes several flash memory particles and a third interface connected to the flash controller.

[0008] Further, the first interface is a PCIe interface.

[0009] Further, the second interface is a flash memory interface, and the flash memory interface supports two flash memory interface standards, ToggleDDR and ONFI.

[0010] Further, the third interface supports the ToggleDDR or ONFI interface standard.

[0011] Further, the memory module uses SCM and / or DRAM.

[0012] Further, SCM is PCM, ReRAM, MRAM, or NRAM.

[0013] The beneficial effects of the all-flash server of the present invention are as follows: By using some CPU cores, memory, and software of the server's multi-core CPU to replace the SSD controller chip, cache chip, and firmware, directly read, write, and delete the SSD particles. Since there are only flash particles in the SSD, not only the number of flash particles under the same circuit board area is increased, but also without the controller chip and cache chip, power consumption can be reduced and costs can be saved. Especially when a flash particle fails or reaches its service life, only the problematic flash particle needs to be replaced, instead of replacing the non-problematic main control chip and cache chip as in traditional SSDs, which can greatly reduce the cost of replacing the SSD. At the same time, it can improve the utilization rate of the server CPU, reduce latency, and improve performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of an SSD connected to a server in the background art;

[0015] Figure 2 It is a schematic diagram of the structure of the all-flash server of the present invention;

[0016] Figure 3 It is a schematic diagram of the structure of an embodiment of the all-flash server of the present invention.

[0017] The realization, functional features, and advantages of the object of the present invention will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0019] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly. The described connection can be a direct connection or an indirect connection.

[0021] In addition, in the present invention, descriptions such as "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments may be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0022] Referring to Figure 2 and Figure 3 , a full flash server includes a multi-core CPU 1 (Central Processing Unit), a memory controller 2, a memory module 3, a PCIe bus 4 (PCI Express, a general specification of a computer bus), a flash controller module 5 plugged into the PCIe bus 4, and a flash module 6 that can be plugged into the flash control module. The multi-core CPU 1 is connected to the memory module 3 through the memory controller 2. The multi-core CPU 1 includes a plurality of CPU cores 11. The PCIe bus 4 is connected to the multi-core CPU 1 and the memory module 3 through the memory controller 2. The flash controller module 5 includes a flash controller 51, a first interface connected to the PCIe bus 4, and a second interface connected to the flash module 6. The flash module 6 includes a plurality of flash memory particles 61 and a third interface connected to the flash controller 51.

[0023] In the present invention, the flash controller 51 of the traditional SSD (Solid State Drives) controller chip is separated and made into a separate flash controller module 5. The flash controller module 5 includes a flash controller 51, a first interface connected to the PCIe bus 4, and a second interface connected to the flash module 6. The first interface is a PCIe interface, and the second interface in the flash controller module 5 is a flash interface. The flash interface supports two flash interface standards, Toggle DDR (a flash interface standard jointly launched by Samsung and Toshiba) and ONFI (Open NAND Flash Interface), where NAND is a NAND gate. The flash controller module 5 is connected to the RC (Root Complex, which is the top layer of the PCIe bus 4 connected to the CPU and memory and is the interface for all downstream port PCIe devices to connect) of the PCIe bus 4 through the PCIe interface. The flash module 6 is plugged into the flash interface of the flash controller module 5. The flash module 6 includes a number of flash memory particles 61 and a third interface connected to the flash controller 51. The third interface in the flash module 6 connected to the flash controller 51 supports the Toggle DDR or ONFI interface standard. The CPU originally in the SSD controller chip can be specified by the system software to be undertaken by a part of the CPU cores 11 in the multi-core CPU 1 on the server host. Generally, a server with a NUMA (Non Uniform Memory Access Architecture) architecture can implement this function. The host interface controller, cache controller, and ECC (Error Checking and Correcting) in the controller chip are all implemented through software. The memory module 3 of the server is used as the cache of the flash module 6, thus forming a virtual SSD on the server. In some embodiments, a Cache (Cache Memory) can also be provided between the multi-core CPU 1 and the memory controller 2 to accelerate the CPU reading speed. The CPU cores 11 are respectively connected to the memory module 3 through the memory controller 2, and a Cache can also be provided between the CPU core 11 and the memory controller 2. In some embodiments, the all-flash server further includes an internal interconnection module 7. The memory controller 2 is connected and interacts through the internal interconnection module 7, enabling each CPU core 11 to access the local memory module 3 through the memory controller 2 connected to it, and also to access the remote memory module 3 through the internal interconnection module 7 and the memory controllers 2 of other cores. The memory module 3 can adopt SCM (Storage Class Memory) and / or DRAM (Dynamic Random Access Memory).That is, part of the memory can use DRAM and part can use SCM, or all of it can use DRAM or SCM. It is preferably to use SCM. Since SCM memory is non-volatile (data will not be lost after power-off), it does not require a UPS (Uninterruptible Power Supply) or a large-capacity capacitor to supply power when power is off like RAM (Random Access Memory) used as the cache of an SSD to flush the data and mapping table stored in the cache to the flash memory particles 61. This not only simplifies the system structure, but also reduces power consumption and improves performance. SCM can be PCM (Phase-change Memory), ReRAM (Resistive Random-access Memory), MRAM (Magnetic Random Access Memory), or NRAM (Nantero’s CNT Random Access Memory), etc. If the memory is all composed of DRAM, a sufficiently large UPS or a large-capacity capacitor needs to be configured to ensure that when power is off, all the data cached in DRAM, the mapping table from logical address to physical address, the status table, etc. can be written into the flash memory module 6. Since there is no controller chip and cache chip in the flash memory module 6, it can reduce energy consumption, reduce size and lower the procurement cost for users. If the flash memory particles 61 are damaged, only the flash memory module 6 needs to be replaced, and there is no need to replace the controller chip and cache chip as in a traditional SSD, which greatly reduces the total cost of ownership for users. The functions such as ECC, RAID (Redundant Arrays of Independent Disks), garbage collection, error handling, bad block management, and FTL (Flash Translation Layer) originally implemented by the controller chip and firmware inside the SSD are implemented by the software running on the CPU core 11 of the server host; global configuration and processing can be performed according to the number and capacity of the flash memory controller module 5 and flash memory module 6 configured in the system and the requirements of the application, so as to improve performance, reduce latency, optimize garbage collection and wear leveling, and increase the effective storage space and lifespan of the flash memory module 6. More importantly, RAID and FTL can be implemented according to the requirements of the application, and all the flash memory modules 6 are combined into a large virtual SSD or array. Since FTL can be continuously modified, it can be deeply integrated with the upper-layer software, reducing duplicate processing and write amplification, which can not only improve performance and reduce power consumption, but also increase the lifespan of the flash memory module 6.,

[0024] Refer to Figure 3, in one embodiment, a 4-core CPU is adopted, that is, the CPU includes 4 CPU cores 11, a server with a NUMA architecture. Each CPU core 11 corresponds to a memory controller 2 and a memory module 3. The CPU cores 11 are respectively connected to the memory module 3 through the memory controller 2. A Cache can also be provided between the CPU core 11 and the memory controller 2. The memory controller is connected and interacts with information through the internal interconnection module 7. Among them, two CPU cores 11 are designated as the CPUs of the virtual SSD controller. The memory module 3 connected to these two CPU cores 11 through the memory controller 2 serves as the cache of the virtual SSD. The memory module 3 uses SCM. The PCIe interface of the flash controller module 5 is plugged into the PCIe interface of the server, and the flash module 6 is plugged into the flash interface of the flash controller module 5. The software running on the CPU core 11 designated as the virtual SSD controller receives the read, write, and delete requests sent by the server host, and executes the operations required by the requests according to these requests, such as actually reading and writing data to ECC, performing garbage collection, wear leveling algorithms, etc. During the operation process, on the one hand, it reasonably allocates the load of data on each flash particle 61, and on the other hand, it undertakes the transfer of all data. The software running on the CPU core 11 realizes the required functions, and schedules hardware such as the SCM memory module 3 and the flash controller module 5 to complete the writing, reading, and deletion of data from the host to the flash module 6.

[0025] The present invention is applicable to general servers with a CPU of more than 2 cores and a PCIe bus 4. In addition to the NUMA structure, the server system architecture of the present invention is also applicable to the SMP (Symmetrical Multi-Processing Architecture) structure and the MPP (Massively Parallel Processing Architecture) structure.

[0026] The beneficial effects of the all-flash server of the present invention are as follows: Using some CPU cores, memory, and software of the server's multi-core CPU to replace the SSD controller chip, cache chip, and firmware, directly performing read, write, and delete operations on the SSD particles. Since there are only flash particles in the SSD, not only the number of flash particles under the same circuit board area is increased, but also there is no controller chip and cache chip, which can reduce power consumption and save costs. Especially when a flash particle fails or reaches the end of its service life, only the problematic flash particle needs to be replaced, without the need to replace the problem-free main control chip and cache chip as in traditional SSDs, which can greatly reduce the cost of replacing the SSD. At the same time, it can improve the utilization rate of the server CPU, reduce latency, and improve performance.

[0027] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. A all-flash server, characterized in that, It includes a multi-core CPU, a memory controller, a memory module, a PCIe bus, a flash controller module plugged into the PCIe bus, and a flash memory module plugged into the flash control module. The multi-core CPU is connected to the memory module through the memory controller. The multi-core CPU includes multiple CPU cores. The PCIe bus is connected to the multi-core CPU and the memory module through the memory controller. The flash controller module includes a flash controller, a first interface connected to the PCIe bus, and a second interface connected to the flash memory module. The flash memory module includes a number of flash memory chips and a third interface connected to the flash controller. The memory module uses SCM. A cache memory is provided between the multi-core CPU and the memory controller. The all-flash server further includes an internal interconnection module. The memory controller is connected and interacts through the internal interconnection module, enabling each CPU core to access the local memory module through the memory controller connected to it, and access the remote memory module through the internal interconnection module and the memory controllers of other cores.

2. The all-flash server according to claim 1, characterized in that, The first interface is a PCIe interface.

3. The all-flash server according to claim 1, characterized in that, The second interface is a flash memory interface, and the flash memory interface supports two flash memory interface standards, ToggleDDR and ONFI.

4. The all-flash server according to claim 1, characterized in that, The third interface supports the ToggleDDR or ONFI interface standard.

5. The all-flash server according to claim 1, characterized in that, The SCM is PCM, ReRAM, MRAM, or NRAM.

Images