Semiconductor Package

Abstract

The present disclosure provides a semiconductor package, which includes a first semiconductor package and an interposer. The first semiconductor package includes a first semiconductor package substrate and a first semiconductor chip thereon. The interposer is disposed on the first semiconductor package. The interposer electrically connects the first semiconductor package to an external semiconductor package and has a first side and a second side opposite to each other. The second side is located between the first side and the first semiconductor package substrate, and a first groove is formed in the second side of the interposer. The first groove has a sidewall extending from the second side of the interposer toward the first side and an upper surface connected to the sidewall, and the upper surface of the first groove faces the first semiconductor chip, and a through hole is located in the interposer. The through hole does not transmit an electrical signal between the first semiconductor package and the external semiconductor package. The semiconductor package of the present disclosure can transfer heat generated from the semiconductor chip in the horizontal direction and the vertical direction to reduce thermal resistance.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2017-0134688 filed on October 17, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor package. Background Art

[0003] As electronic devices become thinner and lighter, the thickness of semiconductor packages continues to decrease. As the thickness of semiconductor packages decreases, various methods of effectively dissipating heat generated by semiconductor chips are being developed. Summary of the invention

[0004] Aspects of the present disclosure provide a semiconductor package capable of transferring heat generated from a semiconductor chip in horizontal and vertical directions to reduce thermal resistance.

[0005] This aspect and other aspects, embodiments and advantages of the present disclosure will become immediately apparent to one of ordinary skill in the art upon review of the detailed description and the appended claims.

[0006] According to some embodiments of the inventive concept, a semiconductor package is provided, comprising: a first semiconductor package, comprising a first semiconductor package substrate and a first semiconductor chip on the first semiconductor package substrate; an interposer, disposed on the first semiconductor package, and wherein the interposer electrically connects the first semiconductor package to an external semiconductor package, and has a first side and a second side opposite to each other, wherein the second side is located between the first side and the first semiconductor package substrate; a first groove, formed in the second side of the interposer, wherein the first groove has a sidewall extending from the second side of the interposer toward the first side and an upper surface connected to the sidewall, and the upper surface of the first groove faces the first semiconductor chip; and a through hole, in the interposer, extending from the second side of the interposer toward the first side and disposed between the upper surface of the first groove and the first side of the interposer, wherein the through hole does not transmit an electrical signal between the first semiconductor package and the external semiconductor package.

[0007] According to some embodiments of the inventive concept, a semiconductor package is provided, comprising: a first semiconductor package including a first semiconductor package substrate and a first semiconductor chip on the first semiconductor package substrate; an interposer disposed on the first semiconductor package, wherein the interposer electrically connects the first semiconductor package with an external semiconductor package and has a first side and a second side opposite to each other, wherein the second side is located between the first side and the first semiconductor package substrate; a first groove formed in the second side of the interposer, wherein the first groove has a sidewall extending from the second side of the interposer toward the first side and an upper surface connected to the sidewall, and the upper surface of the first groove faces the first semiconductor chip; an interposer connecting element disposed on the second side of the interposer and exchanging electrical signals with the first semiconductor package substrate; a first pad disposed on the first side of the interposer and electrically connecting the interposer connecting element with the external semiconductor package; and a through hole disposed in the interposer and extending from the second side of the interposer toward the first side, and disposed between the upper surface of the first groove and the first side of the interposer, wherein the through hole is neither electrically connected to the first pad nor to the interposer connecting element.

[0008] According to some embodiments of the inventive concept, a semiconductor package is provided, comprising: a first semiconductor package, comprising a first semiconductor package substrate and a first semiconductor chip on the first semiconductor package substrate; a second semiconductor package, comprising a second semiconductor package substrate and a second semiconductor chip on the second semiconductor package substrate; an interposer inserted between the first semiconductor package and the second semiconductor package and electrically connecting the first semiconductor package and the second semiconductor package, wherein the interposer comprises a first side and a second side opposite to each other, and the second side is located between the first side and the first semiconductor package substrate; a first groove formed in the second side of the interposer, wherein the first groove comprises a sidewall extending from the second side of the interposer toward the first side and an upper surface connected to the sidewall so as to face the first semiconductor chip; and a through hole in the interposer and extending from the second side of the interposer toward the first side, and disposed between an upper surface of the first groove and the first side of the interposer, wherein the through hole does not transmit an electrical signal between the first semiconductor package and the second semiconductor package.

[0009] In one embodiment, a semiconductor package is provided, comprising: a first semiconductor package, comprising a first semiconductor package substrate and a first semiconductor chip disposed on the first semiconductor package substrate; an interposer disposed on the first semiconductor package, wherein the interposer electrically connects the first semiconductor package with another semiconductor package, the interposer comprising a first groove, a first side, and a second side opposite to the first side, wherein the second side is located between the first side and the first semiconductor package substrate; a first groove formed in the second side of the interposer, and the first groove has a sidewall extending from the second side of the interposer toward the first side and a groove upper surface connected to the sidewall, and the groove upper surface is disposed to face the first semiconductor chip; and a through hole disposed in the interposer, extending from the second side of the interposer toward the first side and disposed between the groove upper surface and the first side of the interposer, wherein the through hole is not configured to transmit an electrical signal between the first semiconductor package and the other semiconductor package.

[0010] In another embodiment, a semiconductor package is provided, comprising: a first semiconductor package including a first semiconductor package substrate and a first semiconductor chip disposed on the first semiconductor package substrate; an interposer disposed on the first semiconductor package, wherein the interposer electrically connects the first semiconductor package with another semiconductor package, the interposer comprising a first groove, a first side, and a second side opposite to the first side, wherein the second side is located between the first side and the first semiconductor package substrate, and the first groove is formed in the second side of the interposer, and the first groove has a sidewall extending from the second side of the interposer toward the first side and a groove upper surface connected to the sidewall, and the groove upper surface is disposed to face the first semiconductor chip; an interposer connecting element disposed on the second side of the interposer and configured to transmit an electrical signal between the interposer and the first semiconductor package substrate; a first pad disposed on the first side of the interposer and electrically connecting the interposer connecting element with another semiconductor package; and a through hole disposed in the interposer and extending from the second side of the interposer toward the first side, and disposed between the groove upper surface and the first side of the interposer, wherein the through hole is not configured to transmit an electrical signal between the first pad and the interposer connecting element.

[0011] In one embodiment, a semiconductor package is provided, comprising: a first semiconductor package, comprising a first semiconductor package substrate and a first semiconductor chip disposed on the first semiconductor package substrate; a second semiconductor package, comprising a second semiconductor package substrate and a second semiconductor chip disposed on the second semiconductor package substrate; an interposer inserted between the first semiconductor package and the second semiconductor package and electrically connecting the first semiconductor package and the second semiconductor package, wherein the interposer comprises a first side and a second side opposite to the first side, and wherein the second side is located between the first side and the first semiconductor package substrate; a first groove formed in the second side of the interposer, wherein the first groove comprises a sidewall extending from the second side of the interposer toward the first side and an upper surface of the groove connected to the sidewall so as to face the first semiconductor chip; and a through hole disposed in the interposer and extending from the second side of the interposer toward the first side, and disposed between the upper surface of the groove and the first side of the interposer, wherein the through hole is not configured to transmit an electrical signal between the first semiconductor package and the second semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above aspects and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0013] Figure 1 is a plan view illustrating an intermediary according to some exemplary embodiments of the present disclosure.

[0014] Figures 2 to 13 are views illustrating semiconductor packages according to some exemplary embodiments of the present disclosure.

[0015] Fig.14 is a plan view showing a third semiconductor chip according to some exemplary embodiments of the present disclosure.

[0016] Figure 15 to Figure 18 is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] In the following, reference will be made to Figure 1 and Figure 2 Semiconductor packages according to some exemplary embodiments of the present disclosure are described.

[0018] Figure 1 is a plan view showing an intermediary 300 according to some exemplary embodiments of the present disclosure. Figure 2 is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure. Figure 2 The cross-sectional view of the intermediary 300 shown in FIG. Figure 1 The line A-A' is intercepted.

[0019] refer to Figure 1 and Figure 2 , a semiconductor package according to some exemplary embodiments of the present disclosure may include a first semiconductor package 100 , a second semiconductor package 200 , and an interposer 300 .

[0020] The first semiconductor package 100 may include a first semiconductor package substrate 101 , a first semiconductor chip 110 , a first molding material 121 , and a first adhesive layer 123 .

[0021] The first semiconductor package substrate 101 can be used for packaging and may include, for example, a printed circuit board (PCB) or a ceramic substrate. The first semiconductor package substrate 101 may include an upper surface and a lower surface opposite to each other, that is, on opposite sides of the first semiconductor package substrate 101. The first semiconductor chip 110 may be mounted on the upper surface of the first semiconductor package substrate 101. External connection terminals 103 (for example, package connection terminals) may be disposed on the lower surface of the first semiconductor package substrate 101. The number of external connection terminals 103 is not limited to the number shown in the accompanying drawings. For example, any number of external connection terminals 103 may be disposed on the lower surface of the first semiconductor package substrate 101 as needed.

[0022] The external connection terminal 103 may be, but is not limited to, a conductive ball or a solder ball. The external connection terminal 103 may be, for example, any one of a conductive bump, a conductive spacer, and a pin grid array (PGA). The first semiconductor package 100 may be electrically connected (e.g., may be configured to be electrically connected) to an external device via the external connection terminal 103.

[0023] The first semiconductor chip 110 may be, for example, in the form of a flip chip. The lower surface of the first semiconductor chip 110 may be a first semiconductor element circuit region 111. The first semiconductor chip 110 may be a single semiconductor chip. Alternatively, the first semiconductor chip 110 may be, for example, a stack of a plurality of semiconductor chips.

[0024] The first connection element 113 may be disposed in the first semiconductor element circuit region 111. The first connection element 113 may be, for example, a solder ball or a conductive bump.

[0025] The first semiconductor chip 110 may be electrically connected to the first semiconductor package substrate 101 via the first connection elements 113. The number of the first connection elements 113 is not limited to the number shown in the drawings. It should be understood that any number of first connection elements 113 may be provided as required.

[0026] The first molding material 121 may include a portion of the hole 310h accommodating the interposer connection element 310. The space between the first semiconductor chip 110 and the first semiconductor package substrate 101 may be completely filled with the first molding material 121. The first molding material 121 may surround a portion of the side surface of the first semiconductor chip 110 and a portion of the interposer connection element 310.

[0027] The first molding material 121 may be, for example, epoxy molding compound (EMC).

[0028] A space between the first molding material 121 and the interposer 300 that is not covered by the first molding material 121 may be filled with the first adhesive layer 123. A space between the first semiconductor chip 110 and the interposer 300 may be completely filled with the first adhesive layer 123. The first adhesive layer 123 may surround the remaining portion of the side surface of the first semiconductor chip 110 that is not covered by the first molding material 121 and the remaining portion of the interposer connecting element 310 that is not covered by the first molding material 121. In an exemplary embodiment, the interposer connecting element 310 may be a single connecting element.

[0029] Although the first adhesive layer 123 is shown in the drawings, it is not an essential element of the present disclosure. For example, the first adhesive layer 123 may be eliminated as needed.

[0030] The second semiconductor package 200 may be disposed on the first semiconductor package 100. For example, the first semiconductor package 100 and the second semiconductor package 200 may form a package-on-package (PoP) structure. The second semiconductor package 200 may include a second semiconductor package substrate 201, a second semiconductor chip 210, and a second molding material 220.

[0031] The second semiconductor package substrate 201 may be of the same type as the first semiconductor package substrate 101 or of a different type. The second semiconductor package substrate 201 may include a first surface and a second surface, and the first surface and the second surface may be opposite to each other, that is, on opposite sides of the second semiconductor package substrate 201. The second semiconductor chip 210 may be mounted on the first surface of the second semiconductor package substrate 201. A second connection element 203 including, for example, a first connection element and a second connection element may be disposed on the second surface of the second semiconductor package substrate 201. The second semiconductor package 200 may be electrically connected to an external device or another semiconductor package or the like via the second connection element 203. For example, the second connection element 203 may be of the same type as the external connection terminal 103. However, the technical concept of the present disclosure is not limited thereto. For example, the second connection element 203 may be of a different type from the external connection terminal 103, as long as the second connection element 203 can electrically connect the second semiconductor package 200 to an external device or another semiconductor package, etc.

[0032] The second connection element 203 may be arranged so that it does not overlap with, for example, the second pad 313 in the vertical direction as shown in the drawings. However, the technical concept of the present disclosure is not limited thereto. For example, the second connection element 203 may overlap with at least a portion of the second pad 313. Even if the second connection element 203 overlaps with the second pad 313, the second connection element 203 may not be electrically connected to the second pad 313.

[0033] The second semiconductor chip 210 can be attached to the second semiconductor package substrate 201 by a second adhesive 215. The second semiconductor chip 210 can be electrically connected to the second semiconductor package substrate 201 via a third connection element 213. The upper surface of the second semiconductor chip 210 can be a second semiconductor element circuit area 211. For example, the third connection element 213 can be a wire bonding. Although the second semiconductor chip 210 is illustrated as a single semiconductor chip in the drawings, this is merely illustrative. For example, the second semiconductor chip 210 can be a stack of multiple semiconductor chips.

[0034] The first semiconductor chip 110 and the second semiconductor chip 210 may be, for example, a memory chip, a logic chip, or the like. When the first semiconductor chip 110 and / or the second semiconductor chip 210 are logic chips, the first semiconductor chip 110 and / or the second semiconductor chip 210 may be variously designed in consideration of the operations to be performed. For example, when the first semiconductor chip 110 and / or the second semiconductor chip 210 are memory chips, the memory chips may be nonvolatile memory chips.

[0035] The second molding material 220 may be formed on the second semiconductor package substrate 201. The second molding material 220 may seal the upper surface of the second semiconductor package substrate 201, the second semiconductor chip 210, and the third connection elements 213. For example, the second molding material 220 may include the same material as the first molding material 121.

[0036] The interposer 300 may be disposed on the first semiconductor package 100. The interposer 300 may be inserted between the first semiconductor package 100 and the second semiconductor package 200. The interposer connection elements 310 may be inserted into (eg, disposed in) the holes 310h of the first molding material 121, respectively.

[0037] The interposer 300 may be electrically connected to the first semiconductor package substrate 101 via the interposer connection element 310 to transmit / receive an electrical signal to / from the first semiconductor package 100 .

[0038] The interposer 300 may electrically connect the first semiconductor package 100 to an external semiconductor package, such as another semiconductor package. For example, the interposer 300 may electrically connect the first semiconductor package 100 to the second semiconductor package 200 .

[0039] The interposer 300 may include a first side 300U and a second side 300L that are opposite to each other (ie, on opposite sides of the interposer 300 ). The second side 300L of the interposer 300 may be located between the first side 300U of the interposer 300 and the first semiconductor package substrate 101 .

[0040] Elements for connecting to an external semiconductor package may be disposed on the first side 300U of the interposer 300. For example, the second connection element 203 may be disposed on the first side 300U of the interposer 300. The second connection element 203 may be inserted between the first side 300U of the interposer 300 and the second semiconductor package substrate 201.

[0041] The first pad 311 and the second pad 313 may be disposed on the first side 300U of the interposer 300. For example, a plurality of first pads 311 may be disposed on the first side 300U of the interposer 300. Although the upper surface of the first pad 311 and the first side 300U of the interposer 300 are depicted as being on the same plane of the drawing, the technical concept of the present disclosure is not limited thereto. For example, at least a portion of the first pad 311 may protrude (e.g., may be protruding) from the first side 300U of the interposer 300.

[0042] The first pad 311 may be electrically connected to an element for connecting to an external semiconductor package disposed on the interposer 300. That is, the first pad 311 may be electrically connected to the external semiconductor package. Therefore, the first pad 311 may allow an electrical signal to be exchanged between the external semiconductor package and the first semiconductor package 100. For example, the first pad 311 may allow the second semiconductor package 200 and the first semiconductor package 100 to transmit / receive electrical signals therebetween. The first pad 311 may electrically connect the interposer connection element 310 to the external semiconductor package (e.g., the second semiconductor package 200). For example, the first pad 311 may include a conductive material.

[0043] The second pad 313 may be spaced apart from the first pad 311 and disposed on the first side 300U of the interposer 300. Although the second pad 313 is illustrated as a continuous single piece in the drawings, this is merely illustrative. It should be understood that in other embodiments, a plurality of separate second pads equal in number to the number of second through holes 323 may be disposed on the first side 300U of the interposer 300. In addition, although the upper surface of the second pad 313 and the first side 300U of the interposer 300 are illustrated in the drawings as being on the same plane, the technical concept of the present disclosure is not limited thereto. For example, at least a portion of the second pad may protrude from the first side 300U of the interposer 300.

[0044] The second pads 313 may not transfer or transmit electrical signals between an external semiconductor package (eg, the second semiconductor package 200 ) disposed on the interposer 300 and the first semiconductor package 100 .

[0045] The second pad 313 may include, for example, a material (eg, a heat transfer material) capable of transferring heat of the first semiconductor package 100 to the outside.

[0046] The interposer connection element 310 may be attached to the second side 300L of the interposer 300. The third pad 331 (including, for example, the third pad) may be disposed on the second side 300L of the interposer 300. For example, a plurality of third pads 331 may be disposed on the second side 300L of the interposer 300. Although the lower surface of the third pad 331 and the second side 300L of the interposer 300 are depicted as being on the same plane of the drawing, the technical concept of the present disclosure is not limited thereto. For example, at least a portion of the third pad 331 may protrude from the second side 300L of the interposer 300.

[0047] The third pad 331 may be electrically connected to the interposer connection element 310. Therefore, the third pad 331 may allow electrical signals to be exchanged between the interposer 300 and the first semiconductor package 100. For example, the third pad 331 may include a conductive material.

[0048] The first pad 311 and the third pad 331 may be connected to each other through, for example, a first through hole 321. The first through hole 321 may be formed in the interposer 300 to penetrate at least a portion of the interposer 300.

[0049] The first through hole 321 may allow the external semiconductor package and the first semiconductor package 100 to transmit / receive electrical signals between the first pad 311 and the third pad 331. For example, the first semiconductor package 100 and the second semiconductor package 200 may transmit electrical signals therebetween via the interposer connection element 310 electrically connected to the first semiconductor package substrate 101, the third pad 331, the first through hole 321, and the first pad 311 and via the second connection element 203 electrically connected to the second semiconductor package substrate 201.

[0050] The second through holes 323 may be formed in the interposer 300. At least some of the second through holes 323 may extend from the second side 300L toward the first side 300U of the interposer 300. For example, the second through holes 323 may be connected to the second pad 313. The second through holes 323 may be disposed between an upper surface R1_U (e.g., a groove upper surface) of the first groove R1 and the first side 300U of the interposer 300.

[0051] The second through-hole 323 may not transmit an electrical signal between an external semiconductor package (e.g., the second semiconductor package 200) and the first semiconductor package 100. The second through-hole 323 may not be electrically connected to the first pad 311, the third pad 331, and the interposer connection element 310. The second through-hole 323 may contain, for example, a material (e.g., a heat transfer material) capable of transferring heat of the first semiconductor package 100 to the outside.

[0052] After forming the first pad 311 , the second pad 313 , the third pad 331 , the first through hole 321 , and the second through hole 323 , a space remaining between the first side 300U and the second side 300L of the interposer 300 may be filled with the interposer insulating layer 301 .

[0053] The first groove R1 may be formed in the second side 300L of the interposer 300. The first groove R1 may have a sidewall R1_S extending from the second side 300L of the interposer 300 to the first side 300U and an upper surface R1_U connected to the sidewall R1_S of the first groove R1 and facing the first semiconductor chip 110. The first groove R1 may not penetrate the interposer 300. In some exemplary embodiments of the present disclosure, a portion of the interposer insulating layer 301 and a portion of the second through hole 323 may be exposed through the first groove R1, for example, the first groove R1 exposes a portion of the interposer insulating layer 301 and a portion of the second through hole 323.

[0054] In some embodiments of the present disclosure, a portion of the first semiconductor chip 110 may be inserted into the first groove R1.

[0055] In the semiconductor package according to some exemplary embodiments of the present disclosure, a portion of the first semiconductor chip 110 may be inserted into the first groove R1 so that the total thickness of the first semiconductor chip 110 can be increased. By increasing the total thickness of the first semiconductor chip 110, the heat generated by the first semiconductor chip 110 can be transferred in the horizontal direction. By transferring heat in the horizontal direction to reduce thermal resistance, the performance of the semiconductor package can be improved. In addition, by transferring heat in the horizontal direction, the temperature distribution inside the semiconductor chip becomes uniform, so that the reliability of the semiconductor package can be improved.

[0056] In the semiconductor package according to some exemplary embodiments of the present disclosure, a portion of the first semiconductor chip 110 is inserted into the first groove R1 and the second through hole 323 is formed on the upper surface R1_U of the first groove R1 so that the heat generated by the first semiconductor chip 110 can be transferred in the vertical direction. The second through hole 323 can transfer the heat generated by the first semiconductor chip 110 partially inserted into the first groove R1 in the vertical direction. By transferring heat in the vertical direction to reduce thermal resistance, the performance of the semiconductor package can be improved.

[0057] In the following, reference will be made to Figure 3 A semiconductor package according to some exemplary embodiments of the present disclosure is described. For clarity of illustration, redundant descriptions will be omitted.

[0058] Figure 3 is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0059] refer to Figure 3 , the sidewall R1_S of the first groove R1 of the semiconductor package according to some exemplary embodiments of the present disclosure may surround the entire sidewall of the first semiconductor chip 110. In other words, the first semiconductor chip 110 may be completely inserted into the first groove R1.

[0060] The first adhesive layer 123 may be disposed along the sidewalls and upper surface (e.g., the first semiconductor chip upper surface) of the first semiconductor chip 110. The first adhesive layer 123 may be disposed between the upper surface R1_U of the first groove R1 and the upper surface of the first semiconductor chip 110 and between the sidewalls R1_S of the first groove R1 and the corresponding sidewalls of the first semiconductor chip 110.

[0061] Since the first semiconductor chip 110 is completely inserted into the first groove R1, the total thickness of the interposer 300 can be increased. For example, the thickness of the interposer 300 can be obtained by measuring the distance from the first side 300U to the second side 300L of the interposer 300. Even if the thickness of the interposer 300 is increased, since the first semiconductor chip 110 is completely inserted into the first groove R1, the thickness of the interposer 300 is increased compared to the thickness of the interposer 300. Figure 1 The total height of the first semiconductor package 100 and the interposer 300 may not increase. For example, the total height of the first semiconductor package 100 and the interposer 300 may refer to the height from the lower surface of the first semiconductor package substrate 101 to the first side 300U of the interposer 300.

[0062] Even if the thickness of the interposer 300 is increased, Figure 1 The total height of the first semiconductor package 100 and the interposer 300 is not increased, so the height of the interposer connection element 310 can be reduced. For example, the height of the interposer connection element 310 can be obtained by measuring the distance from the upper surface of the first semiconductor package substrate 101 to the lower surface of the third pad 331.

[0063] In the following, reference will be made to Figure 4 Semiconductor packages according to some exemplary embodiments of the present disclosure are described. For clarity of illustration, redundant descriptions will be omitted.

[0064] Figure 4 is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0065] refer to Figure 4 , the interposer 300 according to some exemplary embodiments of the present disclosure may include an interposer hole 301h penetrating from an upper surface R1_U of the first groove R1 to the first side 300U of the interposer 300. The interposer hole 301h may be formed so that it overlaps the first semiconductor chip 110. The interposer hole 301h may penetrate the second pad 313. The interposer hole 301h may be formed adjacent to the second through hole 323.

[0066] Since the interposer hole 301 h overlaps the first semiconductor chip 110 , efficiency in transferring heat generated in the first semiconductor chip 110 may be improved.

[0067] In the following, reference will be made to Figure 5 Semiconductor packages according to some exemplary embodiments of the present disclosure are described. For clarity of illustration, redundant descriptions will be omitted.

[0068] Figure 5 is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0069] refer to Figure 5 In the semiconductor package according to some exemplary embodiments of the present disclosure, the interposer hole 301 h may be at least partially filled with the first adhesive layer 123 .

[0070] Although the interposer hole 301 h is completely filled with the first adhesive layer 123 in the drawings, the technical concept of the present disclosure is not limited thereto. For example, it should be understood that only a portion of the interposer hole 301 h may be filled with the first adhesive layer 123 .

[0071] In the following, reference will be made to Figure 6 A semiconductor package according to some exemplary embodiments of the present disclosure is described. For clarity of illustration, redundant descriptions will be omitted.

[0072] Figure 6 is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0073] refer to Figure 6 , the interposer 300 according to some exemplary embodiments of the present disclosure may include a second groove, for example, a second groove R2, formed therein.

[0074] For example, the second groove R2 may be formed on the upper surface R1_U of the first groove R1. The width WR2 of the second groove R2 (e.g., the second groove width) may be smaller than the width WR1 of the first groove R1 (e.g., the first groove width). The width WR1 of the first groove R1 may be obtained by measuring the distance between the opposite side walls in the sidewalls R1_S of the first groove R1. In addition, the width WR1 of the first groove R1 may be measured in a direction parallel to the upper surface of the first semiconductor package substrate 101 in the cross section of the first groove R1. The width WR2 of the second groove R2 may be obtained by measuring the distance between the opposite side walls of the second groove R2. In addition, the width WR2 of the second groove R2 may be measured in a direction parallel to the upper surface of the first semiconductor package substrate 101 in the cross section of the second groove R2.

[0075] In some exemplary embodiments of the present disclosure, the inside of the second groove R2 may remain as a blank space.

[0076] Alternatively, in some embodiments, at least a portion of the interior of the second groove R2 may be filled with the first adhesive layer 123 .

[0077] Although a portion of the first through hole 321 is exposed through the second groove R2 in the drawings, the technical concept of the present disclosure is not limited thereto. The second groove R2 may be formed in the upper surface R1_U of the first groove R1 and in the interposer insulating layer 301 so that a portion of the first through hole 321 is not exposed.

[0078] Since the semiconductor package according to some exemplary embodiments of the present disclosure includes the second groove R2 , a void that may be formed in the first adhesive layer 123 can be removed.

[0079] In the following, reference will be made to Figure 7 A semiconductor package according to some exemplary embodiments of the present disclosure is described. For clarity of illustration, redundant descriptions will be omitted.

[0080] Figure 7 is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0081] refer to Figure 7 , the semiconductor package according to some exemplary embodiments of the present disclosure may further include a fourth pad 341 .

[0082] The fourth pad 341 may be disposed on the upper surface R1_U of the first groove R1. In some embodiments, the fourth pad 341 may be exposed through the first groove R1. The fourth pad 341 may be spaced apart from the second pad 313. The fourth pad 341 may be connected to the second pad 313 through the second through hole 323.

[0083] Although the fourth pad 341 is illustrated as a continuous single piece in the drawings, this is merely illustrative. It should be understood that in other embodiments, a plurality of separate fourth pads equal in number to the number of second through holes 323 may be disposed on the upper surface R1_U of the recess R1.

[0084] The first recess R1 of the semiconductor package according to some exemplary embodiments of the present disclosure may expose the fourth pad 341. For example, before forming the first recess R1, a portion of the interposer insulating layer 301 may be disposed between the fourth pad 341 and the second side 300L of the interposer 300. In other words, a portion of the interposer insulating layer 301 may be disposed on a lower surface of the fourth pad 341. In order to expose the fourth pad 341 through the first recess R1, a portion of the interposer insulating layer 301 may be removed. By removing a portion of the interposer insulating layer 301, the efficiency of transferring heat generated by the first semiconductor chip 110 in the vertical direction may be improved.

[0085] In the following, reference will be made to Figure 8 A semiconductor package according to some exemplary embodiments of the present disclosure is described. For clarity of illustration, redundant descriptions will be omitted.

[0086] Figure 8 is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0087] refer to Figure 8 The semiconductor package according to some exemplary embodiments of the present disclosure may further include a first thermal interface material layer (TIM layer) 125 .

[0088] The first TIM layer 125 may be disposed on the first side 300U of the interposer 300. The first TIM layer 125 may be connected to a semiconductor package substrate (eg, the second semiconductor package substrate 201) of an external semiconductor package.

[0089] The first TIM layer 125 may be disposed, for example, to overlap the second pad 313. The first TIM layer 125 may be disposed, for example, to overlap the second through hole 323.

[0090] The first TIM layer 125 may be disposed, for example, between elements for connecting to an external semiconductor package. For example, the first TIM layer 125 may be disposed between second connecting elements 203, which are elements for connecting to the second semiconductor package 200 and including connecting elements. The first TIM layer 125 may be inserted between an external semiconductor package and an interposer 300. For example, the first TIM layer 125 may be inserted between the second semiconductor package 200 and the interposer 300.

[0091] The first semiconductor chip 110 may be thermally connected to an external semiconductor package (eg, the second semiconductor package 200 ) through the second through vias 323 , the second pads 313 , and the first TIM layer 125 .

[0092] In the following, reference will be made to Fig. 9 Semiconductor packages according to some exemplary embodiments of the present disclosure are described. For clarity of illustration, redundant descriptions will be omitted.

[0093] Fig. 9 is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0094] refer to Fig. 9 , a semiconductor package according to some exemplary embodiments of the present disclosure may include a conductive material layer 130 disposed in the first groove R1.

[0095] The conductive material layer 130 may be disposed between an upper surface of the first semiconductor chip 110 and an upper surface R1_U of the first recess R1. The conductive material layer 130 may be disposed, for example, to be spaced apart from the first semiconductor chip 110 in the first recess R1.

[0096] In some embodiments, the conductive material layer 130 may be surrounded by the first adhesive layer 123. For example, the first adhesive layer 123 may be formed between the upper surface of the first semiconductor chip 110 and the conductive material layer 130, between the conductive material layer 130 and the upper surface R1_U of the first recess R1, and between the sidewalls of the conductive material layer 130 and the corresponding sidewalls R1_S of the first recess R1.

[0097] Although the first semiconductor chip 110 is illustrated in the drawings as not being disposed in the first recess R1 , this is merely illustrative. For example, at least a portion of the first semiconductor chip 110 and the conductive material layer 130 may be disposed in the first recess R1 .

[0098] Although the first semiconductor chip 110 and the conductive material layer 130 are shown as being spaced apart from each other in the drawings, this is merely illustrative. For example, the conductive material layer 130 may be disposed in contact with the upper surface of the first semiconductor chip 110. For another example, the conductive material layer 130 may be disposed in contact with the upper surface R1_U of the first recess R1 and may be in contact with the interposer 300. For another example, the conductive material layer 130 may be disposed in contact with the upper surface R1_U of the first recess R1 to be in contact with the interposer 300 and in contact with the upper surface of the first semiconductor chip 110.

[0099] In the semiconductor package according to some exemplary embodiments of the present disclosure, even if the conductive material layer 130 having higher thermal conductivity than the first semiconductor chip 110 is disposed on the first semiconductor chip 110 , the efficiency of transferring heat in the horizontal and vertical directions can be improved by means of the second through holes 323 .

[0100] In the following, reference will be made to Fig.10 A semiconductor package according to some exemplary embodiments of the present disclosure is described. For clarity of illustration, redundant descriptions will be omitted.

[0101] Fig.10 is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0102] refer to Fig.10 , the semiconductor package according to some exemplary embodiments of the present disclosure may further include a fourth connection element 205_1 , a fourth connection element 205_2 , and a fourth connection element 205_3 .

[0103] The fourth connection element 205_1, the fourth connection element 205_2, and the fourth connection element 205_3 may be disposed on the first side 300U of the interposer 300. For example, the fourth connection element 205_1, the fourth connection element 205_2, and the fourth connection element 205_3 may be disposed on the second pad 313. The fourth connection element 205_1, the fourth connection element 205_2, and the fourth connection element 205_3 may be disposed to overlap with the second through hole 323. The fourth connection element 205_1, the fourth connection element 205_2, and the fourth connection element 205_3 may be connected to a semiconductor package substrate such as an external semiconductor package. The fourth connection element 205_1, the fourth connection element 205_2, and the fourth connection element 205_3 may be attached to the second semiconductor package substrate 201. The fourth connecting element 205_1 , the fourth connecting element 205_2 , and the fourth connecting element 205_3 may be inserted between an external semiconductor package (eg, the second semiconductor package 200 ) and the interposer 300 .

[0104] The fourth connecting elements 205_1 , 205_2 and 205_3 may not be configured to transmit electrical signals between the external semiconductor package and the interposer 300 . For example, the fourth connecting elements 205_1 , 205_2 and 205_3 may not be configured to transmit electrical signals between the second semiconductor package 200 and the interposer 300 .

[0105] The fourth connection elements 205_1, 205_2, and 205_3 may include, for example, a material (e.g., a heat transfer material) capable of transferring heat of the first semiconductor package 100 to the outside. The fourth connection elements 205_1, 205_2, and 205_3 may be thermally connected to the second through-hole 323 through the second pad 313. The first semiconductor chip 110 may be thermally connected to an external semiconductor package (e.g., the second semiconductor package 200) through the second through-hole 323, the second pad 313, and the fourth connection elements 205_1, 205_2, and 205_3.

[0106] In the following, reference will be made to Fig.11 A semiconductor package according to some exemplary embodiments of the present disclosure is described. For clarity of illustration, redundant descriptions will be omitted.

[0107] Fig.11 is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0108] refer to Fig.11, a semiconductor package according to some exemplary embodiments of the present disclosure may include a passive element 350 disposed in an interposer 300 .

[0109] The passive element 350 may be disposed between the first pad 311 and the third pad 331 that are electrically connected to each other. For example, the first pad 311 may be connected to the third through hole 325. The third through hole 325 may be connected to the passive element 350. The passive element 350 may be connected to the fourth through hole 327. The fourth through hole 327 may be connected to the third pad 331. The first semiconductor package 100 may transmit / receive an electrical signal to / from the second semiconductor package 200 through the interposer connecting element 310, the third pad 331, the fourth through hole 327, the passive element 350, the third through hole 325, and the first pad 311.

[0110] In the semiconductor package according to some exemplary embodiments of the present disclosure, the thickness of the interposer 300 may be increased by means of the first recess R1, thereby allowing the passive element 350 to be disposed in the interposer 300. For example, it is assumed that the total height of the interposer without the first recess R1 and the first semiconductor package 100 is substantially equal to the total height of the interposer 300 including the first recess R1 and the first semiconductor package 100. In the hypothetical case, the thickness of the interposer 300 including the first recess R1 may be larger / greater than the thickness of the interposer without the first recess R1 while maintaining the total height because at least a portion of the first semiconductor chip 110 may be inserted into the first recess R1.

[0111] In the following, reference will be made to Fig.12 Semiconductor packages according to some exemplary embodiments of the present disclosure are described. For clarity of illustration, redundant descriptions will be omitted.

[0112] Fig.12 is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0113] refer to Fig.12 In the semiconductor package according to some exemplary embodiments of the present disclosure, a portion of the interposer insulating layer 301 may be disposed between the fourth pad 341 and the upper surface R1_U of the first recess R1. The first recess R1 may expose a portion of the interposer insulating layer 301. The fourth pad 341 may be spaced apart from the first adhesive layer 123.

[0114] In the following, reference will be made to Fig.13 A semiconductor package according to some exemplary embodiments of the present disclosure is described. For clarity of illustration, redundant descriptions will be omitted.

[0115] Fig.13 is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0116] refer to Fig.13 , a semiconductor package according to some exemplary embodiments of the present disclosure may include a second TIM layer 127 disposed on the first semiconductor chip 110. The second TIM layer 127 may be disposed between an upper surface of the first semiconductor chip 110 and an upper surface R1_U of the first recess R1.

[0117] In the following, reference will be made to Fig.14 and Fig.15 Semiconductor packages according to some exemplary embodiments of the present disclosure are described. For clarity of illustration, redundant descriptions will be omitted.

[0118] Fig.14 is a plan view illustrating a third semiconductor chip 410 according to some exemplary embodiments of the present disclosure. Fig.15 is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0119] For example, refer to Fig.14 and Fig.15 , the third semiconductor chip 410 according to some exemplary embodiments of the present disclosure may have a step shape. The third semiconductor chip 410 may include a first portion 410_1 (eg, a first chip portion) and a second portion 410_2 (a second chip portion).

[0120] The second portion 410_2 of the third semiconductor chip 410 may protrude from the first portion 410_1 of the third semiconductor chip 410. A width W41 (e.g., a first portion width) of the first portion 410_1 of the third semiconductor chip 410 may be greater than a width W42 (e.g., a second portion width) of the second portion 410_2 of the third semiconductor chip 410. In some embodiments, the first portion 410_1 of the third semiconductor chip 410 may include, for example, a first semiconductor element circuit region 111. The first portion 410_1 and the second portion 410_2 of the third semiconductor chip 410 may be connected to each other.

[0121] Although the first portion 410_1 and the second portion 410_2 of the third semiconductor chip 410 are illustrated as pieces of a single third semiconductor chip 410, this is merely illustrative. For example, the first portion 410_1 and the second portion 410_2 of the third semiconductor chip 410 may be different semiconductor chips. In this case, the third semiconductor chip 410 may include two different semiconductor chips.

[0122] The first portion 410_1 of the third semiconductor chip 410 may be disposed between the second portion 410_2 of the third semiconductor chip 410 and the first semiconductor package substrate 101. At least a portion of the second portion 410_2 of the third semiconductor chip 410 may be inserted into, for example, the first groove R1.

[0123] In some embodiments, if the second portion 410_2 of the third semiconductor chip 410 is completely inserted into the first groove R1 , a portion of the first portion 410_1 of the third semiconductor chip 410 may be inserted into the first groove R1 .

[0124] A portion of the first portion 410_1 of the third semiconductor chip 410 may be arranged to overlap with the second connection element 203, i.e., overlap with at least a portion. For example, a portion of the first portion 410_1 of the third semiconductor chip 410 may not overlap with the second portion 410_2 of the third semiconductor chip 410. In addition, the second connection element 203 overlapping with at least a portion of the first portion 410_1 of the third semiconductor chip 410 may connect an element disposed close to the second pad 313. The phrase "one element overlaps with another element" may refer to that they overlap with each other, for example, in a vertical direction relative to the first semiconductor package substrate 101.

[0125] In the following, reference will be made to Fig.16 Semiconductor packages according to some exemplary embodiments of the present disclosure are described. For clarity of illustration, redundant descriptions will be omitted.

[0126] Fig.16 is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0127] refer to Fig.16 , the interposer 300 of the semiconductor package according to some exemplary embodiments of the present disclosure may include a third recess R3 .

[0128] The third groove R3 may include a first portion R3_1 (e.g., a first groove portion) and a second portion R3_2 (e.g., a second groove portion). The first portion R3_1 of the third groove R3 may include an upper surface R3_U of the third groove R3. The first width WR31 (e.g., a first groove width) of the first portion R3_1 of the third groove R3 may be smaller than the second width WR32 of the second portion R3_2 of the third groove R3, e.g., a second groove width.

[0129] The third semiconductor chip 410 may be completely inserted into the third groove R3. The sidewall R3_S of the third groove R3 may surround the entire sidewall of the third semiconductor chip 410. For example, the second portion 410_2 of the third semiconductor chip 410 may be disposed in the first portion R3_1 of the third groove R3. In addition, the first portion 410_1 of the third semiconductor chip 410 may be disposed in the second portion R3_2 of the third groove R3.

[0130] In the following, reference will be made to Fig.17 Semiconductor packages according to some exemplary embodiments of the present disclosure are described. For clarity of illustration, redundant descriptions will be omitted.

[0131] Fig.17 is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.

[0132] refer to Fig.17 , the semiconductor package according to some exemplary embodiments of the present disclosure may include an interposer hole 301h and the fourth connecting element 205_1 and the fourth connecting element 205_3. The second TIM layer 127 may be disposed between the interposer 300 and the first semiconductor chip 110 and used to fill the interposer hole 301h and the space between the fourth connecting element 205_1 and the fourth connecting element 205_3 and the second connecting element 203.

[0133] In the following, reference will be made to Fig.18 Semiconductor packages according to some exemplary embodiments of the present disclosure are described. For clarity of illustration, redundant descriptions will be omitted.

[0134] Fig.18 are diagrams illustrating semiconductor packages according to some exemplary embodiments of the present disclosure.

[0135] refer to Fig.18 , a semiconductor package according to some embodiments of the present invention may include a third semiconductor chip 410, an interposer hole 301h, and fourth connecting elements 205_1 and 205_3. A second TIM layer 127 may be disposed between the interposer 300 and the third semiconductor chip 410 and may be used to at least partially fill the interposer hole 301h.

[0136] Although the present invention has been depicted and described with particular reference to the exemplary embodiments of the inventive concept, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the inventive concept as defined in the appended claims. It is therefore contemplated that the embodiments of the present invention are to be considered in all respects as illustrative and non-restrictive, with reference to the appended claims rather than the foregoing description indicating the scope of the invention.

Claims

1. A semiconductor package, comprising: A first semiconductor package comprises a first semiconductor package substrate and a first semiconductor chip disposed on the first semiconductor package substrate; an interposer disposed on the first semiconductor package, wherein the interposer electrically connects the first semiconductor package to another semiconductor package, the interposer comprising a first groove, a first side, and a second side opposite to the first side, wherein the second side is located between the first side and the first semiconductor package substrate, the first groove is formed in the second side of the interposer, and the first groove has a sidewall extending from the second side of the interposer toward the first side and a groove upper surface connected to the sidewall, and the groove upper surface is arranged to face the first semiconductor chip; as well as a through hole disposed in the intermediary, extending from the second side of the intermediary toward the first side and disposed between an upper surface of the groove and the first side of the intermediary; an adhesive layer extending along the first groove of the interposer and the second side of the interposer, wherein a side surface of the first semiconductor chip at least partially contacts the adhesive layer; as well as an interposer connecting element, penetrating through the adhesive layer and electrically connecting the first semiconductor package substrate and the interposer, Wherein the through-via is not configured to transmit an electrical signal between the first semiconductor package and the another semiconductor package. 2 . The semiconductor package according to claim 1 , wherein at least a portion of the first semiconductor chip is disposed in the first groove. 3 . The semiconductor package of claim 1 , wherein the interposer further comprises an interposer hole penetrating from an upper surface of the recess to the first side of the interposer.

4. The semiconductor package according to claim 3, further comprising: A thermal interface material layer is disposed between the upper surface of the groove and the upper surface of the first semiconductor chip, wherein the interposer hole is at least partially filled with the thermal interface material layer.

5. The semiconductor package according to claim 1 , wherein the interposer further comprises a second groove formed in an upper surface of the groove, and The first groove width of the first groove is greater than the second groove width of the second groove.

6. The semiconductor package according to claim 1 , wherein the interposer further comprises a first pad and a second pad, the first pad being disposed on the first side of the interposer, the second pad being disposed in the interposer, and the second pad being spaced apart from the first pad and exposed through the first groove, and The through hole connects the first pad to the second pad.

7. The semiconductor package according to claim 1, further comprising: The thermal interface material layer is arranged between the upper surface of the groove and the upper surface of the first semiconductor chip.

8. The semiconductor package according to claim 1, further comprising: The conductive material layer is arranged between the upper surface of the first semiconductor chip and the upper surface of the groove.

9. The semiconductor package according to claim 1, further comprising: a connecting element disposed on the first side of the interposer and overlapping the through hole, The connecting element is not configured to transmit electrical signals between the other semiconductor package and the interposer.

10. The semiconductor package according to claim 1, wherein the interposer connection element is disposed on the second side of the interposer and is configured to transmit electrical signals between the interposer and the first semiconductor package substrate, and Also includes: a first pad disposed on the first side of the interposer, and the first pad electrically connects the interposer connection element with the other semiconductor package; as well as A passive component is connected to the interposer connection component and the first pad.

11. A semiconductor package, comprising: A first semiconductor package includes a first semiconductor package substrate and a first semiconductor chip disposed on the first semiconductor package substrate; an interposer disposed on the first semiconductor package, wherein the interposer electrically connects the first semiconductor package to another semiconductor package, the interposer comprising a first groove, a first side, and a second side opposite to the first side, wherein the second side is located between the first side and the first semiconductor package substrate, and the first groove is formed in the second side of the interposer, and the first groove has a sidewall extending from the second side of the interposer toward the first side and a groove upper surface connected to the sidewall, and the groove upper surface is arranged to face the first semiconductor chip; an interposer connection element disposed on the second side of the interposer and configured to transmit electrical signals between the interposer and the first semiconductor package substrate; a first pad disposed on the first side of the interposer and electrically connecting the interposer connection element to the other semiconductor package; a through hole disposed in the intermediary and extending from the second side of the intermediary toward the first side, and disposed between an upper surface of the groove and the first side of the intermediary; as well as an adhesive layer extending along the first groove of the interposer and the second side of the interposer, wherein a side surface of the first semiconductor chip is at least partially in contact with the adhesive layer, wherein the through hole is not configured to transmit an electrical signal between the first pad and the interposer connection element, and The interposer connecting element penetrates through the adhesive layer and electrically connects the first semiconductor package substrate and the interposer.

12. The semiconductor package according to claim 11, further comprising: A thermal interface material layer is disposed on the first side of the intermediary.

13. The semiconductor package according to claim 11, further comprising: a second pad disposed on the first side of the interposer, spaced apart from the first pad, connected to the through-hole, and not configured to transmit an electrical signal between the interposer and the other semiconductor package; as well as an interposer insulating layer, disposed between the second pad and the upper surface of the groove, The first groove exposes the interposer insulating layer.

14. The semiconductor package according to claim 11, wherein the first semiconductor chip comprises a first chip portion and a second chip portion protruding from the first chip portion, wherein a first portion width of the first chip portion is greater than a second portion width of the second chip portion, and The first chip portion of the first semiconductor chip is disposed in the first groove.

15. The semiconductor package according to claim 11 , wherein the first groove includes a first groove portion having a first groove width and a second groove portion having a second groove width greater than the first groove width, and the first groove portion of the first groove includes the groove upper surface, The first semiconductor chip includes a first chip portion and a second chip portion protruding from the first chip portion, wherein a first portion width of the first chip portion of the first semiconductor chip is greater than a second portion width of the second chip portion of the first semiconductor chip, wherein the second chip portion of the first semiconductor chip is disposed in the first groove portion of the first groove, and At least a portion of the first chip portion of the first semiconductor chip is disposed in the second groove portion of the first groove.

16. A semiconductor package, comprising: A first semiconductor package comprises a first semiconductor package substrate and a first semiconductor chip disposed on the first semiconductor package substrate; A second semiconductor package comprises a second semiconductor package substrate and a second semiconductor chip disposed on the second semiconductor package substrate; an interposer inserted between the first semiconductor package and the second semiconductor package and electrically connecting the first semiconductor package and the second semiconductor package, wherein the interposer includes a first side and a second side opposite to the first side, and wherein the second side is located between the first side and the first semiconductor package substrate; a first groove formed in the second side of the interposer, wherein the first groove includes a sidewall extending from the second side of the interposer toward the first side and a groove upper surface connected to the sidewall so as to face the first semiconductor chip; a through hole disposed in the intermediary and extending from the second side of the intermediary toward the first side, and disposed between an upper surface of the groove and the first side of the intermediary; an adhesive layer extending along the first groove of the interposer and the second side of the interposer, wherein a side surface of the first semiconductor chip at least partially contacts the adhesive layer; as well as an interposer connecting element, penetrating through the adhesive layer and electrically connecting the first semiconductor package substrate and the interposer, Wherein the via is not configured to transmit an electrical signal between the first semiconductor package and the second semiconductor package. 17 . The semiconductor package according to claim 16 , wherein at least a portion of the first semiconductor chip is disposed in the first groove. 18 . The semiconductor package of claim 16 , wherein the interposer further comprises an interposer hole penetrating from an upper surface of the recess to the first side of the interposer.

19. The semiconductor package according to claim 16, wherein the interposer further comprises a second groove formed in an upper surface of the groove, and The first groove width of the first groove is greater than the second groove width of the second groove.

20. The semiconductor package according to claim 16, further comprising: A first connecting element and a second connecting element are disposed between the second semiconductor package substrate and the interposer. wherein the first connecting element is configured to transmit an electrical signal between the second semiconductor package and the interposer, and The second connection element is disposed to overlap the through hole and is not configured to transmit an electrical signal between the second semiconductor package and the interposer.

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