A parallel ping-pong processing unit, a high-speed frequency scanning device and a method of use

Abstract

The present invention discloses a parallel ping-pong processing unit, a high-speed frequency scanning device and a method of use, and belongs to the field of digital signal processing application technology. A parallel ping-pong processing unit includes N signal processing channels, wherein N≥2 and N is an integer, and the N signal processing channels are connected in parallel with each other; a high-speed frequency scanning device includes a signal processing unit, a frame splicing processing unit and a parallel ping-pong processing unit, and the signal processing unit, the parallel ping-pong processing unit and the frame splicing processing unit are electrically connected in sequence. The present invention can use the signal processing unit to realize the digital processing of the intermediate frequency signal according to the actual design requirements of the user, and the parallel ping-pong processing unit can perform digital FFT transformation on the signal, thereby not only improving the processing speed of the signal, but also improving the spectrum scanning speed.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital signal processing applications, and in particular, relates to a parallel ping-pong processing unit, a high-speed frequency scanning device and a use method thereof. Background Art

[0002] In recent years, digital signal processing has developed rapidly. Digitalization and broadband have become the mainstream of wireless communication today, and have gradually replaced analog signal processing. Digital programmable logic modules have the advantages of high flexibility, reusability, stable operation, and good linearity. With the rapid development of large-scale integrated circuits and the reduction in the cost and size of digital chips, the application of digital signal processing is becoming more and more extensive. Converting analog signals into digital signals through analog-to-digital conversion for filtering, frequency conversion, and FFT Fourier transform has become the main form of digital communication today. FFT Fourier transform takes a long time, which reduces the overall scanning rate.

[0003] Chinese patent publication number: CN 103973324 A; publication date: August 6, 2014, discloses a broadband digital receiver, the purpose of which is to solve the problem of narrow bandwidth and low spectrum resolution of existing digital receivers in real-time spectrum processing. The invention provides a broadband digital receiver, including an input end and an output end, and also includes a first filter group, an analog mixing module, a second filter group, an analog-to-digital conversion module, a spectrum conversion module and a spectrum conversion module. The first filter group is connected to the input end and the analog mixing module respectively, the second filter group is connected to the analog mixing module and the analog-to-digital conversion module respectively, the time-frequency conversion module is connected to the analog-to-digital conversion module and the spectrum splicing module respectively, and the output end is connected to the spectrum splicing module. The invention is suitable for electronic reconnaissance reception, real-time spectrum analysis, radar, communication and other fields. However, the disadvantage of the invention is that after the invention receives a signal, the N filters will directly divide the entire analysis bandwidth of the signal into N channels, and then process and analyze the N channels respectively, and finally the data in the N channels are uniformly sorted. This process is not only complicated and cumbersome, but also prone to errors and difficult to use for a long time. Summary of the invention

[0004] 1. Problems to be solved

[0005] Aiming at the problem of low frequency scanning rate in existing receivers, the present invention provides a parallel ping-pong processing unit, a high-speed frequency scanning device and a use method.

[0006] 2. Technical solution

[0007] To solve the above problems, the present invention adopts the following technical solutions.

[0008] A parallel ping-pong processing unit comprises N signal processing channels, wherein N≥2 and N is an integer, and the N signal processing channels are connected in parallel with each other.

[0009] Furthermore, the signal processing channel includes a RAM data storage module, an FFT module and an ABS amplitude obtaining module, the RAM data storage module is electrically connected to the FFT module and the ABS amplitude obtaining module respectively, and the FFT module is electrically connected to the ABS amplitude obtaining module.

[0010] Furthermore, the RAM data storage module includes a RAM data storage module A and a RAM data storage module B, the RAM data storage module A is electrically connected to the FFT module, and the RAM data storage module B is electrically connected to the ABS amplitude obtaining module.

[0011] A high-speed frequency scanning device comprises a signal processing unit, a frame splicing processing unit and a parallel ping-pong processing unit, wherein the signal processing unit, the parallel ping-pong processing unit and the frame splicing processing unit are electrically connected in sequence.

[0012] Furthermore, the signal processing unit includes an ADC sampling module, a digital down-conversion DDC module, a CIC extraction filter module and a half-band digital filter, and the ADC sampling module, the digital down-conversion DDC module, the CIC extraction filter module and the half-band digital filter are electrically connected in sequence.

[0013] Furthermore, the frame splicing processing unit includes an MCU controller, and the MCU controller is electrically connected to a display.

[0014] A method for using a high-speed frequency scanning device, the steps are as follows:

[0015] The digital signal is processed by the signal processing unit to perform shaping filtering;

[0016] The data of the signal processing unit is processed alternately by the parallel ping-pong processing unit and then enters the frame splicing processing unit;

[0017] The MCU controller continuously splices the received data until a complete data signal is obtained;

[0018] The data signal is sent to a display and displayed by the display.

[0019] Furthermore, before the shaping filter processing is performed, the following steps are also included:

[0020] The A / D sampling chip samples the signal that needs to be sampled;

[0021] The sampled data is transmitted to a signal processing unit.

[0022] Furthermore, the specific process of the shaping filter processing is as follows:

[0023] The sampled digital signal is converted into a baseband signal via a digital down-conversion DDC module;

[0024] The baseband signal changes the sampling rate and resolution bandwidth through the CIC extraction filter module;

[0025] The extracted signal is subjected to shaping filtering through a half-band digital filter.

[0026] Furthermore, the specific process of the parallel ping-pong processing unit alternating processing is as follows:

[0027] The signal after the shaping filter processing is alternately stored in N RAM data storage modules A;

[0028] The signal in the RAM data storage module A is processed by the FFT module to transform the time domain signal into the frequency domain signal, wherein the data of the frequency domain signal includes I data and Q data;

[0029] The data of the frequency domain signal obtains the amplitude value of the data through the ABS amplitude obtaining module;

[0030] The amplitude values ​​are stored in N RAM data storage modules B.

[0031] 3. Beneficial effects

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] (1) The parallel ping-pong processing unit of the present invention includes N signal processing channels, where N ≥ 2 and N is an integer, and the N signal processing channels are connected in parallel to each other, wherein the signal is processed alternately by ping-pong through two signal processing channels, and then outputted in parallel from the parallel ping-pong processing unit, thereby improving the scanning speed of the entire device;

[0034] (2) The signal processing channel of the present invention includes a RAM data storage module, an FFT module and an ABS amplitude obtaining module, wherein the RAM data storage module includes a RAM data storage module A and a RAM data storage module B, the RAM data storage module A is electrically connected to the FFT module, and the RAM data storage module B is electrically connected to the ABS amplitude obtaining module. After the signal is processed by the RAM data storage module, the FFT module and the ABS amplitude obtaining module, the time domain is transformed into the frequency domain, and the amplitude value of the signal IQ data can also be obtained. According to the mutual cooperation between the modules, the amplitude value of the signal is processed, thereby improving the processing speed of the parallel ping-pong processing unit;

[0035] (3) The high-speed frequency scanning device of the present invention comprises a signal processing unit, a frame splicing processing unit and a parallel ping-pong processing unit, wherein the signal processing unit, the parallel ping-pong processing unit and the frame splicing processing unit are electrically connected in sequence, and after the signal is processed by the signal processing unit, it enters the parallel ping-pong processing unit, and after the signal is stored and transformed by the parallel ping-pong processing unit, it enters the frame splicing processing unit again, and the transformed spectrum data will be spliced ​​with a fixed bandwidth, so that the signal scanning in the entire spectrum can be realized;

[0036] (4) The signal processing unit of the present invention comprises an ADC sampling module, a digital down-conversion DDC module, a CIC extraction filter module and a half-band digital filter, wherein the ADC sampling module, the digital down-conversion DDC module, the CIC extraction filter module and the half-band digital filter are electrically connected in sequence, and the resolution bandwidth of the spectrum signal and the bandwidth of the single FFT spectrum signal can be changed by changing the extraction rate of the CIC extraction filter, so as to meet the user's requirements for the resolution, scanning width and scanning time of different signals;

[0037] (5) The frame splicing processing unit of the present invention includes an MCU controller, which is electrically connected to a display, wherein the MCU controller continuously splices the spectrum data after FFT processing until all spectrum signals within the entire frequency bandwidth are obtained, and then sends the spliced ​​signals to the display for display, thereby ensuring the normal operation of the high-speed frequency scanning device as a whole;

[0038] (6) The method of using the present invention can use the signal processing unit to realize digital processing of the intermediate frequency signal according to the actual design requirements of the user, and the parallel ping-pong processing unit can perform digital FFT transformation on the signal, thereby not only improving the signal processing speed, but also improving the spectrum scanning speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 The principle block diagram of the high-speed scanning of the parallel ping-pong processing of the present invention

[0040] Figure 2 It is a schematic diagram of the frame splicing method of the present invention. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present invention are clearly and completely described. Among them, the described embodiments are some embodiments of the present invention, not all embodiments. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but only represents selected embodiments of the present invention.

[0042] It should be noted that, in the description of the present invention, the terms "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" etc. indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0043] Furthermore, it should be understood that for the sake of ease of description, the sizes of the various components shown in the drawings are not drawn according to actual proportions. For example, the thickness or width of certain layers may be exaggerated relative to other layers.

[0044] It should be noted that like reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined or described in one drawing, it will not require further detailed discussion and description in the description of the subsequent drawings.

[0045] Example 1

[0046] refer to Figure 1 The present embodiment provides a parallel ping-pong processing unit, comprising N signal processing channels, wherein N≥2 and N is an integer, and the N signal processing channels are connected in parallel to each other. In the present embodiment, specifically, the number N is selected to be 2, that is, the parallel ping-pong processing unit comprises 2 identical signal processing channels, and the 2 identical signal processing channels are connected in parallel to each other.

[0047] Furthermore, the signal processing channel includes a RAM data storage module, an FFT module and an ABS amplitude obtaining module, wherein the RAM data storage module includes a RAM data storage module A and a RAM data storage module B. In the RAM data storage module, the RAM data storage module A stores the signal that initially enters the parallel ping-pong processing unit, and the RAM data storage module B stores the signal that has been processed in the parallel ping-pong processing unit.

[0048] In this embodiment, specifically, the RAM data storage module is electrically connected to the FFT module and the ABS amplitude obtaining module, wherein the FFT module and the ABS amplitude obtaining module are electrically connected to each other. Furthermore, the RAM data storage module A is electrically connected to the FFT module, and the RAM data storage module B is electrically connected to the ABS amplitude obtaining module. That is to say, the RAM data storage module A, the FFT module, the ABS amplitude obtaining module and the RAM data storage module B are electrically connected in sequence.

[0049] Furthermore, the two identical signal processing channels are signal processing channel A and signal processing channel B. Signal processing channel A includes a RAM11 data storage module, an FFT module, an ABS amplitude obtaining module and a RAM21 data storage module, and the RAM11 data storage module, the FFT module, the ABS amplitude obtaining module and the RAM21 data storage module are electrically connected in sequence.

[0050] Similarly, the signal processing channel B includes a RAM12 data storage module, an FFT module, an ABS amplitude obtaining module and a RAM22 data storage module, and the RAM12 data storage module, the FFT module, the ABS amplitude obtaining module and the RAM22 data storage module are electrically connected in sequence.

[0051] In this embodiment, specifically, after the RAM11 data storage module in the signal processing channel A collects the received signal, it performs FFT transformation, performs FFT transformation through the FFT module, and obtains the amplitude of the transformed data, that is, obtains the amplitude value through the ABS amplitude obtaining module, and the obtained amplitude value data will be stored in the RAM21 data storage module.

[0052] Similarly, after the RAM12 data storage module in the signal processing channel B collects the received signal, it performs FFT transformation, performs FFT transformation through the FFT module, and obtains the amplitude of the transformed data, that is, obtains the amplitude value through the ABS amplitude obtaining module, and the obtained amplitude value data will be stored in the RAM22 data storage module.

[0053] It is worth noting that the length of FFT can be selected by setting the sweep bandwidth and resolution bandwidth. The sweep bandwidth and resolution bandwidth here can be changed according to the actual needs of the user. Similarly, they can also be changed separately. Similarly, the sweep bandwidth and resolution bandwidth can only change one of the data. Each time a frame of FFT is completed, the data will be triggered to move in an interrupt manner, and a frame of amplitude and frequency data will be rotated and thrown.

[0054] The received signal is processed by the ping-pong alternation of the signal processing channel A and the signal processing channel B, and then output in parallel from the parallel ping-pong processing unit, thereby improving the overall scanning speed of the device.

[0055] Example 2

[0056] refer to Figure 1 , this embodiment provides a high-speed frequency scanning device, including a signal processing unit, a frame splicing processing unit and a parallel ping-pong processing unit, wherein the signal processing unit, the parallel ping-pong processing unit and the frame splicing processing unit are electrically connected in sequence.

[0057] In this embodiment, specifically, the signal processing unit includes an ADC sampling module, a digital down-conversion DDC module, a CIC extraction filter module and a half-band digital filter, wherein the ADC sampling module, the digital down-conversion DDC module, the CIC extraction filter module and the half-band digital filter are electrically connected in sequence. At the same time, the signal processing unit can be an FPGA logic chip.

[0058] Furthermore, the ADC sampling module converts the received signal from an analog signal into a digital signal, and then the sampled digital signal is converted down to a baseband signal through a digital down-conversion DDC module. At the same time, the baseband signal will pass through a CIC extraction filter module to change the sampling rate and resolution bandwidth of the baseband signal. This is because the larger the decimation rate, the lower the sampling rate and the narrower the resolution bandwidth.

[0059] The processed baseband signal will be shaped by a half-band digital filter. It is worth noting that changing the decimation rate of the CIC decimation filter can change the resolution bandwidth of the spectrum signal and the bandwidth of the single FFT spectrum signal. This is because the decimation rate of the CIC decimation filter is determined by the sampling rate and the required resolution bandwidth. The larger the decimation rate, the smaller the resolution bandwidth and the smaller the local oscillator step.

[0060] In this embodiment, specifically, the parallel ping-pong processing unit includes two identical signal processing channels, wherein the signal processing channels include a RAM data storage module, an FFT module and an ABS amplitude obtaining module, wherein the RAM data storage module includes a RAM data storage module A and a RAM data storage module B. The RAM data storage module is electrically connected to the FFT module and the ABS amplitude obtaining module, wherein the FFT module and the ABS amplitude obtaining module are electrically connected to each other, and further, the RAM data storage module A is electrically connected to the FFT module, and the RAM data storage module B is electrically connected to the ABS amplitude obtaining module, that is, the RAM data storage module A, the FFT module, the ABS amplitude obtaining module and the RAM data storage module B are electrically connected in sequence.

[0061] Furthermore, after the RAM11 data storage module in the signal processing channel A collects the received signal, it performs FFT transformation, performs FFT transformation through the FFT module, and obtains the amplitude of the transformed data, that is, obtains the amplitude value through the ABS amplitude obtaining module, wherein the obtained amplitude value data will be stored in the RAM21 data storage module. After all the data is written into the RAM21 data storage module, an interrupt signal will be generated and sent to the CPU to notify the CPU to read the data. At the same time, after the data collection in the RAM11 data storage module is completed, an interrupt signal will also be sent to the CPU to notify the CPU to send the local oscillator control data. After the local oscillator step control is completed, the CPU will send an instruction to the RAM12 data storage module to collect data to the signal processing unit.

[0062] Similarly, the data processing method in the signal processing channel B is consistent with the data processing method in the signal processing channel A, and will not be described again in this embodiment. It is worth noting that the number of points, resolution bandwidth, CIC decimation rate, and local oscillator step of each frame of FFT are one-to-one corresponding. Correspondingly, the length of FFT is selected by setting the resolution bandwidth, and each time a frame of FFT is completed, the data is triggered to be moved in an interrupt manner.

[0063] refer to Figure 2 In this embodiment, specifically, the frame splicing processing unit includes an MCU controller, wherein the MCU controller is electrically connected to the parallel ping-pong processing unit, and the MCU controller is also electrically connected to a display. That is to say, after each frame of amplitude frequency data is rotated and thrown, it needs to be displayed by splicing later.

[0064] Furthermore, the MCU controller will continuously splice the spectrum data after FFT processing until all spectrum signals within the entire frequency bandwidth are obtained, and then send the spliced ​​signals to the display for display, thereby ensuring the normal operation of the high-speed frequency scanning device as a whole.

[0065] In this embodiment, specifically, Figure 2 This is a schematic diagram of the frame splicing method. After the first local oscillator frequency is transformed by FFT, the data of FFT window 1 will be obtained through rotation and parabola processing. After the second local oscillator frequency is transformed by FFT, the data of FFT window 2 will be obtained through rotation and parabola processing. Then, the data of FFT window 1 and the data of FFT window 2 are connected and processed. Similarly, the subsequent FFT serial port data are spliced ​​in sequence to complete the splicing of the data of the entire scanned spectrum.

[0066] The rotation of FFT data is to divide the same frame of data into two segments from the middle and exchange the positions of the two frames of data, that is, the data in the second half will be rotated to the first half, and the data in the first half will be rotated to the second half.

[0067] The number of FFT data discarded is due to the uneven data gain at both ends of the filter amplifier, which will cause the spectrum width of each frame of data to be greater than the width of the previous frame of the spectrum display, so the uneven data at both ends need to be discarded. The amount of data discarded at each end is the total number of spectrum in each frame minus half of the data displayed in the actual spectrum. The specific formula is as follows:

[0068] M=Δf / RBW

[0069] CIC=fs / (2*RBW*Nz)

[0070] Where: M is the actual number of points retained; Nz is the number of FFT points; Δf is the local oscillator step length; fs is the A / D sampling clock rate; RBW is the resolution bandwidth.

[0071] Example 3

[0072] refer to Figure 1 and Figure 2 This embodiment provides a method for using a high-speed frequency scanning device, and the specific steps are as follows:

[0073] Step S1: The A / D sampling chip samples the signal to be sampled and transmits the sampled data to the signal processing unit. It is worth noting that the signal transmitted to the signal processing unit is a digital signal.

[0074] Step S2: The digital signal is processed by the signal processing unit and subjected to shaping filter processing. It is worth noting that the data of the signal in the signal processing unit includes I data and Q data, and the specific process of the shaping filter processing is as follows:

[0075] Step S2.1: The sampled digital signal is processed by a digital down-conversion DDC module and converted into a baseband signal;

[0076] Step S2.2: the baseband signal changes the sampling rate and the resolution bandwidth through the CIC decimation filter module, wherein changing the decimation rate of the CIC decimation filter can change the resolution bandwidth of the spectrum signal and the bandwidth of the single FFT spectrum signal, because the decimation rate of the CIC decimation filter is determined by the sampling rate and the required resolution bandwidth;

[0077] Step S2.3: The extracted signal is subjected to shaping filtering through a half-band digital filter.

[0078] Step S3: After the data of the signal processing unit is alternately processed by the parallel ping-pong processing unit, it enters the frame splicing processing unit, wherein the parallel ping-pong processing unit includes two identical signal processing channels. In this embodiment, specifically, the two identical signal processing channels are signal processing channel A and signal processing channel B, wherein signal processing channel A includes RAM11 data storage module, FFT module A, ABS amplitude obtaining module A and RAM21 data storage module; signal processing channel B includes RAM12 data storage module, FFT module B, ABS amplitude obtaining module B and RAM22 data storage module. The specific process of alternating processing is as follows:

[0079] Step S3.1: The signal after the shaping filter processing is first stored in the RAM11 data storage module;

[0080] Step S3.2: The signal stored in the RAM11 data storage module is transformed by FFT module A, and the amplitude value is obtained by ABS amplitude obtaining module A;

[0081] Step S3.3: The obtained amplitude value data will be stored in the RAM21 data storage module;

[0082] Step S3.4: After all the data is written into the RAM21 data storage module, an interrupt signal is generated and sent to the CPU to notify the CPU to read the data;

[0083] Step S3.5: After the data collection in the RAM11 data storage module is completed, an interrupt signal will also be sent to the CPU to notify the CPU to send the local oscillator control data;

[0084] Step S3.6: After the local oscillator stepping control is completed, the CPU will send an instruction for the RAM12 data storage module to collect data to the signal processing unit.

[0085] It is worth noting that after all the data are written into the RAM data storage module B, the processing method in the RAM data storage module B is the same as the data processing method in the RAM data storage module A, and will not be repeatedly described in this embodiment.

[0086] Step S4: The MCU controller continuously splices the received data until a complete data signal is obtained, and sends the data signal to the display for display. The splicing process is as follows:

[0087] Step S4.1: Obtain the data of the first FFT window, that is, after the first local oscillator frequency is FFT transformed, and then the data of the first FFT window is obtained through rotation and parametric processing;

[0088] Step S4.2: Obtain the data of the second FFT window, that is, after the second local oscillator frequency is FFT transformed, and then the data of the second FFT window is obtained through rotation and parametric processing;

[0089] Step S4.3: Connect the data of the first FFT window and the data of the second FFT window. It is worth noting that the data of the subsequent FFT serial ports are spliced ​​in sequence to complete the splicing of the data of the entire scan spectrum.

[0090] The present invention and its embodiments are described schematically above, and the description is not restrictive. The drawings show only one embodiment of the present invention, and the actual structure is not limited thereto. Therefore, if a person skilled in the art is inspired by it and designs a structural method and an embodiment similar to the technical solution without creativity without departing from the purpose of the invention, they shall all fall within the protection scope of the present invention.

Claims

1. A high-speed frequency scanning device, characterized in that: It includes a signal processing unit, a frame splicing processing unit and a parallel ping-pong processing unit, and the signal processing unit, the parallel ping-pong processing unit and the frame splicing processing unit are electrically connected in sequence; the signal processing unit includes an ADC sampling module, a digital down-conversion DDC module, a CIC extraction filter module and a half-band digital filter, and the ADC sampling module, the digital down-conversion DDC module, the CIC extraction filter module and the half-band digital filter are electrically connected in sequence; the ADC sampling module converts the received signal from an analog signal into a digital signal, and then the sampled digital signal is down-converted to a baseband signal through the digital down-conversion DDC module, and at the same time, the baseband signal will change the sampling rate and resolution bandwidth of the baseband signal through the CIC extraction filter module; The frame splicing processing unit splices the data processed by the parallel ping-pong processing unit. After the first local oscillator frequency is FFT-transformed, the frame splicing processing unit obtains the data of FFT window 1 through rotation and parabola processing, and after the second local oscillator frequency is FFT-transformed, the frame splicing processing unit obtains the data of FFT window 2 through rotation and parabola processing, and then the data of FFT window 1 and the data of FFT window 2 are connected and processed, and the subsequent FFT serial port data are spliced ​​in sequence, thereby completing the splicing of the data of the entire scan spectrum; The rotation of the first local oscillator frequency FFT and the second local oscillator frequency FFT is to divide the same frame of data into two segments from the middle and exchange the positions of the two frames of data; The first local oscillator frequency FFT and the second local oscillator frequency FFT are performed by discarding the uneven data at both ends. The amount of data discarded at each end is the total number of spectrums in each frame minus half of the data displayed in the actual spectrum, calculated by the following formula: M=Δf / RBW CIC=fs / (2*RBW*Nz) Where: M is the actual number of points to be retained; Nz is the number of FFT points; Δf is the local oscillator step length; fs is the A / D sampling clock rate; RBW is the resolution bandwidth; CIC is the CIC extraction filter module parameter; The parallel ping-pong processing unit includes N signal processing channels, wherein N≥2 and N is an integer, and the N signal processing channels are connected in parallel with each other.

2. A high-speed frequency scanning device according to claim 1, characterized in that: The signal processing channel includes a RAM data storage module, an FFT module and an ABS amplitude obtaining module. The RAM data storage module is electrically connected to the FFT module and the ABS amplitude obtaining module respectively, and the FFT module is electrically connected to the ABS amplitude obtaining module.

3. A high-speed frequency scanning device according to claim 2, characterized in that: The RAM data storage module includes a RAM data storage module A and a RAM data storage module B. The RAM data storage module A is electrically connected to the FFT module, and the RAM data storage module B is electrically connected to the ABS amplitude obtaining module.

4. A high-speed frequency scanning device according to any one of claims 1 to 3, characterized in that: The frame splicing processing unit includes an MCU controller, and the MCU controller is electrically connected to a display.

5. A method for using the high-speed frequency scanning device according to claim 4, the steps being as follows: The signal to be sampled is sampled by an A / D sampling chip, and the sampled signal is converted into a digital signal; the sampled data is transmitted to a signal processing unit; The digital signal is processed by the signal processing unit to perform shaping filtering; The data of the signal processing unit is processed alternately by the parallel ping-pong processing unit and then enters the frame splicing processing unit; The MCU controller continuously splices the received data until a complete data signal is obtained; The data signal is sent to a display and displayed by the display; The specific process of shaping filter processing is as follows: The sampled digital signal is converted into a baseband signal via a digital down-conversion DDC module; The baseband signal changes the sampling rate and resolution bandwidth through the CIC extraction filter module; The extracted signal is subjected to shaping filtering by a half-band digital filter; in, Changing the decimation rate of the CIC decimation filter can change the resolution bandwidth of the spectrum signal and the bandwidth of the single FFT spectrum signal.

6. The method for using a high-speed frequency scanning device according to claim 5, characterized in that: The specific process of the parallel ping-pong processing unit alternating processing is as follows: The signal after the shaping filter processing is alternately stored in N RAM data storage modules A; The signal in the RAM data storage module A is processed by the FFT module to transform the time domain signal into the frequency domain signal, wherein the data of the frequency domain signal includes I data and Q data; The data of the frequency domain signal obtains the amplitude value of the data through the ABS amplitude obtaining module; The amplitude values ​​are stored in N RAM data storage modules B.

Images