Semiconductor Package and Method of Manufacturing the Same

Abstract

Embodiments of the present invention provide semiconductor packages. One of the semiconductor packages includes a first chip, a second chip, and a molding compound. The first chip has at least one first through hole and a protective layer, and the at least one first through hole is formed in the protective layer. The second chip has at least one second through hole. The molding layer encapsulates the first chip and the second chip. The at least one second through hole is disposed in the molding layer and in contact with the molding layer, and the top surface of the protective layer, the top surface of the at least one first through hole, and the top surface of the at least one second through hole are substantially coplanar with the top surface of the molding layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor packaging. Background Art

[0002] Three-dimensional integration technologies for wafer-level packaging are being developed to meet the requirements of high-density integrated packaging for size reduction, high-performance interconnections, and heterogeneous integration. Summary of the Invention

[0003] A semiconductor package according to an embodiment of the present invention includes a first chip, a second chip, and a molding compound. The first chip has at least one first through hole and a protective layer, and the at least one first through hole is formed in the protective layer. The second chip has at least one second through hole. The molding layer encapsulates the first chip and the second chip. The at least one second through hole is disposed in the molding layer and in contact with the molding layer, and the top surface of the protective layer, the top surface of the at least one first through hole, and the top surface of the at least one second through hole are substantially coplanar with the top surface of the molding layer. Brief Description of the Drawings

[0004] Reading the following detailed description in conjunction with the accompanying drawings will best understand various aspects of the present disclosure. It should be noted that, according to standard practices in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0005] Figures 1A to 1G is a schematic cross-sectional view of various stages in a method of manufacturing a semiconductor package according to some exemplary embodiments.

[0006] Figure 2 is a schematic cross-sectional view showing a semiconductor package according to some exemplary embodiments.

[0007] Figures 3A to 3I is a schematic cross-sectional view of various stages in a method of manufacturing a semiconductor package according to some exemplary embodiments.

[0008] Figure 4 is a schematic cross-sectional view showing a semiconductor package according to some exemplary embodiments.

[0009] Figures 5A to 5F is a schematic cross-sectional view of various stages in a method of manufacturing a semiconductor package according to some exemplary embodiments of the present disclosure.

[0010] Figure 6 is a schematic cross-sectional view showing a semiconductor package according to some exemplary embodiments. Detailed Description

[0011] Numerous different embodiments or examples are provided below to implement different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature "on" or "above" a second feature in the examples below can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where additional features can be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may reuse reference numerals and / or letters in various examples. This reuse is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to facilitate the description of the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or other orientations), and the spatially relative terms used herein may be interpreted accordingly.

[0013] Additionally, for ease of description, terms such as "first", "second", "third", "fourth", etc. may be used herein to describe elements or features that are similar or different from those shown in the figures, and may be used interchangeably depending on the order in which they exist or the context of the description.

[0014] Other features and processes may also be included. For example, test structures may be included to assist in verification testing of three-dimensional (3D) packages or three-dimensional integrated circuits (3DICs). The test structures may include, for example, test pads formed in a redistribution layer or on a substrate to enable testing of the 3D package or 3D integrated circuit, use of probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. Additionally, the structures and methods disclosed herein may be used in combination with test methods that include intermediate verification of known good dies to increase yield and reduce costs.

[0015] Figures 1A to 1Gis a schematic cross-sectional view of each stage in a method of manufacturing a semiconductor package according to some exemplary embodiments. In the exemplary embodiments, the semiconductor manufacturing method is part of a packaging process. In some embodiments, two chips are shown to represent a plurality of chips, and one or more packages are shown to represent a plurality of semiconductor packages obtained after the semiconductor manufacturing method.

[0016] Referring Figure 1A , a carrier C is provided. A release layer DB and an adhesive layer 103 are sequentially stacked on the carrier C. In some embodiments, the release layer DB is formed on the upper surface of the carrier C, and the release layer DB is located between the carrier C and the adhesive layer 103. The carrier C is, for example, a glass substrate. On the other hand, in some embodiments, the release layer DB is a light-to heat-conversion (LTHC) release layer formed on a glass substrate. In some embodiments, the adhesive layer 103 is a die attach film (DAF). However, the materials of the release layer DB, the carrier C, and the adhesive layer 103 are for illustrative purposes only, and the present disclosure is not limited thereto.

[0017] Referring Figure 1B , a plurality of through interlayer vias (TIVs) 102, a first chip (die) 110, and a second chip (die) 130 are disposed on the carrier C. The first chip 110 and the second chip 130 are placed on the release layer DB on which the through interlayer vias 102 are formed using the adhesive layer 103. The first chip 110 and the second chip 130 are adjacent to each other and surrounded by the through interlayer vias 102. In some embodiments, the first chip 110 and the second chip 130 may be the same type of chip or different types of chips, and may be digital chips, analog chips, or mixed-signal chips, such as application-specific integrated circuit (ASIC) chips, high-bandwidth memory (HBM) chips, sensor chips, wireless and radiofrequency chips, memory chips, logic chips, or voltage regulator chips.

[0018] In some embodiments, the first chip 110 and the second chip 130 have different thicknesses t1, t2. In some embodiments, the first chip 110 includes an active surface 112, a plurality of pads 114 distributed on the active surface 112, a passivation layer 116 covering the active surface 112, a plurality of first vias 118, and a protective layer 120. The pads 114 are partially exposed by the passivation layer 116. The first vias 118 are disposed on the pads 114 and electrically connected to the pads 114, and the protective layer 120 covers the first vias 118 and the passivation layer 116. For example, the first vias 118 may have different heights or the same height in a range of about 20 μm to about 25 μm measured from the active surface 112 to the top surface of the first vias 118 themselves. In an exemplary embodiment, the first vias 118 include a seed layer 118a and a metal layer 118b, and the seed layer 118a is disposed only on the bottom of the metal layer 118b. The materials of the seed layer 118a and the metal layer 118b may include, for example, copper, copper alloy, or other suitable material options. In some embodiments, the protective layer 120 may be a polybenzoxazole (PBO) layer, a polyimide (PI) layer, or other suitable polymers. In some alternative embodiments, the protective layer 120 may be made of an inorganic material.

[0019] In some embodiments, the second chip 130 includes an active surface 132, a plurality of pads 134 distributed on the active surface 132, a passivation layer 136 covering the active surface 132, and a plurality of second vias 138. The pads 134 are partially exposed by the passivation layer 136, and the second vias 138 are disposed on the pads 134 and electrically connected to the pads 134. It should be noted that the second vias 138 are exposed. In other words, compared with the first vias 118 covered by the protective layer 120 of the first chip 110, the second vias 138 of the second chip 130 are exposed and not covered. In an exemplary embodiment, the second vias 138 include a seed layer 138a and a metal layer 138b, and the seed layer 138a is disposed only on the bottom of the metal layer 138b. In some embodiments, for example, the second vias 138 may have different heights or the same height in a range of about 20 μm to about 25 μm measured from the active surface 132 to the top surface of the second vias 138 themselves. The second vias 138 and the first vias 118 may have different or the same heights. In some embodiments, for example, the top surface of the second vias 138 is higher than the top surface of the first vias 118. As Figure 1B shown, the top surface of the first chip 110 and the top surface of the second chip 130 are lower than the top surface of the interlayer via 102. However, the present disclosure is not limited thereto. In some alternative embodiments, the top surface of the first chip 110 and the top surface of the second chip 130 may be higher than the top surface of the interlayer via 102 or substantially coplanar with the top surface of the interlayer via 102.

[0020] Referring to Figure 1C , a molding compound 140 is formed over a carrier C to encapsulate the via 102, the first chip 110, and the second chip 130. In some embodiments, the molding compound 140 is formed by a molding process. The via 102, the protective layer 120 of the first chip 110, and the second via 138 of the second chip 130 are encapsulated by the molding compound 140. In other words, the via 102, the protective layer 120 of the first chip 110, and the second via 138 of the second chip 130 are not exposed and are well protected by the molding compound 140. In some embodiments, the molding compound 140 may include epoxy or other suitable materials. In an exemplary embodiment, the molding compound 140 may include a material without fillers.

[0021] Referring to Figure 1D , the molding compound 140 and the protective layer 120 of the first chip 110 are polished until the top surfaces of the first via 118 and the second via 138 are exposed. After polishing the molding compound 140, a molding layer 140' is formed over the adhesive layer 103. During the above polishing process, some portions of the protective layer 120 are also polished to form a protective layer 120'. In some embodiments, during the above polishing process of the molding compound 140 and the protective layer 120, some portions of the first via 118, some portions of the second via 138, and some portions of the via 102 are polished until the top surfaces of the first via 118, the second via 138, and the via 102 are exposed. In other words, the molding layer 140' exposes at least a portion of the first chip 110, at least a portion of the second chip 130, and at least a portion of the via 102. In some embodiments, the molding layer 140' may be formed by mechanical polishing, chemical mechanical polishing (CMP), or another suitable mechanism.

[0022] The molding layer 140' encapsulates the sidewalls of the first chip 110 and the second chip 130, the protective layer 120', and the second vias 138, and the molding layer 140' is penetrated by the interlayer vias 102. In other words, the first chip 110, the second chip 130, and the interlayer vias 102 are embedded in the molding layer 140'. It should be noted that although the first chip 110, the second chip 130, and the interlayer vias 102 are embedded in the molding layer 140', the molding layer 140' exposes the top surfaces of the first chip 110, the second chip 130, and the interlayer vias 102. In other words, the top surface of the interlayer vias 102, the top surface of the protective layer 120', and the top surfaces of the first via 118 and the second via 138 are substantially coplanar with the top surface of the molding layer 140'. Additionally, the second via 138 is disposed in the molding layer 140' and is in contact with the molding layer 140', while the first via 118 is disposed in the protective layer 120' and is in contact with the protective layer 120'.

[0023] Referring to Figure 1E , after forming the molding layer 140' and the protective layer 120', a redistribution layer 150 electrically connected to the first via 118 of the first chip 110, the second via 138 of the second chip 130, and the interlayer vias 102 is formed on the top surface of the interlayer vias 102, the top surface of the molding layer 140', the top surface of the first via 118, the top surface of the second via 138, and the top surface of the protective layer 120'. As Figure 1E shown, the redistribution layer 150 includes a plurality of interlayer dielectric layers 152 and a plurality of redistribution conductive patterns 154 stacked alternately. The redistribution conductive patterns 154 are electrically connected to the first via 118 embedded in the protective layer 120' and the second via 138 and the interlayer vias 102 embedded in the molding layer 140'. In some embodiments, the top surfaces of the first via 118, the second via 138, and the interlayer vias 102 are in contact with the bottommost redistribution conductive pattern 154 of the redistribution layer 150. The top surfaces of the first via 118, the second via 138, and the interlayer vias 102 are partially covered by the bottommost interlayer dielectric layer 152. In an exemplary embodiment, the redistribution conductive pattern 154 includes a seed layer 154a and a conductive layer 154b, and the seed layer 154a is disposed on the bottom of the conductive layer 154b. Additionally, the topmost redistribution conductive pattern 154 includes a plurality of pads. In some embodiments, the above pads include a plurality of under-ball metallurgy (UBM) patterns 156a for ball mount and / or at least one connection pad 156b for mounting passive components. The number of the under-ball metallurgy patterns 156a and the connection pads 156b is not limited in the present disclosure.

[0024] Referring to Figure 1F , after forming the redistribution layer 150, a plurality of conductive terminals 160 are placed on the under-bump metal pattern 156a, and a plurality of passive components 162 are mounted on the connection pads 156b. In some embodiments, the conductive terminals 160 can be placed on the under-bump metal pattern 156a by a ball placement process or other suitable process, and the passive components 162 can be mounted on the connection pads 156b by a soldering process, a reflow soldering process, or other suitable process.

[0025] Referring to Figure 1F and Figure 1G , after mounting the conductive terminals 160 and the passive components 162 on the redistribution layer 150, the Figure 1G shown structure is peeled off from the carrier C. That is, the carrier C, the release layer DB, and the adhesive layer 103 are removed. In some embodiments, the release layer DB (e.g., a photothermal conversion release layer) can be irradiated by an ultraviolet laser. Here, the formation of the integrated fan-out (INFO) package 10 is substantially completed. In some embodiments, the integrated fan-out package 10 can be connected to and / or stacked with other electronic devices.

[0026] Figure 2 is a schematic cross-sectional view showing a semiconductor package according to some exemplary embodiments. In Figure 2 , a semiconductor package 10 similar to the Figure 1G shown structure is described, except that the interlayer vias are omitted. In the semiconductor package 10, the second through-hole 138 of the second chip 130 is disposed in the molding layer 140', and the top surface of the second through-hole 138 is substantially coplanar and flush with the polished top surface of the molding layer 140' and the top surface of the first through-hole 118 of the first chip 110.

[0027] In some embodiments, a planarization process is performed to eliminate the thickness difference between the first chip and the second chip and the height difference between the through-hole and the interlayer via. Therefore, chips with different thicknesses (e.g., different types of chips or chips from different suppliers) can be placed on the carrier for packaging. Additionally, the second through-hole is encapsulated by the molding layer after bonding the second substrate to the carrier, while the first through-hole is encapsulated by the protective layer before bonding the first chip to the carrier. In other words, the first through-hole of the first chip is disposed in the protective layer and in contact with the protective layer, and the second through-hole of the second chip is disposed in the molding layer and in contact with the molding layer.

[0028] Figures 3A to 3IIt is a schematic cross-sectional view of each stage in a method for manufacturing a semiconductor package according to some exemplary embodiments. In some embodiments, two chips are shown to represent a plurality of chips, and one or more packages are shown to represent a plurality of semiconductor packages obtained after a semiconductor manufacturing method. Elements that are similar or substantially the same as the above-described elements will be denoted by the same reference numerals, and certain details or descriptions of the same elements will not be repeated herein.

[0029] Referring to Figure 3A , a carrier C is provided. In some embodiments, a release layer DB and a dielectric layer DI are sequentially stacked on the carrier C. In some embodiments, the dielectric layer DI is, for example, a polymer such as polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or a similar material. In some alternative embodiments, the dielectric layer DI may comprise a non-organic dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or a similar material. However, the material of the dielectric layer DI is for illustrative purposes only, and the present disclosure is not limited thereto.

[0030] Next, an interlayer via 102, a first chip 110 having a first adhesive layer 104, and a second chip 130 having a second adhesive layer 106 are disposed on the dielectric layer DI. In an exemplary embodiment, the first chip 110 and the second chip 130 have different thicknesses t1, t2. However, by adjusting the thickness t1' of the first adhesive layer 104 and the thickness t2' of the second adhesive layer 106, the total thickness of the first chip 110 and the first adhesive layer 104 is substantially equal to the total thickness of the second chip 130 and the second adhesive layer 106, for example, t1 + t1' = t2 + t2'. Accordingly, the active surface 112 of the first chip 110 and the active surface 132 of the second chip 130 are substantially coplanar. In some embodiments, the first chip 110 includes an active surface 112, a plurality of pads 114 distributed on the active surface 112, and a passivation layer 116 covering the active surface 112. In some embodiments, the second chip 130 includes an active surface 132, a plurality of pads 134 distributed on the active surface 132, and a passivation layer 136 covering the active surface 132. As Figure 3A shown, for example, the top surface of the first chip 110 and the top surface of the second chip 130 are lower than the top surface of the interlayer via 102.

[0031] Referring to Figure 3B, a molding layer 140a is formed on a carrier C to encapsulate the first chip 110 and the second chip 130, and a top surface of the molding layer 140a is not higher than an active surface 112 of the first chip 110 and an active surface 132 of the second chip 130. In some embodiments, the first chip 110 and the second chip 130 on the dielectric layer DI and a portion of the via 102 located above the carrier C are encapsulated in the molding layer 140a. In some embodiments, the molding layer 140a covers the dielectric layer DI and fills between the first chip 110 and the second chip 130 and the via 102. In an exemplary embodiment, the molding layer 140a is formed by: using a mold chase (not shown in the figure) with a release film (not shown in the figure) attached to its inner surface to cover the active surface 112 of the first chip 110, the active surface 132 of the second chip 130, and a top portion of the via 102, but exposing lateral sides of the first chip 110, lateral sides of the second chip 130, and a bottom portion of the via 102. That is, the top surface of the molding layer 140a is lower than the active surface 112 of the first chip 110 and the active surface 132 of the second chip 130 and lower than the top surface of the via 102. In an exemplary embodiment, the top surface of the molding layer 140a has a dish-shaped depression due to the pressure from the release film. In an exemplary embodiment, the material of the molding layer 140a includes at least one type of filler-containing resin, and the resin can be an epoxy resin, a phenolic resin, or a silicone-containing resin. In an exemplary embodiment, the filler is made of a non-molten inorganic material, and the filler includes metal oxide particles, silica particles, or silicate particles with an average particle size in a range of about 3 μm to about 20 μm, about 10 μm to about 20 μm, or in a range of about 15 μm to about 20 μm. The surface roughness or surface flatness of the cured molding compound varies depending on whether fine filler particles or coarse filler particles are added to the molding compound material. If a planarization process is performed on the molding compound, some pits may be formed in the molding compound due to the removal of the filler, resulting in relatively large surface roughness, or even unevenness and possible connection failures. In some embodiments, the molding layer 140a is formed without performing a planarization process.

[0032] Referring to Figure 3C , a first via 118 and a second via 138 are respectively formed on the active surface 112 of the first chip 110 and the active surface 132 of the second chip 130. As Figure 3CAs shown, the molding layer 140a does not cover the top portion of the interlayer vias 102 that are exposed from the molding layer 140a. That is, the first through-hole 118, the second through-hole 138, and the top portion of the interlayer vias 102 protrude from the top surface of the molding layer 140a. In an exemplary embodiment, for example, the first through-hole 118 and the second through-hole 138 have seed layers 118a, 138a and metal layers 118b, 138b. The first through-hole 118 and the second through-hole 138 can be formed as follows. First, a seed layer is formed over the passivation layers 116, 126, and a mask having an opening is formed over the passivation layers 116, 126, the opening exposing a portion of the seed layer. The material of the seed layer can include, for example, copper, a copper alloy, or other suitable material options. In some embodiments, the seed layer can be formed by physical vapor deposition or other applicable methods. Next, a metal material is filled into the opening of the mask, thereby forming the metal layers 118b, 138b. In some embodiments, the metal material can be formed by a plating process. The plating process is, for example, electroplating, electroless plating, immersion plating, etc. The metal material is, for example, copper, a copper alloy, or a similar material. The seed layer and the metal material can comprise the same material. Then, the mask is removed, and the seed layer is patterned to form the seed layers 118a, 138a. In some embodiments, the seed layers 118a, 138a are only provided on the bottom of the metal layers 118b, 138b, and no seed layer is provided on the sidewalls of the metal layers 118b, 138b. In some alternative embodiments, the seed layer can be omitted, and the first through-hole 118 and the second through-hole 138 can be formed by other suitable methods.

[0033] Referring to Figure 3D , is formed on the molding layer 140a. The dielectric layer 142 is formed conformally with the underlying components and the molding layer 140a. In other words, the top surface of the dielectric layer 142 is not planar. The material of the dielectric layer 142 is different from the material of the molding layer 140a, and the dielectric layer 142 does not contain fillers. As Figure 3DAs shown, a dielectric layer 142 is formed over the molding layer 140a, the active surfaces 112 of the first chip 110 and 132 of the second chip 130, and the top portions of the first via 118, the second via 138, and the interlayer via 102 that are exposed from the molding layer 140a, such that the overall interlayer via 102, the first chip 110, the second chip 130, and the first via 118 and the second via 138 are jointly encapsulated by the molding layer 140a and the dielectric layer 142. In some embodiments, the first via 118, the second via 138, and the top portions of the interlayer via 102 are encapsulated by the dielectric layer 142. That is, the top surface of the dielectric layer 142 is higher than the top surface of the interlayer via 102 and higher than the top surfaces of the first via 118 and the second via 138. In some embodiments, for example, the thickness of the dielectric layer 142 (measured from the top surface of the molding layer 140a to the top surface of the dielectric layer 142) ranges from about 10 μm to about 15 μm. In an exemplary embodiment, the material of the dielectric layer 142 includes a filler-free polymeric material, and the polymeric material is selected from low-temperature curable polyimide (PI) materials, high-temperature curable polyimide (PI) materials, photosensitive dry film materials or non-photosensitive dry film materials, epoxy resins, benzocyclobutene, polybenzoxazole, or any other suitable dielectric material. In some embodiments, the dielectric layer 142 is formed by a coating process, a deposition process, or other applicable methods.

[0034] Referring to Figure 3E, in some embodiments, a planarization process is performed on the dielectric layer 142 to form the dielectric layer 142', such that some portions of the dielectric layer 142 and some portions of the via holes 102 are removed, and the first vias 118 of the first chip 110 and the second vias 138 of the second chip 130 are exposed from the dielectric layer 142'. As an alternative, in one embodiment, some portions of the first vias 118 and some portions of the second vias 138 may also be removed. In some embodiments, after planarization, the dielectric layer 142' has a planar top surface, and the first vias 118, the second vias 138, the via holes 102, and the dielectric layer 142' become flat and substantially flush (i.e., the top surfaces of the first vias 118, the second vias 138, and the top surface of the via holes 102 are substantially coplanar and flush with the polished top surface of the dielectric layer 142'). In some embodiments, the planarization process for planarizing the dielectric layer 142 and the via holes 102 includes a fly cut process, a grinding process, or a chemical mechanical polishing (“CMP”) process. In some embodiments, for example, the thickness of the planar dielectric layer 142' (measured from the planar top surface of the molding layer 140a to the planar top surface of the dielectric layer 142') ranges from about 5 μm to about 10 μm. The first vias 118, the second vias 138, and the via holes 102 are exposed from the top surface of the planar dielectric layer 142' for further connection. The planar dielectric layer 142' and the molding layer 140a form a composite molding compound. Since the material of the dielectric layer 142' does not contain fillers and has better flow ability, the dielectric layer 142' can provide better coverage and filling ability over the underlying components and the molding layer 140a, thereby resulting in better surface flatness, as well as structural integrity and strength for the composite structure of the molding layer 140a and the dielectric layer 142'.

[0035] Referring to Figure 3F , in some embodiments, a redistribution layer 150 is formed that is electrically connected to the first vias 118 of the first chip 110, the second vias 138 of the second chip 130, and the via holes 102.

[0036] Referring to Figure 3G , in some embodiments, after forming the redistribution layer 150, a plurality of conductive terminals 160 are placed on the under-bump metal pattern 156a, and a plurality of passive components 162 are mounted on the connection pads 156b.

[0037] Referring to Figure 3H, after installing the conductive terminals 160 and the passive components 162 on the redistribution layer 150, the dielectric layer DI formed on the bottom surface of the molding layer 140a is peeled off from the release layer DB so that the dielectric layer DI is separated from the carrier C. Then, a plurality of conductive terminals 164 are placed in the contact openings, and a plurality of contact openings O are formed to locally expose the vias 102. In some embodiments, the release layer DB (e.g., a photothermal conversion release layer) can be irradiated with an ultraviolet laser so that the dielectric layer DI adhered to the bottom surface of the molding layer 140a is peeled off from the carrier C. As Figure 3H shown, the dielectric layer DI is then patterned so that a plurality of contact openings O are formed to locally expose the vias 102. The number of contact openings O corresponds to the number of vias 102. In some embodiments, the contact openings O of the dielectric layer DI are formed by a laser drilling process, a mechanical drilling process, or other suitable processes.

[0038] Referring to Figure 3I , after the contact openings O are formed in the dielectric layer DI, a plurality of conductive terminals 164 are placed in the contact openings O, and the conductive terminals 164 are electrically connected to the vias 102. Here, the formation of the integrated fan-out (INFO) package 10 is substantially completed. In some embodiments, the integrated fan-out package 10 can be stacked with other electronic devices. For example, another package (e.g., an integrated circuit (IC) package) is provided, and the package is stacked on top of the integrated fan-out package 10 and electrically connected to the integrated fan-out package 10 through the conductive terminals 164 so that a package-on-package (POP) structure is fabricated.

[0039] Figure 4 is a schematic cross-sectional view showing a semiconductor package according to some exemplary embodiments. In Figure 4 , a semiconductor package 10 similar to the structure shown in Figure 3I is described, except that the vias are omitted. In some embodiments, the first chip 110 and the second chip 130 have pads 122, 124 on the surfaces opposite to the active surfaces 112, 132, the contact openings O are formed to locally expose the pads 122, 124, and the conductive terminals 164 are placed in the contact openings O corresponding to the pads 122, 124.

[0040] Figures 5A to 5F is a schematic cross-sectional view of each stage in a method for manufacturing a semiconductor package according to some exemplary embodiments of the present disclosure. Figures 3C to 3I The method of Figures 5A to 5FThe difference between the methods lies in the formation methods of the first through-hole and the second through-hole. The difference is shown in detail below, and the similarities will not be repeated herein.

[0041] Referring to Figure 5A , there is provided Figure 3B the structure shown, and a dielectric layer 142 having an opening 144 is formed on the molding layer 140a, and some portions of the pads 114 of the first chip 110 and some portions of the pads 134 of the second chip 130 are exposed by the opening 144. In some embodiments, the dielectric layer 142 may be formed by physical vapor deposition or other applicable methods, and the opening 144 is formed by a photolithography process and an etching process. The dielectric layer 142 is formed substantially conformally with the underlying components and the molding layer 140a, and thus the top surface of the dielectric layer 142 is not planar. In some embodiments, the top surface of the dielectric layer 142 is higher than the top surface of the via 102, and thus the via 102 is encapsulated in the dielectric layer 142 and the molding layer 140a. The formation method, material, and thickness of the dielectric layer 142 are similar to Figure 3D the formation method, material, and thickness of the dielectric layer 142 described.

[0042] Referring to Figure 5B , a conductive layer 148 is formed on the dielectric layer 142 and the conductive layer 148 fills the opening 144. In some embodiments, the conductive layer 148 is formed by: forming a seed layer 148a on the top surface of the dielectric layer 142 and on the sidewalls and bottom of the opening 144; and then forming a metal layer 148b on the seed layer 148a and filling the opening 144. The formation methods and materials of the seed layer 148a and the metal layer 148b are similar to Figure 3C the formation methods and materials of the seed layer and the metal layer described.

[0043] Referring to Figure 5C, a planarization process is performed on the dielectric layer 142 and the conductive layer 148 to form the dielectric layer 142' and form the first via 118 and the second via 138 in the dielectric layer 142'. In some embodiments, the planarization process for planarizing the dielectric layer 142, the interlayer via 102, and the conductive layer 148 includes a flycut process, a grinding process, or a chemical mechanical polishing ("CMP") process. In some embodiments, the first via 118 includes a seed layer 118a and a metal layer 118b, and the second via 138 includes a seed layer 138a and a metal layer 138b. In some embodiments, after planarization, the dielectric layer 142' has a planar top surface, and the first via 118 and the second via 138, the interlayer via 102, and the dielectric layer 142' become flat and substantially flush (i.e., the top surfaces of the first via 118 and the second via 138 and the top surface of the interlayer via 102 are substantially coplanar and flush with the polished top surface of the dielectric layer 142').

[0044] Referring to Figure 5D , in some embodiments, a redistribution layer 150 is formed that is electrically connected to the first via 118 of the first chip 110, the second via 138 of the second chip 130, and the interlayer via 102. After forming the redistribution layer 150, a plurality of conductive terminals 160 are placed on the under-bump metal pattern 156a, and a plurality of passive components 162 are mounted on the connection pads 156b.

[0045] Referring to Figure 5E , the dielectric layer DI formed on the bottom surface of the molding layer 140a is peeled from the release layer DB so that the dielectric layer DI is separated from the carrier C. Then, a plurality of conductive terminals 164 are placed in the contact openings, and a plurality of contact openings O are formed to locally expose the interlayer via 102.

[0046] Referring to Figure 5F , a plurality of conductive terminals 164 are placed in the contact openings O, and the conductive terminals 164 are electrically connected to the interlayer via 102. Here, the formation of the integrated fan-out (INFO) package 10 is substantially completed.

[0047] Figure 6 is a schematic cross-sectional view showing a semiconductor package according to some exemplary embodiments. In Figure 6 it is described in connection with Figure 5FThe semiconductor package 10 with a similar structure as shown, except for the omission of the interlayer vias. In some embodiments, the first chip 110 and the second chip 130 have pads 122, 124 on the surfaces opposite to the active surfaces 112, 132, the contact openings O are formed to locally expose the pads 122, 124, and the conductive terminals 164 are placed in the contact openings O. Additionally, in some embodiments, the dielectric layer 142' is used as the bottommost interlayer dielectric layer of the redistribution layer 150, and thus there is no need to additionally form the bottommost interlayer dielectric layer, which reduces the process and cost of the semiconductor package.

[0048] In some embodiments, the thickness difference between the chips is compensated by increasing the adhesive layers with different thicknesses. Thus, different types of chips can be placed on the carrier for packaging. In some embodiments, the molding layer is formed such that its top surface is not higher than the active surfaces of the chips, i.e., the molding layer is not formed by over-molding technology. Therefore, there is no need for a planarization process for the molding layer, and the problem of pits caused by performing a planarization process on the molding layer containing fillers is prevented. Additionally, a dielectric layer is formed on top of the molding layer and the dielectric layer is planarized to provide a better planar surface, which is beneficial for forming metal lines or wirings on the dielectric layer later, especially for metal lines with fine line / space. Additionally, the dielectric layer provides insulation for the vias of the chips, and thus, the vias of the chips do not require a passivation layer. In other words, forming the molding layer and the dielectric layer covering the molding layer provides flexibility in material selection, provides a larger process window for the molding layer, improves the reliability of the redistribution layer with fine line / space, and simplifies the manufacturing method. Therefore, the cost of the semiconductor package can be reduced, and the performance of the semiconductor package can be improved.

[0049] According to some embodiments, a semiconductor package includes a first chip, a second chip, and a molding compound. The first chip has at least one first via and a protective layer, and the at least one first via is formed in the protective layer. The second chip has at least one second via. The molding layer encapsulates the first chip and the second chip. The at least one second via is disposed in the molding layer and in contact with the molding layer, and the top surface of the protective layer, the top surface of the at least one first via, and the top surface of the at least one second via are substantially coplanar with the top surface of the molding layer.

[0050] In some embodiments, a redistribution layer is further included, and the redistribution layer is disposed on the molding layer and electrically connected to the at least one first via and the at least one second via.

[0051] In some embodiments, the thickness of the first chip is different from the thickness of the second chip.

[0052] In some embodiments, the molding layer comprises a material without fillers.

[0053] In some embodiments, the molding layer is disposed between the at least one second via hole.

[0054] According to some embodiments, a semiconductor package includes a first chip, a molding layer, and a dielectric layer. The first chip has at least one first via hole thereon, the at least one first via hole includes a seed layer and a conductive layer, and the seed layer is disposed along the sidewall and bottom of the conductive layer. The molding layer encapsulates the first chip, and the top surface of the molding layer is not higher than the active surface of the first chip. The dielectric layer is located above the molding layer, and the at least one first via hole is disposed in the dielectric layer.

[0055] In some embodiments, a second chip is further included, and the second chip has at least one second via hole thereon, wherein the at least one second via hole is disposed in the dielectric layer.

[0056] In some embodiments, the at least one second via hole includes a conductive layer and a seed layer disposed along the sidewall and bottom of the conductive layer.

[0057] In some embodiments, the dielectric layer is disposed between the at least one first via hole and the at least one second via hole.

[0058] In some embodiments, the thickness of the first chip is different from the thickness of the second chip.

[0059] In some embodiments, the dielectric layer has a planar surface.

[0060] In some embodiments, the top surface of the molding layer is substantially flush with the active surface of the first chip.

[0061] In some embodiments, the top surface of the molding layer has a dish-shaped depression.

[0062] In some embodiments, a redistribution layer is further included, and the redistribution layer is located above the dielectric layer and electrically connected to the at least one first via hole.

[0063] According to some embodiments, a method of manufacturing a semiconductor package includes at least the following steps. Provide a first chip having a first adhesive layer and a second chip having a second adhesive layer on a carrier, and an active surface of the first chip and an active surface of the second chip are substantially coplanar. Form a molding layer to encapsulate the first chip and the second chip, and a top surface of the molding layer is not higher than the active surface of the first chip and the active surface of the second chip. Form at least one first via and at least one second via in a dielectric layer above the molding layer. The at least one first via and the at least one second via are respectively disposed on the first chip and the second chip, and a top surface of the dielectric layer, a top surface of the at least one first via, and a top surface of the at least one second via are substantially coplanar.

[0064] In some embodiments, the step of forming the at least one first via, the at least one second via, and the dielectric layer includes: forming the at least one first via and the at least one second via on the first chip and the second chip respectively; forming the dielectric layer above the molding layer to cover the at least one first via and the at least one second via; and performing a planarization process to remove a portion of the dielectric layer to expose the top surface of the at least one first via and the top surface of the at least one second via.

[0065] In some embodiments, the step of forming the at least one first via, the at least one second via, and the dielectric layer includes: forming the dielectric layer above the molding layer; forming a plurality of openings in the dielectric layer; forming a conductive layer above the dielectric layer, the conductive layer filling the openings; and performing a planarization process to remove a portion of the conductive layer and a portion of the dielectric layer, thereby forming the at least one first via and the at least one second via disposed in the dielectric layer.

[0066] In some embodiments, the step of forming the conductive layer includes: forming a seed layer above the dielectric layer, wherein the seed layer is formed on sidewalls and bottoms of each of the openings; and forming a metal layer from the seed layer.

[0067] In some embodiments, further includes: forming a redistribution layer above the dielectric layer to be electrically connected to the at least one first via and the at least one second via respectively.

[0068] In some embodiments, the molding layer comprises a material having a filler.

[0069] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should know that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, characterized in that, Comprising: A first chip having at least one first via hole thereon; A second chip having at least one second via hole thereon; A molding layer encapsulating the first chip and the second chip; A dielectric layer located above the molding layer, and the at least one first via hole and at least one second via hole are provided in the dielectric layer; and At least one via hole, wherein the at least one via hole is located in the molding layer and the dielectric layer and the side wall of the at least one via hole is in contact with the molding layer and the dielectric layer, and the top surface of the dielectric layer, the top surface of the at least one first via hole and the top surface of the at least one second via hole are substantially coplanar with the top surface of the at least one via hole.

2. The semiconductor package according to claim 1, further comprising a redistribution layer provided above the dielectric layer and electrically connected to the at least one first via hole and the at least one second via hole.

3. The semiconductor package according to claim 1, wherein the thickness of the first chip is different from the thickness of the second chip.

4. The semiconductor package according to claim 1, wherein the molding layer comprises a material without fillers.

5. The semiconductor package according to claim 1, wherein the at least one second via hole includes a plurality of second via holes, and the dielectric layer is provided between the second via holes.

6. A semiconductor package, characterized in that, Comprising: A first chip having at least one first via hole thereon, the at least one first via hole including a seed layer and a conductive layer, and the seed layer is provided along the side wall and bottom of the conductive layer; A second chip having at least one second via hole thereon; A molding layer encapsulating the first chip and the second chip, and the top surface of the molding layer is not higher than the active surface of the first chip; And A dielectric layer located above the molding layer, and the at least one first via hole and at least one second via hole are provided in the dielectric layer, wherein the top surface of the at least one first via hole is substantially coplanar with the top surface of the dielectric layer, and the dielectric layer continuously extends between the at least one first via hole and the at least one second via hole.

7. The semiconductor package according to claim 6, wherein the thickness of the first chip is different from the thickness of the second chip.

8. The semiconductor package according to claim 6, wherein the dielectric layer has a planar surface.

9. The semiconductor package according to claim 6, wherein the top surface of the molding layer is substantially flush with the active surface of the first chip.

10. The semiconductor package according to claim 6, wherein the top surface of the molding layer has a dish-shaped depression.

11. The semiconductor package according to claim 6, further comprising a redistribution layer located above the dielectric layer and electrically connected to the at least one first via hole.

12. A manufacturing method of a semiconductor package, characterized in that, Comprising: Providing a first chip having a first adhesive layer and a second chip having a second adhesive layer on a carrier, and the active surface of the first chip is substantially coplanar with the active surface of the second chip; A molding layer is formed to encapsulate the first chip and the second chip, and a top surface of the molding layer is not higher than an active surface of the first chip and an active surface of the second chip; A conductive layer of at least one first via hole and at least one second via hole is formed in a dielectric layer above the molding layer; And After forming the conductive layer, a planarization process is performed to remove a part of the dielectric layer, wherein the at least one first via hole and the at least one second via hole are respectively disposed on the first chip and the second chip, and a top surface of the dielectric layer, a top surface of the at least one first via hole and a top surface of the at least one second via hole are substantially coplanar.

13. The method according to claim 12, wherein the step of forming the at least one first via hole, the at least one second via hole and the dielectric layer comprises: Forming the conductive layer to form the at least one first via hole and the at least one second via hole on the first chip and the second chip respectively; Forming the dielectric layer above the molding layer to cover the at least one first via hole and the at least one second via hole; And Performing the planarization process to remove a part of the dielectric layer to expose the top surface of the at least one first via hole and the top surface of the at least one second via hole.

14. The method according to claim 12, wherein the step of forming the at least one first via hole, the at least one second via hole and the dielectric layer comprises: Forming the dielectric layer above the molding layer; Forming a plurality of openings in the dielectric layer; Forming the conductive layer above the dielectric layer, and the conductive layer fills the openings; And Performing the planarization process to remove a part of the conductive layer and a part of the dielectric layer, thereby forming the at least one first via hole and the at least one second via hole disposed in the dielectric layer.

15. The method according to claim 14, wherein the step of forming the conductive layer comprises: Forming a seed layer above the dielectric layer, wherein the seed layer is formed on sidewalls and bottoms of each of the openings; And Forming a metal layer from the seed layer.

16. The method according to claim 12 further comprises: A redistribution layer is formed above the dielectric layer to be electrically connected to the at least one first via hole and the at least one second via hole respectively.

17. The method according to claim 12, wherein the molding layer comprises a material having a filler.

18. A semiconductor package, characterized in that, Comprising: A first chip and a second chip; A first adhesive layer on a first surface of the first chip and a second adhesive layer on a second surface of the second chip, wherein thicknesses of the first adhesive layer and the second adhesive layer are different, and a total thickness of the first chip and the first adhesive layer is substantially equal to a total thickness of the second chip and the second adhesive layer; And A molding layer encapsulating the first chip, the second chip, the first adhesive layer and the second adhesive layer, wherein a top surface of the molding layer is not higher than a first top surface of the first chip and a second top surface of the second chip.

19. The semiconductor package according to claim 18, wherein the first top surface is substantially flush with the second top surface.

20. The semiconductor package according to claim 18, further comprising a dielectric layer on the molding layer, wherein the first chip includes a first via hole in the dielectric layer, the second chip includes a second via hole in the dielectric layer, and the top surfaces of the dielectric layer, the first via hole, and the second via hole are substantially coplanar.

21. The semiconductor package according to claim 18, wherein the thickness of the molding layer is substantially equal to the total thickness of the first chip and the first adhesive layer.

22. The semiconductor package according to claim 18, wherein the top surface of the molding layer has a dish-shaped depression.

23. The semiconductor package according to claim 18, wherein the molding layer comprises a material having a filler.

24. A semiconductor package, characterized in that, Comprising: A first chip having a first adhesive layer on the first chip; A second chip having a second adhesive layer on the second chip, wherein the thicknesses of the first adhesive layer and the second adhesive layer are different; And A molding layer encapsulating the first chip and the second chip, wherein the top surface of the molding layer is not higher than the top surfaces of the first chip and the second chip.

25. The semiconductor package according to claim 24, wherein the first chip includes an active surface, a plurality of pads on the active surface, and a protective layer covering the active surface and exposing a portion of the pads, and the molding layer encapsulates the sidewalls of the protective layer.

26. The semiconductor package according to claim 24, further comprising a dielectric layer on the molding layer, wherein the first chip includes a first via hole in the dielectric layer, the second chip includes a second via hole in the dielectric layer, and the top surfaces of the dielectric layer, the first via hole, and the second via hole are substantially coplanar.

27. The semiconductor package according to claim 26, wherein the dielectric layer contacts the first via hole and the second via hole.

28. The semiconductor package according to claim 26, wherein the material of the molding layer contains a filler, and the material of the dielectric layer does not contain a filler.

29. The semiconductor package according to claim 26, further comprising a redistribution layer disposed on the dielectric layer and contacting the dielectric layer.

30. The semiconductor package according to claim 24, wherein the thickness of the first chip is different from the thickness of the second chip.

31. The semiconductor package according to claim 24, wherein the top surface of the molding layer is substantially flush with the top surfaces of the first chip and the second chip.

32. A semiconductor package, characterized in that, Comprising: A first chip having an active surface and a first via hole on the active surface; A plurality of vias located beside the first chip; A molding layer encapsulating the first chip and the vias, wherein the top surface of the molding layer is not higher than the active surface of the first chip; And A dielectric layer, on the molding layer, wherein the first through hole is located in the dielectric layer, and the top surface of the first through hole and the top surface of the dielectric layer are substantially coplanar.

33. The semiconductor package according to claim 32, wherein the dielectric layer covers the active surface.

34. The semiconductor package according to claim 32, wherein the dielectric layer contacts the first through hole.

35. The semiconductor package according to claim 32, wherein the top surface of the molding layer is substantially flush with the active surface of the first chip.

36. The semiconductor package according to claim 32, wherein the first chip further includes a plurality of pads located on the active surface and a protective layer covering the active surface and exposing a portion of the pads, and the molding layer encapsulates the sidewalls of the protective layer.

37. The semiconductor package according to claim 32, further comprising a redistribution layer disposed on the dielectric layer and the first through hole and contacting the dielectric layer and the first through hole.

38. A semiconductor package, characterized in that, Comprising: A first chip having a first through hole and a protective layer thereon, wherein the first through hole is disposed in the protective layer; A plurality of vias located beside the first chip; And A molding layer encapsulating the first chip and the vias, wherein the surface of the molding layer is substantially coplanar with the surfaces of the protective layer and the vias.

39. The semiconductor package according to claim 38, further comprising a second chip encapsulated by the molding layer, wherein at least one of the vias is located between the first chip and the second chip.

40. The semiconductor package according to claim 38, further comprising a second chip having a second through hole thereon, the second through hole being disposed in the molding layer and contacting the molding layer.

41. The semiconductor package according to claim 40, wherein the surface of the second through hole is substantially coplanar with the surfaces of the molding layer, the protective layer, and the vias.

42. The semiconductor package according to claim 40, wherein the thicknesses of the first chip and the second chip are different.

43. The semiconductor package according to claim 38, further comprising a redistribution layer disposed on the molding layer, the redistribution layer electrically connecting the first through hole and the vias.

44. A semiconductor package, characterized in that, Comprising: A first chip having a first surface and a first through hole on the first surface; A second chip having a second surface and a second through hole on the second surface; A molding compound encapsulating the first chip and the second chip and exposing the first surface and the second surface; A first dielectric layer on the surface of the molding compound, the first surface of the first chip, and the second surface of the second chip; And A redistribution layer on the first dielectric layer, electrically connecting the first chip and the second chip through the first through hole and the second through hole, and including a first conductive pattern in direct contact with the top surface of the first dielectric layer and the top surface of the first through hole.

45. The semiconductor package according to claim 44, wherein the redistribution layer further includes a second dielectric layer located above the first dielectric layer and a second conductive pattern located above the first conductive pattern, and the second conductive pattern includes a first portion located in the second dielectric layer and a second portion located on the second dielectric layer and integrally formed with the first portion.

46. The semiconductor package according to claim 45, wherein the first conductive pattern is in direct contact with the second dielectric layer and the first portion of the second conductive pattern.

47. The semiconductor package according to claim 44, further including a first adhesive layer located under the first chip, wherein the thickness of the molding compound is substantially equal to the total thickness of the first chip and the first adhesive layer.

48. The semiconductor package according to claim 47, wherein the first chip further includes a plurality of conductive terminals passing through the first adhesive layer.

49. The semiconductor package according to claim 44, wherein the material of the molding compound contains fillers, and the material of the first dielectric layer does not contain fillers.

50. The semiconductor package according to claim 44, further including a plurality of conductive terminals located above the redistribution layer and electrically connecting the redistribution layer.

51. A method for manufacturing a semiconductor package, characterized in that, Comprising: Providing a first chip having a first through hole on a first surface of the first chip; Providing a second chip having a second through hole on a second surface of the second chip; Encapsulating the first chip and the second chip with a molding layer, and a top surface of the molding layer is not higher than the first surface of the first chip and the second surface of the second chip; Encapsulating the first through hole and the second through hole with a dielectric layer, and the dielectric layer continuously extends between the first through hole and the second through hole; And Performing a planarization process until surfaces of the dielectric layer, the first through hole, and the second through hole are substantially coplanar.

52. The method according to claim 51, wherein a portion of at least one of the dielectric layer, the first through hole, and the second through hole is removed by the planarization process.

53. The method according to claim 51, wherein the dielectric layer is in direct contact with the second through hole.

54. The method according to claim 51, wherein before performing the planarization process, a total thickness of the first chip and the first through hole is different from a total thickness of the second chip and the second through hole.

55. The method according to claim 51, further including: Forming a plurality of vias between the first chip and the second chip; Encapsulating the vias with the molding layer and the dielectric layer; And Performing the planarization process until a surface of the vias is substantially coplanar with the surfaces of the dielectric layer, the first through hole, and the second through hole.

56. The method according to claim 51, further including forming a redistribution layer on the dielectric layer, the first through hole, and the second through hole, and the redistribution layer electrically connects the first chip and the second chip through the first through hole and the second through hole.

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