A protection circuit with high efficiency current detection and current limiting function

Abstract

The present invention discloses a protection circuit with high-efficiency current detection and current limiting functions, wherein the protection circuit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first resistor, a second resistor, a first capacitor, and a first operational amplifier. A reference current IREF transmits current through the first NMOS tube and the second NMOS tube as a bias current of the entire module. Current is provided to an external load from the drain end of the fifth PMOS tube. The present invention can achieve constant current output through a current detection circuit and a current limiting feedback regulation loop when the chip output is under heavy load or short circuit, thereby protecting the circuit from high-power damage.

Description

Technical Field

[0001] The present invention relates to the application of load switches in the field of power management technology. Aiming at the shortcomings of traditional load switches, such as high power consumption, low efficiency and no current limiting function, a protection circuit implementation method of efficient current detection and current limiting function is proposed. By adopting a current detection circuit with a SENSEFET structure to detect the output current in real time, the maximum output current is limited, and the power supply system collapse caused by overload or short circuit is prevented. Background Art

[0002] With the development of power management technology and energy-saving technology, in the application of electronic systems such as laptop motherboards, LCDTV motherboards, STB set-top boxes, etc., there are multiple power supplies with different voltages inside. It is usually necessary to use MOSFET as a power distribution switch to distribute the power of the power supply system to the required equipment. Its function is to control the power-on timing of the power supply to suppress the surge current and isolate the power supply system and the equipment. Since the power MOSFET of the power switch is in the linear region during normal operation, the output voltage is approximately equal to the input voltage, so the power switch realizes a linear switch function. The output power of the early power supply was not large, and the demand for overcurrent protection was not large. Therefore, the traditional linear switch did not have current detection and current limiting functions and the static current was large. With the development of the times, the output power of the power supply has reached an output current of 10A+, and a distribution switch with current detection and current limiting functions is on the agenda. A distribution switch is needed that can not only accurately detect and limit the output current, but also effectively prevent chip damage caused by overload or short circuit. Summary of the invention

[0003] The purpose of the present invention is to design a protection circuit with high-efficiency current detection and current limiting functions. When the load switch output is overloaded or short-circuited, the circuit can limit the maximum output current through the internal current detection and limiting structure, so that the power supply is in a constant current state, effectively preventing chip damage caused by high power.

[0004] In order to solve the above problems, the present invention designs a protection circuit with current detection and current limiting functions, and its technical solution is:

[0005] The first NMOS tube MN1, the second NMOS tube MN2, the third NMOS tube MN3, the fourth NMOS tube MN4, the fifth NMOS tube MN5, the sixth NMOS tube MN6, the seventh NMOS tube MN7, the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4, the fifth PMOS tube MP5, the sixth PMOS tube MP6, the first resistor R1, the second resistor RL, the first capacitor C1, and the first operational amplifier EA1. The drain of the first NMOS tube (MN1) is connected to the reference current IREF, the gate of the first NMOS tube and the gate of the third NMOS tube (MN3). The source of the first NMOS tube is connected to the drain and gate of the second NMOS tube MN2, the gate of the fourth NMOS tube (MN4), the gate of the sixth NMOS tube (MN6) and the positive phase end of the first capacitor C1. The substrate of the first NMOS tube is grounded (GND). The source of the second NMOS tube (MN2) and the substrate are grounded. The negative phase end of the first capacitor C1 is grounded. The drain of the third NMOS tube (MN3) is connected to the gate and drain of the first PMOS tube (MP1), and is connected to the gate of the second PMOS tube (MP2). The source of the third NMOS tube is connected to the drain of the fourth NMOS tube (MN4). The substrate of the third NMOS tube, the source and the substrate of the fourth NMOS tube are all grounded. The gate of the fifth NMOS tube (MN5) is connected to the gate and drain of the seventh NMOS tube (MN7) and the drain of the sixth PMOS tube (MP6). The drain of the fifth NMOS tube is connected to the drain of the second PMOS tube (MP2) and the gate of the third PMOS tube (MP3). The source and the substrate of the fifth NMOS tube, the sixth NMOS tube and the seventh NMOS tube are all grounded. The drain of the sixth NMOS tube is connected to the drain of the third PMOS tube, the gate of the fourth PMOS tube (MP4) and the gate of the fifth PMOS tube (MP5). One end of the first resistor (R1) is connected to the drain of the fourth PMOS tube, and the other end is connected to the source and the substrate of the sixth PMOS tube and the negative phase end of the first error amplifier (EA1). The output of the first error amplifier is connected to the gate of the sixth PMOS tube. The source and substrate of the third PMOS tube (MP3) and the first and second PMOS tubes are all connected to VDD. The source of the fourth PMOS tube and the fifth PMOS tube are all connected to IN, and the substrate is all connected to VDD. The output terminal OUT is connected to the drain of the fifth PMOS tube, the positive phase terminal of the first error amplifier and one end of the second resistor (RL). The other end of the second resistor (RL) is grounded.

[0006] In the above-mentioned protection circuit with high-efficiency current detection and current limiting functions, the first operational amplifier is an operational amplifier composed of a PMOS tube and an NMOS tube.

[0007] In the above-mentioned protection circuit with efficient current detection and current limiting function, the input signal IREF is the input reference current signal, the input signals IN and VDD are chip input power terminal signals, and the output signal OUT is the chip output terminal signal.

[0008] The beneficial effects of the present invention are as follows: in the protection circuit with efficient current detection and current limiting function proposed by the present invention, when the load is overloaded or short-circuited, the internal current sampling tube can detect the load current change in time, and by comparing with the reference current, a negative feedback loop is used to limit the output current to a safe constant current state, thereby preventing high power output under overload or short-circuit conditions, which may cause the chip to burn out. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a schematic diagram of the specific structure of an embodiment of the present invention.

[0010] Figure 2 This is a simulation result diagram under the overcurrent state in the present invention. DETAILED DESCRIPTION

[0011] like Figure 1As shown, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a first resistor R1, a second resistor RL, a first capacitor C1, and a first operational amplifier EA1. The drain of the first NMOS tube (MN1) is connected to a reference current IREF, a gate of the first NMOS tube, and a gate of the third NMOS tube (MN3). The source of the first NMOS tube is connected to a drain and a gate of the second NMOS tube MN2, a gate of the fourth NMOS tube (MN4), a gate of the sixth NMOS tube (MN6), and a positive phase end of the first capacitor C1. The substrate of the first NMOS tube is grounded (GND). The source of the second NMOS tube (MN2) and the substrate are grounded. The negative phase end of the first capacitor C1 is grounded. The drain of the third NMOS tube (MN3) is connected to the gate and drain of the first PMOS tube (MP1), and is connected to the gate of the second PMOS tube (MP2). The source of the third NMOS tube is connected to the drain of the fourth NMOS tube (MN4). The substrate of the third NMOS tube, the source and the substrate of the fourth NMOS tube are all grounded. The gate of the fifth NMOS tube (MN5) is connected to the gate and drain of the seventh NMOS tube (MN7) and the drain of the sixth PMOS tube (MP6). The drain of the fifth NMOS tube is connected to the drain of the second PMOS tube (MP2) and the gate of the third PMOS tube (MP3). The source and the substrate of the fifth NMOS tube, the sixth NMOS tube and the seventh NMOS tube are all grounded. The drain of the sixth NMOS tube is connected to the drain of the third PMOS tube, the gate of the fourth PMOS tube (MP4) and the gate of the fifth PMOS tube (MP5). One end of the first resistor (R1) is connected to the drain of the fourth PMOS tube, and the other end is connected to the source and the substrate of the sixth PMOS tube and the negative phase end of the first error amplifier (EA1). The output of the first error amplifier is connected to the gate of the sixth PMOS tube. The source and substrate of the third PMOS tube (MP3) and the first and second PMOS tubes are all connected to VDD. The source of the fourth PMOS tube and the fifth PMOS tube are all connected to IN, and the substrate is all connected to VDD. The output terminal OUT is connected to the drain of the fifth PMOS tube, the positive phase terminal of the first error amplifier and one end of the second resistor (RL). The other end of the second resistor (RL) is grounded.

[0012] In the above-mentioned protection circuit with high-efficiency current detection and current limiting functions, the first operational amplifier is an operational amplifier composed of a PMOS tube and an NMOS tube.

[0013] In the above-mentioned protection circuit with efficient current detection and current limiting function, the input signal IREF is the input reference current signal, the input signals IN and VDD are chip input power terminal signals, and the output signal OUT is the chip output terminal signal.

[0014] like Figure 2 As shown, the IREF reference current flows into MN1, MN2, MN3 and MN4 as an input signal to form a common source and common gate current mirror, providing bias current for the entire module. The current mirror composed of MP1 and MP2 further actively amplifies IREF and compares it with the load current sampling signal provided by MN5, thereby controlling the gate potential of MP3, and further adjusting the gate potential of the sampling tube MP4 and the power tube MP5, so that the power tube is in a linear switching state, or a constant current state under overcurrent. The role of the operational amplifier EA1 is to clamp the drain voltage of MP4 and MP5, thereby ensuring a high degree of matching of the sampling current.

[0015] The reference current signal IREF provides the entire module with a current signal that is little affected by temperature and voltage, and its current accuracy directly affects the accuracy of the current limiting value. The present invention uses a common source and common gate structure current mirror to receive this signal. The clamping effect of MN1 and MN3 makes the drain potentials of MN2 and MN4 equal, thereby reducing the influence of the channel length modulation effect on the current matching degree. Capacitor C1 plays the role of anti-noise filtering to ensure the stability of the gate voltage of MN2 and MN4. At the same time, MN1 and MN3 receive the gate voltage formed by the current signal to provide a bias point for MN6, and MN6 acts as an active load. The PMOS current mirror MP1 and MP2 receive and amplify the reference current IREF. By designing the proportional factor M of the width-to-length ratio of MP1 and MP2, (M=(W / L) MP2 :(W / L) MP1 )) The current limit value in the overcurrent condition can be adjusted. The reference current provided by MP2 is compared with the sampled current provided by MN5 to control the operation of the negative feedback loop.

[0016] Under normal working conditions, when the load resistor RL is lightly loaded or unloaded, the output current of the power tube MP5 is very small. The sampling tube MP4 detects that the output current is very small and inputs the micro-current into the diode-connected MN7 tube. Due to the micro-current bias, the gate voltage of MN7 is very low. Similarly, the gate voltage of MN5 tube is very low. Since MP2 provides a strong pull-up capability for the reference current, the drain of MP2 is pulled up, and MP2 is in the deep linear region to maintain a weak current. At this time, the gate potential of MP3 is close to VDD, resulting in a zero gate-source voltage difference of MP3, and MP3 is turned off. The active load MN6 of MP3 is always turned on, pulling the drain potential of MP3 to zero. At this time, the gate voltage of MP4 and MP5 is close to zero, and MP4 and MP5 are in the deep linear region, maintaining a very small current output. At the same time, the effect of R1 makes the voltage at the drain end of the current sampling tube MP4 higher than the voltage at the drain end of the power MOS tube MP5 by about tens of mV. This prevents leakage from occurring under no-load conditions.

[0017] When the system is overloaded or short-circuited, when the load circuit RL is very small, the source-drain voltage difference of the power tube MP5 is very large, it is in the saturation region, and the output current is very large. At this time, the sampling tube MP4 detects the current change in time and inputs a larger sampling current to the MN7 tube. MN7 is an active load connected by a diode. In order to maintain a larger sampling current, the gate voltage of MN7 becomes higher, so that the gate voltage of MN5 becomes higher, and it is compared with the reference current provided by MP2. The gate voltage of MN5 becomes higher, and the drain voltage of MP2 becomes lower after the common source amplification formed by the MN5 tube. Then, after the common source amplification formed by the MP3 tube, the gate voltage of the MP4 tube and the MP5 tube becomes lower. Then, after the common source amplification formed by the MP4 tube and the MP5 tube, the drain potential of the MP4 tube and the MP5 tube becomes higher, thereby suppressing the trend of OUT becoming lower, thereby forming a negative feedback loop, and finally limiting the output current to a constant current value. In order to sample the output current more accurately, the operational amplifier EA1 is used. By virtue of its high gain characteristics, the drain potential of the sampling tube MP4 and the power tube MP5 is equal, thereby eliminating the influence of the channel length modulation effect.

[0018] In the protection scheme of efficient current detection and current limiting function proposed by the present invention, the external reference current IREF is used as the input current. When the sampling tube detects that the load is in a heavy load or short circuit state, a negative feedback loop is formed by comparing the sampling current with the reference current to make the power tube in a constant current state. In order to ensure a high degree of matching of current limiting accuracy, an error amplifier is used internally to make the drain voltage of the sampling tube and the power tube equal by virtue of its high gain characteristics, thereby obtaining a high-precision current limiting value.

[0019] The above technical solution can detect the change of output current in time when the output terminal OUT is overloaded or short-circuited, and limit the output current to a safe constant value to avoid chip damage under high power conditions.

[0020] The content and features of the present invention have been disclosed above. The circuit structure described above is only an example in the art and can be applied to the current detection and protection circuit of any power management chip.

Claims

1. A protection circuit for realizing current detection and current limiting functions, characterized in that The protection circuit includes a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a first resistor R1, a second resistor RL, a first capacitor C1, and a first operational amplifier EA1; wherein, The drain of the first NMOS transistor MN1 is connected to the reference current IREF, the gate of the first NMOS transistor MN1 and the gate of the third NMOS transistor MN3; the source of the first NMOS transistor MN1 is connected to the drain and gate of the second NMOS transistor MN2, the gate of the fourth NMOS transistor MN4, the gate of the sixth NMOS transistor MN6 and the positive phase end of the first capacitor C1; the substrate of the first NMOS transistor MN1 is grounded GND; The source electrode and substrate of the second NMOS tube MN2 are grounded; The negative phase terminal of the first capacitor C1 is grounded; The drain of the third NMOS tube MN3 is connected to the gate and drain of the first PMOS tube MP1, and is connected to the gate of the second PMOS tube MP2; the source of the third NMOS tube MN3 is connected to the drain of the fourth NMOS tube MN4; the substrate of the third NMOS tube MN3, the source and the substrate of the fourth NMOS tube MN4 are all grounded; The gate of the fifth NMOS tube MN5 is connected to the gate and drain of the seventh NMOS tube MN7 and the drain of the sixth PMOS tube MP6; the drain of the fifth NMOS tube MN5 is connected to the drain of the second PMOS tube MP2 and the gate of the third PMOS tube MP3; The source electrodes and substrates of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 are all grounded; The drain of the sixth NMOS tube MN6 is connected to the drain of the third PMOS tube MP3, the gate of the fourth PMOS tube MP4 and the gate of the fifth PMOS tube MP5; One end of the first resistor R1 is connected to the drain of the fourth PMOS tube MP4, and the other end is connected to the source and substrate of the sixth PMOS tube and the negative phase terminal of the first operational amplifier EA1; the output of the first operational amplifier EA1 is connected to the gate of the sixth PMOS tube MP6; the source and substrate of the third PMOS tube MP3 and the first PMOS tube MP1 and the second PMOS tube MP2 are all connected to VDD; The sources of the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are both connected to IN, and the substrates are both connected to VDD; The output terminal OUT is connected to the drain of the fifth PMOS transistor MP5, the positive phase terminal of the first operational amplifier EA1 and one end of the second resistor RL; the other end of the second resistor RL is grounded; The first operational amplifier EA1 is an operational amplifier composed of a PMOS tube and an NMOS tube.

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